Clean up F7 SDMMC
This commit is contained in:
David Sidrane
parent
0bf68df3c7
commit
adf0e8d357
@ -1215,12 +1215,16 @@ config STM32F7_SDMMC1
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bool "SDMMC1"
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default n
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select ARCH_HAVE_SDIO
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select ARCH_HAVE_SDIOWAIT_WRCOMPLETE
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select SDIO_PREFLIGHT
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config STM32F7_SDMMC2
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bool "SDMMC2"
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default n
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depends on STM32F7_HAVE_SDMMC2
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select ARCH_HAVE_SDIO
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select ARCH_HAVE_SDIOWAIT_WRCOMPLETE
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select SDIO_PREFLIGHT
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config STM32F7_SPDIFRX
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bool "SPDIFRX"
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@ -1710,6 +1714,86 @@ config STM32F7_I2C_DUTY16_9
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endmenu # "I2C Configuration"
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config STM32F7_SDMMC_XFRDEBUG
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bool "SDMMC transfer debug"
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depends on DEBUG_FS_INFO && (STM32F7_SDMMC1 || STM32F7_SDMMC2)
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default n
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---help---
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Enable special debug instrumentation analyze SDMMC data transfers.
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This logic is as non-invasive as possible: It samples SDMMC
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registers at key points in the data transfer and then dumps all of
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the registers at the end of the transfer. If DEBUG_DMA is also
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enabled, then DMA register will be collected as well. Requires also
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DEBUG_FS and CONFIG_DEBUG_INFO.
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menu "SDMMC1 Configuration"
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depends on STM32F7_SDMMC1
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config SDMMC1_DMA
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bool "Support DMA data transfers on SDMMC1"
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default y if STM32F7_DMA2
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depends on STM32F7_DMA2
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---help---
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Support DMA data transfers on SDMMC1. Requires STM32F7_SDMMC1 and config STM32F7_DMA2.
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config SDMMC1_PRI
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hex "SDMMC1 interrupt priority"
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default 128
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depends on ARCH_IRQPRIO && EXPERIMENTAL
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---help---
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Select SDMMC1 interrupt priority. Default: 128.
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config SDMMC1_DMAPRIO
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hex "SDMMC1 DMA priority"
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default 0x00010000
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---help---
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Select SDMMC1 DMA prority.
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Options are: 0x00000000 low, 0x00010000 medium,
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0x00020000 high, 0x00030000 very high. Default: medium.
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config SDMMC1_WIDTH_D1_ONLY
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bool "Use D1 only on SDMMC1"
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default n
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---help---
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Select 1-bit transfer mode. Default: 4-bit transfer mode.
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endmenu # "SDMMC1 Configuration"
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menu "SDMMC2 Configuration"
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depends on STM32F7_SDMMC2
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config SDMMC2_DMA
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bool "Support DMA data transfers on SDMMC2"
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default y if STM32F7_DMA2
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depends on STM32F7_DMA2
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---help---
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Support DMA data transfers on SDMMC2. Requires STM32F7_SDMMC2 and config STM32F7_DMA2.
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config SDMMC2_PRI
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hex "SDMMC2 interrupt priority"
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default 128
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depends on ARCH_IRQPRIO && EXPERIMENTAL
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---help---
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Select SDMMC2 interrupt priority. Default: 128.
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config SDMMC2_DMAPRIO
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hex "SDMMC2 DMA priority"
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default 0x00010000
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---help---
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Select SDMMC1 DMA prority.
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Options are: 0x00000000 low, 0x00010000 medium,
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0x00020000 high, 0x00030000 very high. Default: medium.
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config SDMMC2_WIDTH_D1_ONLY
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bool "Use D1 only on SDMMC2"
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default n
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---help---
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Select 1-bit transfer mode. Default: 4-bit transfer mode.
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endmenu # "SDMMC2 Configuration"
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config STM32F7_CUSTOM_CLOCKCONFIG
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bool "Custom clock configuration"
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default n
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@ -2,7 +2,8 @@
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* arch/arm/src/stm32f7/chip/stm32_sdmmc.h
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -43,8 +44,9 @@
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#include <nuttx/config.h>
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#include "chip.h"
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#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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# include "stm32f74xx75xx_sdmmc.h"
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#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
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defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
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# include "stm32f74xx77xx_sdmmc.h"
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#else
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# error "Unsupported STM32 F7 part"
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#endif
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@ -1,268 +0,0 @@
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/************************************************************************************
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* arch/arm/src/stm32f7/chip/stm32_sdmmc.h
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*
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* Copyright (C) 2009, 2011-2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SDMMC_H
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#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SDMMC_H
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32_SDMMC1_POWER_OFFSET 0x0000 /* SDIO power control register */
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#define STM32_SDMMC1_CLKCR_OFFSET 0x0004 /* SDI clock control register */
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#define STM32_SDMMC1_ARG_OFFSET 0x0008 /* SDIO argument register */
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#define STM32_SDMMC1_CMD_OFFSET 0x000c /* SDIO command register */
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#define STM32_SDMMC1_RESPCMD_OFFSET 0x0010 /* SDIO command response register */
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#define STM32_SDMMC1_RESP_OFFSET(n) (0x0010+4*(n))
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#define STM32_SDMMC1_RESP1_OFFSET 0x0014 /* SDIO response 1 register */
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#define STM32_SDMMC1_RESP2_OFFSET 0x0018 /* SDIO response 2 register */
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#define STM32_SDMMC1_RESP3_OFFSET 0x001c /* SDIO response 3 register */
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#define STM32_SDMMC1_RESP4_OFFSET 0x0020 /* SDIO response 4 register */
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#define STM32_SDMMC1_DTIMER_OFFSET 0x0024 /* SDIO data timer register */
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#define STM32_SDMMC1_DLEN_OFFSET 0x0028 /* SDIO data length register */
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#define STM32_SDMMC1_DCTRL_OFFSET 0x002c /* SDIO data control register */
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#define STM32_SDMMC1_DCOUNT_OFFSET 0x0030 /* SDIO data counter register */
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#define STM32_SDMMC1_STA_OFFSET 0x0034 /* SDIO status register */
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#define STM32_SDMMC1_ICR_OFFSET 0x0038 /* SDIO interrupt clear register */
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#define STM32_SDMMC1_MASK_OFFSET 0x003c /* SDIO mask register */
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#define STM32_SDMMC1_FIFOCNT_OFFSET 0x0048 /* SDIO FIFO counter register */
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#define STM32_SDMMC1_FIFO_OFFSET 0x0080 /* SDIO data FIFO register */
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/* Register Addresses ***************************************************************/
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#define STM32_SDMMC1_POWER (STM32_SDMMC1_BASE+STM32_SDMMC1_POWER_OFFSET)
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#define STM32_SDMMC1_CLKCR (STM32_SDMMC1_BASE+STM32_SDMMC1_CLKCR_OFFSET)
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#define STM32_SDMMC1_ARG (STM32_SDMMC1_BASE+STM32_SDMMC1_ARG_OFFSET)
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#define STM32_SDMMC1_CMD (STM32_SDMMC1_BASE+STM32_SDMMC1_CMD_OFFSET)
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#define STM32_SDMMC1_RESPCMD (STM32_SDMMC1_BASE+STM32_SDMMC1_RESPCMD_OFFSET)
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#define STM32_SDMMC1_RESP(n) (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP_OFFSET(n))
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#define STM32_SDMMC1_RESP1 (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP1_OFFSET)
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#define STM32_SDMMC1_RESP2 (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP2_OFFSET)
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#define STM32_SDMMC1_RESP3 (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP3_OFFSET)
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#define STM32_SDMMC1_RESP4 (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP4_OFFSET)
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#define STM32_SDMMC1_DTIMER (STM32_SDMMC1_BASE+STM32_SDMMC1_DTIMER_OFFSET)
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#define STM32_SDMMC1_DLEN (STM32_SDMMC1_BASE+STM32_SDMMC1_DLEN_OFFSET)
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#define STM32_SDMMC1_DCTRL (STM32_SDMMC1_BASE+STM32_SDMMC1_DCTRL_OFFSET)
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#define STM32_SDMMC1_DCOUNT (STM32_SDMMC1_BASE+STM32_SDMMC1_DCOUNT_OFFSET)
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#define STM32_SDMMC1_STA (STM32_SDMMC1_BASE+STM32_SDMMC1_STA_OFFSET)
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#define STM32_SDMMC1_ICR (STM32_SDMMC1_BASE+STM32_SDMMC1_ICR_OFFSET)
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#define STM32_SDMMC1_MASK (STM32_SDMMC1_BASE+STM32_SDMMC1_MASK_OFFSET)
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#define STM32_SDMMC1_FIFOCNT (STM32_SDMMC1_BASE+STM32_SDMMC1_FIFOCNT_OFFSET)
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#define STM32_SDMMC1_FIFO (STM32_SDMMC1_BASE+STM32_SDMMC1_FIFO_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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#define SDIO_POWER_PWRCTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */
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#define SDIO_POWER_PWRCTRL_MASK (3 << SDIO_POWER_PWRCTRL_SHIFT)
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# define SDIO_POWER_PWRCTRL_OFF (0 << SDIO_POWER_PWRCTRL_SHIFT) /* 00: Power-off: card clock stopped */
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# define SDIO_POWER_PWRCTRL_PWRUP (2 << SDIO_POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */
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# define SDIO_POWER_PWRCTRL_ON (3 << SDIO_POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */
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#define SDIO_POWER_RESET (0) /* Reset value */
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#define SDIO_CLKCR_CLKDIV_SHIFT (0) /* Bits 7-0: Clock divide factor */
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#define SDIO_CLKCR_CLKDIV_MASK (0xff << SDIO_CLKCR_CLKDIV_SHIFT)
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#define SDIO_CLKCR_CLKEN (1 << 8) /* Bit 8: Clock enable bit */
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#define SDIO_CLKCR_PWRSAV (1 << 9) /* Bit 9: Power saving configuration bit */
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#define SDIO_CLKCR_BYPASS (1 << 10) /* Bit 10: Clock divider bypass enable bit */
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#define SDIO_CLKCR_WIDBUS_SHIFT (11) /* Bits 12-11: Wide bus mode enable bits */
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#define SDIO_CLKCR_WIDBUS_MASK (3 << SDIO_CLKCR_WIDBUS_SHIFT)
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# define SDIO_CLKCR_WIDBUS_D1 (0 << SDIO_CLKCR_WIDBUS_SHIFT) /* 00: Default (SDIO_D0) */
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# define SDIO_CLKCR_WIDBUS_D4 (1 << SDIO_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (SDIO_D[3:0]) */
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# define SDIO_CLKCR_WIDBUS_D8 (2 << SDIO_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (SDIO_D[7:0]) */
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#define SDIO_CLKCR_NEGEDGE (1 << 13) /* Bit 13: SDIO_CK dephasing selection bit */
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#define SDIO_CLKCR_HWFC_EN (1 << 14) /* Bit 14: HW Flow Control enable */
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#define SDIO_CLKCR_RESET (0) /* Reset value */
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#define SDIO_ARG_RESET (0) /* Reset value */
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#define SDIO_CLKCR_CLKEN_BB (STM32_SDMMC1_CLKCR_BB + (8 * 4))
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#define SDIO_CLKCR_PWRSAV_BB (STM32_SDMMC1_CLKCR_BB + (9 * 4))
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#define SDIO_CLKCR_BYPASS_BB (STM32_SDMMC1_CLKCR_BB + (10 * 4))
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#define SDIO_CLKCR_NEGEDGE_BB (STM32_SDMMC1_CLKCR_BB + (13 * 4))
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#define SDIO_CLKCR_HWFC_EN_BB (STM32_SDMMC1_CLKCR_BB + (14 * 4))
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#define SDIO_CMD_CMDINDEX_SHIFT (0)
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#define SDIO_CMD_CMDINDEX_MASK (0x3f << SDIO_CMD_CMDINDEX_SHIFT)
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#define SDIO_CMD_WAITRESP_SHIFT (6) /* Bits 7-6: Wait for response bits */
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#define SDIO_CMD_WAITRESP_MASK (3 << SDIO_CMD_WAITRESP_SHIFT)
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# define SDIO_CMD_NORESPONSE (0 << SDIO_CMD_WAITRESP_SHIFT) /* 00/10: No response */
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# define SDIO_CMD_SHORTRESPONSE (1 << SDIO_CMD_WAITRESP_SHIFT) /* 01: Short response */
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# define SDIO_CMD_LONGRESPONSE (3 << SDIO_CMD_WAITRESP_SHIFT) /* 11: Long response */
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#define SDIO_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */
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#define SDIO_CMD_WAITPEND (1 << 9) /* Bit 9: CPSM Waits for ends of data transfer */
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#define SDIO_CMD_CPSMEN (1 << 10) /* Bit 10: Command path state machine enable */
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#define SDIO_CMD_SUSPEND (1 << 11) /* Bit 11: SD I/O suspend command */
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#define SDIO_CMD_ENDCMD (1 << 12) /* Bit 12: Enable CMD completion */
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#define SDIO_CMD_NIEN (1 << 13) /* Bit 13: not Interrupt Enable */
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#define SDIO_CMD_ATACMD (1 << 14) /* Bit 14: CE-ATA command */
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#define SDIO_CMD_RESET (0) /* Reset value */
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#define SDIO_CMD_WAITINT_BB (STM32_SDMMC1_CMD_BB + (8 * 4))
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#define SDIO_CMD_WAITPEND_BB (STM32_SDMMC1_CMD_BB + (9 * 4))
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#define SDIO_CMD_CPSMEN_BB (STM32_SDMMC1_CMD_BB + (10 * 4))
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#define SDIO_CMD_SUSPEND_BB (STM32_SDMMC1_CMD_BB + (11 * 4))
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#define SDIO_CMD_ENCMD_BB (STM32_SDMMC1_CMD_BB + (12 * 4))
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#define SDIO_CMD_NIEN_BB (STM32_SDMMC1_CMD_BB + (13 * 4))
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#define SDIO_CMD_ATACMD_BB (STM32_SDMMC1_CMD_BB + (14 * 4))
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#define SDIO_RESPCMD_SHIFT (0)
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#define SDIO_RESPCMD_MASK (0x3f << SDIO_RESPCMD_SHIFT)
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#define SDIO_DTIMER_RESET (0) /* Reset value */
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#define SDIO_DLEN_SHIFT (0)
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#define SDIO_DLEN_MASK (0x01ffffff << SDIO_DLEN_SHIFT)
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#define SDIO_DLEN_RESET (0) /* Reset value */
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#define SDIO_DCTRL_DTEN (1 << 0) /* Bit 0: Data transfer enabled bit */
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#define SDIO_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */
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#define SDIO_DCTRL_DTMODE (1 << 2) /* Bit 2: Data transfer mode */
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#define SDIO_DCTRL_DMAEN (1 << 3) /* Bit 3: DMA enable bit */
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#define SDIO_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 7-4: Data block size */
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#define SDIO_DCTRL_DBLOCKSIZE_MASK (15 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
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# define SDIO_DCTRL_1BYTE (0 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
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# define SDIO_DCTRL_2BYTES (1 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
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# define SDIO_DCTRL_4BYTES (2 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
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# define SDIO_DCTRL_8BYTES (3 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
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# define SDIO_DCTRL_16BYTES (4 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
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# define SDIO_DCTRL_32BYTES (5 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
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# define SDIO_DCTRL_64BYTES (6 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
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# define SDIO_DCTRL_128BYTES (7 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
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# define SDIO_DCTRL_256BYTES (8 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
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# define SDIO_DCTRL_512BYTES (9 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
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# define SDIO_DCTRL_1KBYTE (10 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
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# define SDIO_DCTRL_2KBYTES (11 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
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# define SDIO_DCTRL_4KBYTES (12 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
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# define SDIO_DCTRL_8KBYTES (13 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
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# define SDIO_DCTRL_16KBYTES (14 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
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#define SDIO_DCTRL_RWSTART (1 << 8) /* Bit 8: Read wait start */
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#define SDIO_DCTRL_RWSTOP (1 << 9) /* Bit 9: Read wait stop */
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#define SDIO_DCTRL_RWMOD (1 << 10) /* Bit 10: Read wait mode */
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#define SDIO_DCTRL_SDIOEN (1 << 11) /* Bit 11: SD I/O enable functions */
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#define SDIO_DCTRL_RESET (0) /* Reset value */
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#define SDIO_DCTRL_DTEN_BB (STM32_SDMMC1_DCTRL_BB + (0 * 4))
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#define SDIO_DCTRL_DTDIR_BB (STM32_SDMMC1_DCTRL_BB + (1 * 4))
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#define SDIO_DCTRL_DTMODE_BB (STM32_SDMMC1_DCTRL_BB + (2 * 4))
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#define SDIO_DCTRL_DMAEN_BB (STM32_SDMMC1_DCTRL_BB + (3 * 4))
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#define SDIO_DCTRL_RWSTART_BB (STM32_SDMMC1_DCTRL_BB + (8 * 4))
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#define SDIO_DCTRL_RWSTOP_BB (STM32_SDMMC1_DCTRL_BB + (9 * 4))
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#define SDIO_DCTRL_RWMOD_BB (STM32_SDMMC1_DCTRL_BB + (10 * 4))
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#define SDIO_DCTRL_SDIOEN_BB (STM32_SDMMC1_DCTRL_BB + (11 * 4))
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#define SDIO_DATACOUNT_SHIFT (0)
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#define SDIO_DATACOUNT_MASK (0x01ffffff << SDIO_DATACOUNT_SHIFT)
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#define SDIO_STA_CCRCFAIL (1 << 0) /* Bit 0: Command response CRC fail */
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#define SDIO_STA_DCRCFAIL (1 << 1) /* Bit 1: Data block CRC fail */
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#define SDIO_STA_CTIMEOUT (1 << 2) /* Bit 2: Command response timeout */
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#define SDIO_STA_DTIMEOUT (1 << 3) /* Bit 3: Data timeout */
|
||||
#define SDIO_STA_TXUNDERR (1 << 4) /* Bit 4: Transmit FIFO underrun error */
|
||||
#define SDIO_STA_RXOVERR (1 << 5) /* Bit 5: Received FIFO overrun error */
|
||||
#define SDIO_STA_CMDREND (1 << 6) /* Bit 6: Command response received */
|
||||
#define SDIO_STA_CMDSENT (1 << 7) /* Bit 7: Command sent */
|
||||
#define SDIO_STA_DATAEND (1 << 8) /* Bit 8: Data end */
|
||||
#define SDIO_STA_STBITERR (1 << 9) /* Bit 9: Start bit not detected */
|
||||
#define SDIO_STA_DBCKEND (1 << 10) /* Bit 10: Data block sent/received */
|
||||
#define SDIO_STA_CMDACT (1 << 11) /* Bit 11: Command transfer in progress */
|
||||
#define SDIO_STA_TXACT (1 << 12) /* Bit 12: Data transmit in progress */
|
||||
#define SDIO_STA_RXACT (1 << 13) /* Bit 13: Data receive in progress */
|
||||
#define SDIO_STA_TXFIFOHE (1 << 14) /* Bit 14: Transmit FIFO half empty */
|
||||
#define SDIO_STA_RXFIFOHF (1 << 15) /* Bit 15: Receive FIFO half full */
|
||||
#define SDIO_STA_TXFIFOF (1 << 16) /* Bit 16: Transmit FIFO full */
|
||||
#define SDIO_STA_RXFIFOF (1 << 17) /* Bit 17: Receive FIFO full */
|
||||
#define SDIO_STA_TXFIFOE (1 << 18) /* Bit 18: Transmit FIFO empty */
|
||||
#define SDIO_STA_RXFIFOE (1 << 19) /* Bit 19: Receive FIFO empty */
|
||||
#define SDIO_STA_TXDAVL (1 << 20) /* Bit 20: Data available in transmit FIFO */
|
||||
#define SDIO_STA_RXDAVL (1 << 21) /* Bit 21: Data available in receive FIFO */
|
||||
#define SDIO_STA_SDIOIT (1 << 22) /* Bit 22: SDIO interrupt received */
|
||||
#define SDIO_STA_CEATAEND (1 << 23) /* Bit 23: CMD6 CE-ATA command completion */
|
||||
|
||||
#define SDIO_ICR_CCRCFAILC (1 << 0) /* Bit 0: CCRCFAIL flag clear bit */
|
||||
#define SDIO_ICR_DCRCFAILC (1 << 1) /* Bit 1: DCRCFAIL flag clear bit */
|
||||
#define SDIO_ICR_CTIMEOUTC (1 << 2) /* Bit 2: CTIMEOUT flag clear bit */
|
||||
#define SDIO_ICR_DTIMEOUTC (1 << 3) /* Bit 3: DTIMEOUT flag clear bit */
|
||||
#define SDIO_ICR_TXUNDERRC (1 << 4) /* Bit 4: TXUNDERR flag clear bit */
|
||||
#define SDIO_ICR_RXOVERRC (1 << 5) /* Bit 5: RXOVERR flag clear bit */
|
||||
#define SDIO_ICR_CMDRENDC (1 << 6) /* Bit 6: CMDREND flag clear bit */
|
||||
#define SDIO_ICR_CMDSENTC (1 << 7) /* Bit 7: CMDSENT flag clear bit */
|
||||
#define SDIO_ICR_DATAENDC (1 << 8) /* Bit 8: DATAEND flag clear bit */
|
||||
#define SDIO_ICR_STBITERRC (1 << 9) /* Bit 9: STBITERR flag clear bit */
|
||||
#define SDIO_ICR_DBCKENDC (1 << 10) /* Bit 10: DBCKEND flag clear bit */
|
||||
#define SDIO_ICR_SDIOITC (1 << 22) /* Bit 22: SDIOIT flag clear bit */
|
||||
#define SDIO_ICR_CEATAENDC (1 << 23) /* Bit 23: CEATAEND flag clear bit */
|
||||
|
||||
#define SDIO_ICR_RESET 0x00c007ff
|
||||
#define SDIO_ICR_STATICFLAGS 0x000005ff
|
||||
|
||||
#define SDIO_MASK_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */
|
||||
#define SDIO_MASK_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */
|
||||
#define SDIO_MASK_CTIMEOUTIE (1 << 2) /* Bit 2: Command timeout interrupt enable */
|
||||
#define SDIO_MASK_DTIMEOUTIE (1 << 3) /* Bit 3: Data timeout interrupt enable */
|
||||
#define SDIO_MASK_TXUNDERRIE (1 << 4) /* Bit 4: Tx FIFO underrun error interrupt enable */
|
||||
#define SDIO_MASK_RXOVERRIE (1 << 5) /* Bit 5: Rx FIFO overrun error interrupt enable */
|
||||
#define SDIO_MASK_CMDRENDIE (1 << 6) /* Bit 6: Command response received interrupt enable */
|
||||
#define SDIO_MASK_CMDSENTIE (1 << 7) /* Bit 7: Command sent interrupt enable */
|
||||
#define SDIO_MASK_DATAENDIE (1 << 8) /* Bit 8: Data end interrupt enable */
|
||||
#define SDIO_MASK_STBITERRIE (1 << 9) /* Bit 9: Start bit error interrupt enable */
|
||||
#define SDIO_MASK_DBCKENDIE (1 << 10) /* Bit 10: Data block end interrupt enable */
|
||||
#define SDIO_MASK_CMDACTIE (1 << 11) /* Bit 11: Command acting interrupt enable */
|
||||
#define SDIO_MASK_TXACTIE (1 << 12) /* Bit 12: Data transmit acting interrupt enable */
|
||||
#define SDIO_MASK_RXACTIE (1 << 13) /* Bit 13: Data receive acting interrupt enable */
|
||||
#define SDIO_MASK_TXFIFOHEIE (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */
|
||||
#define SDIO_MASK_RXFIFOHFIE (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */
|
||||
#define SDIO_MASK_TXFIFOFIE (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */
|
||||
#define SDIO_MASK_RXFIFOFIE (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */
|
||||
#define SDIO_MASK_TXFIFOEIE (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */
|
||||
#define SDIO_MASK_RXFIFOEIE (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */
|
||||
#define SDIO_MASK_TXDAVLIE (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */
|
||||
#define SDIO_MASK_RXDAVLIE (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */
|
||||
#define SDIO_MASK_SDIOITIE (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */
|
||||
#define SDIO_MASK_CEATAENDIE (1 << 23) /* Bit 23: CE-ATA command completion interrupt enable */
|
||||
|
||||
#define SDIO_MASK_RESET (0)
|
||||
|
||||
#define SDIO_FIFOCNT_SHIFT (0)
|
||||
#define SDIO_FIFOCNT_MASK (0x01ffffff << SDIO_FIFOCNT_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SDMMC_H */
|
||||
|
||||
224
arch/arm/src/stm32f7/chip/stm32f74xx77xx_sdmmc.h
Normal file
224
arch/arm/src/stm32f7/chip/stm32f74xx77xx_sdmmc.h
Normal file
@ -0,0 +1,224 @@
|
||||
/* arch/arm/src/stm32f7/chip/stm32f74xx77xx_sdmmc.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011-2016 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SDMMC_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SDMMC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_SDMMC_POWER_OFFSET 0x0000 /* SDMMC power control register */
|
||||
#define STM32_SDMMC_CLKCR_OFFSET 0x0004 /* SDMMC clock control register */
|
||||
#define STM32_SDMMC_ARG_OFFSET 0x0008 /* SDMMC argument register */
|
||||
#define STM32_SDMMC_CMD_OFFSET 0x000c /* SDMMC command register */
|
||||
#define STM32_SDMMC_RESPCMD_OFFSET 0x0010 /* SDMMC command response register */
|
||||
#define STM32_SDMMC_RESP_OFFSET(n) (0x0010+4*(n))
|
||||
#define STM32_SDMMC_RESP1_OFFSET 0x0014 /* SDMMC response 1 register */
|
||||
#define STM32_SDMMC_RESP2_OFFSET 0x0018 /* SDMMC response 2 register */
|
||||
#define STM32_SDMMC_RESP3_OFFSET 0x001c /* SDMMC response 3 register */
|
||||
#define STM32_SDMMC_RESP4_OFFSET 0x0020 /* SDMMC response 4 register */
|
||||
#define STM32_SDMMC_DTIMER_OFFSET 0x0024 /* SDMMC data timer register */
|
||||
#define STM32_SDMMC_DLEN_OFFSET 0x0028 /* SDMMC data length register */
|
||||
#define STM32_SDMMC_DCTRL_OFFSET 0x002c /* SDMMC data control register */
|
||||
#define STM32_SDMMC_DCOUNT_OFFSET 0x0030 /* SDMMC data counter register */
|
||||
#define STM32_SDMMC_STA_OFFSET 0x0034 /* SDMMC status register */
|
||||
#define STM32_SDMMC_ICR_OFFSET 0x0038 /* SDMMC interrupt clear register */
|
||||
#define STM32_SDMMC_MASK_OFFSET 0x003c /* SDMMC mask register */
|
||||
#define STM32_SDMMC_FIFOCNT_OFFSET 0x0048 /* SDMMC FIFO counter register */
|
||||
#define STM32_SDMMC_FIFO_OFFSET 0x0080 /* SDMMC data FIFO register */
|
||||
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
#define STM32_SDMMC_POWER_PWRCTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */
|
||||
#define STM32_SDMMC_POWER_PWRCTRL_MASK (3 << STM32_SDMMC_POWER_PWRCTRL_SHIFT)
|
||||
# define STM32_SDMMC_POWER_PWRCTRL_OFF (0 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 00: Power-off: card clock stopped */
|
||||
# define STM32_SDMMC_POWER_PWRCTRL_PWRUP (2 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */
|
||||
# define STM32_SDMMC_POWER_PWRCTRL_ON (3 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */
|
||||
|
||||
#define STM32_SDMMC_POWER_RESET (0) /* Reset value */
|
||||
|
||||
#define STM32_SDMMC_CLKCR_CLKDIV_SHIFT (0) /* Bits 7-0: Clock divide factor */
|
||||
#define STM32_SDMMC_CLKCR_CLKDIV_MASK (0xff << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#define STM32_SDMMC_CLKCR_CLKEN (1 << 8) /* Bit 8: Clock enable bit */
|
||||
#define STM32_SDMMC_CLKCR_PWRSAV (1 << 9) /* Bit 9: Power saving configuration bit */
|
||||
#define STM32_SDMMC_CLKCR_BYPASS (1 << 10) /* Bit 10: Clock divider bypass enable bit */
|
||||
#define STM32_SDMMC_CLKCR_WIDBUS_SHIFT (11) /* Bits 12-11: Wide bus mode enable bits */
|
||||
#define STM32_SDMMC_CLKCR_WIDBUS_MASK (3 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT)
|
||||
# define STM32_SDMMC_CLKCR_WIDBUS_D1 (0 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 00: Default (STM32_SDMMC_D0) */
|
||||
# define STM32_SDMMC_CLKCR_WIDBUS_D4 (1 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (STM32_SDMMC_D[3:0]) */
|
||||
# define STM32_SDMMC_CLKCR_WIDBUS_D8 (2 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (STM32_SDMMC_D[7:0]) */
|
||||
#define STM32_SDMMC_CLKCR_NEGEDGE (1 << 13) /* Bit 13: STM32_SDMMC_CK dephasing selection bit */
|
||||
#define STM32_SDMMC_CLKCR_HWFC_EN (1 << 14) /* Bit 14: HW Flow Control enable */
|
||||
|
||||
#define STM32_SDMMC_CLKCR_RESET (0) /* Reset value */
|
||||
|
||||
#define STM32_SDMMC_ARG_RESET (0) /* Reset value */
|
||||
|
||||
#define STM32_SDMMC_CMD_CMDINDEX_SHIFT (0)
|
||||
#define STM32_SDMMC_CMD_CMDINDEX_MASK (0x3f << STM32_SDMMC_CMD_CMDINDEX_SHIFT)
|
||||
#define STM32_SDMMC_CMD_WAITRESP_SHIFT (6) /* Bits 7-6: Wait for response bits */
|
||||
#define STM32_SDMMC_CMD_WAITRESP_MASK (3 << STM32_SDMMC_CMD_WAITRESP_SHIFT)
|
||||
# define STM32_SDMMC_CMD_NORESPONSE (0 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 00/10: No response */
|
||||
# define STM32_SDMMC_CMD_SHORTRESPONSE (1 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 01: Short response */
|
||||
# define STM32_SDMMC_CMD_LONGRESPONSE (3 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 11: Long response */
|
||||
#define STM32_SDMMC_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */
|
||||
#define STM32_SDMMC_CMD_WAITPEND (1 << 9) /* Bit 9: CPSM Waits for ends of data transfer */
|
||||
#define STM32_SDMMC_CMD_CPSMEN (1 << 10) /* Bit 10: Command path state machine enable */
|
||||
#define STM32_SDMMC_CMD_SUSPEND (1 << 11) /* Bit 11: SD I/O suspend command */
|
||||
#define STM32_SDMMC_CMD_ENDCMD (1 << 12) /* Bit 12: Enable CMD completion */
|
||||
#define STM32_SDMMC_CMD_NIEN (1 << 13) /* Bit 13: not Interrupt Enable */
|
||||
#define STM32_SDMMC_CMD_ATACMD (1 << 14) /* Bit 14: CE-ATA command */
|
||||
|
||||
#define STM32_SDMMC_CMD_RESET (0) /* Reset value */
|
||||
|
||||
#define STM32_SDMMC_RESPCMD_SHIFT (0)
|
||||
#define STM32_SDMMC_RESPCMD_MASK (0x3f << STM32_SDMMC_RESPCMD_SHIFT)
|
||||
|
||||
#define STM32_SDMMC_DTIMER_RESET (0) /* Reset value */
|
||||
|
||||
#define STM32_SDMMC_DLEN_SHIFT (0)
|
||||
#define STM32_SDMMC_DLEN_MASK (0x01ffffff << STM32_SDMMC_DLEN_SHIFT)
|
||||
|
||||
#define STM32_SDMMC_DLEN_RESET (0) /* Reset value */
|
||||
|
||||
#define STM32_SDMMC_DCTRL_DTEN (1 << 0) /* Bit 0: Data transfer enabled bit */
|
||||
#define STM32_SDMMC_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */
|
||||
#define STM32_SDMMC_DCTRL_DTMODE (1 << 2) /* Bit 2: Data transfer mode */
|
||||
#define STM32_SDMMC_DCTRL_DMAEN (1 << 3) /* Bit 3: DMA enable bit */
|
||||
#define STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 7-4: Data block size */
|
||||
#define STM32_SDMMC_DCTRL_DBLOCKSIZE_MASK (15 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define STM32_SDMMC_DCTRL_1BYTE (0 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define STM32_SDMMC_DCTRL_2BYTES (1 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define STM32_SDMMC_DCTRL_4BYTES (2 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define STM32_SDMMC_DCTRL_8BYTES (3 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define STM32_SDMMC_DCTRL_16BYTES (4 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define STM32_SDMMC_DCTRL_32BYTES (5 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define STM32_SDMMC_DCTRL_64BYTES (6 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define STM32_SDMMC_DCTRL_128BYTES (7 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define STM32_SDMMC_DCTRL_256BYTES (8 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define STM32_SDMMC_DCTRL_512BYTES (9 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define STM32_SDMMC_DCTRL_1KBYTE (10 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define STM32_SDMMC_DCTRL_2KBYTES (11 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define STM32_SDMMC_DCTRL_4KBYTES (12 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define STM32_SDMMC_DCTRL_8KBYTES (13 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define STM32_SDMMC_DCTRL_16KBYTES (14 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
#define STM32_SDMMC_DCTRL_RWSTART (1 << 8) /* Bit 8: Read wait start */
|
||||
#define STM32_SDMMC_DCTRL_RWSTOP (1 << 9) /* Bit 9: Read wait stop */
|
||||
#define STM32_SDMMC_DCTRL_RWMOD (1 << 10) /* Bit 10: Read wait mode */
|
||||
#define STM32_SDMMC_DCTRL_SDIOEN (1 << 11) /* Bit 11: SD I/O enable functions */
|
||||
|
||||
#define STM32_SDMMC_DCTRL_RESET (0) /* Reset value */
|
||||
|
||||
#define STM32_SDMMC_DCOUNT_SHIFT (0)
|
||||
#define STM32_SDMMC_DCOUNT_MASK (0x01ffffff << STM32_SDMMC_DCOUNT_SHIFT)
|
||||
|
||||
#define STM32_SDMMC_STA_CCRCFAIL (1 << 0) /* Bit 0: Command response CRC fail */
|
||||
#define STM32_SDMMC_STA_DCRCFAIL (1 << 1) /* Bit 1: Data block CRC fail */
|
||||
#define STM32_SDMMC_STA_CTIMEOUT (1 << 2) /* Bit 2: Command response timeout */
|
||||
#define STM32_SDMMC_STA_DTIMEOUT (1 << 3) /* Bit 3: Data timeout */
|
||||
#define STM32_SDMMC_STA_TXUNDERR (1 << 4) /* Bit 4: Transmit FIFO underrun error */
|
||||
#define STM32_SDMMC_STA_RXOVERR (1 << 5) /* Bit 5: Received FIFO overrun error */
|
||||
#define STM32_SDMMC_STA_CMDREND (1 << 6) /* Bit 6: Command response received */
|
||||
#define STM32_SDMMC_STA_CMDSENT (1 << 7) /* Bit 7: Command sent */
|
||||
#define STM32_SDMMC_STA_DATAEND (1 << 8) /* Bit 8: Data end */
|
||||
#define STM32_SDMMC_STA_STBITERR (1 << 9) /* Bit 9: Start bit not detected */
|
||||
#define STM32_SDMMC_STA_DBCKEND (1 << 10) /* Bit 10: Data block sent/received */
|
||||
#define STM32_SDMMC_STA_CMDACT (1 << 11) /* Bit 11: Command transfer in progress */
|
||||
#define STM32_SDMMC_STA_TXACT (1 << 12) /* Bit 12: Data transmit in progress */
|
||||
#define STM32_SDMMC_STA_RXACT (1 << 13) /* Bit 13: Data receive in progress */
|
||||
#define STM32_SDMMC_STA_TXFIFOHE (1 << 14) /* Bit 14: Transmit FIFO half empty */
|
||||
#define STM32_SDMMC_STA_RXFIFOHF (1 << 15) /* Bit 15: Receive FIFO half full */
|
||||
#define STM32_SDMMC_STA_TXFIFOF (1 << 16) /* Bit 16: Transmit FIFO full */
|
||||
#define STM32_SDMMC_STA_RXFIFOF (1 << 17) /* Bit 17: Receive FIFO full */
|
||||
#define STM32_SDMMC_STA_TXFIFOE (1 << 18) /* Bit 18: Transmit FIFO empty */
|
||||
#define STM32_SDMMC_STA_RXFIFOE (1 << 19) /* Bit 19: Receive FIFO empty */
|
||||
#define STM32_SDMMC_STA_TXDAVL (1 << 20) /* Bit 20: Data available in transmit FIFO */
|
||||
#define STM32_SDMMC_STA_RXDAVL (1 << 21) /* Bit 21: Data available in receive FIFO */
|
||||
#define STM32_SDMMC_STA_SDIOIT (1 << 22) /* Bit 22: SDIO interrupt received */
|
||||
#define STM32_SDMMC_STA_CEATAEND (1 << 23) /* Bit 23: CMD6 CE-ATA command completion */
|
||||
|
||||
#define STM32_SDMMC_ICR_CCRCFAILC (1 << 0) /* Bit 0: CCRCFAIL flag clear bit */
|
||||
#define STM32_SDMMC_ICR_DCRCFAILC (1 << 1) /* Bit 1: DCRCFAIL flag clear bit */
|
||||
#define STM32_SDMMC_ICR_CTIMEOUTC (1 << 2) /* Bit 2: CTIMEOUT flag clear bit */
|
||||
#define STM32_SDMMC_ICR_DTIMEOUTC (1 << 3) /* Bit 3: DTIMEOUT flag clear bit */
|
||||
#define STM32_SDMMC_ICR_TXUNDERRC (1 << 4) /* Bit 4: TXUNDERR flag clear bit */
|
||||
#define STM32_SDMMC_ICR_RXOVERRC (1 << 5) /* Bit 5: RXOVERR flag clear bit */
|
||||
#define STM32_SDMMC_ICR_CMDRENDC (1 << 6) /* Bit 6: CMDREND flag clear bit */
|
||||
#define STM32_SDMMC_ICR_CMDSENTC (1 << 7) /* Bit 7: CMDSENT flag clear bit */
|
||||
#define STM32_SDMMC_ICR_DATAENDC (1 << 8) /* Bit 8: DATAEND flag clear bit */
|
||||
#define STM32_SDMMC_ICR_STBITERRC (1 << 9) /* Bit 9: STBITERR flag clear bit */
|
||||
#define STM32_SDMMC_ICR_DBCKENDC (1 << 10) /* Bit 10: DBCKEND flag clear bit */
|
||||
#define STM32_SDMMC_ICR_SDIOITC (1 << 22) /* Bit 22: SDIOIT flag clear bit */
|
||||
#define STM32_SDMMC_ICR_CEATAENDC (1 << 23) /* Bit 23: CEATAEND flag clear bit */
|
||||
|
||||
#define STM32_SDMMC_ICR_RESET 0x00c007ff
|
||||
#define STM32_SDMMC_ICR_STATICFLAGS 0x000005ff
|
||||
|
||||
#define STM32_SDMMC_MASK_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */
|
||||
#define STM32_SDMMC_MASK_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */
|
||||
#define STM32_SDMMC_MASK_CTIMEOUTIE (1 << 2) /* Bit 2: Command timeout interrupt enable */
|
||||
#define STM32_SDMMC_MASK_DTIMEOUTIE (1 << 3) /* Bit 3: Data timeout interrupt enable */
|
||||
#define STM32_SDMMC_MASK_TXUNDERRIE (1 << 4) /* Bit 4: Tx FIFO underrun error interrupt enable */
|
||||
#define STM32_SDMMC_MASK_RXOVERRIE (1 << 5) /* Bit 5: Rx FIFO overrun error interrupt enable */
|
||||
#define STM32_SDMMC_MASK_CMDRENDIE (1 << 6) /* Bit 6: Command response received interrupt enable */
|
||||
#define STM32_SDMMC_MASK_CMDSENTIE (1 << 7) /* Bit 7: Command sent interrupt enable */
|
||||
#define STM32_SDMMC_MASK_DATAENDIE (1 << 8) /* Bit 8: Data end interrupt enable */
|
||||
#define STM32_SDMMC_MASK_STBITERRIE (1 << 9) /* Bit 9: Start bit error interrupt enable */
|
||||
#define STM32_SDMMC_MASK_DBCKENDIE (1 << 10) /* Bit 10: Data block end interrupt enable */
|
||||
#define STM32_SDMMC_MASK_CMDACTIE (1 << 11) /* Bit 11: Command acting interrupt enable */
|
||||
#define STM32_SDMMC_MASK_TXACTIE (1 << 12) /* Bit 12: Data transmit acting interrupt enable */
|
||||
#define STM32_SDMMC_MASK_RXACTIE (1 << 13) /* Bit 13: Data receive acting interrupt enable */
|
||||
#define STM32_SDMMC_MASK_TXFIFOHEIE (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */
|
||||
#define STM32_SDMMC_MASK_RXFIFOHFIE (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */
|
||||
#define STM32_SDMMC_MASK_TXFIFOFIE (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */
|
||||
#define STM32_SDMMC_MASK_RXFIFOFIE (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */
|
||||
#define STM32_SDMMC_MASK_TXFIFOEIE (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */
|
||||
#define STM32_SDMMC_MASK_RXFIFOEIE (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */
|
||||
#define STM32_SDMMC_MASK_TXDAVLIE (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */
|
||||
#define STM32_SDMMC_MASK_RXDAVLIE (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */
|
||||
#define STM32_SDMMC_MASK_SDIOITIE (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */
|
||||
#define STM32_SDMMC_MASK_CEATAENDIE (1 << 23) /* Bit 23: CE-ATA command completion interrupt enable */
|
||||
|
||||
#define STM32_SDMMC_MASK_RESET (0)
|
||||
|
||||
#define STM32_SDMMC_FIFOCNT_SHIFT (0)
|
||||
#define STM32_SDMMC_FIFOCNT_MASK (0x0ffffff << STM32_SDMMC_FIFOCNT_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SDMMC_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -40,13 +40,13 @@
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include "chip/stm32_sdmmc.h"
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <sys/types.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/stm32_sdmmc.h"
|
||||
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
|
||||
Loading…
Reference in New Issue
Block a user