From ae005eb968b9d169f3e768e5c26eed43652e75eb Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Sun, 11 Oct 2009 19:52:20 +0000
Subject: [PATCH] Basic USART setup works

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2126 42af7a65-404d-4744-a932-0658087f49c3
---
 arch/arm/src/stm32/stm32_flash.h       |  99 +++++++++++++++++++++++++
 arch/arm/src/stm32/stm32_internal.h    |   2 +-
 arch/arm/src/stm32/stm32_lowputc.c     |  20 ++---
 arch/arm/src/stm32/stm32_memorymap.h   |  11 +--
 arch/arm/src/stm32/stm32_rcc.c         |  10 ++-
 arch/arm/src/stm32/stm32_serial.c      |  39 ++++------
 configs/stm3210e-eval/README.txt       |   3 +
 configs/stm3210e-eval/RIDE/nuttx.ctx   |  27 +++++--
 configs/stm3210e-eval/RIDE/nuttx.rapp  |  62 ++++++++++++----
 configs/stm3210e-eval/RIDE/nuttx.rdb   | Bin 114688 -> 116736 bytes
 configs/stm3210e-eval/ostest/Make.defs |   2 +-
 configs/stm3210e-eval/ostest/defconfig |   2 +-
 12 files changed, 210 insertions(+), 67 deletions(-)
 create mode 100755 arch/arm/src/stm32/stm32_flash.h

diff --git a/arch/arm/src/stm32/stm32_flash.h b/arch/arm/src/stm32/stm32_flash.h
new file mode 100755
index 0000000000..8b22ae90b8
--- /dev/null
+++ b/arch/arm/src/stm32/stm32_flash.h
@@ -0,0 +1,99 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_flash.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_FLASH_H
+#define __ARCH_ARM_SRC_STM32_STM32_FLASH_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+#include "stm32_memorymap.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_FLASH_ACR_OFFSET     0x0000
+#define STM32_FLASH_KEYR_OFFSET    0x0004
+#define STM32_FLASH_OPTKEYR_OFFSET 0x0008
+#define STM32_FLASH_SR_OFFSET      0x000c
+#define STM32_FLASH_CR_OFFSET      0x0010
+#define STM32_FLASH_AR_OFFSET      0x0014
+#define STM32_FLASH_OBR_OFFSET     0x001c
+#define STM32_FLASH_WRPR_OFFSET    0x0020
+
+/* Register Addresses ***************************************************************/
+
+#define STM32_FLASH_ACR            (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET)
+#define STM32_FLASH_KEYR           (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET)
+#define STM32_FLASH_OPTKEYR        (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET)
+#define STM32_FLASH_SR             (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
+#define STM32_FLASH_CR             (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)
+#define STM32_FLASH_AR             (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET)
+#define STM32_FLASH_OBR            (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET)
+#define STM32_FLASH_WRPR           (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+/* TODO: FLASH details from the STM32F10xxx Flash programming manual. */
+
+/* Flash Access Control Register (ACR) */
+
+#define ACR_LATENCY_SHIFT          (0)
+#define ACR_LATENCY_MASK           (7 << ACR_LATENCY_SHIFT)
+#  define ACR_LATENCY_0            (0 << ACR_LATENCY_SHIFT)  /* FLASH Zero Latency cycle */
+#  define ACR_LATENCY_1            (1 << ACR_LATENCY_SHIFT)) /* FLASH One Latency cycle */
+#  define ACR_LATENCY_2            (2 << ACR_LATENCY_SHIFT)  /* FLASH Two Latency cycles */
+#define ACR_HLFCYA                 (1 << 3)                  /* FLASH half cycle access */
+#define ACR_PRTFBE                 (1 << 4)                  /* FLASH prefetch enable */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_FLASH_H */
diff --git a/arch/arm/src/stm32/stm32_internal.h b/arch/arm/src/stm32/stm32_internal.h
index 0b4dbdb84c..ba0011dd54 100755
--- a/arch/arm/src/stm32/stm32_internal.h
+++ b/arch/arm/src/stm32/stm32_internal.h
@@ -72,7 +72,7 @@
 #define GPIO_ALT                      (0)
 
 /* These bits set the primary function of the pin:
- * .... .... .... .... FFF. .... .... ....
+ * .... .... .... .... .FF. .... .... ....
  */
 
 #define GPIO_CNF_SHIFT                13                         /* Bits 13-14: GPIO function */
diff --git a/arch/arm/src/stm32/stm32_lowputc.c b/arch/arm/src/stm32/stm32_lowputc.c
index da6cdc138c..692ef679a2 100644
--- a/arch/arm/src/stm32/stm32_lowputc.c
+++ b/arch/arm/src/stm32/stm32_lowputc.c
@@ -220,11 +220,11 @@ void up_lowputc(char ch)
 #ifdef HAVE_CONSOLE
   /* Wait until the TX FIFO is not full */
 
-  while ((getreg16(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) & USART_SR_TXE) != 0);
+  while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) & USART_SR_TXE) == 0);
 
   /* Then send the character */
 
-  putreg16((uint16)ch, STM32_CONSOLE_BASE + STM32_USART_DR_OFFSET);
+  putreg32((uint32)ch, STM32_CONSOLE_BASE + STM32_USART_DR_OFFSET);
 #endif
 }
 
@@ -330,24 +330,24 @@ void stm32_lowsetup(void)
 #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_USART_CONFIG)
   /* Configure CR2 */
 
-  cr  = getreg16(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
+  cr  = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
   cr &= ~USART_CR2_CLRBITS;
   cr |= USART_CR2_SETBITS;
-  putreg16(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
+  putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
 
   /* Configure CR1 */
 
-  cr  = getreg16(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
+  cr  = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
   cr &= ~USART_CR1_CLRBITS;
   cr |= USART_CR1_SETBITS;
-  putreg16(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
+  putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
 
   /* Configure CR3 */
 
-  cr  = getreg16(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
+  cr  = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
   cr &= ~USART_CR3_CLRBITS;
   cr |= USART_CR3_SETBITS;
-  putreg16(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
+  putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
 
   /* Configure the USART Baud Rate */
 
@@ -355,9 +355,9 @@ void stm32_lowsetup(void)
 
   /* Enable Rx, Tx, and the USART */
 
-  cr  = getreg16(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
+  cr  = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
   cr |= (USART_CR1_UE|USART_CR1_TE|USART_CR1_RE);
-  putreg16(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
+  putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
 #endif
 #endif /* CONFIG_STM32_USART1 || CONFIG_STM32_USART2 || CONFIG_STM32_USART3 */
 }
diff --git a/arch/arm/src/stm32/stm32_memorymap.h b/arch/arm/src/stm32/stm32_memorymap.h
index 0f271e44e0..89cfcafded 100755
--- a/arch/arm/src/stm32/stm32_memorymap.h
+++ b/arch/arm/src/stm32/stm32_memorymap.h
@@ -122,11 +122,12 @@
                                            /* 0x40023400 - 0x40027fff: Reserved */
 #define STM32_ETHERNET_BASE 0x40028000     /* 0x40028000 - 0x40029fff: Ethernet */
                                            /* 0x40030000 - 0x4fffffff: Reserved */
-
-/* Other registers */
-
-#define STM32_NVIC_BASE     0xe000e000     /* 0xe000e00-0xe000efff: Nested Vectored Interrupt Controller */
-#define STM32_DEBUGMCU_BASE 0xe0042000
+
+/* Other registers */
+
+#define STM32_SCS_BASE      0xe000e000
+#define STM32_NVIC_BASE     0xe000e000     /* 0xe000e00-0xe000efff: Nested Vectored Interrupt Controller */
+#define STM32_DEBUGMCU_BASE 0xe0042000
 
 /************************************************************************************
  * Public Types
diff --git a/arch/arm/src/stm32/stm32_rcc.c b/arch/arm/src/stm32/stm32_rcc.c
index 3678f8ca15..10ed409122 100755
--- a/arch/arm/src/stm32/stm32_rcc.c
+++ b/arch/arm/src/stm32/stm32_rcc.c
@@ -48,6 +48,7 @@
 
 #include "chip.h"
 #include "stm32_rcc.h"
+#include "stm32_flash.h"
 #include "stm32_internal.h"
 
 /****************************************************************************
@@ -356,11 +357,12 @@ void stm32_clockconfig(void)
 
   if( timeout > 0)
     {
-#if 0
-      /* Enable Prefetch Buffer */
+    /* Enable FLASH prefetch buffer and 2 wait states */
 
-      /* Flash 2 wait state */
-#endif
+    regval  = getreg32(STM32_FLASH_ACR);
+    regval &= ~ACR_LATENCY_MASK;
+    regval |= (ACR_LATENCY_2|ACR_PRTFBE);
+    putreg32(regval, STM32_FLASH_ACR);
 
     /* Set the HCLK source/divider */
  
diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c
index e56a8e7d0b..c2518707e1 100644
--- a/arch/arm/src/stm32/stm32_serial.c
+++ b/arch/arm/src/stm32/stm32_serial.c
@@ -325,29 +325,20 @@ static uart_dev_t g_usart3port =
  * Name: up_serialin
  ****************************************************************************/
 
-static inline uint16 up_serialin(struct up_dev_s *priv, int offset)
+static inline uint32 up_serialin(struct up_dev_s *priv, int offset)
 {
-  return getreg16(priv->usartbase + offset);
+  return getreg32(priv->usartbase + offset);
 }
 
 /****************************************************************************
  * Name: up_serialout
  ****************************************************************************/
 
-static inline void up_serialout(struct up_dev_s *priv, int offset, uint16 value)
+static inline void up_serialout(struct up_dev_s *priv, int offset, uint32 value)
 {
   putreg16(value, priv->usartbase + offset);
 }
 
-/****************************************************************************
- * Name: up_serialout32
- ****************************************************************************/
-
-static inline void up_serialout32(struct up_dev_s *priv, int offset, uint32 value)
-{
-  putreg32(value, priv->usartbase + offset);
-}
-
 /****************************************************************************
  * Name: up_disableusartint
  ****************************************************************************/
@@ -356,8 +347,8 @@ static inline void up_disableusartint(struct up_dev_s *priv, uint16 *ie)
 {
   if (ie)
     {
-      uint16 cr1;
-      uint16 cr3;
+      uint32 cr1;
+      uint32 cr3;
 
       /* USART interrupts:
        *
@@ -399,7 +390,7 @@ static inline void up_disableusartint(struct up_dev_s *priv, uint16 *ie)
 
 static inline void up_restoreusartint(struct up_dev_s *priv, uint16 ie)
 {
-  uint16 cr;
+  uint32 cr;
 
   /* Save the interrupt mask */
 
@@ -435,7 +426,7 @@ static int up_setup(struct uart_dev_s *dev)
   uint32 mantissa;
   uint32 fraction;
   uint32 brr;
-  uint16 regval;
+  uint32 regval;
 
   /* Note: The logic here depends on the fact that that the USART module
    * was enabled and the pins were configured in stm32_lowsetup().
@@ -458,13 +449,13 @@ static int up_setup(struct uart_dev_s *dev)
 
   /* Configure CR1 */
   /* Clear M, PCE, PS, TE, REm and all interrupt enable bits */
-
+
   regval  = up_serialin(priv, STM32_USART_CR1_OFFSET);
   regval &= ~(USART_CR1_M|USART_CR1_PCE|USART_CR1_PS|USART_CR1_TE|
               USART_CR1_RE|USART_CR1_ALLINTS);
 
   /* Configure word length and parity mode */
-
+
   if (priv->bits == 9)				/* Default: 1 start, 8 data, n stop */
     {
       regval |= USART_CR1_M;			/* 1 start, 9 data, n stop */
@@ -481,7 +472,7 @@ static int up_setup(struct uart_dev_s *dev)
   up_serialout(priv, STM32_USART_CR1_OFFSET, regval);
 
   /* Configure CR3 */
-  /* Clear CTSE, RTSE, and all interrupt enable bits */
+  /* Clear CTSE, RTSE, and all interrupt enable bits */
 
   regval  = up_serialin(priv, STM32_USART_CR3_OFFSET);
   regval &= ~(USART_CR3_CTSIE|USART_CR3_CTSE|USART_CR3_RTSE|USART_CR3_EIE);
@@ -517,7 +508,7 @@ static int up_setup(struct uart_dev_s *dev)
 
    fraction   = (usartdiv32 - (mantissa << 5) + 1) >> 1;
    brr       |= fraction << USART_BRR_FRAC_SHIFT;
-   up_serialout32(priv, STM32_USART1_BRR, brr);
+   up_serialout(priv, STM32_USART1_BRR, brr);
 
   /* Enable Rx, Tx, and the USART */
 
@@ -544,7 +535,7 @@ static int up_setup(struct uart_dev_s *dev)
 static void up_shutdown(struct uart_dev_s *dev)
 {
   struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  uint16 regval;
+  uint32 regval;
 
   /* Disable all interrupts */
 
@@ -786,7 +777,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
 static int up_receive(struct uart_dev_s *dev, uint32 *status)
 {
   struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  uint16 dr;
+  uint32 dr;
 
   /* Get the Rx byte */
 
@@ -794,7 +785,7 @@ static int up_receive(struct uart_dev_s *dev, uint32 *status)
 
   /* Get the Rx byte plux error information.  Return those in status */
 
-  *status  = (uint32)priv->sr << 16 | dr;
+  *status  = priv->sr << 16 | dr;
   priv->sr = 0;
 
   /* Then return the actual received byte */
@@ -880,7 +871,7 @@ static boolean up_rxavailable(struct uart_dev_s *dev)
 static void up_send(struct uart_dev_s *dev, int ch)
 {
   struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  up_serialout(priv, STM32_USART_DR_OFFSET, (uint16)ch);
+  up_serialout(priv, STM32_USART_DR_OFFSET, (uint32)ch);
 }
 
 /****************************************************************************
diff --git a/configs/stm3210e-eval/README.txt b/configs/stm3210e-eval/README.txt
index 37a2c21489..b36d4f20b5 100755
--- a/configs/stm3210e-eval/README.txt
+++ b/configs/stm3210e-eval/README.txt
@@ -346,4 +346,7 @@ Where <subdir> is one of the following:
     This configuration directory, performs a simple OS test using
     examples/ostest.
 
+  RIDE
+    This configuration builds a trivial bring-up binary.  It is
+    useful only because it words with the RIDE7 IDE and R-Link debugger.
 
diff --git a/configs/stm3210e-eval/RIDE/nuttx.ctx b/configs/stm3210e-eval/RIDE/nuttx.ctx
index 8dad95fea2..eaa41d318a 100755
--- a/configs/stm3210e-eval/RIDE/nuttx.ctx
+++ b/configs/stm3210e-eval/RIDE/nuttx.ctx
@@ -1,11 +1,11 @@
 
 <Debug>
-	<Views/>
+	<FindStrings/>
+	<ReplaceStrings/>
 	<nuttx>
-		<MemoryView Focus="4294967294" TopRow="0" NbPerLine="8" />
-		<MemoryView Focus="4294967294" TopRow="0" NbPerLine="8" />
-		<CodeView Focus="4294967294" TopRow="0" NbPerLine="8" />
-		<CodeView Focus="4294967294" TopRow="0" NbPerLine="8" />
+		<CodeView TopRow="134220190" Focus="4294967295" />
+		<CodeView TopRow="134220190" Focus="4294967295" />
+						
 	</nuttx>
 	<Flags>
 		<Report>
@@ -18,8 +18,23 @@
 				<Col Type="PT_STRING" Header="Condition" sizeCache="DDDDDDDDDDDDDDDDDDDDDDDD" AutoSize="1" Edit="0" Sortable="0" />
 				<Col Type="PT_STRING" Header="Line" sizeCache="DDDDDD" AutoSize="1" Edit="0" Sortable="1" Visible="1" />
 				<Col Type="PT_STRING" Header="Path" sizeCache="DDDDDDDDDDDDDDDDDDDD" AutoSize="1" Edit="0" Sortable="1" Visible="1" />
+							
 			</Def>
-			<Rows/>
+			<Rows>
+				<Row Check="True" Kind="Breakpoint" KindID="0" Space="code" SpaceID="0" Condition="" Line="L:148" Path="C:\cygwin\home\Owner\projects\nuttx\nuttx\arch\arm\src\stm32\stm32_start.c" />
+							
+			</Rows>
+					
+		</Report>
+			
+	</Flags>
+	<Views/>
+</Debug>AutoSize="1" Edit="0" Sortable="1" Visible="1" />
+				<Col Type="PT_STRING" Header="Path" sizeCache="DDDDDDDDDDDDDDDDDDDD" AutoSize="1" Edit="0" Sortable="1" Visible="1" />
+			</Def>
+			<Rows>
+				<Row Check="True" Kind="Breakpoint" KindID="0" Space="code" SpaceID="0" Condition="" Line="L:148" Path="C:\cygwin\home\Owner\projects\nuttx\nuttx\arch\arm\src\stm32\stm32_start.c" />
+			</Rows>
 		</Report>
 	</Flags>
 </Debug>
\ No newline at end of file
diff --git a/configs/stm3210e-eval/RIDE/nuttx.rapp b/configs/stm3210e-eval/RIDE/nuttx.rapp
index d4fdfd6d45..3a57d815d1 100755
--- a/configs/stm3210e-eval/RIDE/nuttx.rapp
+++ b/configs/stm3210e-eval/RIDE/nuttx.rapp
@@ -1,47 +1,79 @@
 
 <ApplicationBuild Header="nuttx" Extern=".\nuttx.rapp" Path=".\nuttx.rapp" OutputFile=".\nuttx.elf" sate="98" >
-	<NodeC Path="..\..\..\arch\arm\src\stm32\stm32_timerisr.c" Header="stm32_timerisr.c" Marker="-1" OutputFile=".\stm32_timerisr.o" sate="0" />
 	<NodeC Path="..\..\..\arch\arm\src\stm32\stm32_gpio.c" Header="stm32_gpio.c" Marker="-1" OutputFile=".\stm32_gpio.o" sate="0" />
 	<NodeC Path="..\..\..\arch\arm\src\stm32\stm32_irq.c" Header="stm32_irq.c" Marker="-1" OutputFile=".\stm32_irq.o" sate="0" />
 	<NodeC Path="..\..\..\arch\arm\src\stm32\stm32_lowputc.c" Header="stm32_lowputc.c" Marker="-1" OutputFile=".\stm32_lowputc.o" sate="0" />
 	<NodeC Path="..\..\..\arch\arm\src\stm32\stm32_rcc.c" Header="stm32_rcc.c" Marker="-1" OutputFile=".\stm32_rcc.o" sate="0" />
 	<NodeC Path="..\..\..\arch\arm\src\stm32\stm32_serial.c" Header="stm32_serial.c" Marker="-1" OutputFile=".\stm32_serial.o" sate="0" />
 	<NodeC Path="..\..\..\arch\arm\src\stm32\stm32_start.c" Header="stm32_start.c" Marker="-1" OutputFile=".\stm32_start.o" sate="0" />
+	<NodeC Path=".\bigfatstub.c" Header="bigfatstub.c" Marker="-1" OutputFile=".\bigfatstub.o" sate="0" />
+	<NodeC Path="..\..\..\arch\arm\src\cortexm3\up_svcall.c" Header="up_svcall.c" Marker="-1" OutputFile=".\up_svcall.o" sate="0" />
+	<NodeC Path="..\..\..\arch\arm\src\cortexm3\up_hardfault.c" Header="up_hardfault.c" Marker="-1" OutputFile=".\up_hardfault.o" sate="0" />
+	<NodeC Path="..\src\up_leds.c" Header="up_leds.c" Marker="-1" OutputFile=".\up_leds.o" sate="0" />
+	<NodeC Path="..\src\up_boot.c" Header="up_boot.c" Marker="-1" OutputFile=".\up_boot.o" sate="0" />
+	<NodeC Path="..\..\..\sched\irq_unexpectedisr.c" Header="irq_unexpectedisr.c" Marker="-1" OutputFile=".\irq_unexpectedisr.o" sate="0" />
+	<NodeC Path="..\..\..\lib\lib_memcpy.c" Header="lib_memcpy.c" Marker="-1" OutputFile=".\lib_memcpy.o" sate="0" />
 	<Options>
 		<Config Header="Standard" >
 			<Set Header="ApplicationBuild" >
 				<Section Header="General" >
 					<Property Header="TargetFamily" Value="ARM" />
-																									
+																																		
 				</Section>
 				<Section Header="Directories" >
 					<Property Header="IncDir" Value=".;C:\cygwin\home\Owner\projects\nuttx\nuttx\arch\arm\src\common;C:\cygwin\home\Owner\projects\nuttx\nuttx\arch\arm\src\cortexm3;C:\cygwin\home\Owner\projects\nuttx\nuttx\arch\arm\src\stm32;C:\cygwin\home\Owner\projects\nuttx\nuttx\include;C:\cygwin\home\Owner\projects\nuttx\nuttx\sched" Removable="1" />
-																
-				</Section>
-												
-			</Set>
-			<Set Header="Target" >
-				<Section Header="ProcessorARM" >
-					<Property Header="Processor" Value="STM32F101VET6" />
-																									
-				</Section>
-				<Section Header="ToolSetARM" >
-					<Property Header="BuildToolSetARM" Value="ARM\\GNU.config" Removable="1" />
 																									
 				</Section>
 																			
 			</Set>
+			<Set Header="Target" >
+				<Section Header="ProcessorARM" >
+					<Property Header="Processor" Value="STM32F101VET6" />
+																																		
+				</Section>
+				<Section Header="ToolSetARM" >
+					<Property Header="BuildToolSetARM" Value="ARM\\GNU.config" Removable="1" />
+																																		
+				</Section>
+																										
+			</Set>
 			<Set Header="AS" >
 				<Section Header="Options" >
 					<Property Header="More" Value="-D __ASSEMBLY__" />
-																
+																									
 				</Section>
-												
+																			
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 			<Set Header="LD" >
 				<Section Header="Startup" >
 					<Property Header="DEFAULTSTARTUP" Value="No" Removable="1" />
 					<Property Header="File" Value="C:\cygwin\home\Owner\projects\nuttx\nuttx\arch\arm\src\stm32_vectors.o" Removable="1" />
+																
+				</Section>
+				<Section Header="More" >
+					<Property Header="More" Value="-nostdlib" />
+							
+				</Section>
+				<Section Header="LIB" >
+					<Property Header="STLIB" Value="0" Removable="1" />
+					<Property Header="UART0PUTC" Value="0" Removable="1" />
+					<Property Header="SMALLP" Value="0" Removable="1" />
+							
+				</Section>
+				<Section Header="Scripts" >
+					<Property Header="SCRIPTFILES" Value="No" Removable="1" />
+					<Property Header="File" Value="C:\cygwin\home\Owner\projects\nuttx\nuttx\configs\stm3210e-eval\RIDE\stm32-nuttx.ld" Removable="1" />
+							
+				</Section>
+				<Section Header="Linker" >
+					<Property Header="GC_SECTIONS" Value="" Removable="1" />
+							
+				</Section>
+					
+			</Set>
+			<Set Header="GCC" >
+				<Section Header="More" >
+					<Property Header="More" Value="-nostdinc" />
 							
 				</Section>
 					
diff --git a/configs/stm3210e-eval/RIDE/nuttx.rdb b/configs/stm3210e-eval/RIDE/nuttx.rdb
index bba763865265e628ab0011d8bfc5afad1d643485..5a4c7145cef268e1c65e4d9d59af9191d2d571e2 100755
GIT binary patch
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diff --git a/configs/stm3210e-eval/ostest/Make.defs b/configs/stm3210e-eval/ostest/Make.defs
index 773b3e71ca..2940b86fd0 100644
--- a/configs/stm3210e-eval/ostest/Make.defs
+++ b/configs/stm3210e-eval/ostest/Make.defs
@@ -37,7 +37,7 @@ include ${TOPDIR}/.config
 
 # Setup for the selected toolchain
 
-ifeq ($(CONFIG_STM32_DFU)y)
+ifeq ($(CONFIG_STM32_DFU),y)
   LDSCRIPT		= ld.script.dfu
 else
   LDSCRIPT		= ld.script
diff --git a/configs/stm3210e-eval/ostest/defconfig b/configs/stm3210e-eval/ostest/defconfig
index 7c5afbdf78..f490ea9fc0 100755
--- a/configs/stm3210e-eval/ostest/defconfig
+++ b/configs/stm3210e-eval/ostest/defconfig
@@ -92,7 +92,7 @@ CONFIG_STM32_CODESOURCERY=n
 CONFIG_STM32_DEVKITARM=n
 CONFIG_STM32_RAISONANCE=n
 CONFIG_STM32_BUILDROOT=y
-CONFIG_STM32_DFU=n
+CONFIG_STM32_DFU=y
 
 #
 #  Individual subsystems can be enabled: