More serial logic
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2736 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -55,27 +55,103 @@
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* Private Definitions
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* Private Definitions
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**************************************************************************/
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**************************************************************************/
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/* Select UART parameters for the selected console */
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#if defined(CONFIG_UART0_SERIAL_CONSOLE)
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# define CONSOLE_BASE LPC17_UART0_BASE
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# define CONSOLE_BAUD CONFIG_UART0_BAUD
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# define CONSOLE_BITS CONFIG_UART0_BITS
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# define CONSOLE_PARITY CONFIG_UART0_PARITY
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# define CONSOLE_2STOP CONFIG_UART0_2STOP
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#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
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# define CONSOLE_BASE LPC17_UART1_BASE
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# define CONSOLE_BAUD CONFIG_UART1_BAUD
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# define CONSOLE_BITS CONFIG_UART1_BITS
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# define CONSOLE_PARITY CONFIG_UART1_PARITY
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# define CONSOLE_2STOP CONFIG_UART1_2STOP
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#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
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# define CONSOLE_BASE LPC17_UART2_BASE
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# define CONSOLE_BAUD CONFIG_UART2_BAUD
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# define CONSOLE_BITS CONFIG_UART2_BITS
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# define CONSOLE_PARITY CONFIG_UART2_PARITY
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# define CONSOLE_2STOP CONFIG_UART2_2STOP
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#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
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# define CONSOLE_BASE LPC17_UART3_BASE
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# define CONSOLE_BAUD CONFIG_UART3_BAUD
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# define CONSOLE_BITS CONFIG_UART3_BITS
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# define CONSOLE_PARITY CONFIG_UART3_PARITY
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# define CONSOLE_2STOP CONFIG_UART3_2STOP
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#else
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# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
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#endif
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/* Get word length setting for the console */
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#if CONSOLE_BITS == 5
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# define CONSOLE_LCR_WLS UART_LCR_WLS_5BIT
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#elif CONSOLE_BITS == 6
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# define CONSOLE_LCR_WLS UART_LCR_WLS_6BIT
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#elif CONSOLE_BITS == 7
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# define CONSOLE_LCR_WLS UART_LCR_WLS_7BIT
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#elif CONSOLE_BITS == 8
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# define CONSOLE_LCR_WLS UART_LCR_WLS_8BIT
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#else
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# error "Invalid CONFIG_UARTn_BITS setting for console "
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#endif
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/* Get parity setting for the console */
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#if CONSOLE_PARITY == 0
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# define CONSOLE_LCR_PAR 0
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#elif CONSOLE_PARITY == 1
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# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_ODD)
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#elif CONSOLE_PARITY == 2
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# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_EVEN)
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#elif CONSOLE_PARITY == 3
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# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK1)
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#elif CONSOLE_PARITY == 4
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# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK0)
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#else
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# error "Invalid CONFIG_UARTn_PARITY setting for CONSOLE"
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#endif
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/* Get stop-bit setting for the console and UART0-3 */
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#if CONSOLE_2STOP != 0
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# define CONSOLE_LCR_STOP LPC214X_LCR_STOP_2
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#else
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# define CONSOLE_LCR_STOP LPC214X_LCR_STOP_1
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#endif
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/* LCR and FCR values for the console */
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#define CONSOLE_LCR_VALUE (CONSOLE_LCR_WLS | CONSOLE_LCR_PAR | CONSOLE_LCR_STOP)
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#define CONSOLE_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\
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UART_FCR_RXRST | UART_FCR_FIFOEN)
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/* Baud calculations
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/* Baud calculations
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*
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BAUD = PCLK / (16 x (256 x DLM + DLL) x (1 + DIVADDVAL/MULVAL))
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* BAUD = PCLK / ((16 x DL) x (1 + DIVADDVAL/MULVAL))
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*
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Where PCLK is the peripheral clock, DLM and DLL are the standard
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* Where:
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UART baud rate divider registers, and DIVADDVAL and MULVAL are UART
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*
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fractional baud rate generator specific parameters.
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* - PCLK is the peripheral clock
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* - DL is (256*DML + DLL), the standard UART baud rate divider registers, and
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The value of MULVAL and DIVADDVAL should comply to the following conditions:
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* - DIVADDVAL and MULVAL are UART fractional baud rate generator specific
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* parameters.
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1. 1 <= MULVAL <= 15
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*
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2. 0 <= DIVADDVAL <= 14
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* The value of MULVAL and DIVADDVAL should comply to the following conditions:
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3. DIVADDVAL < MULVAL
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*
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* 1. 1 <= MULVAL <= 15
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The peripheral clock is controlled by:
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* 2. 0 <= DIVADDVAL <= 14
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* 3. DIVADDVAL < MULVAL
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#define SYSCON_PCLKSET_CCLK4 PCLK_peripheral = CCLK/4
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*
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#define SYSCON_PCLKSET_CCLK PCLK_peripheral = CCLK
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* The peripheral clock is controlled by:
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#define SYSCON_PCLKSET_CCLK2 PCLK_peripheral = CCLK/2
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*
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#define SYSCON_PCLKSET_CCLK6 PCLK_peripheral = CCLK/8 (except CAN1, CAN2, and CAN)
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* SYSCON_PCLKSEL_CCLK4: PCLK_peripheral = CCLK/4
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#define SYSCON_PCLKSET_CCLK8 PCLK_peripheral = CCLK/6 (CAN1, CAN2, and CAN)
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* SYSCON_PCLKSEL_CCLK: PCLK_peripheral = CCLK
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* SYSCON_PCLKSEL_CCLK2: PCLK_peripheral = CCLK/2
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* SYSCON_PCLKSEL_CCLK8: PCLK_peripheral = CCLK/8
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*/
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*/
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/**************************************************************************
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/**************************************************************************
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@ -112,6 +188,7 @@ The peripheral clock is controlled by:
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void up_lowputc(char ch)
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void up_lowputc(char ch)
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{
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{
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#ifdef HAVE_UART
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/* Wait for the transmitter to be available */
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/* Wait for the transmitter to be available */
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while ((getreg32(CONSOLE_BASE+LPC17_UART_LSR_OFFSET) & UART_LSR_THRE) == 0);
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while ((getreg32(CONSOLE_BASE+LPC17_UART_LSR_OFFSET) & UART_LSR_THRE) == 0);
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@ -119,6 +196,7 @@ void up_lowputc(char ch)
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/* Send the character */
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/* Send the character */
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putreg32((uint32_t)ch, CONSOLE_BASE+LPC17_UART_THR_OFFSET);
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putreg32((uint32_t)ch, CONSOLE_BASE+LPC17_UART_THR_OFFSET);
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#endif
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}
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}
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/**************************************************************************
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/**************************************************************************
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@ -153,6 +231,8 @@ void up_lowputc(char ch)
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void lpc17_lowsetup(void)
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void lpc17_lowsetup(void)
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{
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{
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#ifdef HAVE_UART
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#if 0
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#if 0
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uint32_t regval;
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uint32_t regval;
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@ -288,6 +368,7 @@ void lpc17_lowsetup(void)
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CONSOLE_BASE+LPC17_UART_CR_OFFSET);
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CONSOLE_BASE+LPC17_UART_CR_OFFSET);
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#endif
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#endif
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#endif /* 0 */
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#endif /* 0 */
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#endif /* HAVE_UART */
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}
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}
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@ -68,7 +68,7 @@
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* provide some minimal implementation of up_putc.
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* provide some minimal implementation of up_putc.
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*/
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*/
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#ifdef CONFIG_USE_SERIALDRIVER
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#if defined(CONFIG_USE_SERIALDRIVER) && defined(HAVE_UART)
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/* Configuration *********************************************************************/
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/* Configuration *********************************************************************/
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@ -84,6 +84,7 @@ struct up_dev_s
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uint8_t irq; /* IRQ associated with this UART */
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uint8_t irq; /* IRQ associated with this UART */
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uint8_t parity; /* 0=none, 1=odd, 2=even */
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uint8_t parity; /* 0=none, 1=odd, 2=even */
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uint8_t bits; /* Number of bits (7 or 8) */
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uint8_t bits; /* Number of bits (7 or 8) */
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uint8_t cclkdiv; /* Divisor needed to get PCLK from CCLK */
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bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
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bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
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};
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};
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@ -504,7 +505,7 @@ static int up_setup(struct uart_dev_s *dev)
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{
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{
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#ifndef CONFIG_SUPPRESS_LPC17_UART_CONFIG
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#ifndef CONFIG_SUPPRESS_LPC17_UART_CONFIG
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struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
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struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
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uint16_t baud;
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uint16_t dl;
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uint8_t lcr;
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uint8_t lcr;
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/* Clear fifos */
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/* Clear fifos */
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@ -552,9 +553,9 @@ static int up_setup(struct uart_dev_s *dev)
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/* Set the BAUD divisor */
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/* Set the BAUD divisor */
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baud = UART_BAUD(priv->baud);
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dl = lpc17_uartdl(priv->baud, priv->cclkdiv);
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up_serialout(priv, LPC17_UART_DLM_OFFSET, baud >> 8);
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up_serialout(priv, LPC17_UART_DLM_OFFSET, dl >> 8);
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up_serialout(priv, LPC17_UART_DLL_OFFSET, baud & 0xff);
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up_serialout(priv, LPC17_UART_DLL_OFFSET, dl & 0xff);
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/* Clear DLAB */
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/* Clear DLAB */
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@ -961,15 +962,19 @@ void up_earlyserialinit(void)
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/* Disable all UARTS */
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/* Disable all UARTS */
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#ifdef TTYS0_DEV
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#ifdef TTYS0_DEV
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TTYS0_DEV.cclkdiv = lpc17_uartcclkdiv(CONFIG_UART0_BAUD);
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up_disableuartint(TTYS0_DEV.priv, NULL);
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up_disableuartint(TTYS0_DEV.priv, NULL);
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#endif
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#endif
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#ifdef TTYS1_DEV
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#ifdef TTYS1_DEV
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TTYS1_DEV.cclkdiv = lpc17_uartcclkdiv(CONFIG_UART1_BAUD);
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up_disableuartint(TTYS1_DEV.priv, NULL);
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up_disableuartint(TTYS1_DEV.priv, NULL);
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#endif
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#endif
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#ifdef TTYS2_DEV
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#ifdef TTYS2_DEV
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TTYS2_DEV.cclkdiv = lpc17_uartcclkdiv(CONFIG_UART2_BAUD);
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up_disableuartint(TTYS2_DEV.priv, NULL);
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up_disableuartint(TTYS2_DEV.priv, NULL);
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#endif
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#endif
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#ifdef TTYS3_DEV
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#ifdef TTYS3_DEV
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TTYS3_DEV.cclkdiv = lpc17_uartcclkdiv(CONFIG_UART3_BAUD);
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up_disableuartint(TTYS3_DEV.priv, NULL);
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up_disableuartint(TTYS3_DEV.priv, NULL);
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#endif
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#endif
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@ -1050,6 +1055,7 @@ int up_putc(int ch)
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int up_putc(int ch)
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int up_putc(int ch)
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{
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{
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#ifdef HAVE_UART
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/* Check for LF */
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/* Check for LF */
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if (ch == '\n')
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if (ch == '\n')
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@ -1060,6 +1066,7 @@ int up_putc(int ch)
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}
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}
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up_lowputc(ch);
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up_lowputc(ch);
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#endif
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return ch;
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return ch;
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}
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}
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@ -41,6 +41,10 @@
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************************************************************************************/
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************************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/config.h>
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#include <arch/board/board.h>
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#include "lpc17_uart.h"
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#include "lpc17_syscon.h"
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/************************************************************************************
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/************************************************************************************
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* Pre-processor Definitions
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* Pre-processor Definitions
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@ -48,7 +52,17 @@
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/* Configuration *********************************************************************/
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/* Configuration *********************************************************************/
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/* Is there a serial console? It could be on any UARTn, n=0,1,2,3 */
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/* Are any UARTs enabled? */
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#undef HAVE_UART
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#if defined(CONFIG_LPC17_UART0) || defined(CONFIG_LPC17_UART1) || \
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defined(CONFIG_LPC17_UART2) || defined(CONFIG_LPC17_UART3)
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# define HAVE_UART1
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#endif
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/* Is there a serial console? There should be at most one defined. It could be on
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* any UARTn, n=0,1,2,3
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*/
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#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART0)
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#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART0)
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# undef CONFIG_UART1_SERIAL_CONSOLE
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# undef CONFIG_UART1_SERIAL_CONSOLE
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@ -78,239 +92,12 @@
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# undef HAVE_CONSOLE
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# undef HAVE_CONSOLE
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#endif
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#endif
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/* Select UART parameters for the selected console */
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/* We cannot allow the DLM/DLL divisor to become to small or will will lose too
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* much accuracy. This following is a "fudge factor" that represents the minimum
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* value of the divisor that we will permit.
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*/
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#if defined(CONFIG_UART0_SERIAL_CONSOLE)
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#define UART_MINDL 32
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# define CONSOLE_BASE LPC17_UART0_BASE
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# define CONSOLE_BAUD CONFIG_UART0_BAUD
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# define CONSOLE_BITS CONFIG_UART0_BITS
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# define CONSOLE_PARITY CONFIG_UART0_PARITY
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# define CONSOLE_2STOP CONFIG_UART0_2STOP
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#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
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# define CONSOLE_BASE LPC17_UART1_BASE
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# define CONSOLE_BAUD CONFIG_UART1_BAUD
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# define CONSOLE_BITS CONFIG_UART1_BITS
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# define CONSOLE_PARITY CONFIG_UART1_PARITY
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# define CONSOLE_2STOP CONFIG_UART1_2STOP
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#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
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# define CONSOLE_BASE LPC17_UART2_BASE
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# define CONSOLE_BAUD CONFIG_UART2_BAUD
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# define CONSOLE_BITS CONFIG_UART2_BITS
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# define CONSOLE_PARITY CONFIG_UART2_PARITY
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# define CONSOLE_2STOP CONFIG_UART2_2STOP
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#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
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# define CONSOLE_BASE LPC17_UART3_BASE
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# define CONSOLE_BAUD CONFIG_UART3_BAUD
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# define CONSOLE_BITS CONFIG_UART3_BITS
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# define CONSOLE_PARITY CONFIG_UART3_PARITY
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# define CONSOLE_2STOP CONFIG_UART3_2STOP
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#else
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# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
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#endif
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/* Get word length setting for the console UART and UART0-3 */
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#if CONSOLE_BITS == 5
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# define CONSOLE_LCR_WLS UART_LCR_WLS_5BIT
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#elif CONSOLE_BITS == 6
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# define CONSOLE_LCR_WLS UART_LCR_WLS_6BIT
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#elif CONSOLE_BITS == 7
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# define CONSOLE_LCR_WLS UART_LCR_WLS_7BIT
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#elif CONSOLE_BITS == 8
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# define CONSOLE_LCR_WLS UART_LCR_WLS_8BIT
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#else
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# error "Invalid CONFIG_UARTn_BITS setting for console "
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#endif
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#ifdef CONFIG_LPC17_UART0
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# if CONFIG_UART0_BITS == 5
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# define UART0_LCR_WLS UART_LCR_WLS_5BIT
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# elif CONFIG_UART0_BITS == 6
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# define UART0_LCR_WLS UART_LCR_WLS_6BIT
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# elif CONFIG_UART0_BITS == 7
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# define UART0_LCR_WLS UART_LCR_WLS_7BIT
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# elif CONFIG_UART0_BITS == 8
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# define UART0_LCR_WLS UART_LCR_WLS_8BIT
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# else
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# error "Invalid CONFIG_UARTn_BITS setting for UART0 "
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# endif
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#endif
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#ifdef CONFIG_LPC17_UART1
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# if CONFIG_UART1_BITS == 5
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# define UART1_LCR_WLS UART_LCR_WLS_5BIT
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# elif CONFIG_UART1_BITS == 6
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# define UART1_LCR_WLS UART_LCR_WLS_6BIT
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|
||||||
# elif CONFIG_UART1_BITS == 7
|
|
||||||
# define UART1_LCR_WLS UART_LCR_WLS_7BIT
|
|
||||||
# elif CONFIG_UART1_BITS == 8
|
|
||||||
# define UART1_LCR_WLS UART_LCR_WLS_8BIT
|
|
||||||
# else
|
|
||||||
# error "Invalid CONFIG_UARTn_BITS setting for UART1 "
|
|
||||||
# endif
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_LPC17_UART2
|
|
||||||
# if CONFIG_UART2_BITS == 5
|
|
||||||
# define UART2_LCR_WLS UART_LCR_WLS_5BIT
|
|
||||||
# elif CONFIG_UART2_BITS == 6
|
|
||||||
# define UART2_LCR_WLS UART_LCR_WLS_6BIT
|
|
||||||
# elif CONFIG_UART2_BITS == 7
|
|
||||||
# define UART2_LCR_WLS UART_LCR_WLS_7BIT
|
|
||||||
# elif CONFIG_UART2_BITS == 8
|
|
||||||
# define UART2_LCR_WLS UART_LCR_WLS_8BIT
|
|
||||||
# else
|
|
||||||
# error "Invalid CONFIG_UARTn_BITS setting for UART2 "
|
|
||||||
# endif
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_LPC17_UART3
|
|
||||||
# if CONFIG_UART3_BITS == 5
|
|
||||||
# define UART3_LCR_WLS UART_LCR_WLS_5BIT
|
|
||||||
# elif CONFIG_UART3_BITS == 6
|
|
||||||
# define UART3_LCR_WLS UART_LCR_WLS_6BIT
|
|
||||||
# elif CONFIG_UART3_BITS == 7
|
|
||||||
# define UART3_LCR_WLS UART_LCR_WLS_7BIT
|
|
||||||
# elif CONFIG_UART3_BITS == 8
|
|
||||||
# define UART3_LCR_WLS UART_LCR_WLS_8BIT
|
|
||||||
# else
|
|
||||||
# error "Invalid CONFIG_UARTn_BITS setting for UART3 "
|
|
||||||
# endif
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Get parity setting for the console UART and UART0-3 */
|
|
||||||
|
|
||||||
#if CONSOLE_PARITY == 0
|
|
||||||
# define CONSOLE_LCR_PAR 0
|
|
||||||
#elif CONSOLE_PARITY == 1
|
|
||||||
# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_ODD)
|
|
||||||
#elif CONSOLE_PARITY == 2
|
|
||||||
# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_EVEN)
|
|
||||||
#elif CONSOLE_PARITY == 3
|
|
||||||
# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK1)
|
|
||||||
#elif CONSOLE_PARITY == 4
|
|
||||||
# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK0)
|
|
||||||
#else
|
|
||||||
# error "Invalid CONFIG_UARTn_PARITY setting for CONSOLE"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_LPC17_UART0
|
|
||||||
# if CONFIG_UART0_PARITY == 0
|
|
||||||
# define UART0_LCR_PAR 0
|
|
||||||
# elif CONFIG_UART0_PARITY == 1
|
|
||||||
# define UART0_LCR_PAR (UART_LCR_PE|UART_LCR_PS_ODD)
|
|
||||||
# elif CONFIG_UART0_PARITY == 2
|
|
||||||
# define UART0_LCR_PAR (UART_LCR_PE|UART_LCR_PS_EVEN)
|
|
||||||
# elif CONFIG_UART0_PARITY == 3
|
|
||||||
# define UART0_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK1)
|
|
||||||
# elif CONFIG_UART0_PARITY == 4
|
|
||||||
# define UART0_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK0)
|
|
||||||
# else
|
|
||||||
# error "Invalid CONFIG_UARTn_PARITY setting for UART0"
|
|
||||||
# endif
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_LPC17_UART1
|
|
||||||
# if CONFIG_UART1_PARITY == 0
|
|
||||||
# define UART1_LCR_PAR 0
|
|
||||||
# elif CONFIG_UART1_PARITY == 1
|
|
||||||
# define UART1_LCR_PAR (UART_LCR_PE|UART_LCR_PS_ODD)
|
|
||||||
# elif CONFIG_UART1_PARITY == 2
|
|
||||||
# define UART1_LCR_PAR (UART_LCR_PE|UART_LCR_PS_EVEN)
|
|
||||||
# elif CONFIG_UART1_PARITY == 3
|
|
||||||
# define UART1_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK1)
|
|
||||||
# elif CONFIG_UART1_PARITY == 4
|
|
||||||
# define UART1_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK0)
|
|
||||||
# else
|
|
||||||
# error "Invalid CONFIG_UARTn_PARITY setting for UART1"
|
|
||||||
# endif
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_LPC17_UART2
|
|
||||||
# if CONFIG_UART2_PARITY == 0
|
|
||||||
# define UART2_LCR_PAR 0
|
|
||||||
# elif CONFIG_UART2_PARITY == 1
|
|
||||||
# define UART2_LCR_PAR (UART_LCR_PE|UART_LCR_PS_ODD)
|
|
||||||
# elif CONFIG_UART2_PARITY == 2
|
|
||||||
# define UART2_LCR_PAR (UART_LCR_PE|UART_LCR_PS_EVEN)
|
|
||||||
# elif CONFIG_UART2_PARITY == 3
|
|
||||||
# define UART2_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK1)
|
|
||||||
# elif CONFIG_UART2_PARITY == 4
|
|
||||||
# define UART2_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK0)
|
|
||||||
# else
|
|
||||||
# error "Invalid CONFIG_UARTn_PARITY setting for UART2"
|
|
||||||
# endif
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_LPC17_UART3
|
|
||||||
# if CONFIG_UART3_PARITY == 0
|
|
||||||
# define UART3_LCR_PAR 0
|
|
||||||
# elif CONFIG_UART3_PARITY == 1
|
|
||||||
# define UART3_LCR_PAR (UART_LCR_PE|UART_LCR_PS_ODD)
|
|
||||||
# elif CONFIG_UART3_PARITY == 2
|
|
||||||
# define UART3_LCR_PAR (UART_LCR_PE|UART_LCR_PS_EVEN)
|
|
||||||
# elif CONFIG_UART3_PARITY == 3
|
|
||||||
# define UART3_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK1)
|
|
||||||
# elif CONFIG_UART3_PARITY == 4
|
|
||||||
# define UART3_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK0)
|
|
||||||
# else
|
|
||||||
# error "Invalid CONFIG_UARTn_PARITY setting for UART3"
|
|
||||||
# endif
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Get stop-bit setting for the console UART and UART0-3 */
|
|
||||||
|
|
||||||
#if CONSOLE_2STOP != 0
|
|
||||||
# define CONSOLE_LCR_STOP LPC214X_LCR_STOP_2
|
|
||||||
#else
|
|
||||||
# define CONSOLE_LCR_STOP LPC214X_LCR_STOP_1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if CONFIG_UART0_2STOP != 0
|
|
||||||
# define UART0_LCR_STOP LPC214X_LCR_STOP_2
|
|
||||||
#else
|
|
||||||
# define UART0_LCR_STOP LPC214X_LCR_STOP_1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if CONFIG_UART1_2STOP != 0
|
|
||||||
# define UART1_LCR_STOP LPC214X_LCR_STOP_2
|
|
||||||
#else
|
|
||||||
# define UART1_LCR_STOP LPC214X_LCR_STOP_1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if CONFIG_UART2_2STOP != 0
|
|
||||||
# define UART2_LCR_STOP LPC214X_LCR_STOP_2
|
|
||||||
#else
|
|
||||||
# define UART2_LCR_STOP LPC214X_LCR_STOP_1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if CONFIG_UART3_2STOP != 0
|
|
||||||
# define UART3_LCR_STOP LPC214X_LCR_STOP_2
|
|
||||||
#else
|
|
||||||
# define UART3_LCR_STOP LPC214X_LCR_STOP_1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* LCR and FCR values */
|
|
||||||
|
|
||||||
#define CONSOLE_LCR_VALUE (CONSOLE_LCR_WLS | CONSOLE_LCR_PAR | CONSOLE_LCR_STOP)
|
|
||||||
#define CONSOLE_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\
|
|
||||||
UART_FCR_RXRST | UART_FCR_FIFOEN)
|
|
||||||
|
|
||||||
#define UART0_LCR_VALUE (UART0_LCR_WLS | UART0_LCR_PAR | UART0_LCR_STOP)
|
|
||||||
#define UART0_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\
|
|
||||||
UART_FCR_RXRST | UART_FCR_FIFOEN)
|
|
||||||
|
|
||||||
#define UART1_LCR_VALUE (UART1_LCR_WLS | UART1_LCR_PAR | UART1_LCR_STOP)
|
|
||||||
#define UART1_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\
|
|
||||||
UART_FCR_RXRST | UART_FCR_FIFOEN)
|
|
||||||
|
|
||||||
#define UART2_LCR_VALUE (UART2_LCR_WLS | UART2_LCR_PAR | UART2_LCR_STOP)
|
|
||||||
#define UART2_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\
|
|
||||||
UART_FCR_RXRST | UART_FCR_FIFOEN)
|
|
||||||
|
|
||||||
#define UART3_LCR_VALUE (UART3_LCR_WLS | UART3_LCR_PAR | UART3_LCR_STOP)
|
|
||||||
#define UART3_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\
|
|
||||||
UART_FCR_RXRST | UART_FCR_FIFOEN)
|
|
||||||
|
|
||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* Public Types
|
* Public Types
|
||||||
@ -320,6 +107,149 @@
|
|||||||
* Public Data
|
* Public Data
|
||||||
************************************************************************************/
|
************************************************************************************/
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Inline Functions
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Name: lpc17_uartcclkdiv
|
||||||
|
*
|
||||||
|
* Descrption:
|
||||||
|
* Select a CCLK divider to produce the UART PCLK. The stratey is to select the
|
||||||
|
* smallest divisor that results in an solution within range of the 16-bit
|
||||||
|
* DLM and DLL divisor:
|
||||||
|
*
|
||||||
|
* PCLK = CCLK / divisor
|
||||||
|
* BAUD = PCLK / (16 * DL)
|
||||||
|
*
|
||||||
|
* Ignoring the fractional divider for now.
|
||||||
|
*
|
||||||
|
* NOTE: This is an inline function. If a typical optimization level is used and
|
||||||
|
* a constant is provided for the desired frequency, then most of the following
|
||||||
|
* logic will be optimized away.
|
||||||
|
*
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
static inline uint8_t lpc17_uartcclkdiv(uint32_t baud)
|
||||||
|
{
|
||||||
|
/* Ignoring the fractional divider, the BAUD is given by:
|
||||||
|
*
|
||||||
|
* BAUD = PCLK / (16 * DL), or
|
||||||
|
* DL = PCLK / BAUD / 16
|
||||||
|
*
|
||||||
|
* Where:
|
||||||
|
*
|
||||||
|
* PCLK = CCLK / divisor.
|
||||||
|
*
|
||||||
|
* Check divisor == 1. This works if the upper limit is met
|
||||||
|
*
|
||||||
|
* DL < 0xffff, or
|
||||||
|
* PCLK / BAUD / 16 < 0xffff, or
|
||||||
|
* CCLK / BAUD / 16 < 0xffff, or
|
||||||
|
* CCLK < BAUD * 0xffff * 16
|
||||||
|
* BAUD > CCLK / 0xffff / 16
|
||||||
|
*
|
||||||
|
* And the lower limit is met (we can't allow DL to get very close to one).
|
||||||
|
*
|
||||||
|
* DL >= MinDL
|
||||||
|
* CCLK / BAUD / 16 >= MinDL, or
|
||||||
|
* BAUD <= CCLK / 16 / MinDL
|
||||||
|
*/
|
||||||
|
|
||||||
|
if (baud < (LPC17_CCLK / 16 / UART_MINDL ))
|
||||||
|
{
|
||||||
|
return SYSCON_PCLKSEL_CCLK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check divisor == 2. This works if:
|
||||||
|
*
|
||||||
|
* 2 * CCLK / BAUD / 16 < 0xffff, or
|
||||||
|
* BAUD > CCLK / 0xffff / 8
|
||||||
|
*
|
||||||
|
* And
|
||||||
|
*
|
||||||
|
* 2 * CCLK / BAUD / 16 >= MinDL, or
|
||||||
|
* BAUD <= CCLK / 8 / MinDL
|
||||||
|
*/
|
||||||
|
|
||||||
|
else if (baud < (LPC17_CCLK / 8 / UART_MINDL ))
|
||||||
|
{
|
||||||
|
return SYSCON_PCLKSEL_CCLK2;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check divisor == 4. This works if:
|
||||||
|
*
|
||||||
|
* 4 * CCLK / BAUD / 16 < 0xffff, or
|
||||||
|
* BAUD > CCLK / 0xffff / 4
|
||||||
|
*
|
||||||
|
* And
|
||||||
|
*
|
||||||
|
* 4 * CCLK / BAUD / 16 >= MinDL, or
|
||||||
|
* BAUD <= CCLK / 4 / MinDL
|
||||||
|
*/
|
||||||
|
|
||||||
|
else if (baud < (LPC17_CCLK / 4 / UART_MINDL ))
|
||||||
|
{
|
||||||
|
return SYSCON_PCLKSEL_CCLK4;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check divisor == 8. This works if:
|
||||||
|
*
|
||||||
|
* 8 * CCLK / BAUD / 16 < 0xffff, or
|
||||||
|
* BAUD > CCLK / 0xffff / 2
|
||||||
|
*
|
||||||
|
* And
|
||||||
|
*
|
||||||
|
* 8 * CCLK / BAUD / 16 >= MinDL, or
|
||||||
|
* BAUD <= CCLK / 2 / MinDL
|
||||||
|
*/
|
||||||
|
|
||||||
|
else /* if (baud < (LPC17_CCLK / 2 / UART_MINDL )) */
|
||||||
|
{
|
||||||
|
return SYSCON_PCLKSEL_CCLK8;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Name: lpc17_uartdl
|
||||||
|
*
|
||||||
|
* Descrption:
|
||||||
|
* Select a divider to produce the BAUD from the UART PCLK.
|
||||||
|
*
|
||||||
|
* BAUD = PCLK / (16 * DL), or
|
||||||
|
* DL = PCLK / BAUD / 16
|
||||||
|
*
|
||||||
|
* Ignoring the fractional divider for now.
|
||||||
|
*
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
static inline uint32_t lpc17_uartdl(uint32_t baud, uint8_t divcode)
|
||||||
|
{
|
||||||
|
uint32_t num;
|
||||||
|
|
||||||
|
switch (divcode)
|
||||||
|
{
|
||||||
|
|
||||||
|
case SYSCON_PCLKSEL_CCLK4: /* PCLK_peripheral = CCLK/4 */
|
||||||
|
num = (LPC17_CCLK / 4);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case SYSCON_PCLKSEL_CCLK: /* PCLK_peripheral = CCLK */
|
||||||
|
num = LPC17_CCLK;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case SYSCON_PCLKSEL_CCLK2: /* PCLK_peripheral = CCLK/2 */
|
||||||
|
num = (LPC17_CCLK / 2);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case SYSCON_PCLKSEL_CCLK8: /* PCLK_peripheral = CCLK/8 (except CAN1, CAN2, and CAN) */
|
||||||
|
default:
|
||||||
|
num = (LPC17_CCLK / 8);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
return num / (baud << 4);
|
||||||
|
}
|
||||||
|
|
||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* Public Functions
|
* Public Functions
|
||||||
************************************************************************************/
|
************************************************************************************/
|
||||||
|
|||||||
@ -212,7 +212,7 @@
|
|||||||
|
|
||||||
#define SYSCON_CLKSRCSEL_SHIFT (0) /* Bits 0-1: Clock selection */
|
#define SYSCON_CLKSRCSEL_SHIFT (0) /* Bits 0-1: Clock selection */
|
||||||
#define SYSCON_CLKSRCSEL_MASK (3 << SYSCON_CLKSRCSEL_SHIFT)
|
#define SYSCON_CLKSRCSEL_MASK (3 << SYSCON_CLKSRCSEL_SHIFT)
|
||||||
# define SYSCON_CLKSRCSEL_MAIN (0 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = internal RC oscillator */
|
# define SYSCON_CLKSRCSEL_INTRC (0 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = internal RC oscillator */
|
||||||
# define SYSCON_CLKSRCSEL_RTC (1 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = main oscillator */
|
# define SYSCON_CLKSRCSEL_RTC (1 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = main oscillator */
|
||||||
# define SYSCON_CLKSRCSEL_MAIN (2 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = RTC oscillator */
|
# define SYSCON_CLKSRCSEL_MAIN (2 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = RTC oscillator */
|
||||||
/* Bits 2-31: Reserved */
|
/* Bits 2-31: Reserved */
|
||||||
@ -282,12 +282,12 @@
|
|||||||
/* Bits 8-31: Reserved */
|
/* Bits 8-31: Reserved */
|
||||||
/* Peripheral Clock Selection registers 0 and 1 */
|
/* Peripheral Clock Selection registers 0 and 1 */
|
||||||
|
|
||||||
#define SYSCON_PCLKSET_CCLK4 (0) /* PCLK_peripheral = CCLK/4 */
|
#define SYSCON_PCLKSEL_CCLK4 (0) /* PCLK_peripheral = CCLK/4 */
|
||||||
#define SYSCON_PCLKSET_CCLK (1) /* PCLK_peripheral = CCLK */
|
#define SYSCON_PCLKSEL_CCLK (1) /* PCLK_peripheral = CCLK */
|
||||||
#define SYSCON_PCLKSET_CCLK2 (2) /* PCLK_peripheral = CCLK/2 */
|
#define SYSCON_PCLKSEL_CCLK2 (2) /* PCLK_peripheral = CCLK/2 */
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#define SYSCON_PCLKSET_CCLK6 (3) /* PCLK_peripheral = CCLK/8 (except CAN1, CAN2, and CAN) */
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#define SYSCON_PCLKSEL_CCLK8 (3) /* PCLK_peripheral = CCLK/8 (except CAN1, CAN2, and CAN) */
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#define SYSCON_PCLKSET_CCLK8 (3) /* PCLK_peripheral = CCLK/6 (CAN1, CAN2, and CAN) */
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#define SYSCON_PCLKSEL_CCLK6 (3) /* PCLK_peripheral = CCLK/6 (CAN1, CAN2, and CAN) */
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#define SYSCON_PCLKSET_MASK (3)
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#define SYSCON_PCLKSEL_MASK (3)
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#define SYSCON_PCLKSEL0_WDT_SHIFT (0) /* Bits 0-1: Peripheral clock WDT */
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#define SYSCON_PCLKSEL0_WDT_SHIFT (0) /* Bits 0-1: Peripheral clock WDT */
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#define SYSCON_PCLKSEL0_WDT_MASK (3 << SYSCON_PCLKSEL0_WDT_SHIFT)
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#define SYSCON_PCLKSEL0_WDT_MASK (3 << SYSCON_PCLKSEL0_WDT_SHIFT)
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Loading…
Reference in New Issue
Block a user