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Add SAM3X/3A peripheral clock controls

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This commit is contained in:
Gregory Nutt 2013-06-26 14:00:26 -06:00
parent 8865cf8be0
commit ae6dbb9bf9
4 changed files with 264 additions and 26 deletions
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97
arch/arm/src/sam34/chip/sam3u_pmc.h
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@ -56,7 +56,7 @@
#define SAM_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */
#define SAM_PMC_SCSR_OFFSET 0x0008 /* System Clock Status Register */
/* 0x000c: Reserved */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_PMC_PCER0_OFFSET 0x0010 /* Peripheral Clock Enable Register 0 */
# define SAM_PMC_PCDR0_OFFSET 0x0014 /* Peripheral Clock Disable Register 0 */
# define SAM_PMC_PCSR0_OFFSET 0x0018 /* Peripheral Clock Status Register 0 */
@ -66,7 +66,7 @@
# define SAM_PMC_PCSR_OFFSET 0x0018 /* Peripheral Clock Status Register */
#endif
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_PMC_CKGR_UCKR_OFFSET 0x001c /* UTMI Clock Register */
#endif
/* 0x001c: Reserved (SAM4S)*/
@ -80,7 +80,7 @@
/* 0x002c: Reserved (SAM3U)*/
#define SAM_PMC_MCKR_OFFSET 0x0030 /* Master Clock Register */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
/* 0x0034 Reserved */
# define SAM_PMC_USB_OFFSET 0x0038 /* USB Clock Register PMC_USB */
/* 0x003c Reserved */
@ -102,12 +102,18 @@
#define SAM_PMC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */
#define SAM_PMC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
/* 0x00ec-0x00fc Reserved */
# define SAM_PMC_PCER1_OFFSET 0x0100 /* Peripheral Clock Enable Register 1 */
# define SAM_PMC_PCDR1_OFFSET 0x0104 /* Peripheral Clock Disable Register 1 */
# define SAM_PMC_PCSR1_OFFSET 0x0108 /* Peripheral Clock Status Register 1 */
#endif
/* 0x010c Reserved */
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_PMC_PCR_OFFSET 0x010c /* Peripheral Control Register */
#endif
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_PMC_OCR_OFFSET 0x0110 /* Oscillator Calibration Register */
/* 0x003c Reserved */
#endif
@ -118,16 +124,17 @@
#define SAM_PMC_SCDR (SAM_PMC_BASE+SAM_PMC_SCDR_OFFSET)
#define SAM_PMC_SCSR (SAM_PMC_BASE+SAM_PMC_SCSR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_PMC_PCER0 (SAM_PMC_BASE+SAM_PMC_PCER0_OFFSET)
# define SAM_PMC_PCDR0 (SAM_PMC_BASE+SAM_PMC_PCDR0_OFFSET)
# define SAM_PMC_PCSR0 (SAM_PMC_BASE+SAM_PMC_PCSR0_OFFSET)
#elif defined(CONFIG_ARCH_CHIP_SAM3U)
# define SAM_PMC_PCER (SAM_PMC_BASE+SAM_PMC_PCER_OFFSET)
# define SAM_PMC_PCDR (SAM_PMC_BASE+SAM_PMC_PCDR_OFFSET)
# define SAM_PMC_PCSR (SAM_PMC_BASE+SAM_PMC_PCSR_OFFSET)
#endif
#define SAM_PMC_PCDR (SAM_PMC_BASE+SAM_PMC_PCDR_OFFSET)
#define SAM_PMC_PCSR (SAM_PMC_BASE+SAM_PMC_PCSR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_PMC_CKGR_UCKR (SAM_PMC_BASE+SAM_PMC_CKGR_UCKR_OFFSET)
#endif
@ -137,6 +144,9 @@
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_PMC_CKGR_PLLBR (SAM_PMC_BASE+SAM_PMC_CKGR_PLLBR_OFFSET)
#endif
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_PMC_USB (SAM_PMC_BASE+SAM_PMC_USB_OFFSET)
#endif
@ -155,10 +165,16 @@
#define SAM_PMC_WPMR (SAM_PMC_BASE+SAM_PMC_WPMR_OFFSET)
#define SAM_PMC_WPSR (SAM_PMC_BASE+SAM_PMC_WPSR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_PMC_PCER1 (SAM_PMC_BASE+SAM_PMC_PCER1_OFFSET)
# define SAM_PMC_PCDR1 (SAM_PMC_BASE+SAM_PMC_PCDR1_OFFSET)
# define SAM_PMC_PCSR1 (SAM_PMC_BASE+SAM_PMC_PCSR1_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_PMC_PCR (SAM_PMC_BASE+SAM_PMC_PCR_OFFSET)
#endif
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_PMC_OCR (SAM_PMC_BASE+SAM_PMC_OCR_OFFSET)
#endif
@ -168,6 +184,10 @@
* Clock Status Register common bit-field definitions
*/
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4S)
# define PMC_UOTGCLK (1 << 5) /* Bit 5: Enable USB OTG Clock (48 MHz, USB_48M) for UTMI */
#endif
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define PMC_UDP (1 << 7) /* Bit 7: USB Device Port Clock Enable */
#endif
@ -215,7 +235,7 @@
/* PMC UTMI Clock Configuration Register */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define PMC_CKGR_UCKR_UPLLEN (1 << 16) /* Bit 16: UTMI PLL Enable */
# define PMC_CKGR_UCKR_UPLLCOUNT_SHIFT (20) /* Bits 20-23: UTMI PLL Start-up Time */
# define PMC_CKGR_UCKR_UPLLCOUNT_MASK (15 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT)
@ -225,7 +245,11 @@
#define PMC_CKGR_MOR_MOSCXTEN (1 << 0) /* Bit 0: Main Crystal Oscillator Enable */
#define PMC_CKGR_MOR_MOSCXTBY (1 << 1) /* Bit 1: Main Crystal Oscillator Bypass */
#define PMC_CKGR_MOR_WAITMODE (1 << 2) /* Bit 2: Wait Mode Command */
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S)
# define PMC_CKGR_MOR_WAITMODE (1 << 2) /* Bit 2: Wait Mode Command */
#endif
#define PMC_CKGR_MOR_MOSCRCEN (1 << 3) /* Bit 3: Main On-Chip RC Oscillator Enable */
#define PMC_CKGR_MOR_MOSCRCF_SHIFT (4) /* Bits 4-6: Main On-Chip RC Oscillator Frequency Selection */
#define PMC_CKGR_MOR_MOSCRCF_MASK (7 << PMC_CKGR_MOR_MOSCRCF_SHIFT)
@ -288,7 +312,7 @@
/* USB Clock Register PMC_USB */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
# define PMC_USB_USBS (1 << 0) /* Bit 0: USB Input Clock Selection */
# define PMC_USB_USBS_PLLA (0)
# define PMC_USB_USBS_PLLB PMC_USB_USBS
@ -306,7 +330,7 @@
# if defined(CONFIG_ARCH_CHIP_SAM4S)
# define PMC_MCKR_CSS_PLLB (3 << PMC_MCKR_CSS_SHIFT) /* PLLB Clock */
# elif defined(CONFIG_ARCH_CHIP_SAM3U)
# elif defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define PMC_MCKR_CSS_UPLL (3 << PMC_MCKR_CSS_SHIFT) /* UPLL Clock */
# endif
@ -321,11 +345,14 @@
# define PMC_MCKR_PRES_DIV64 (6 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 64 */
# define PMC_MCKR_PRES_DIV3 (7 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 3 */
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
# define PMC_MCKR_PLLADIV2 (1 << 12) /* Bit 12: PLLA Divider */
#endif
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define PMC_MCKR_PLLADIV2 (1 << 13) /* Bit 13: PLLA Divider */
# define PMC_MCKR_PLLBDIV2 (1 << 14) /* Bit 14: PLLB Divider */
#elif defined(CONFIG_ARCH_CHIP_SAM3U)
# define PMC_MCKR_UPLLDIV (1 << 13) /* Bit 13: UPLL Divider */
# define PMC_MCKR_PLLBDIV2 (1 << 13) /* Bit 13: PLLB Divider */
#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM3U)
# define PMC_MCKR_UPLLDIV2 (1 << 13) /* Bit 13: UPLL Divider */
#endif
/* PMC Programmable Clock Register (0,1,2) */
@ -338,7 +365,7 @@
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define PMC_PCK_CSS_PLLB (3 << PMC_PCK_CSS_MASK) /* PLLB Clock */
#elif defined(CONFIG_ARCH_CHIP_SAM3U)
#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM3U)
# define PMC_PCK_CSS_UPLL (3 << PMC_PCK_CSS_MASK) /* UPLL Clock */
#endif
@ -367,7 +394,7 @@
#define PMC_INT_MCKRDY (1 << 3) /* Bit 3: Master Clock Ready Interrupt */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM3U)
# define PMC_INT_LOCKU (1 << 6) /* Bit 6: UTMI PLL Lock Interrupt */
#endif
@ -407,7 +434,7 @@
#define PMC_FSMR_RTCAL (1 << 17) /* Bit 17: RTC Alarm Enable (MR only) */
#define PMC_FSMR_USBAL (1 << 18) /* Bit 18: USB Alarm Enable (MR only) */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM3U)
# define PMC_FSMR_LPM (1 << 20) /* Bit 20: Low Power Mode (MR only) */
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
# define PMC_FSMR_FLPM_SHIFT (21) /* Bit 21-22: Low Power Mode (MR only) */
@ -442,11 +469,37 @@
/* Peripheral Clock Disable Register 1 */
/* Peripheral Clock Status Register 1 */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM4S)
# define PMC_PIDH(n) (1 << ((n) - 32))
# define PMC_PID32 (1 << 0) /* Bit 0: PID32 */
# define PMC_PID33 (1 << 1) /* Bit 1: PID33 */
# define PMC_PID34 (1 << 2) /* Bit 2: PID34 */
# if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3X)
# define PMC_PID35 (1 << 3) /* Bit 3: PID35 */
# define PMC_PID36 (1 << 4) /* Bit 4: PID36 */
# define PMC_PID37 (1 << 5) /* Bit 5: PID37 */
# define PMC_PID38 (1 << 6) /* Bit 6: PID38 */
# define PMC_PID39 (1 << 7) /* Bit 7: PID39 */
# define PMC_PID40 (1 << 8) /* Bit 8: PID40 */
# define PMC_PID41 (1 << 9) /* Bit 9: PID41 */
# define PMC_PID42 (1 << 10) /* Bit 10: PID42 */
# define PMC_PID43 (1 << 11) /* Bit 11: PID43 */
# define PMC_PID44 (1 << 12) /* Bit 12: PID44 */
# endif
#endif
/* Peripheral Control Register */
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define PMC_PCR_PID_SHIFT (0) /* Bits 0-5: Peripheral ID */
# define PMC_PCR_PID_MASK (63 < PMC_PCR_PID_SHIFT)
# define PMC_PCR_CMD (1 << 12) /* Bit 12: Command */
# define PMC_PCR_DIV_SHIFT (16) /* Bits 16-17: Divisor Value */
# define PMC_PCR_DIV_MASK (3 < PMC_PCR_DIV_SHIFT)
# define PMC_PCR_DIV1 (0 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK */
# define PMC_PCR_DIV2 (1 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/2 */
# define PMC_PCR_DIV4 (2 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/4 */
# define PMC_PCR_EN (1 << 0) /* Bit 0: Enable */
#endif
/* Oscillator Calibration Register */

183
arch/arm/src/sam34/sam3x_periphclks.h Normal file
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@ -0,0 +1,183 @@
/************************************************************************************
* arch/arm/src/sam34/sam3x_periphclks.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_SAM3X_PERIPHCLKS_H
#define __ARCH_ARM_SRC_SAM34_SAM3X_PERIPHCLKS_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/irq.h>
#include "chip/sam3u_pmc.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Helper macros */
#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1)
#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PDER0)
#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PDER1)
#define sam_supc_enableclk() sam_enableperiph0(SAM_PID_SUPC)
#define sam_rstc_enableclk() sam_enableperiph0(SAM_PID_RSTC)
#define sam_rtc_enableclk() sam_enableperiph0(SAM_PID_RTC)
#define sam_rtt_enableclk() sam_enableperiph0(SAM_PID_RTT)
#define sam_wdt_enableclk() sam_enableperiph0(SAM_PID_WDT)
#define sam_pmc_enableclk() sam_enableperiph0(SAM_PID_PMC)
#define sam_eefc0_enableclk() sam_enableperiph0(SAM_PID_EEFC0)
#define sam_eefc1_enableclk() sam_enableperiph0(SAM_PID_EEFC1)
#define sam_uart0_enableclk() sam_enableperiph0(SAM_PID_UART0)
#define sam_smc_enableclk() sam_enableperiph0(SAM_PID_SMC)
#define sam_sdramc_enableclk() sam_enableperiph0(SAM_PID_SDRAMC)
#define sam_pioa_enableclk() sam_enableperiph0(SAM_PID_PIOA)
#define sam_piob_enableclk() sam_enableperiph0(SAM_PID_PIOB)
#define sam_pioc_enableclk() sam_enableperiph0(SAM_PID_PIOC)
#define sam_piod_enableclk() sam_enableperiph0(SAM_PID_PIOD)
#define sam_pioe_enableclk() sam_enableperiph0(SAM_PID_PIOE)
#define sam_piof_enableclk() sam_enableperiph0(SAM_PID_PIOF)
#define sam_usart0_enableclk() sam_enableperiph0(SAM_PID_USART0)
#define sam_usart1_enableclk() sam_enableperiph0(SAM_PID_USART1)
#define sam_usart2_enableclk() sam_enableperiph0(SAM_PID_USART2)
#define sam_usart3_enableclk() sam_enableperiph0(SAM_PID_USART3)
#define sam_hsmci_enableclk() sam_enableperiph0(SAM_PID_HSMCI)
#define sam_twi0_enableclk() sam_enableperiph0(SAM_PID_TWI0)
#define sam_twi1_enableclk() sam_enableperiph0(SAM_PID_TWI1)
#define sam_spi0_enableclk() sam_enableperiph0(SAM_PID_SPI0)
#define sam_spi1_enableclk() sam_enableperiph0(SAM_PID_SPI1)
#define sam_ssc_enableclk() sam_enableperiph0(SAM_PID_SSC)
#define sam_tc0_enableclk() sam_enableperiph0(SAM_PID_TC0)
#define sam_tc1_enableclk() sam_enableperiph0(SAM_PID_TC1)
#define sam_tc2_enableclk() sam_enableperiph0(SAM_PID_TC2)
#define sam_tc3_enableclk() sam_enableperiph0(SAM_PID_TC3)
#define sam_tc4_enableclk() sam_enableperiph0(SAM_PID_TC4)
#define sam_tc5_enableclk() sam_enableperiph1(SAM_PID_TC5)
#define sam_tc6_enableclk() sam_enableperiph1(SAM_PID_TC6)
#define sam_tc7_enableclk() sam_enableperiph1(SAM_PID_TC7)
#define sam_tc8_enableclk() sam_enableperiph1(SAM_PID_TC8)
#define sam_pwm_enableclk() sam_enableperiph1(SAM_PID_PWM)
#define sam_adc_enableclk() sam_enableperiph1(SAM_PID_ADC)
#define sam_dacc_enableclk() sam_enableperiph1(SAM_PID_DACC)
#define sam_dmac_enableclk() sam_enableperiph1(SAM_PID_DMAC)
#define sam_uotghs_enableclk() sam_enableperiph1(SAM_PID_UOTGHS)
#define sam_trng_enableclk() sam_enableperiph1(SAM_PID_TRNG)
#define sam_emac_enableclk() sam_enableperiph1(SAM_PID_EMAC)
#define sam_can0_enableclk() sam_enableperiph1(SAM_PID_CAN0)
#define sam_can1_enableclk() sam_enableperiph1(SAM_PID_CAN1)
#define sam_supc_disableclk() sam_disableperiph0(SAM_PID_SUPC)
#define sam_rstc_disableclk() sam_disableperiph0(SAM_PID_RSTC)
#define sam_rtc_disableclk() sam_disableperiph0(SAM_PID_RTC)
#define sam_rtt_disableclk() sam_disableperiph0(SAM_PID_RTT)
#define sam_wdt_disableclk() sam_disableperiph0(SAM_PID_WDT)
#define sam_pmc_disableclk() sam_disableperiph0(SAM_PID_PMC)
#define sam_eefc0_disableclk() sam_disableperiph0(SAM_PID_EEFC0)
#define sam_eefc1_disableclk() sam_disableperiph0(SAM_PID_EEFC1)
#define sam_uart0_disableclk() sam_disableperiph0(SAM_PID_UART0)
#define sam_smc_disableclk() sam_disableperiph0(SAM_PID_SMC)
#define sam_sdramc_disableclk() sam_disableperiph0(SAM_PID_SDRAMC)
#define sam_pioa_disableclk() sam_disableperiph0(SAM_PID_PIOA)
#define sam_piob_disableclk() sam_disableperiph0(SAM_PID_PIOB)
#define sam_pioc_disableclk() sam_disableperiph0(SAM_PID_PIOC)
#define sam_piod_disableclk() sam_disableperiph0(SAM_PID_PIOD)
#define sam_pioe_disableclk() sam_disableperiph0(SAM_PID_PIOE)
#define sam_piof_disableclk() sam_disableperiph0(SAM_PID_PIOF)
#define sam_usart0_disableclk() sam_disableperiph0(SAM_PID_USART0)
#define sam_usart1_disableclk() sam_disableperiph0(SAM_PID_USART1)
#define sam_usart2_disableclk() sam_disableperiph0(SAM_PID_USART2)
#define sam_usart3_disableclk() sam_disableperiph0(SAM_PID_USART3)
#define sam_hsmci_disableclk() sam_disableperiph0(SAM_PID_HSMCI)
#define sam_twi0_disableclk() sam_disableperiph0(SAM_PID_TWI0)
#define sam_twi1_disableclk() sam_disableperiph0(SAM_PID_TWI1)
#define sam_spi0_disableclk() sam_disableperiph0(SAM_PID_SPI0)
#define sam_spi1_disableclk() sam_disableperiph0(SAM_PID_SPI1)
#define sam_ssc_disableclk() sam_disableperiph0(SAM_PID_SSC)
#define sam_tc0_disableclk() sam_disableperiph0(SAM_PID_TC0)
#define sam_tc1_disableclk() sam_disableperiph0(SAM_PID_TC1)
#define sam_tc2_disableclk() sam_disableperiph0(SAM_PID_TC2)
#define sam_tc3_disableclk() sam_disableperiph0(SAM_PID_TC3)
#define sam_tc4_disableclk() sam_disableperiph0(SAM_PID_TC4)
#define sam_tc5_disableclk() sam_disableperiph1(SAM_PID_TC5)
#define sam_tc6_disableclk() sam_disableperiph1(SAM_PID_TC6)
#define sam_tc7_disableclk() sam_disableperiph1(SAM_PID_TC7)
#define sam_tc8_disableclk() sam_disableperiph1(SAM_PID_TC8)
#define sam_pwm_disableclk() sam_disableperiph1(SAM_PID_PWM)
#define sam_adc_disableclk() sam_disableperiph1(SAM_PID_ADC)
#define sam_dacc_disableclk() sam_disableperiph1(SAM_PID_DACC)
#define sam_dmac_disableclk() sam_disableperiph1(SAM_PID_DMAC)
#define sam_uotghs_disableclk() sam_disableperiph1(SAM_PID_UOTGHS)
#define sam_trng_disableclk() sam_disableperiph1(SAM_PID_TRNG)
#define sam_emac_disableclk() sam_disableperiph1(SAM_PID_EMAC)
#define sam_can0_disableclk() sam_disableperiph1(SAM_PID_CAN0)
#define sam_can1_disableclk() sam_disableperiph1(SAM_PID_CAN1)
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Public Data
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAM34_SAM3X_PERIPHCLKS_H */

8
arch/arm/src/sam34/sam4s_periphclks.h
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@ -50,10 +50,10 @@
************************************************************************************/
/* Helper macros */
#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1)
#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PDER0)
#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PDER1)
#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1)
#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PDER0)
#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PDER1)
#define sam_supc_enableclk() sam_enableperiph0(SAM_PID_SUPC)
#define sam_rstc_enableclk() sam_enableperiph0(SAM_PID_RSTC)

2
arch/arm/src/sam34/sam_periphclks.h
View File

@ -44,6 +44,8 @@
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# include "sam3u_periphclks.h"
#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# include "sam3x_periphclks.h"
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
# include "sam4l_periphclks.h"
#elif defined(CONFIG_ARCH_CHIP_SAM4S)