arm64/arm64_boot.c: Fix exception caused by accesses to ICC_SRE_EL3 when GICv3 was not implemented
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@ -89,6 +89,7 @@ void arm64_boot_el3_init(void)
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SCR_SMD_BIT); /* Do not trap SMC */
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write_sysreg(reg, scr_el3);
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#if CONFIG_ARM64_GIC_VERSION > 2
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reg = read_sysreg(ICC_SRE_EL3);
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reg |= (ICC_SRE_ELX_DFB_BIT | /* Disable FIQ bypass */
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ICC_SRE_ELX_DIB_BIT | /* Disable IRQ bypass */
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@ -96,6 +97,7 @@ void arm64_boot_el3_init(void)
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ICC_SRE_EL3_EN_BIT); /* Enables lower Exception level access to
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* ICC_SRE_EL1 */
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write_sysreg(reg, ICC_SRE_EL3);
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#endif
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ARM64_ISB();
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}
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