From ae9ef972c06985751a935e1334dfc3e649519d5a Mon Sep 17 00:00:00 2001 From: Tiago Medicci Serrano Date: Thu, 29 Feb 2024 16:21:23 -0300 Subject: [PATCH] paging: Rename existing CONFIG_PAGING to CONFIG_LEGACY_PAGING Current `CONFIG_PAGING` refers to an experimental implementation to enable embedded MCUs with some limited RAM space to execute large programs from some non-random access media. On-demand paging should be implemented for the kernel mode with address environment implementation enabled. --- Documentation/quickstart/debugging.rst | 2 +- arch/Kconfig | 14 ++++----- arch/arm/include/arm/irq.h | 2 +- arch/arm/include/armv7-a/irq.h | 2 +- arch/arm/include/armv7-r/irq.h | 2 +- arch/arm/include/armv8-r/irq.h | 2 +- arch/arm/src/a1x/a1x_boot.c | 8 ++--- arch/arm/src/a1x/hardware/a10_memorymap.h | 16 +++++----- arch/arm/src/am335x/am335x_boot.c | 8 ++--- .../src/am335x/hardware/am3358_memorymap.h | 14 ++++----- arch/arm/src/arm/Make.defs | 2 +- arch/arm/src/arm/arm_allocpage.c | 6 ++-- arch/arm/src/arm/arm_checkmapping.c | 4 +-- arch/arm/src/arm/arm_dataabort.c | 16 +++++----- arch/arm/src/arm/arm_head.S | 28 ++++++++--------- arch/arm/src/arm/arm_pginitialize.c | 4 +-- arch/arm/src/arm/arm_prefetchabort.c | 6 ++-- arch/arm/src/arm/arm_va2pte.c | 4 +-- arch/arm/src/arm/arm_vectors.S | 2 +- arch/arm/src/arm/pg_macros.h | 22 +++++++------- arch/arm/src/armv7-a/CMakeLists.txt | 2 +- arch/arm/src/armv7-a/Make.defs | 2 +- arch/arm/src/armv7-a/arm_allocpage.c | 6 ++-- arch/arm/src/armv7-a/arm_checkmapping.c | 4 +-- arch/arm/src/armv7-a/arm_dataabort.c | 12 ++++---- arch/arm/src/armv7-a/arm_head.S | 2 +- arch/arm/src/armv7-a/arm_pghead.S | 4 +-- arch/arm/src/armv7-a/arm_pginitialize.c | 4 +-- arch/arm/src/armv7-a/arm_prefetchabort.c | 8 ++--- arch/arm/src/armv7-a/arm_va2pte.c | 4 +-- arch/arm/src/armv7-a/mmu.h | 24 +++++++-------- arch/arm/src/common/arm_internal.h | 12 ++++---- arch/arm/src/imx6/hardware/imx_memorymap.h | 8 ++--- arch/arm/src/imx6/imx_boot.c | 8 ++--- arch/arm/src/lpc31xx/lpc31_allocateheap.c | 4 +-- arch/arm/src/lpc31xx/lpc31_boot.c | 10 +++---- arch/arm/src/lpc31xx/lpc31_memorymap.h | 22 +++++++------- .../src/sama5/hardware/_sama5d2x_memorymap.h | 30 +++++++++---------- .../src/sama5/hardware/_sama5d3x_memorymap.h | 24 +++++++-------- .../src/sama5/hardware/_sama5d4x_memorymap.h | 28 ++++++++--------- arch/arm/src/sama5/sam_boot.c | 8 ++--- arch/arm/src/sama5/sama5d2x_memorymap.c | 2 +- arch/arm/src/sama5/sama5d3x_memorymap.c | 2 +- arch/arm/src/sama5/sama5d4x_memorymap.c | 2 +- arch/arm64/include/irq.h | 2 +- arch/arm64/src/a64/a64_boot.c | 2 +- arch/arm64/src/common/arm64_internal.h | 6 ++-- arch/arm64/src/goldfish/goldfish_boot.c | 2 +- arch/arm64/src/imx8/imx8_boot.c | 2 +- arch/arm64/src/qemu/qemu_boot.c | 2 +- arch/arm64/src/rk3399/rk3399_boot.c | 2 +- .../lpc31xx/ea3131/configs/pgnsh/defconfig | 4 +-- boards/arm/lpc31xx/ea3131/src/Makefile | 2 +- boards/arm/lpc31xx/ea3131/src/ea3131.h | 2 +- boards/arm/lpc31xx/ea3131/src/lpc31_boot.c | 2 +- .../arm/lpc31xx/ea3131/src/lpc31_fillpage.c | 4 +-- boards/arm/lpc31xx/ea3152/src/Makefile | 2 +- boards/arm/lpc31xx/ea3152/src/ea3152.h | 2 +- boards/arm/lpc31xx/ea3152/src/lpc31_boot.c | 2 +- .../arm/lpc31xx/ea3152/src/lpc31_fillpage.c | 4 +-- include/nuttx/page.h | 4 +-- include/nuttx/sched.h | 2 +- sched/init/init.h | 4 +-- sched/init/nx_bringup.c | 12 ++++---- sched/init/nx_start.c | 4 +-- sched/paging/CMakeLists.txt | 2 +- sched/paging/Make.defs | 2 +- sched/paging/paging.h | 4 +-- sched/paging/pg_miss.c | 4 +-- sched/paging/pg_worker.c | 4 +-- sched/sched/sched.h | 2 +- sched/sched/sched_get_stateinfo.c | 2 +- 72 files changed, 242 insertions(+), 242 deletions(-) diff --git a/Documentation/quickstart/debugging.rst b/Documentation/quickstart/debugging.rst index 546f72560a..d9bc13d3a8 100644 --- a/Documentation/quickstart/debugging.rst +++ b/Documentation/quickstart/debugging.rst @@ -129,7 +129,7 @@ as there are some options hardcoded into opencd. By default, it assumes: * ``CONFIG_DISABLE_MQUEUE=y`` - * ``CONFIG_PAGING=n`` + * ``CONFIG_LEGACY_PAGING=n`` If you need these options to be set differently, you will have to edit ``./src/rtos/nuttx_header.h`` from ``openocd``, change the corresponding settings and then rebuild it. diff --git a/arch/Kconfig b/arch/Kconfig index 664a80b569..73061ece40 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -903,16 +903,16 @@ config ARCH_PGPOOL_SIZE endif # ARCH_PGPOOL_MAPPING endif # ARCH_ADDRENV && ARCH_NEED_ADDRENV_MAPPING -menuconfig PAGING - bool "On-demand paging" +menuconfig LEGACY_PAGING + bool "Legacy On-demand paging" default n - depends on ARCH_USE_MMU && !ARCH_ROMPGTABLE + depends on EXPERIMENTAL && ARCH_USE_MMU && !ARCH_ROMPGTABLE ---help--- - If set =y in your configation file, this setting will enable the on-demand - paging feature as described in + If set =y in your configation file, this setting will enable lazy loading + backed up by the experimental on-demand paging feature as described in https://nuttx.apache.org/docs/latest/components/paging.html. -if PAGING +if LEGACY_PAGING config PAGING_PAGESIZE int "Page size (bytes)" @@ -1030,7 +1030,7 @@ config PAGING_TIMEOUT_TICKS number if microseconds, then a fatal error will be declared. Default: No timeouts monitored -endif # PAGING +endif # LEGACY_PAGING config ARCH_IRQPRIO bool "Prioritized interrupt support" diff --git a/arch/arm/include/arm/irq.h b/arch/arm/include/arm/irq.h index 2d65c735f0..dd7ab7cb0a 100644 --- a/arch/arm/include/arm/irq.h +++ b/arch/arm/include/arm/irq.h @@ -153,7 +153,7 @@ struct xcptcontext * address register (FAR) at the time of data abort exception. */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING uintptr_t far; #endif }; diff --git a/arch/arm/include/armv7-a/irq.h b/arch/arm/include/armv7-a/irq.h index d95e0b9545..b62a5aeb4a 100644 --- a/arch/arm/include/armv7-a/irq.h +++ b/arch/arm/include/armv7-a/irq.h @@ -273,7 +273,7 @@ struct xcptcontext * address register (FAR) at the time of data abort exception. */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING uintptr_t far; #endif diff --git a/arch/arm/include/armv7-r/irq.h b/arch/arm/include/armv7-r/irq.h index 8091153704..09a107a317 100644 --- a/arch/arm/include/armv7-r/irq.h +++ b/arch/arm/include/armv7-r/irq.h @@ -272,7 +272,7 @@ struct xcptcontext * address register (FAR) at the time of data abort exception. */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING uintptr_t far; #endif diff --git a/arch/arm/include/armv8-r/irq.h b/arch/arm/include/armv8-r/irq.h index f0ca5e0fbd..b59bc54896 100644 --- a/arch/arm/include/armv8-r/irq.h +++ b/arch/arm/include/armv8-r/irq.h @@ -272,7 +272,7 @@ struct xcptcontext * address register (FAR) at the time of data abort exception. */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING uintptr_t far; #endif diff --git a/arch/arm/src/a1x/a1x_boot.c b/arch/arm/src/a1x/a1x_boot.c index 59d675661a..f4be425153 100644 --- a/arch/arm/src/a1x/a1x_boot.c +++ b/arch/arm/src/a1x/a1x_boot.c @@ -27,7 +27,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include #endif @@ -128,7 +128,7 @@ static inline void a1x_setupmappings(void) ****************************************************************************/ #if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && \ - defined(CONFIG_PAGING) + defined(CONFIG_LEGACY_PAGING) static void a1x_vectorpermissions(uint32_t mmuflags) { /* The PTE for the beginning of ISRAM is at the base of the L2 page table */ @@ -226,7 +226,7 @@ static void a1x_copyvectorblock(void) * read only, then temporarily mark the mapping write-able (non-buffered). */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING a1x_vectorpermissions(MMU_L2_VECTRWFLAGS); #endif @@ -250,7 +250,7 @@ static void a1x_copyvectorblock(void) /* Make the vectors read-only, cacheable again */ -#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING) +#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_LEGACY_PAGING) a1x_vectorpermissions(MMU_L2_VECTORFLAGS); #endif } diff --git a/arch/arm/src/a1x/hardware/a10_memorymap.h b/arch/arm/src/a1x/hardware/a10_memorymap.h index 40465dc56b..6455701875 100644 --- a/arch/arm/src/a1x/hardware/a10_memorymap.h +++ b/arch/arm/src/a1x/hardware/a10_memorymap.h @@ -441,11 +441,11 @@ #else /* PGTABLE_BASE_PADDR || PGTABLE_BASE_VADDR */ - /* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory - * map probably do not apply because paging logic will probably partition - * the SRAM section differently. In particular, if the page table is - * located at the end of SRAM, then the virtual page table address defined - * below will probably be in error. + /* If CONFIG_LEGACY_PAGING is selected, then parts of the 1-to-1 virtual + * memory map probably do not apply because paging logic will probably + * partition the SRAM section differently. In particular, if the page + * table is located at the end of SRAM, then the virtual page table address + * defined below will probably be in error. * In that case PGTABLE_BASE_VADDR is defined in the file mmu.h * * We must declare the page table at the bottom or at the top of internal @@ -514,8 +514,8 @@ * * 1) One mapping the vector table (only when CONFIG_ARCH_LOWVECTORS is not * defined). - * 2) If on-demand paging is supported (CONFIG_PAGING=y), than an additional - * L2 page table is needed. + * 2) If on-demand paging is supported (CONFIG_LEGACY_PAGING=y), than an + * additional L2 page table is needed. */ #ifndef CONFIG_ARCH_LOWVECTORS @@ -546,7 +546,7 @@ /* Paging L2 page table base addresses * - * NOTE: If CONFIG_PAGING is defined, mmu.h will re-assign the virtual + * NOTE: If CONFIG_LEGACY_PAGING is defined, mmu.h will re-assign the virtual * address of the page table. */ diff --git a/arch/arm/src/am335x/am335x_boot.c b/arch/arm/src/am335x/am335x_boot.c index ee68fad9ad..2bd19b5485 100644 --- a/arch/arm/src/am335x/am335x_boot.c +++ b/arch/arm/src/am335x/am335x_boot.c @@ -29,7 +29,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include #endif @@ -198,7 +198,7 @@ static inline void am335x_remap(void) ****************************************************************************/ #if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && \ - defined(CONFIG_PAGING) + defined(CONFIG_LEGACY_PAGING) static void am335x_vectorpermissions(uint32_t mmuflags) { /* The PTE for the beginning of OCMC0 RAM is at the base of the L2 page @@ -307,7 +307,7 @@ static void am335x_copyvectorblock(void) uint32_t *end; uint32_t *dest; -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /* If we are using re-mapped vectors in an area that has been marked * read only, then temporarily mark the mapping write-able (non-buffered). */ @@ -334,7 +334,7 @@ static void am335x_copyvectorblock(void) *dest++ = *src++; } -#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING) +#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_LEGACY_PAGING) /* Make the vectors read-only, cache-able again */ am335x_vectorpermissions(MMU_L2_VECTORFLAGS); diff --git a/arch/arm/src/am335x/hardware/am3358_memorymap.h b/arch/arm/src/am335x/hardware/am3358_memorymap.h index e745691b92..4e52293a26 100644 --- a/arch/arm/src/am335x/hardware/am3358_memorymap.h +++ b/arch/arm/src/am335x/hardware/am3358_memorymap.h @@ -461,12 +461,12 @@ #else /* PGTABLE_BASE_PADDR || PGTABLE_BASE_VADDR */ - /* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory - * map probably do not apply because paging logic will probably partition - * the SRAM section differently. In particular, if the page table is - * located at the end of SRAM, then the virtual page table address defined - * below will probably be in error. In that case PGTABLE_BASE_VADDR is - * defined in the file mmu.h + /* If CONFIG_LEGACY_PAGING is selected, then parts of the 1-to-1 virtual + * memory map probably do not apply because paging logic will probably + * partition the SRAM section differently. In particular, if the page + * table is located at the end of SRAM, then the virtual page table address + * defined below will probably be in error. + * In that case PGTABLE_BASE_VADDR is defined in the file mmu.h * * We must declare the page table at the bottom or at the top of internal * SRAM. We pick the bottom of internal SRAM *unless* there are vectors @@ -547,7 +547,7 @@ /* Paging L2 page table base addresses * - * NOTE: If CONFIG_PAGING is defined, mmu.h will re-assign the virtual + * NOTE: If CONFIG_LEGACY_PAGING is defined, mmu.h will re-assign the virtual * address of the page table. */ diff --git a/arch/arm/src/arm/Make.defs b/arch/arm/src/arm/Make.defs index 60a8d576da..ceed32eb30 100644 --- a/arch/arm/src/arm/Make.defs +++ b/arch/arm/src/arm/Make.defs @@ -32,6 +32,6 @@ CMN_CSRCS += arm_undefinedinsn.c CMN_ASRCS += arm_cache.S arm_vectors.S arm_vectortab.S CMN_ASRCS += arm_saveusercontext.S -ifeq ($(CONFIG_PAGING),y) +ifeq ($(CONFIG_LEGACY_PAGING),y) CMN_CSRCS += arm_pginitialize.c arm_checkmapping.c arm_allocpage.c arm_va2pte.c endif diff --git a/arch/arm/src/arm/arm_allocpage.c b/arch/arm/src/arm/arm_allocpage.c index 480a034674..003ffa7267 100644 --- a/arch/arm/src/arm/arm_allocpage.c +++ b/arch/arm/src/arm/arm_allocpage.c @@ -32,7 +32,7 @@ #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING #include @@ -171,7 +171,7 @@ int up_allocpage(struct tcb_s *tcb, void **vpage) */ pgndx = g_pgndx++; - if (g_pgndx >= CONFIG_PAGING) + if (g_pgndx >= CONFIG_LEGACY_PAGING) { g_pgndx = 0; g_pgwrap = true; @@ -225,4 +225,4 @@ int up_allocpage(struct tcb_s *tcb, void **vpage) return OK; } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/arch/arm/src/arm/arm_checkmapping.c b/arch/arm/src/arm/arm_checkmapping.c index fd935ec72a..5657cf3ae4 100644 --- a/arch/arm/src/arm/arm_checkmapping.c +++ b/arch/arm/src/arm/arm_checkmapping.c @@ -35,7 +35,7 @@ #include "arm_internal.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /**************************************************************************** * Pre-processor Definitions @@ -106,4 +106,4 @@ bool up_checkmapping(struct tcb_s *tcb) return (*pte != 0); } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/arch/arm/src/arm/arm_dataabort.c b/arch/arm/src/arm/arm_dataabort.c index ae59292ec9..642569625f 100644 --- a/arch/arm/src/arm/arm_dataabort.c +++ b/arch/arm/src/arm/arm_dataabort.c @@ -34,7 +34,7 @@ #include "sched/sched.h" #include "arm_internal.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include # include "arm.h" #endif @@ -49,8 +49,8 @@ * Input Parameters: * regs - The standard, ARM register save array. * - * If CONFIG_PAGING is selected in the NuttX configuration file, then these - * additional input values are expected: + * If CONFIG_LEGACY_PAGING is selected in the NuttX configuration file, then + * these additional input values are expected: * * far - Fault address register. On a data abort, the ARM MMU places the * miss virtual address (MVA) into the FAR register. This is the address @@ -65,11 +65,11 @@ * ****************************************************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING void arm_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr) { struct tcb_s *tcb = this_task(); -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING uint32_t *savestate; /* Save the saved processor context in CURRENT_REGS where it can be @@ -80,7 +80,7 @@ void arm_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr) #endif CURRENT_REGS = regs; -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /* In the NuttX on-demand paging implementation, only the read-only, .text * section is paged. However, the ARM compiler generated PC-relative data * fetches from within the .text sections. Also, it is customary to locate @@ -149,7 +149,7 @@ segfault: PANIC_WITH_REGS("panic", regs); } -#else /* CONFIG_PAGING */ +#else /* CONFIG_LEGACY_PAGING */ void arm_dataabort(uint32_t *regs) { @@ -165,4 +165,4 @@ void arm_dataabort(uint32_t *regs) PANIC_WITH_REGS("panic", regs); } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/arch/arm/src/arm/arm_head.S b/arch/arm/src/arm/arm_head.S index e087c61fb7..c46bae2ec2 100644 --- a/arch/arm/src/arm/arm_head.S +++ b/arch/arm/src/arm/arm_head.S @@ -28,7 +28,7 @@ #include "chip.h" #include "arm_internal.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include # include "pg_macros.h" #endif @@ -128,7 +128,7 @@ * NPAGE1=(1024 -((a) & 0x00000fff) >> 2) NPAGE1=1-1024 */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # define PG_L2_TEXT_PBASE (PG_L2_TEXT_PADDR & PG_L1_PADDRMASK) # define PG_L2_TEXT_NPAGE1 (PTE_NPAGES - ((PG_L2_TEXT_PADDR & ~PG_L1_PADDRMASK) >> 2)) # define PG_L2_PGTABLE_PBASE (PG_L2_PGTABLE_PADDR & PG_L1_PADDRMASK) @@ -253,7 +253,7 @@ __start: str r3, [r4, r0, lsr #18] /* identity mapping */ #endif -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /* Map the read-only .text region in place. This must be done * before the MMU is enabled and the virtual addressing takes @@ -292,7 +292,7 @@ __start: ldmia r0, {r0, r1, r2, r3} pg_l2map r0, r1, r2, r3, r5 -#else /* CONFIG_PAGING */ +#else /* CONFIG_LEGACY_PAGING */ #ifdef CONFIG_IDENTITY_TEXTMAP mksection r0, r4 /* r0=phys. base section */ @@ -317,7 +317,7 @@ __start: * can only be assumed to cover the initial .text region. */ -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ #endif /* CONFIG_ARCH_ROMPGTABLE */ /* The following logic will set up the ARM920/ARM926 for normal operation. @@ -443,7 +443,7 @@ __start: .long PGTABLE_BASE_VADDR /* Virtual start of page table */ #endif -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING .Ltxtspan: .long PG_L1_TEXT_PADDR /* Physical address in the L1 table */ @@ -471,7 +471,7 @@ __start: .long PG_PGTABLE_NPAGES /* Total mapped page table pages */ .long MMU_L2_PGTABFLAGS /* L2 MMU flags to use */ -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ .size __start, .-__start /**************************************************************************** @@ -501,7 +501,7 @@ __start: str r0, [r4, r3, lsr #18] /* Undo identity mapping */ #endif -#if defined(CONFIG_PAGING) +#if defined(CONFIG_LEGACY_PAGING) /* Populate the L1 table for the data region */ adr r0, .Ldataspan @@ -557,7 +557,7 @@ __start: * will still probably be located in a separate (virtual) address region. */ -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ #endif /* CONFIG_ARCH_ROMPGTABLE */ /* Zero BSS and set up the stack pointer */ @@ -583,7 +583,7 @@ __start: * address region. */ -#if defined(CONFIG_BOOT_RUNFROMFLASH) || defined(CONFIG_PAGING) +#if defined(CONFIG_BOOT_RUNFROMFLASH) || defined(CONFIG_LEGACY_PAGING) adr r3, .Ldatainit ldmia r3, {r0, r1, r2} @@ -622,14 +622,14 @@ __start: .long _ebss .long _ebss+CONFIG_IDLETHREAD_STACKSIZE -#if !defined(CONFIG_PAGING) && !defined(CONFIG_BOOT_RUNFROMFLASH) +#if !defined(CONFIG_LEGACY_PAGING) && !defined(CONFIG_BOOT_RUNFROMFLASH) .LCnuttxpaddr: .long NUTTX_START_PADDR & 0xfff00000 #endif -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING .Ldataspan: .long PG_L1_DATA_VADDR /* Virtual address in the L1 table */ @@ -644,9 +644,9 @@ __start: .long PG_DATA_NPAGES /* Number of pages in the data region */ .long MMU_L2_DATAFLAGS /* L2 MMU flags to use */ -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ -#if defined(CONFIG_BOOT_RUNFROMFLASH) || defined(CONFIG_PAGING) +#if defined(CONFIG_BOOT_RUNFROMFLASH) || defined(CONFIG_LEGACY_PAGING) .Ldatainit: .long _eronly /* Where .data defaults are stored in FLASH */ .long _sdata /* Where .data needs to reside in SDRAM */ diff --git a/arch/arm/src/arm/arm_pginitialize.c b/arch/arm/src/arm/arm_pginitialize.c index 22a1aed7db..fb5fb5340d 100644 --- a/arch/arm/src/arm/arm_pginitialize.c +++ b/arch/arm/src/arm/arm_pginitialize.c @@ -31,7 +31,7 @@ #include "arm_internal.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /**************************************************************************** * Pre-processor Definitions @@ -77,4 +77,4 @@ void arm_pginitialize(void) */ } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/arch/arm/src/arm/arm_prefetchabort.c b/arch/arm/src/arm/arm_prefetchabort.c index fbfa62dc59..c96143066e 100644 --- a/arch/arm/src/arm/arm_prefetchabort.c +++ b/arch/arm/src/arm/arm_prefetchabort.c @@ -30,7 +30,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include #endif @@ -65,7 +65,7 @@ void arm_prefetchabort(uint32_t *regs) { -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING uint32_t *savestate; /* Save the saved processor context in CURRENT_REGS where it can be @@ -76,7 +76,7 @@ void arm_prefetchabort(uint32_t *regs) #endif CURRENT_REGS = regs; -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /* Get the (virtual) address of instruction that caused the prefetch * abort. When the exception occurred, this address was provided in the * lr register and this value was saved in the context save area as the PC diff --git a/arch/arm/src/arm/arm_va2pte.c b/arch/arm/src/arm/arm_va2pte.c index 4e8ae09745..7f1715cb21 100644 --- a/arch/arm/src/arm/arm_va2pte.c +++ b/arch/arm/src/arm/arm_va2pte.c @@ -35,7 +35,7 @@ #include "pg_macros.h" #include "arm_internal.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /**************************************************************************** * Pre-processor Definitions @@ -103,4 +103,4 @@ uint32_t *arm_va2pte(uintptr_t vaddr) return &L2[ndx]; } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/arch/arm/src/arm/arm_vectors.S b/arch/arm/src/arm/arm_vectors.S index 940ce1177f..bad5c41142 100644 --- a/arch/arm/src/arm/arm_vectors.S +++ b/arch/arm/src/arm/arm_vectors.S @@ -397,7 +397,7 @@ arm_vectordata: mov fp, #0 /* Init frame pointer */ mov r0, sp /* Get r0=xcp */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING mrc p15, 0, r1, c6, c0, 0 /* Get R1=FAR */ mrc p15, 0, r2, c5, c0, 0 /* Get r2=FSR */ #endif diff --git a/arch/arm/src/arm/pg_macros.h b/arch/arm/src/arm/pg_macros.h index d1c59b57a7..f890113e3e 100644 --- a/arch/arm/src/arm/pg_macros.h +++ b/arch/arm/src/arm/pg_macros.h @@ -41,14 +41,14 @@ /* Configuration ************************************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /* Sanity check -- we cannot be using a ROM page table and supporting on- * demand paging. */ #ifdef CONFIG_ARCH_ROMPGTABLE -# error "Cannot support both CONFIG_PAGING and CONFIG_ARCH_ROMPGTABLE" +# error "Cannot support both CONFIG_LEGACY_PAGING and CONFIG_ARCH_ROMPGTABLE" #endif /* Virtual Page Table Location **********************************************/ @@ -342,7 +342,7 @@ #define PG_POOL_PGPADDR(ndx) (PG_PAGED_PBASE + ((ndx) << PAGESHIFT)) #define PG_POOL_PGVADDR(ndx) (PG_PAGED_VBASE + ((ndx) << PAGESHIFT)) -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ /**************************************************************************** * Assembly Macros @@ -355,8 +355,8 @@ * * Description: * Write several, contiguous L2 page table entries. npages entries will be - * written. This macro is used when CONFIG_PAGING is enable. This case, - * it is used as follows: + * written. This macro is used when CONFIG_LEGACY_PAGING is enable. + * This case, it is used as follows: * * ldr r0, =PGTABLE_L2_BASE_PADDR <-- Address in L2 table * ldr r1, =PG_LOCKED_PBASE <-- Physical page memory address @@ -385,7 +385,7 @@ * ****************************************************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING .macro pg_l2map, l2, ppage, npages, mmuflags, tmp b 2f 1: @@ -418,7 +418,7 @@ cmp \npages, #0 bgt 1b .endm -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ /**************************************************************************** * Name: pg_l1span @@ -426,8 +426,8 @@ * Description: * Write several, contiguous unmapped coarse L1 page table entries. As * many entries will be written as many as needed to span npages. This - * macro is used when CONFIG_PAGING is enable. This case, it is used as - * follows: + * macro is used when CONFIG_LEGACY_PAGING is enable. + * This case, it is used as follows: * * ldr r0, =PG_L1_PGTABLE_PADDR <-- Address in the L1 table * ldr r1, =PG_L2_PGTABLE_PADDR <-- Physical address of L2 page table @@ -461,7 +461,7 @@ * ****************************************************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING .macro pg_l1span, l1, l2, npages, ppage, mmuflags, tmp b 2f 1: @@ -499,7 +499,7 @@ bgt 1b .endm -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ #endif /* __ASSEMBLY__ */ /**************************************************************************** diff --git a/arch/arm/src/armv7-a/CMakeLists.txt b/arch/arm/src/armv7-a/CMakeLists.txt index 809b8b591c..cacf074507 100644 --- a/arch/arm/src/armv7-a/CMakeLists.txt +++ b/arch/arm/src/armv7-a/CMakeLists.txt @@ -60,7 +60,7 @@ if(CONFIG_ARMV7A_L2CC_PL310) list(APPEND SRCS arm_l2cc_pl310.c) endif() -if(CONFIG_PAGING) +if(CONFIG_LEGACY_PAGING) list( APPEND SRCS diff --git a/arch/arm/src/armv7-a/Make.defs b/arch/arm/src/armv7-a/Make.defs index acdf143dc3..a529f05b7a 100644 --- a/arch/arm/src/armv7-a/Make.defs +++ b/arch/arm/src/armv7-a/Make.defs @@ -55,7 +55,7 @@ ifeq ($(CONFIG_ARMV7A_L2CC_PL310),y) CMN_CSRCS += arm_l2cc_pl310.c endif -ifeq ($(CONFIG_PAGING),y) +ifeq ($(CONFIG_LEGACY_PAGING),y) CMN_CSRCS += arm_allocpage.c arm_checkmapping.c arm_pginitialize.c CMN_CSRCS += arm_va2pte.c CMN_ASRCS += arm_pghead.S diff --git a/arch/arm/src/armv7-a/arm_allocpage.c b/arch/arm/src/armv7-a/arm_allocpage.c index aed3a4d6a7..4c897d91ec 100644 --- a/arch/arm/src/armv7-a/arm_allocpage.c +++ b/arch/arm/src/armv7-a/arm_allocpage.c @@ -32,7 +32,7 @@ #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING #include @@ -163,7 +163,7 @@ int arm_allocpage(struct tcb_s *tcb, void **vpage) */ pgndx = g_pgndx++; - if (g_pgndx >= CONFIG_PAGING) + if (g_pgndx >= CONFIG_LEGACY_PAGING) { g_pgndx = 0; g_pgwrap = true; @@ -219,4 +219,4 @@ int arm_allocpage(struct tcb_s *tcb, void **vpage) return OK; } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/arch/arm/src/armv7-a/arm_checkmapping.c b/arch/arm/src/armv7-a/arm_checkmapping.c index 3a5c16d4fb..41ce634168 100644 --- a/arch/arm/src/armv7-a/arm_checkmapping.c +++ b/arch/arm/src/armv7-a/arm_checkmapping.c @@ -33,7 +33,7 @@ #include "arm_internal.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /**************************************************************************** * Public Functions @@ -92,4 +92,4 @@ bool arm_checkmapping(struct tcb_s *tcb) return (*pte != 0); } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/arch/arm/src/armv7-a/arm_dataabort.c b/arch/arm/src/armv7-a/arm_dataabort.c index 2c2952b129..13f562baa8 100644 --- a/arch/arm/src/armv7-a/arm_dataabort.c +++ b/arch/arm/src/armv7-a/arm_dataabort.c @@ -33,7 +33,7 @@ #include "sched/sched.h" #include "arm_internal.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include # include "arm.h" #endif @@ -48,8 +48,8 @@ * Input Parameters: * regs - The standard, ARM register save array. * - * If CONFIG_PAGING is selected in the NuttX configuration file, then these - * additional input values are expected: + * If CONFIG_LEGACY_PAGING is selected in the NuttX configuration file, then + * these additional input values are expected: * * dfar - Fault address register. On a data abort, the ARM MMU places the * miss virtual address (MVA) into the DFAR register. This is the @@ -64,7 +64,7 @@ * ****************************************************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr) { struct tcb_s *tcb = this_task(); @@ -144,7 +144,7 @@ segfault: return regs; /* To keep the compiler happy */ } -#else /* CONFIG_PAGING */ +#else /* CONFIG_LEGACY_PAGING */ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr) { @@ -162,4 +162,4 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr) return regs; /* To keep the compiler happy */ } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/arch/arm/src/armv7-a/arm_head.S b/arch/arm/src/armv7-a/arm_head.S index af1b39a673..9e0b0330ff 100644 --- a/arch/arm/src/armv7-a/arm_head.S +++ b/arch/arm/src/armv7-a/arm_head.S @@ -41,7 +41,7 @@ #define IDLE_STACK_TOP (IDLE_STACK_BASE + CONFIG_IDLETHREAD_STACKSIZE) -#ifndef CONFIG_PAGING +#ifndef CONFIG_LEGACY_PAGING .file "arm_head.S" diff --git a/arch/arm/src/armv7-a/arm_pghead.S b/arch/arm/src/armv7-a/arm_pghead.S index b0c6533f2f..b2d45c59e5 100644 --- a/arch/arm/src/armv7-a/arm_pghead.S +++ b/arch/arm/src/armv7-a/arm_pghead.S @@ -32,7 +32,7 @@ #include "chip.h" #include "arm_internal.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING .file "arm_pghead.S" @@ -50,7 +50,7 @@ /* The page table cannot be in ROM if we are going to do pagin! */ #ifndef CONFIG_ARCH_ROMPGTABLE -# error CONFIG_PAGING and CONFIG_ARCH_ROMPGTABLE are incompatible options +# error CONFIG_LEGACY_PAGING and CONFIG_ARCH_ROMPGTABLE are incompatible options #endif /* There are three operational memory configurations: diff --git a/arch/arm/src/armv7-a/arm_pginitialize.c b/arch/arm/src/armv7-a/arm_pginitialize.c index 787804f483..3df18ae9fd 100644 --- a/arch/arm/src/armv7-a/arm_pginitialize.c +++ b/arch/arm/src/armv7-a/arm_pginitialize.c @@ -31,7 +31,7 @@ #include "arm_internal.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /**************************************************************************** * Public Functions @@ -65,4 +65,4 @@ void arm_pginitialize(void) */ } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/arch/arm/src/armv7-a/arm_prefetchabort.c b/arch/arm/src/armv7-a/arm_prefetchabort.c index b071b7c14e..0728a69a40 100644 --- a/arch/arm/src/armv7-a/arm_prefetchabort.c +++ b/arch/arm/src/armv7-a/arm_prefetchabort.c @@ -29,7 +29,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include #endif @@ -50,7 +50,7 @@ * ****************************************************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr) { @@ -117,7 +117,7 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr) return regs; } -#else /* CONFIG_PAGING */ +#else /* CONFIG_LEGACY_PAGING */ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr) { @@ -135,4 +135,4 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr) return regs; /* To keep the compiler happy */ } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/arch/arm/src/armv7-a/arm_va2pte.c b/arch/arm/src/armv7-a/arm_va2pte.c index df692ff971..f9dd94a4f2 100644 --- a/arch/arm/src/armv7-a/arm_va2pte.c +++ b/arch/arm/src/armv7-a/arm_va2pte.c @@ -34,7 +34,7 @@ #include "chip.h" #include "arm_internal.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /**************************************************************************** * Public Functions @@ -90,4 +90,4 @@ uint32_t *arm_va2pte(uintptr_t vaddr) return &L2[ndx]; } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/arch/arm/src/armv7-a/mmu.h b/arch/arm/src/armv7-a/mmu.h index 83be9370f6..ff70897209 100644 --- a/arch/arm/src/armv7-a/mmu.h +++ b/arch/arm/src/armv7-a/mmu.h @@ -49,16 +49,16 @@ /* Configuration ************************************************************/ -#if defined(CONFIG_PAGING) || defined(CONFIG_ARCH_ADDRENV) +#if defined(CONFIG_LEGACY_PAGING) || defined(CONFIG_ARCH_ADDRENV) /* Sanity check -- we cannot be using a ROM page table and supporting on- * demand paging. */ #ifdef CONFIG_ARCH_ROMPGTABLE -# error "Cannot support both CONFIG_PAGING/CONFIG_ARCH_ADDRENV and CONFIG_ARCH_ROMPGTABLE" +# error "Cannot support both CONFIG_LEGACY_PAGING/CONFIG_ARCH_ADDRENV and CONFIG_ARCH_ROMPGTABLE" #endif -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ /* MMU CP15 Register Bit Definitions ****************************************/ @@ -654,7 +654,7 @@ /* Virtual Page Table Location **********************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /* Check if the virtual address of the page table has been defined. It * should not be defined: architecture specific logic should suppress * defining PGTABLE_BASE_VADDR unless: (1) it is defined in the NuttX @@ -894,7 +894,7 @@ #define PG_POOL_PGPADDR(ndx) (PG_PAGED_PBASE + ((ndx) << PAGESHIFT)) #define PG_POOL_PGVADDR(ndx) (PG_PAGED_VBASE + ((ndx) << PAGESHIFT)) -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ /**************************************************************************** * Public Types @@ -1053,8 +1053,8 @@ struct page_mapping_s * * Description: * Write several, contiguous L2 page table entries. npages entries will be - * written. This macro is used when CONFIG_PAGING is enable. This case, - * it is used as follows: + * written. This macro is used when CONFIG_LEGACY_PAGING is enable. + * This case, it is used as follows: * * ldr r0, =PGTABLE_L2_BASE_PADDR <-- Address in L2 table * ldr r1, =PG_LOCKED_PBASE <-- Physical page memory address @@ -1083,7 +1083,7 @@ struct page_mapping_s * ****************************************************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING .macro pg_l2map, l2, ppage, npages, mmuflags, tmp b 2f 1: @@ -1116,7 +1116,7 @@ struct page_mapping_s cmp \npages, #0 bgt 1b .endm -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ /**************************************************************************** * Name: pg_l1span @@ -1124,7 +1124,7 @@ struct page_mapping_s * Description: * Write several, contiguous, unmapped, small L1 page table entries. * As many entries will be written as many as needed to span npages. - * This macro is used when CONFIG_PAGING is enable. In this case, + * This macro is used when CONFIG_LEGACY_PAGING is enable. In this case, * it is used as follows: * * ldr r0, =PG_L1_PGTABLE_PADDR <-- Address in the L1 table @@ -1159,7 +1159,7 @@ struct page_mapping_s * ****************************************************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING .macro pg_l1span, l1, l2, npages, ppage, mmuflags, tmp b 2f 1: @@ -1197,7 +1197,7 @@ struct page_mapping_s bgt 1b .endm -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ #endif /* __ASSEMBLY__ */ /**************************************************************************** diff --git a/arch/arm/src/common/arm_internal.h b/arch/arm/src/common/arm_internal.h index f8971cf41c..e229f6190f 100644 --- a/arch/arm/src/common/arm_internal.h +++ b/arch/arm/src/common/arm_internal.h @@ -404,12 +404,12 @@ int arm_securefault(int irq, void *context, void *arg); /* Paging support */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING void arm_pginitialize(void); uint32_t *arm_va2pte(uintptr_t vaddr); -#else /* CONFIG_PAGING */ +#else /* CONFIG_LEGACY_PAGING */ # define arm_pginitialize() -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ /* Exception Handlers */ @@ -424,14 +424,14 @@ uint32_t *arm_undefinedinsn(uint32_t *regs); /* Paging support (and exception handlers) */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING void arm_pginitialize(void); uint32_t *arm_va2pte(uintptr_t vaddr); void arm_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr); -#else /* CONFIG_PAGING */ +#else /* CONFIG_LEGACY_PAGING */ # define arm_pginitialize() void arm_dataabort(uint32_t *regs); -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ /* Exception handlers */ diff --git a/arch/arm/src/imx6/hardware/imx_memorymap.h b/arch/arm/src/imx6/hardware/imx_memorymap.h index 2067a92ca9..e4bba00fbf 100644 --- a/arch/arm/src/imx6/hardware/imx_memorymap.h +++ b/arch/arm/src/imx6/hardware/imx_memorymap.h @@ -923,9 +923,9 @@ * memory to address 0x0000:0000 using both the MMU and the AXI matrix * REMAP register. So no L2 page table is required. * - * 2) If on-demand paging is supported (CONFIG_PAGING=y), than an additional - * L2 page table is needed. This page table will use the remainder of - * the address space. + * 2) If on-demand paging is supported (CONFIG_LEGACY_PAGING=y), than an + * additional L2 page table is needed. This page table will use the + * remainder of the address space. */ #ifndef CONFIG_ARCH_LOWVECTORS @@ -974,7 +974,7 @@ /* Paging L2 page table base addresses * - * NOTE: If CONFIG_PAGING is defined, mmu.h will re-assign the virtual + * NOTE: If CONFIG_LEGACY_PAGING is defined, mmu.h will re-assign the virtual * address of the page table. */ diff --git a/arch/arm/src/imx6/imx_boot.c b/arch/arm/src/imx6/imx_boot.c index 764943cbd7..cb27a2ac49 100644 --- a/arch/arm/src/imx6/imx_boot.c +++ b/arch/arm/src/imx6/imx_boot.c @@ -29,7 +29,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include #endif @@ -111,7 +111,7 @@ static inline void imx_remap(void) ****************************************************************************/ #if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && \ - defined(CONFIG_PAGING) + defined(CONFIG_LEGACY_PAGING) static void imx_vectorpermissions(uint32_t mmuflags) { /* The PTE for the beginning of OCRAM is at the base of the L2 page table */ @@ -215,7 +215,7 @@ static void imx_copyvectorblock(void) uint32_t *end; uint32_t *dest; -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /* If we are using re-mapped vectors in an area that has been marked * read only, then temporarily mark the mapping write-able (non-buffered). */ @@ -241,7 +241,7 @@ static void imx_copyvectorblock(void) *dest++ = *src++; } -#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING) +#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_LEGACY_PAGING) /* Make the vectors read-only, cacheable again */ imx_vectorpermissions(MMU_L2_VECTORFLAGS); diff --git a/arch/arm/src/lpc31xx/lpc31_allocateheap.c b/arch/arm/src/lpc31xx/lpc31_allocateheap.c index 11f7d91530..513eb92bfb 100644 --- a/arch/arm/src/lpc31xx/lpc31_allocateheap.c +++ b/arch/arm/src/lpc31xx/lpc31_allocateheap.c @@ -37,7 +37,7 @@ #include "arm_internal.h" #include "lpc31_memorymap.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include # include "pg_macros.h" #endif @@ -134,7 +134,7 @@ * will let the heap run all the way to the end of SRAM. */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # ifdef PGTABLE_IN_HIGHSRAM # define LPC31_HEAP_VEND (PG_LOCKED_VBASE + PG_TOTAL_VSIZE - PGTABLE_SIZE) # else diff --git a/arch/arm/src/lpc31xx/lpc31_boot.c b/arch/arm/src/lpc31xx/lpc31_boot.c index 9618c2b381..e7a4f3b036 100644 --- a/arch/arm/src/lpc31xx/lpc31_boot.c +++ b/arch/arm/src/lpc31xx/lpc31_boot.c @@ -29,7 +29,7 @@ #include "arm.h" #include "arm_internal.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include # include "pg_macros.h" #endif @@ -71,7 +71,7 @@ static const struct section_mapping_s g_section_mapping[] = { { LPC31_SHADOWSPACE_PSECTION, LPC31_SHADOWSPACE_VSECTION, LPC31_SHADOWSPACE_MMUFLAGS, LPC31_SHADOWSPACE_NSECTIONS}, -#ifndef CONFIG_PAGING /* SRAM is already fully mapped */ +#ifndef CONFIG_LEGACY_PAGING /* SRAM is already fully mapped */ { LPC31_INTSRAM_PSECTION, LPC31_INTSRAM_VSECTION, LPC31_INTSRAM_MMUFLAGS, LPC31_INTSRAM_NSECTIONS}, #endif @@ -188,7 +188,7 @@ static void up_setupmappings(void) * ****************************************************************************/ -#if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING) +#if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_LEGACY_PAGING) static void up_vectorpermissions(uint32_t mmuflags) { /* The PTE for the beginning of ISRAM is at the base of the L2 page table */ @@ -281,7 +281,7 @@ static void up_copyvectorblock(void) */ #if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && \ - defined(CONFIG_PAGING) + defined(CONFIG_LEGACY_PAGING) up_vectorpermissions(MMU_L2_VECTRWFLAGS); #endif @@ -306,7 +306,7 @@ static void up_copyvectorblock(void) /* Make the vectors read-only, cacheable again */ -#if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING) +#if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_LEGACY_PAGING) up_vectorpermissions(MMU_L2_VECTROFLAGS); #endif diff --git a/arch/arm/src/lpc31xx/lpc31_memorymap.h b/arch/arm/src/lpc31xx/lpc31_memorymap.h index 53c95c5f02..93631b4c70 100644 --- a/arch/arm/src/lpc31xx/lpc31_memorymap.h +++ b/arch/arm/src/lpc31xx/lpc31_memorymap.h @@ -243,7 +243,7 @@ #elif defined(CONFIG_BOOT_RUNFROMEXTSRAM) # define NUTTX_START_VADDR LPC31_EXTSRAM0_VADDR # define NUTTX_START_PADDR LPC31_EXTSRAM0_PADDR -#else /* CONFIG_BOOT_RUNFROMISRAM, CONFIG_PAGING */ +#else /* CONFIG_BOOT_RUNFROMISRAM, CONFIG_LEGACY_PAGING */ # define NUTTX_START_VADDR LPC31_INTSRAM0_VADDR # define NUTTX_START_PADDR LPC31_INTSRAM0_PADDR #endif @@ -277,18 +277,18 @@ # error "CONFIG_ARCH_ROMPGTABLE defined; PGTABLE_BASE_P/VADDR not defined" # else -/* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory - * map probably do not apply because paging logic will probably partition - * the SRAM section differently. In particular, if the page table is located - * at the end of SRAM, then the virtual page table address defined below - * will probably be in error. +/* If CONFIG_LEGACY_PAGING is selected, then parts of the 1-to-1 virtual + * memory map probably do not apply because paging logic will probably + * partition the SRAM section differently. In particular, if the page + * table is located at the end of SRAM, then the virtual page table address + * defined below will probably be in error. * * We work around this header file interdependency by (1) insisting that * pg_macros.h be included AFTER this header file, then (2) allowing the * pg_macros.h header file to redefine PGTABLE_BASE_VADDR. */ -# if defined(CONFIG_PAGING) && defined(__ARCH_ARM_SRC_ARM_PG_MACROS_H) +# if defined(CONFIG_LEGACY_PAGING) && defined(__ARCH_ARM_SRC_ARM_PG_MACROS_H) # error "pg_macros.h must be included AFTER this header file" # endif @@ -312,11 +312,11 @@ # endif # define PGTABLE_IN_HIGHSRAM 1 -/* If CONFIG_PAGING is defined, insist that pg_macros.h assign the virtual +/* If CONFIG_LEGACY_PAGING is defined, insist that pg_macros.h assign the * address of the page table. */ -# ifdef CONFIG_PAGING +# ifdef CONFIG_LEGACY_PAGING # undef PGTABLE_BASE_VADDR # endif # else @@ -341,8 +341,8 @@ * (for normal operation). We will reuse this memory for coarse page tables * as follows: * - * NOTE: If CONFIG_PAGING is defined, pg_macros.h will re-assign the virtual - * address of the page table. + * NOTE: If CONFIG_LEGACY_PAGING is defined, pg_macros.h will re-assign the + * virtual address of the page table. */ #define PGTABLE_L2_COARSE_OFFSET ((((LPC31_LAST_PSECTION >> 20) + 255) & ~255) << 2) diff --git a/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h b/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h index e5b870e5a6..3e527cb707 100644 --- a/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h +++ b/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h @@ -664,12 +664,12 @@ # error "CONFIG_ARCH_ROMPGTABLE defined; PGTABLE_BASE_P/VADDR not defined" # endif -/* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory - * map probably do not apply because paging logic will probably partition - * the SRAM section differently. In particular, if the page table is located - * at the end of SRAM, then the virtual page table address defined below - * will probably be in error. In that case PGTABLE_BASE_VADDR is defined - * in the file mmu.h +/* If CONFIG_LEGACY_PAGING is selected, then parts of the 1-to-1 virtual + * memory map probably do not apply because paging logic will probably + * partition the SRAM section differently. In particular, if the page + * table is located at the end of SRAM, then the virtual page table address + * defined below will probably be in error. In that case PGTABLE_BASE_VADDR + * is defined in the file mmu.h * * We must declare the page table at the bottom or at the top of internal * SRAM. We pick the bottom of internal SRAM *unless* there are vectors @@ -681,18 +681,18 @@ /* In this case, page table must lie at the top 16Kb of ISRAM1 (or ISRAM0 * if ISRAM1 is not available in this architecture) * - * If CONFIG_PAGING is defined, then mmu.h assign the virtual address - * of the page table. + * If CONFIG_LEGACY_PAGING is defined, then mmu.h assign the virtual + * address of the page table. */ # if SAM_ISRAM1_SIZE > 0 # define PGTABLE_BASE_PADDR (SAM_ISRAM1_PADDR+SAM_ISRAM1_SIZE-PGTABLE_SIZE) -# ifndef CONFIG_PAGING +# ifndef CONFIG_LEGACY_PAGING # define PGTABLE_BASE_VADDR (SAM_ISRAM1_VADDR+SAM_ISRAM1_SIZE-PGTABLE_SIZE) # endif # else # define PGTABLE_BASE_PADDR (SAM_ISRAM0_PADDR+SAM_ISRAM0_SIZE-PGTABLE_SIZE) -# ifndef CONFIG_PAGING +# ifndef CONFIG_LEGACY_PAGING # define PGTABLE_BASE_VADDR (SAM_ISRAM0_VADDR+SAM_ISRAM0_SIZE-PGTABLE_SIZE) # endif # endif @@ -721,7 +721,7 @@ */ # define PGTABLE_BASE_PADDR SAM_ISRAM0_PADDR -# ifndef CONFIG_PAGING +# ifndef CONFIG_LEGACY_PAGING # define PGTABLE_BASE_VADDR SAM_ISRAM0_VADDR # endif # define PGTABLE_IN_LOWSRAM 1 @@ -803,9 +803,9 @@ * memory to address 0x0000:0000 using both the MMU and the AXI matrix * REMAP register. So no L2 page table is required. * - * 2) If on-demand paging is supported (CONFIG_PAGING=y), than an additional - * L2 page table is needed. This page table will use the remainder of - * the address space. + * 2) If on-demand paging is supported (CONFIG_LEGACY_PAGING=y), than an + * additional L2 page table is needed. This page table will use the + * remainder of the address space. */ #ifndef CONFIG_ARCH_LOWVECTORS @@ -838,7 +838,7 @@ /* Paging L2 page table base addresses * - * NOTE: If CONFIG_PAGING is defined, mmu.h will re-assign the virtual + * NOTE: If CONFIG_LEGACY_PAGING is defined, mmu.h will re-assign the virtual * address of the page table. */ diff --git a/arch/arm/src/sama5/hardware/_sama5d3x_memorymap.h b/arch/arm/src/sama5/hardware/_sama5d3x_memorymap.h index 796e21d564..3f4b5140e1 100644 --- a/arch/arm/src/sama5/hardware/_sama5d3x_memorymap.h +++ b/arch/arm/src/sama5/hardware/_sama5d3x_memorymap.h @@ -572,12 +572,12 @@ # error "CONFIG_ARCH_ROMPGTABLE defined; PGTABLE_BASE_P/VADDR not defined" # endif -/* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory - * map probably do not apply because paging logic will probably partition - * the SRAM section differently. In particular, if the page table is located - * at the end of SRAM, then the virtual page table address defined below - * will probably be in error. In that case PGTABLE_BASE_VADDR is defined - * in the file mmu.h +/* If CONFIG_LEGACY_PAGING is selected, then parts of the 1-to-1 virtual + * memory map probably do not apply because paging logic will probably + * partition the SRAM section differently. In particular, if the page + * table is located at the end of SRAM, then the virtual page table address + * defined below will probably be in error. In that case PGTABLE_BASE_VADDR + * is defined in the file mmu.h * * We must declare the page table at the bottom or at the top of internal * SRAM. We pick the bottom of internal SRAM *unless* there are vectors @@ -589,18 +589,18 @@ /* In this case, page table must lie at the top 16Kb of ISRAM1 (or ISRAM0 * if ISRAM1 is not available in this architecture) * - * If CONFIG_PAGING is defined, then mmu.h assign the virtual address + * If CONFIG_LEGACY_PAGING is defined, then mmu.h assign the virtual address * of the page table. */ # if SAM_ISRAM1_SIZE > 0 # define PGTABLE_BASE_PADDR (SAM_ISRAM1_PADDR+SAM_ISRAM1_SIZE-PGTABLE_SIZE) -# ifndef CONFIG_PAGING +# ifndef CONFIG_LEGACY_PAGING # define PGTABLE_BASE_VADDR (SAM_ISRAM1_VADDR+SAM_ISRAM1_SIZE-PGTABLE_SIZE) # endif # else # define PGTABLE_BASE_PADDR (SAM_ISRAM0_PADDR+SAM_ISRAM0_SIZE-PGTABLE_SIZE) -# ifndef CONFIG_PAGING +# ifndef CONFIG_LEGACY_PAGING # define PGTABLE_BASE_VADDR (SAM_ISRAM0_VADDR+SAM_ISRAM0_SIZE-PGTABLE_SIZE) # endif # endif @@ -629,7 +629,7 @@ */ # define PGTABLE_BASE_PADDR SAM_ISRAM0_PADDR -# ifndef CONFIG_PAGING +# ifndef CONFIG_LEGACY_PAGING # define PGTABLE_BASE_VADDR SAM_ISRAM0_VADDR # endif # define PGTABLE_IN_LOWSRAM 1 @@ -711,7 +711,7 @@ * boot memory to address 0x0000:0000 using both the MMU and the AXI * matrix REMAP register. So no L2 page table is required. * - * 2) If on-demand paging is supported (CONFIG_PAGING=y), than an + * 2) If on-demand paging is supported (CONFIG_LEGACY_PAGING=y), than an * additional L2 page table is needed. * This page table will use the remainder of the address space. */ @@ -746,7 +746,7 @@ /* Paging L2 page table base addresses * - * NOTE: If CONFIG_PAGING is defined, mmu.h will re-assign the virtual + * NOTE: If CONFIG_LEGACY_PAGING is defined, mmu.h will re-assign the virtual * address of the page table. */ diff --git a/arch/arm/src/sama5/hardware/_sama5d4x_memorymap.h b/arch/arm/src/sama5/hardware/_sama5d4x_memorymap.h index 7945a42ed7..d8639ae75d 100644 --- a/arch/arm/src/sama5/hardware/_sama5d4x_memorymap.h +++ b/arch/arm/src/sama5/hardware/_sama5d4x_memorymap.h @@ -562,12 +562,12 @@ # error "CONFIG_ARCH_ROMPGTABLE defined; PGTABLE_BASE_P/VADDR not defined" # endif -/* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory - * map probably do not apply because paging logic will probably partition - * the SRAM section differently. In particular, if the page table is located - * at the end of SRAM, then the virtual page table address defined below - * will probably be in error. In that case PGTABLE_BASE_VADDR is defined - * in the file mmu.h +/* If CONFIG_LEGACY_PAGING is selected, then parts of the 1-to-1 virtual + * memory map probably do not apply because paging logic will probably + * partition the SRAM section differently. In particular, if the page + * table is located at the end of SRAM, then the virtual page table address + * defined below will probably be in error. In that case PGTABLE_BASE_VADDR + * is defined in the file mmu.h * * We must declare the page table at the bottom or at the top of internal * SRAM. We pick the bottom of internal SRAM *unless* there are vectors @@ -579,18 +579,18 @@ /* In this case, page table must lie at the top 16Kb of ISRAM1 (or ISRAM0 * if ISRAM1 is not available in this architecture) * - * If CONFIG_PAGING is defined, then mmu.h assign the virtual address + * If CONFIG_LEGACY_PAGING is defined, then mmu.h assign the virtual address * of the page table. */ # if SAM_ISRAM1_SIZE > 0 # define PGTABLE_BASE_PADDR (SAM_ISRAM1_PADDR+SAM_ISRAM1_SIZE-PGTABLE_SIZE) -# ifndef CONFIG_PAGING +# ifndef CONFIG_LEGACY_PAGING # define PGTABLE_BASE_VADDR (SAM_ISRAM1_VADDR+SAM_ISRAM1_SIZE-PGTABLE_SIZE) # endif # else # define PGTABLE_BASE_PADDR (SAM_ISRAM0_PADDR+SAM_ISRAM0_SIZE-PGTABLE_SIZE) -# ifndef CONFIG_PAGING +# ifndef CONFIG_LEGACY_PAGING # define PGTABLE_BASE_VADDR (SAM_ISRAM0_VADDR+SAM_ISRAM0_SIZE-PGTABLE_SIZE) # endif # endif @@ -619,7 +619,7 @@ */ # define PGTABLE_BASE_PADDR SAM_ISRAM0_PADDR -# ifndef CONFIG_PAGING +# ifndef CONFIG_LEGACY_PAGING # define PGTABLE_BASE_VADDR SAM_ISRAM0_VADDR # endif # define PGTABLE_IN_LOWSRAM 1 @@ -703,9 +703,9 @@ * memory to address 0x0000:0000 using both the MMU and the AXI matrix * REMAP register. So no L2 page table is required. * - * 2) If on-demand paging is supported (CONFIG_PAGING=y), than an additional - * L2 page table is needed. This page table will use the remainder of - * the address space. + * 2) If on-demand paging is supported (CONFIG_LEGACY_PAGING=y), than an + * additional L2 page table is needed. This page table will use the + * remainder of the address space. */ #ifndef CONFIG_ARCH_LOWVECTORS @@ -738,7 +738,7 @@ /* Paging L2 page table base addresses * - * NOTE: If CONFIG_PAGING is defined, mmu.h will re-assign the virtual + * NOTE: If CONFIG_LEGACY_PAGING is defined, mmu.h will re-assign the virtual * address of the page table. */ diff --git a/arch/arm/src/sama5/sam_boot.c b/arch/arm/src/sama5/sam_boot.c index 7efbb28f8e..b3c2524656 100644 --- a/arch/arm/src/sama5/sam_boot.c +++ b/arch/arm/src/sama5/sam_boot.c @@ -29,7 +29,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include #endif @@ -102,7 +102,7 @@ static inline void sam_remap(void) ****************************************************************************/ #if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && \ - defined(CONFIG_PAGING) + defined(CONFIG_LEGACY_PAGING) static void sam_vectorpermissions(uint32_t mmuflags) { /* The PTE for the beginning of ISRAM is at the base of the L2 page table */ @@ -217,7 +217,7 @@ static void sam_copyvectorblock(void) uint32_t *end; uint32_t *dest; -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /* If we are using re-mapped vectors in an area that has been marked * read only, then temporarily mark the mapping write-able (non-buffered). */ @@ -243,7 +243,7 @@ static void sam_copyvectorblock(void) *dest++ = *src++; } -#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING) +#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_LEGACY_PAGING) /* Make the vectors read-only, cacheable again */ sam_vectorpermissions(MMU_L2_VECTORFLAGS); diff --git a/arch/arm/src/sama5/sama5d2x_memorymap.c b/arch/arm/src/sama5/sama5d2x_memorymap.c index 3e5ce8feb7..76b8dea231 100644 --- a/arch/arm/src/sama5/sama5d2x_memorymap.c +++ b/arch/arm/src/sama5/sama5d2x_memorymap.c @@ -97,7 +97,7 @@ const struct section_mapping_s g_section_mapping[] = SAM_NFCSRAM_MMUFLAGS, SAM_NFCSRAM_NSECTIONS }, -#ifndef CONFIG_PAGING /* Internal SRAM is already fully mapped */ +#ifndef CONFIG_LEGACY_PAGING /* Internal SRAM is already fully mapped */ { SAM_ISRAM_PSECTION, SAM_ISRAM_VSECTION, SAM_ISRAM_MMUFLAGS, SAM_ISRAM_NSECTIONS }, diff --git a/arch/arm/src/sama5/sama5d3x_memorymap.c b/arch/arm/src/sama5/sama5d3x_memorymap.c index 5916f0447b..59a13169de 100644 --- a/arch/arm/src/sama5/sama5d3x_memorymap.c +++ b/arch/arm/src/sama5/sama5d3x_memorymap.c @@ -110,7 +110,7 @@ const struct section_mapping_s g_section_mapping[] = SAM_NFCSRAM_MMUFLAGS, SAM_NFCSRAM_NSECTIONS }, -#ifndef CONFIG_PAGING /* Internal SRAM is already fully mapped */ +#ifndef CONFIG_LEGACY_PAGING /* Internal SRAM is already fully mapped */ { SAM_ISRAM_PSECTION, SAM_ISRAM_VSECTION, SAM_ISRAM_MMUFLAGS, SAM_ISRAM_NSECTIONS }, diff --git a/arch/arm/src/sama5/sama5d4x_memorymap.c b/arch/arm/src/sama5/sama5d4x_memorymap.c index 914d311682..5c32bb608b 100644 --- a/arch/arm/src/sama5/sama5d4x_memorymap.c +++ b/arch/arm/src/sama5/sama5d4x_memorymap.c @@ -110,7 +110,7 @@ const struct section_mapping_s g_section_mapping[] = SAM_NFCSRAM_MMUFLAGS, SAM_NFCSRAM_NSECTIONS }, -#ifndef CONFIG_PAGING /* Internal SRAM is already fully mapped */ +#ifndef CONFIG_LEGACY_PAGING /* Internal SRAM is already fully mapped */ { SAM_ISRAM_PSECTION, SAM_ISRAM_VSECTION, SAM_ISRAM_MMUFLAGS, SAM_ISRAM_NSECTIONS }, diff --git a/arch/arm64/include/irq.h b/arch/arm64/include/irq.h index ccaf44e1b5..ffba10d75a 100644 --- a/arch/arm64/include/irq.h +++ b/arch/arm64/include/irq.h @@ -254,7 +254,7 @@ struct xcptcontext * address register (FAR) at the time of data abort exception. */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING uintptr_t far; #endif diff --git a/arch/arm64/src/a64/a64_boot.c b/arch/arm64/src/a64/a64_boot.c index fc7c2eb15b..fc9f212243 100644 --- a/arch/arm64/src/a64/a64_boot.c +++ b/arch/arm64/src/a64/a64_boot.c @@ -29,7 +29,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include #endif diff --git a/arch/arm64/src/common/arm64_internal.h b/arch/arm64/src/common/arm64_internal.h index a1a98d456f..bd8bfe0d26 100644 --- a/arch/arm64/src/common/arm64_internal.h +++ b/arch/arm64/src/common/arm64_internal.h @@ -299,11 +299,11 @@ uint64_t *arm64_doirq(int irq, uint64_t *regs); /* Paging support */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING void arm64_pginitialize(void); -#else /* CONFIG_PAGING */ +#else /* CONFIG_LEGACY_PAGING */ # define arm64_pginitialize() -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ uint64_t * arm64_syscall_switch(uint64_t *regs); int arm64_syscall(uint64_t *regs); diff --git a/arch/arm64/src/goldfish/goldfish_boot.c b/arch/arm64/src/goldfish/goldfish_boot.c index bc9ce37ae2..aac71e1a2d 100644 --- a/arch/arm64/src/goldfish/goldfish_boot.c +++ b/arch/arm64/src/goldfish/goldfish_boot.c @@ -29,7 +29,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include #endif diff --git a/arch/arm64/src/imx8/imx8_boot.c b/arch/arm64/src/imx8/imx8_boot.c index 5d383430fc..62e6b1f0fd 100644 --- a/arch/arm64/src/imx8/imx8_boot.c +++ b/arch/arm64/src/imx8/imx8_boot.c @@ -29,7 +29,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include #endif diff --git a/arch/arm64/src/qemu/qemu_boot.c b/arch/arm64/src/qemu/qemu_boot.c index e9e28ec574..151a7101a3 100644 --- a/arch/arm64/src/qemu/qemu_boot.c +++ b/arch/arm64/src/qemu/qemu_boot.c @@ -29,7 +29,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include #endif diff --git a/arch/arm64/src/rk3399/rk3399_boot.c b/arch/arm64/src/rk3399/rk3399_boot.c index 85cdb6f8ba..3d77452d03 100644 --- a/arch/arm64/src/rk3399/rk3399_boot.c +++ b/arch/arm64/src/rk3399/rk3399_boot.c @@ -29,7 +29,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include #endif diff --git a/boards/arm/lpc31xx/ea3131/configs/pgnsh/defconfig b/boards/arm/lpc31xx/ea3131/configs/pgnsh/defconfig index cf80de95b2..0aa1a3e572 100644 --- a/boards/arm/lpc31xx/ea3131/configs/pgnsh/defconfig +++ b/boards/arm/lpc31xx/ea3131/configs/pgnsh/defconfig @@ -19,9 +19,10 @@ CONFIG_BOARD_LOOPSPERMSEC=16945 CONFIG_BOOT_RUNFROMISRAM=y CONFIG_BUILD_2PASS=y CONFIG_DEFAULT_SMALL=y +CONFIG_EXPERIMENTAL=y CONFIG_FS_FAT=y -CONFIG_HOST_WINDOWS=y CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LEGACY_PAGING=y CONFIG_LPC31_SPI=y CONFIG_LPC31_UART=y CONFIG_M25P_SPIMODE=3 @@ -29,7 +30,6 @@ CONFIG_MMCSD=y CONFIG_MTD=y CONFIG_MTD_M25P=y CONFIG_NSH_ARCHINIT=y -CONFIG_PAGING=y CONFIG_PAGING_BLOCKINGFILL=y CONFIG_PAGING_NDATA=32 CONFIG_PAGING_NPPAGED=96 diff --git a/boards/arm/lpc31xx/ea3131/src/Makefile b/boards/arm/lpc31xx/ea3131/src/Makefile index 1a3cdaee01..c1217fb5d2 100644 --- a/boards/arm/lpc31xx/ea3131/src/Makefile +++ b/boards/arm/lpc31xx/ea3131/src/Makefile @@ -42,7 +42,7 @@ ifeq ($(CONFIG_BOARDCTL),y) CSRCS += lpc31_appinit.c endif -ifeq ($(CONFIG_PAGING),y) +ifeq ($(CONFIG_LEGACY_PAGING),y) CSRCS += lpc31_fillpage.c endif diff --git a/boards/arm/lpc31xx/ea3131/src/ea3131.h b/boards/arm/lpc31xx/ea3131/src/ea3131.h index cb3f253462..4d2d4e7f54 100644 --- a/boards/arm/lpc31xx/ea3131/src/ea3131.h +++ b/boards/arm/lpc31xx/ea3131/src/ea3131.h @@ -133,7 +133,7 @@ int lpc31_usbhost_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING void weak_function lpc31_pginitialize(void); #endif diff --git a/boards/arm/lpc31xx/ea3131/src/lpc31_boot.c b/boards/arm/lpc31xx/ea3131/src/lpc31_boot.c index 3d3b939813..52fa4207fb 100644 --- a/boards/arm/lpc31xx/ea3131/src/lpc31_boot.c +++ b/boards/arm/lpc31xx/ea3131/src/lpc31_boot.c @@ -108,7 +108,7 @@ void lpc31_boardinitialize(void) /* Set up mass storage device to support on demand paging */ -#if defined(CONFIG_PAGING) +#if defined(CONFIG_LEGACY_PAGING) if (lpc31_pginitialize) { lpc31_pginitialize(); diff --git a/boards/arm/lpc31xx/ea3131/src/lpc31_fillpage.c b/boards/arm/lpc31xx/ea3131/src/lpc31_fillpage.c index 95d04f9071..f06e7aceb0 100644 --- a/boards/arm/lpc31xx/ea3131/src/lpc31_fillpage.c +++ b/boards/arm/lpc31xx/ea3131/src/lpc31_fillpage.c @@ -31,7 +31,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING #ifdef CONFIG_PAGING_BINPATH # include # include @@ -520,4 +520,4 @@ void weak_function lpc31_pginitialize(void) */ } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/boards/arm/lpc31xx/ea3152/src/Makefile b/boards/arm/lpc31xx/ea3152/src/Makefile index 204429c316..c42caa3d0d 100644 --- a/boards/arm/lpc31xx/ea3152/src/Makefile +++ b/boards/arm/lpc31xx/ea3152/src/Makefile @@ -36,7 +36,7 @@ endif ifeq ($(CONFIG_BOARDCTL),y) CSRCS += lpc31_appinit.c endif -ifeq ($(CONFIG_PAGING),y) +ifeq ($(CONFIG_LEGACY_PAGING),y) CSRCS += lpc31_fillpage.c endif diff --git a/boards/arm/lpc31xx/ea3152/src/ea3152.h b/boards/arm/lpc31xx/ea3152/src/ea3152.h index 576a72e04b..acb76da85a 100644 --- a/boards/arm/lpc31xx/ea3152/src/ea3152.h +++ b/boards/arm/lpc31xx/ea3152/src/ea3152.h @@ -103,7 +103,7 @@ void weak_function lpc31_usbinitialize(void); * ****************************************************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING void weak_function lpc31_pginitialize(void); #endif diff --git a/boards/arm/lpc31xx/ea3152/src/lpc31_boot.c b/boards/arm/lpc31xx/ea3152/src/lpc31_boot.c index 8a1bfeb1b4..c6fc1e34f7 100644 --- a/boards/arm/lpc31xx/ea3152/src/lpc31_boot.c +++ b/boards/arm/lpc31xx/ea3152/src/lpc31_boot.c @@ -95,7 +95,7 @@ void lpc31_boardinitialize(void) /* Set up mass storage device to support on demand paging */ -#if defined(CONFIG_PAGING) +#if defined(CONFIG_LEGACY_PAGING) if (lpc31_pginitialize) { lpc31_pginitialize(); diff --git a/boards/arm/lpc31xx/ea3152/src/lpc31_fillpage.c b/boards/arm/lpc31xx/ea3152/src/lpc31_fillpage.c index a5e214c94f..46bb94187f 100644 --- a/boards/arm/lpc31xx/ea3152/src/lpc31_fillpage.c +++ b/boards/arm/lpc31xx/ea3152/src/lpc31_fillpage.c @@ -31,7 +31,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING #ifdef CONFIG_PAGING_BINPATH # include # include @@ -523,4 +523,4 @@ void weak_function lpc31_pginitialize(void) */ } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/include/nuttx/page.h b/include/nuttx/page.h index 2971e14fb6..adce1c2ddb 100644 --- a/include/nuttx/page.h +++ b/include/nuttx/page.h @@ -33,7 +33,7 @@ # include #endif -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /**************************************************************************** * Pre-processor Definitions @@ -455,5 +455,5 @@ int up_fillpage(FAR struct tcb_s *tcb, FAR void *vpage, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ #endif /* __INCLUDE_NUTTX_PAGE_H */ diff --git a/include/nuttx/sched.h b/include/nuttx/sched.h index 820436669d..059bd5b06d 100644 --- a/include/nuttx/sched.h +++ b/include/nuttx/sched.h @@ -226,7 +226,7 @@ enum tstate_e TSTATE_WAIT_MQNOTEMPTY, /* BLOCKED - Waiting for a MQ to become not empty. */ TSTATE_WAIT_MQNOTFULL, /* BLOCKED - Waiting for a MQ to become not full. */ #endif -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING TSTATE_WAIT_PAGEFILL, /* BLOCKED - Waiting for page fill */ #endif #ifdef CONFIG_SIG_SIGSTOP_ACTION diff --git a/sched/init/init.h b/sched/init/init.h index 1e389b5cd0..31d3357728 100644 --- a/sched/init/init.h +++ b/sched/init/init.h @@ -97,8 +97,8 @@ void nx_idle_trampoline(void); * the conclusion of basic OS initialization. These initial system tasks * may include: * - * - pg_worker: The page-fault worker thread (only if CONFIG_PAGING is - * defined. + * - pg_worker: The page-fault worker thread (if CONFIG_LEGACY_PAGING is + * defined). * - work_thread: The work thread. This general thread can be used to * perform most any kind of queued work. Its primary * function is to serve as the "bottom half" of device diff --git a/sched/init/nx_bringup.c b/sched/init/nx_bringup.c index b9922eb3b6..c1944a45be 100644 --- a/sched/init/nx_bringup.c +++ b/sched/init/nx_bringup.c @@ -42,7 +42,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include "paging/paging.h" #endif @@ -151,7 +151,7 @@ extern const unsigned int romfs_img_len; * ****************************************************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING static inline void nx_pgworker(void) { /* Start the page fill worker kernel thread that will resolve page faults. @@ -167,10 +167,10 @@ static inline void nx_pgworker(void) DEBUGASSERT(g_pgworker > 0); } -#else /* CONFIG_PAGING */ +#else /* CONFIG_LEGACY_PAGING */ # define nx_pgworker() -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ /**************************************************************************** * Name: nx_workqueues @@ -456,8 +456,8 @@ static inline void nx_create_initthread(void) * the conclusion of basic OS initialization. These initial system tasks * may include: * - * - pg_worker: The page-fault worker thread (only if CONFIG_PAGING is - * defined. + * - pg_worker: The page-fault worker thread (if CONFIG_LEGACY_PAGING is + * defined). * - work_thread: The work thread. This general thread can be used to * perform most any kind of queued work. Its primary * function is to serve as the "bottom half" of device diff --git a/sched/init/nx_start.c b/sched/init/nx_start.c index 98a5f1cfb7..8b9c411ecf 100644 --- a/sched/init/nx_start.c +++ b/sched/init/nx_start.c @@ -142,7 +142,7 @@ dq_queue_t g_pendingtasks; dq_queue_t g_waitingforsignal; -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /* This is the list of all tasks that are blocking waiting for a page fill */ dq_queue_t g_waitingforfill; @@ -239,7 +239,7 @@ const struct tasklist_s g_tasklisttable[NUM_TASK_STATES] = TLIST_ATTR_PRIORITIZED | TLIST_ATTR_OFFSET } #endif -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING , { /* TSTATE_WAIT_PAGEFILL */ &g_waitingforfill, diff --git a/sched/paging/CMakeLists.txt b/sched/paging/CMakeLists.txt index 2130aaeb20..5504143b9d 100644 --- a/sched/paging/CMakeLists.txt +++ b/sched/paging/CMakeLists.txt @@ -18,7 +18,7 @@ # # ############################################################################## -if(CONFIG_PAGING) +if(CONFIG_LEGACY_PAGING) target_sources(sched PRIVATE pg_miss.c pg_worker.c) diff --git a/sched/paging/Make.defs b/sched/paging/Make.defs index f609926bb9..b717d1c25e 100644 --- a/sched/paging/Make.defs +++ b/sched/paging/Make.defs @@ -18,7 +18,7 @@ # ############################################################################ -ifeq ($(CONFIG_PAGING),y) +ifeq ($(CONFIG_LEGACY_PAGING),y) CSRCS += pg_miss.c pg_worker.c diff --git a/sched/paging/paging.h b/sched/paging/paging.h index 948713d09e..84caa49b46 100644 --- a/sched/paging/paging.h +++ b/sched/paging/paging.h @@ -29,7 +29,7 @@ #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /**************************************************************************** * Pre-processor Definitions @@ -102,5 +102,5 @@ extern FAR struct tcb_s *g_pftcb; int pg_worker(int argc, FAR char *argv[]); #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ #endif /* __SCHED_PAGING_PAGING_H */ diff --git a/sched/paging/pg_miss.c b/sched/paging/pg_miss.c index f6c9260edf..707b9f3b4d 100644 --- a/sched/paging/pg_miss.c +++ b/sched/paging/pg_miss.c @@ -33,7 +33,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING #include "sched/sched.h" #include "paging/paging.h" @@ -183,4 +183,4 @@ void pg_miss(void) } } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/sched/paging/pg_worker.c b/sched/paging/pg_worker.c index 4e11d00f24..9e6f4824e9 100644 --- a/sched/paging/pg_worker.c +++ b/sched/paging/pg_worker.c @@ -42,7 +42,7 @@ #include "sched/sched.h" #include "paging/paging.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /**************************************************************************** * Public Data @@ -693,4 +693,4 @@ int pg_worker(int argc, FAR char *argv[]) return OK; /* To keep some compilers happy */ } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/sched/sched/sched.h b/sched/sched/sched.h index 9057f86f91..37aed2d4c7 100644 --- a/sched/sched/sched.h +++ b/sched/sched/sched.h @@ -194,7 +194,7 @@ extern dq_queue_t g_waitingforsignal; /* This is the list of all tasks that are blocking waiting for a page fill */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING extern dq_queue_t g_waitingforfill; #endif diff --git a/sched/sched/sched_get_stateinfo.c b/sched/sched/sched_get_stateinfo.c index b2105431a1..e8c3a00909 100644 --- a/sched/sched/sched_get_stateinfo.c +++ b/sched/sched/sched_get_stateinfo.c @@ -53,7 +53,7 @@ static FAR const char * const g_statenames[] = , "Waiting,MQ empty" , "Waiting,MQ full" #endif -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING , "Waiting,Paging fill" #endif #ifdef CONFIG_SIG_SIGSTOP_ACTION