diff --git a/arch/arm/include/samd5e5/samd5e5_irq.h b/arch/arm/include/samd5e5/samd5e5_irq.h index e3fe951d7f..77b0dbb12a 100644 --- a/arch/arm/include/samd5e5/samd5e5_irq.h +++ b/arch/arm/include/samd5e5/samd5e5_irq.h @@ -86,8 +86,8 @@ #define SAM_IRQ_EXTINT14 (SAM_IRQ_EXTINT + 26) /* 26 EIC: EXTINT14 */ #define SAM_IRQ_EXTINT15 (SAM_IRQ_EXTINT + 27) /* 27 EIC: EXTINT15 */ #define SAM_IRQ_FREQM (SAM_IRQ_EXTINT + 28) /* 28 FREQM: Done */ -#define SAM_IRQ_NVMCTRL0 (SAM_IRQ_EXTINT + 29) /* 29 NVMCTRL: 0-7 */ -#define SAM_IRQ_NVMCTRL1 (SAM_IRQ_EXTINT + 30) /* 30 NVMCTRL: 8-10 */ +#define SAM_IRQ_NVMCTRL0 (SAM_IRQ_EXTINT + 29) /* 29 NVMCTRL: INTFLAG[0-7] */ +#define SAM_IRQ_NVMCTRL1 (SAM_IRQ_EXTINT + 30) /* 30 NVMCTRL: INTFLAG[8-10] */ #define SAM_IRQ_DMACH0 (SAM_IRQ_EXTINT + 31) /* 31 DMA Channel 0: SUSP, TCMPL, TERR */ #define SAM_IRQ_DMACH1 (SAM_IRQ_EXTINT + 32) /* 32 DMA Channel 1: SUSP, TCMPL, TERR */ #define SAM_IRQ_DMACH2 (SAM_IRQ_EXTINT + 33) /* 33 DMA Channel 2: SUSP, TCMPL, TERR */ @@ -100,38 +100,38 @@ #define SAM_IRQ_EVSYS4_11 (SAM_IRQ_EXTINT + 40) /* 40 EVSYS Channels 4-11: EVD, OVR */ #define SAM_IRQ_PAC (SAM_IRQ_EXTINT + 41) /* 41 PAC: ERR */ #define SAM_IRQ_RAMECC (SAM_IRQ_EXTINT + 45) /* 45 RAM ECC: 0-1 */ -#define SAM_IRQ_SERCOM0_0 (SAM_IRQ_EXTINT + 46) /* 46 SERCOM0: 0 */ -#define SAM_IRQ_SERCOM0_1 (SAM_IRQ_EXTINT + 47) /* 47 SERCOM0: 1 */ -#define SAM_IRQ_SERCOM0_2 (SAM_IRQ_EXTINT + 48) /* 48 SERCOM0: 2 */ -#define SAM_IRQ_SERCOM0_46 (SAM_IRQ_EXTINT + 49) /* 49 SERCOM0: 4-6 */ -#define SAM_IRQ_SERCOM1_0 (SAM_IRQ_EXTINT + 50) /* 50 SERCOM1: 0 */ -#define SAM_IRQ_SERCOM1_1 (SAM_IRQ_EXTINT + 51) /* 51 SERCOM1: 1 */ -#define SAM_IRQ_SERCOM1_2 (SAM_IRQ_EXTINT + 52) /* 52 SERCOM1: 2 */ -#define SAM_IRQ_SERCOM1_46 (SAM_IRQ_EXTINT + 53) /* 53 SERCOM1: 4-6 */ -#define SAM_IRQ_SERCOM2_0 (SAM_IRQ_EXTINT + 54) /* 54 SERCOM2: 0 */ -#define SAM_IRQ_SERCOM2_1 (SAM_IRQ_EXTINT + 55) /* 55 SERCOM2: 1 */ -#define SAM_IRQ_SERCOM2_2 (SAM_IRQ_EXTINT + 56) /* 56 SERCOM2: 2 */ -#define SAM_IRQ_SERCOM2_46 (SAM_IRQ_EXTINT + 57) /* 57 SERCOM2: 4-6 */ -#define SAM_IRQ_SERCOM3_0 (SAM_IRQ_EXTINT + 58) /* 58 SERCOM3: 0 */ -#define SAM_IRQ_SERCOM3_1 (SAM_IRQ_EXTINT + 59) /* 59 SERCOM3: 1 */ -#define SAM_IRQ_SERCOM3_2 (SAM_IRQ_EXTINT + 60) /* 60 SERCOM3: 2 */ -#define SAM_IRQ_SERCOM3_46 (SAM_IRQ_EXTINT + 61) /* 61 SERCOM3: 4-6 */ -#define SAM_IRQ_SERCOM4_0 (SAM_IRQ_EXTINT + 62) /* 62 SERCOM4: 0 */ -#define SAM_IRQ_SERCOM4_1 (SAM_IRQ_EXTINT + 63) /* 63 SERCOM4: 1 */ -#define SAM_IRQ_SERCOM4_2 (SAM_IRQ_EXTINT + 64) /* 64 SERCOM4: 2 */ -#define SAM_IRQ_SERCOM4_46 (SAM_IRQ_EXTINT + 65) /* 65 SERCOM4: 4-6 */ -#define SAM_IRQ_SERCOM5_0 (SAM_IRQ_EXTINT + 66) /* 66 SERCOM5: 0 */ -#define SAM_IRQ_SERCOM5_1 (SAM_IRQ_EXTINT + 67) /* 67 SERCOM5: 1 */ -#define SAM_IRQ_SERCOM5_2 (SAM_IRQ_EXTINT + 68) /* 68 SERCOM5: 2 */ -#define SAM_IRQ_SERCOM5_46 (SAM_IRQ_EXTINT + 69) /* 69 SERCOM5: 4-6 */ -#define SAM_IRQ_SERCOM6_0 (SAM_IRQ_EXTINT + 70) /* 70 SERCOM6: 0 */ -#define SAM_IRQ_SERCOM6_1 (SAM_IRQ_EXTINT + 71) /* 71 SERCOM6: 1 */ -#define SAM_IRQ_SERCOM6_2 (SAM_IRQ_EXTINT + 72) /* 72 SERCOM6: 2 */ -#define SAM_IRQ_SERCOM6_46 (SAM_IRQ_EXTINT + 73) /* 73 SERCOM6: 4-6 */ -#define SAM_IRQ_SERCOM7_0 (SAM_IRQ_EXTINT + 74) /* 74 SERCOM7: 0 */ -#define SAM_IRQ_SERCOM7_1 (SAM_IRQ_EXTINT + 75) /* 75 SERCOM7: 1 */ -#define SAM_IRQ_SERCOM7_2 (SAM_IRQ_EXTINT + 76) /* 76 SERCOM7: 2 */ -#define SAM_IRQ_SERCOM7_46 (SAM_IRQ_EXTINT + 77) /* 77 SERCOM7: 4-6 */ +#define SAM_IRQ_SERCOM0_0 (SAM_IRQ_EXTINT + 46) /* 46 SERCOM0: INTFLAG[0] */ +#define SAM_IRQ_SERCOM0_1 (SAM_IRQ_EXTINT + 47) /* 47 SERCOM0: INTFLAG[1] */ +#define SAM_IRQ_SERCOM0_2 (SAM_IRQ_EXTINT + 48) /* 48 SERCOM0: INTFLAG[2] */ +#define SAM_IRQ_SERCOM0_46 (SAM_IRQ_EXTINT + 49) /* 49 SERCOM0: INTFLAG[3-6] */ +#define SAM_IRQ_SERCOM1_0 (SAM_IRQ_EXTINT + 50) /* 50 SERCOM1: INTFLAG[0] */ +#define SAM_IRQ_SERCOM1_1 (SAM_IRQ_EXTINT + 51) /* 51 SERCOM1: INTFLAG[1] */ +#define SAM_IRQ_SERCOM1_2 (SAM_IRQ_EXTINT + 52) /* 52 SERCOM1: INTFLAG[2] */ +#define SAM_IRQ_SERCOM1_46 (SAM_IRQ_EXTINT + 53) /* 53 SERCOM1: INTFLAG[3-6] */ +#define SAM_IRQ_SERCOM2_0 (SAM_IRQ_EXTINT + 54) /* 54 SERCOM2: INTFLAG[0] */ +#define SAM_IRQ_SERCOM2_1 (SAM_IRQ_EXTINT + 55) /* 55 SERCOM2: INTFLAG[1] */ +#define SAM_IRQ_SERCOM2_2 (SAM_IRQ_EXTINT + 56) /* 56 SERCOM2: INTFLAG[2] */ +#define SAM_IRQ_SERCOM2_46 (SAM_IRQ_EXTINT + 57) /* 57 SERCOM2: INTFLAG[3-6] */ +#define SAM_IRQ_SERCOM3_0 (SAM_IRQ_EXTINT + 58) /* 58 SERCOM3: INTFLAG[0] */ +#define SAM_IRQ_SERCOM3_1 (SAM_IRQ_EXTINT + 59) /* 59 SERCOM3: INTFLAG[1] */ +#define SAM_IRQ_SERCOM3_2 (SAM_IRQ_EXTINT + 60) /* 60 SERCOM3: INTFLAG[2] */ +#define SAM_IRQ_SERCOM3_46 (SAM_IRQ_EXTINT + 61) /* 61 SERCOM3: INTFLAG[3-6] */ +#define SAM_IRQ_SERCOM4_0 (SAM_IRQ_EXTINT + 62) /* 62 SERCOM4: INTFLAG[0] */ +#define SAM_IRQ_SERCOM4_1 (SAM_IRQ_EXTINT + 63) /* 63 SERCOM4: INTFLAG[1] */ +#define SAM_IRQ_SERCOM4_2 (SAM_IRQ_EXTINT + 64) /* 64 SERCOM4: INTFLAG[2] */ +#define SAM_IRQ_SERCOM4_46 (SAM_IRQ_EXTINT + 65) /* 65 SERCOM4: INTFLAG[3-6] */ +#define SAM_IRQ_SERCOM5_0 (SAM_IRQ_EXTINT + 66) /* 66 SERCOM5: INTFLAG[0] */ +#define SAM_IRQ_SERCOM5_1 (SAM_IRQ_EXTINT + 67) /* 67 SERCOM5: INTFLAG[1] */ +#define SAM_IRQ_SERCOM5_2 (SAM_IRQ_EXTINT + 68) /* 68 SERCOM5: INTFLAG[2] */ +#define SAM_IRQ_SERCOM5_46 (SAM_IRQ_EXTINT + 69) /* 69 SERCOM5: INTFLAG[3-6] */ +#define SAM_IRQ_SERCOM6_0 (SAM_IRQ_EXTINT + 70) /* 70 SERCOM6: INTFLAG[0] */ +#define SAM_IRQ_SERCOM6_1 (SAM_IRQ_EXTINT + 71) /* 71 SERCOM6: INTFLAG[1] */ +#define SAM_IRQ_SERCOM6_2 (SAM_IRQ_EXTINT + 72) /* 72 SERCOM6: INTFLAG[2] */ +#define SAM_IRQ_SERCOM6_46 (SAM_IRQ_EXTINT + 73) /* 73 SERCOM6: INTFLAG[3-6] */ +#define SAM_IRQ_SERCOM7_0 (SAM_IRQ_EXTINT + 74) /* 74 SERCOM7: INTFLAG[0] */ +#define SAM_IRQ_SERCOM7_1 (SAM_IRQ_EXTINT + 75) /* 75 SERCOM7: INTFLAG[1] */ +#define SAM_IRQ_SERCOM7_2 (SAM_IRQ_EXTINT + 76) /* 76 SERCOM7: INTFLAG[2] */ +#define SAM_IRQ_SERCOM7_46 (SAM_IRQ_EXTINT + 77) /* 77 SERCOM7: INTFLAG[3-6] */ #define SAM_IRQ_CAN0 (SAM_IRQ_EXTINT + 78) /* 78 CAN0: Line0, Line1 */ #define SAM_IRQ_CAN1 (SAM_IRQ_EXTINT + 79) /* 79 CAN1: Line0, Line1 */ #define SAM_IRQ_USB (SAM_IRQ_EXTINT + 80) /* 80 USB: EORSM, DNRSM, EORST RST, diff --git a/configs/metro-m4/README.txt b/configs/metro-m4/README.txt index 7916efc6ba..ec8d6b9b9c 100644 --- a/configs/metro-m4/README.txt +++ b/configs/metro-m4/README.txt @@ -99,16 +99,28 @@ STATUS +#define BOARD_GCLK3_SOURCE 4 /* Select OSCULP32K as GCLK3 source */ With that workaround, the port gets past all clock and USART - configuration and, in fact, completely through OS initialization and - application startup! The NSH shell runs and the NSH prompt is presented - on the serial console at the correct baud. Serial input, however, is - not received. There are no serial Rx interrupts! So there is still - more to be done. + configuration. A new configuration option was added, + CONFIG_METRO_M4_32KHZXTAL. By default this workaround is in place. + But you can enable CONFIG_METRO_M4_32KHZXTAL if you want to further + study the XOSC32K problem. - A new configuration option was added, CONFIG_METRO_M4_32KHZXTAL. By - default this workaround is in place. But you can enabled - CONFIG_METRO_M4_32KHZXTAL if you want to further study the XOSC32K - problem. + With that workaround (and a bunch of other fixes), the basic NSH + configuration appears fully function, indicating the the board bring- + up is complete: + + NuttShell (NSH) NuttX-7.25 + nsh> help + help usage: help [-v] [] + + [ cmp false mkdir set uname + ? dirname help mh sh usleep + basename dd hexdump mv sleep xd + break echo kill mw test + cat exec ls rm time + cp exit mb rmdir true + + Builtin Apps: + nsh> Unlocking FLASH =============== diff --git a/configs/metro-m4/include/board.h b/configs/metro-m4/include/board.h index dc1595406d..63558ec1c3 100644 --- a/configs/metro-m4/include/board.h +++ b/configs/metro-m4/include/board.h @@ -445,8 +445,8 @@ #define BOARD_SERCOM3_PINMAP_PAD2 0 /* PAD2: (not used) */ #define BOARD_SERCOM3_PINMAP_PAD3 0 /* PAD3: (not used) */ -#define BOARD_TXIRQ_SERCOM3 SAM_IRQ_SERCOM3_0 /* PAD0 */ -#define BOARD_RXIRQ_SERCOM3 SAM_IRQ_SERCOM3_1 /* PAD1 */ +#define BOARD_TXIRQ_SERCOM3 SAM_IRQ_SERCOM3_0 /* INTFLAG[0] DRE */ +#define BOARD_RXIRQ_SERCOM3 SAM_IRQ_SERCOM3_2 /* INTFLAG[2] RXC */ #define BOARD_SERCOM3_COREGEN 1 /* 48MHz Core clock */ #define BOARD_SERCOM3_CORELOCK FALSE /* Don't lock the CORECLOCK */