Tiva Ethernet: Update Ethernet intializaiton logic. Still things to be done
This commit is contained in:
Gregory Nutt
parent
9b04fb5318
commit
aef65efd38
@ -73,8 +73,10 @@
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#include "tiva_syscontrol.h"
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#include "tiva_enablepwr.h"
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#include "tiva_enableclks.h"
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#include "tiva_periphrdy.h"
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#include "tiva_ethernet.h"
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#include "chip/tiva_pinmap.h"
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#include <arch/board/board.h>
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/* TIVA_NETHCONTROLLERS determines the number of physical interfaces
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@ -299,14 +301,14 @@
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* EMAC_CFG_IPC IPv4 checksum offload Depends on CONFIG_TIVA_EMAC_HWCHECKSUM
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* EMAC_CFG_LOOPBM Loopback mode 0 (disabled)
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* EMAC_CFG_DRO Receive own disable 0 (enabled)
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* EMAC_CFG_PS Port Select
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* EMAC_CFG_PS Port Select (read-only)
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* EMAC_CFG_DISCRS Carrier sense disable 0 (enabled)
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* EMAC_CFG_IFG Interframe gap 0 (96 bits)
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* EMAC_CFG_JFEN Jumbo Frame Enable
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* EMAC_CFG_JFEN Jumbo Frame Enable 0 (jumbo frame creates error)
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* EMAC_CFG_JD Jabber disable 0 (enabled)
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* EMAC_CFG_WDDIS Watchdog disable 0 (enabled)
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* EMAC_CFG_CST CRC stripping for Type frames 0 (disabled, F2/F4 only)
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* EMAC_CFG_TWOKPEN IEEE 802
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* EMAC_CFG_TWOKPEN IEEE 802 0 (>1518 == giant frame)
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* EMAC_CFG_SADDR Source Address Insertion or
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* Replacement Control
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*
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@ -359,7 +361,7 @@
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* EMAC_FRAMEFLTR_SAIF Source address inverse filtering 0 (not used)
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* EMAC_FRAMEFLTR_SAF Source address filter 0 (disabled)
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* EMAC_FRAMEFLTR_HPF Hash or perfect filter 0 (Only matching frames passed)
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* EMAC_FRAMEFLTR_VTFE VLAN Tag Filter Enable
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* EMAC_FRAMEFLTR_VTFE VLAN Tag Filter Enable 0 (VLAN tag ignored)
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* EMAC_FRAMEFLTR_RA Receive all 0 (disabled)
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*/
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@ -493,8 +495,8 @@
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* EMAC_DMABUSMOD_8XPBL 8x programmable burst length mode 0 (disabled)
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* EMAC_DMABUSMOD_AAL Address-aligned beats 1 (enabled)
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* EMAC_DMABUSMOD_MB Mixed burst 0 (disabled, F2/F4 only)
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* EMAC_DMABUSMOD_TXPR Transmit Priority
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* EMAC_DMABUSMOD_RIB Rebuild Burst
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* EMAC_DMABUSMOD_TXPR Transmit Priority 0 (RX DMA has priority over TX)
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* EMAC_DMABUSMOD_RIB Rebuild Burst 0
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*/
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#ifdef CONFIG_TIVA_EMAC_ENHANCEDDESC
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@ -681,7 +683,9 @@ static int tiva_phyinit(FAR struct tiva_ethmac_s *priv);
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/* MAC/DMA Initialization */
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static inline void tiva_ethgpioconfig(FAR struct tiva_ethmac_s *priv);
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static inline void tiva_phy_reconfigure(FAR struct tiva_ethmac_s *priv);
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static inline void tiva_phy_gpioconfig(FAR struct tiva_ethmac_s *priv);
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static void tiva_ethreset(FAR struct tiva_ethmac_s *priv);
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static int tiva_macconfig(FAR struct tiva_ethmac_s *priv);
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static void tiva_macaddress(FAR struct tiva_ethmac_s *priv);
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@ -3146,10 +3150,10 @@ static int tiva_phyinit(FAR struct tiva_ethmac_s *priv)
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}
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/****************************************************************************
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* Function: tiva_ethgpioconfig
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* Function: tiva_phy_reconfigure
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*
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* Description:
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* Configure GPIOs for the Ethernet interface.
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* Configure to support the internal PHY
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*
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* Parameters:
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* priv - A reference to the private driver state structure
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@ -3161,7 +3165,223 @@ static int tiva_phyinit(FAR struct tiva_ethmac_s *priv)
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*
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****************************************************************************/
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static inline void tiva_ethgpioconfig(FAR struct tiva_ethmac_s *priv)
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#ifdef CONFIG_TIVA_PHY_INTERNAL
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static inline void tiva_phy_reconfigure(FAR struct tiva_ethmac_s *priv)
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{
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/* No special actions need to taken after a reset if the internal PHY
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* is used.
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*/
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}
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#endif
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/****************************************************************************
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* Function: tiva_phy_gpioconfig
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*
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* Description:
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* Configure to support the internal PHY
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*
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* Parameters:
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* priv - A reference to the private driver state structure
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*
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* Returned Value:
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* None.
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*
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* Assumptions:
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*
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****************************************************************************/
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#ifdef CONFIG_TIVA_PHY_INTERNAL
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static inline void tiva_phy_gpioconfig(FAR struct tiva_ethmac_s *priv)
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{
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uint32_t regval;
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/* Integrated PHY:
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*
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* "The Ethernet Controller Module and Integrated PHY receive two clock inputs:
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* - A gated system clock acts as the clock source to the Control and Status
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* registers (CSR) of the Ethernet MAC. The SYSCLK frequency for Run, Sleep
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* and Deep Sleep mode is programmed in the System Control module. ...
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* - The PHY receives the main oscillator (MOSC) which must be 25 MHz ± 50 ppm
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* for proper operation. The MOSC source can be a single-ended source or a
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* crystal."
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*
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* These are currently set up in tiva_clockconfig() before this function runs.
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*
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* MII/RMII Clocking:
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*
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* External PHY support is not yet implemented.
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*/
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/* Enable the Ethernet PHY in its default configuration */
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/* Hold the Ethernet PHY from transmitting energy on the line during
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* configuration by setting the PHYHOLD bit in the EMACPC register.
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*/
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regval = tiva_getreg(TIVA_EMAC_PC);
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regval |= EMAC_PC_PHYHOLD;
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tiva_putreg(regval, TIVA_EMAC_PC);
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/* Enable the clock to the PHY module */
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tiva_ephy_enableclk();
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/* What until the PREPHY register indicates that the PHY is ready before
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* continuing.
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*/
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while (!tiva_ephy_periphrdy())
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{
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}
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/* Enable power to the Ethernet PHY */
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tiva_ephy_enablepwr();
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/* What until the PREPHY register indicates that the PHY registers are ready
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* to be accessed.
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*/
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while (!tiva_ephy_periphrdy())
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{
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}
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/* The EMAC interface defaults to MII mode. */
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/* PHY interface pins:
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*
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* EN0TXOP - Fixed pin assignment
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* EN0TXON - Fixed pin assignment
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* EN0RXIP - Fixed pin assignment
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* EN0RXIN - Fixed pin assignment
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* RBIAS - Fixed pin assignment
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* EN0LED0 - Configured GPIO output
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* EN0LED1 - Configured GPIO output
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* EN0LED2 - Configured GPIO output
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*/
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tiva_configgpio(GPIO_EN0_LED0);
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tiva_configgpio(GPIO_EN0_LED1);
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tiva_configgpio(GPIO_EN0_LED2);
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}
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#endif
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/****************************************************************************
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* Function: tiva_phy_reconfigure
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*
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* Description:
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* Configure to support an external PHY
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*
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* Parameters:
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* priv - A reference to the private driver state structure
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*
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* Returned Value:
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* None.
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*
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* Assumptions:
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*
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****************************************************************************/
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#ifndef CONFIG_TIVA_PHY_INTERNAL
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static inline void tiva_phy_reconfigure(FAR struct tiva_ethmac_s *priv)
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{
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/* Enable the Ethernet PHY in a custom configuration */
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/* 1. Hold the Ethernet PHY from transmitting energy on the line during
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* configuration by setting the PHYHOLD bit in the EMACPC register.
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*/
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regval = tiva_getreg(TIVA_EMAC_PC);
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regval |= EMAC_PC_PHYHOLD;
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tiva_putreg(regval, TIVA_EMAC_PC)
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/* Enable the clock to the PHY module */
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tiva_ephy_enableclk();
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/* What until the PREPHY register indicates that the PHY is ready before
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* continuing.
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*/
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while (!tiva_ephy_periphrdy())
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{
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}
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/* Enable power to the Ethernet PHY */
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tiva_ephy_enablepwr();
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/* What until the PREPHY register indicates that the PHY registers are ready
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* to be accessed.
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*/
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while (!tiva_ephy_periphrdy())
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{
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}
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/* Set up the custom PHY configuration.
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*
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* NOTE: This custom PHY configuration will be lost after a reset.
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*/
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#if defined(CONFIG_TIVA_PHY_MII)
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/* Set up the external MII interface configuration */
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#warning Missing logic
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#elif defined(CONFIG_TIVA_PHY_RMII)
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/* Set up the external RMII interface configuration */
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#warning Missing logic
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/* Enable the external clock source input to the RMII interface signal
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* EN0RREF_CLK by setting both the ECEXT and CLKEN bit in the in the Ethernet
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* Clock Configuration (EMACCC) register. The external clock source must be
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* 50 MHz with a frequency tolerance of 50 PPM.
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*/
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#warning Missing logic
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/* Select the RMII interface by programming the PINTFS bit field to 0x4 in
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* the Ethernet Peripheral Configuration (EMACPC) register.
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*/
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#warning Missing logic
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/* Reset the Ethernet MAC to latch the new RMII configuration by setting the
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* SWR bit in the EMACDMABUSMOD register. This bit resets the Ethernet MAC
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* registers in addition to configuring the RMII interface.
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*/
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#warning Missing logic
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/* Software must poll the SWR bit to determine when the new configuration has
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* been registered.
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*
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* Note: After this configuration is active, if the Ethernet MAC is reset by
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* setting the R0 bit in the Ethernet MAC Software Reset (SREMAC) register in
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* the System Control Module, then the interface is set back to its default
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* MII configuration. In this case, the steps listed above must be repeated to
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* return to an RMII interface.
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*/
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#warning Missing logic
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#endif
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}
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#endif
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/****************************************************************************
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* Function: tiva_phy_gpioconfig
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*
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* Description:
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* Configure to support an external PHY
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*
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* Parameters:
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* priv - A reference to the private driver state structure
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*
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* Returned Value:
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* None.
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*
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* Assumptions:
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*
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****************************************************************************/
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#ifndef CONFIG_TIVA_PHY_INTERNAL
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static inline void tiva_phy_gpioconfig(FAR struct tiva_ethmac_s *priv)
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{
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#if defined(CONFIG_TIVA_PHY_MII) || defined(CONFIG_TIVA_PHY_RMII)
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/* Configure GPIO pins to support Ethernet */
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@ -3174,9 +3394,6 @@ static inline void tiva_ethgpioconfig(FAR struct tiva_ethmac_s *priv)
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#if defined(CONFIG_TIVA_PHY_MII)
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/* Select the MII interface */
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#warning Missing logic
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/* "Four clock inputs are driven into the Ethernet MAC when the MII
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* configuration is enabled. The clocks are described as follows:
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*
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@ -3226,9 +3443,6 @@ static inline void tiva_ethgpioconfig(FAR struct tiva_ethmac_s *priv)
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#elif defined(CONFIG_TIVA_PHY_RMII)
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/* Select the RMII interface */
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#warning Missing logic
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/* "There are three clock sources that interface to the Ethernet MAC in
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* an RMII configuration:
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*
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@ -3251,6 +3465,35 @@ static inline void tiva_ethgpioconfig(FAR struct tiva_ethmac_s *priv)
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* for receive and transmit data."
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*/
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/* Enable the external clock source input to the RMII interface signal
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* EN0RREF_CLK by setting both the ECEXT and CLKEN bit in the in the Ethernet
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* Clock Configuration (EMACCC) register. The external clock source must be
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* 50 MHz with a frequency tolerance of 50 PPM.
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*/
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#warning Missing logic
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/* Select the RMII interface by programming the PINTFS bit field to 0x4 in
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* the Ethernet Peripheral Configuration (EMACPC) register.
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*/
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#warning Missing logic
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/* Reset the Ethernet MAC to latch the new RMII configuration by setting the
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* SWR bit in the EMACDMABUSMOD register. This bit resets the Ethernet MAC
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* registers in addition to configuring the RMII interface.
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*/
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#warning Missing logic
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/* Software must poll the SWR bit to determine when the new configuration has
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* been registered.
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*
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* Note: After this configuration is active, if the Ethernet MAC is reset by
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* setting the R0 bit in the Ethernet MAC Software Reset (SREMAC) register in
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* the System Control Module, then the interface is set back to its default
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* MII configuration. In this case, the steps listed above must be repeated to
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* return to an RMII interface.
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*/
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#warning Missing logic
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/* RMII interface pins (7):
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*
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* RMII_TXD[1:0], RMII_TX_EN, RMII_RXD[1:0], RMII_CRS_DV, MDC, MDIO,
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@ -3273,6 +3516,7 @@ static inline void tiva_ethgpioconfig(FAR struct tiva_ethmac_s *priv)
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tiva_configgpio(GPIO_EN0_PPS);
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#endif
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}
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#endif
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/****************************************************************************
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* Function: tiva_ethreset
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@ -3303,6 +3547,19 @@ static void tiva_ethreset(FAR struct tiva_ethmac_s *priv)
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regval &= ~SYSCON_SREMAC_R0;
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tiva_putreg(regval, TIVA_SYSCON_SREMAC);
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/* Reset the internal PHY
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*
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* NOTE: If a custom PHY configuration is used, then that configuration
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* will be lost after the reset.
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*/
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regval = tiva_getreg(TIVA_SYSCON_SREPHY);
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regval |= SYSCON_SREPHY_R0;
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tiva_putreg(regval, TIVA_SYSCON_SREPHY);
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regval &= ~SYSCON_SREPHY_R0;
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tiva_putreg(regval, TIVA_SYSCON_SREPHY);
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/* Perform a software reset by setting the SR bit in the DMABUSMOD register.
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* This Resets all MAC subsystem internal registers and logic. After this
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* reset all the registers holds their reset values.
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@ -3317,6 +3574,16 @@ static void tiva_ethreset(FAR struct tiva_ethmac_s *priv)
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*/
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while ((tiva_getreg(TIVA_EMAC_DMABUSMOD) & EMAC_DMABUSMOD_SWR) != 0);
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/* If the RMII configuration is active when the Ethernet MAC is reset,
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* then the interface is set back to its default MII configuration. In
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* this case, the we must restore the RMII interface configuration.
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*
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* Also, if the PHY is used any custom configuration, then the PHY
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* must be reconfigured after the reset.
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*/
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tiva_phy_reconfigure(priv);
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}
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/****************************************************************************
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@ -3637,12 +3904,12 @@ int tiva_ethinitialize(int intf)
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/* Create a watchdog for timing polling for and timing of transmissions */
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priv->txpoll = wd_create(); /* Create periodic poll timer */
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priv->txtimeout = wd_create(); /* Create TX timeout timer */
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priv->txpoll = wd_create(); /* Create periodic poll timer */
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priv->txtimeout = wd_create(); /* Create TX timeout timer */
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/* Enable power and clocking to the Ethernet MAC
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*
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* - Enable Power: Applies power (only) to the UART peripheral. This is not
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* - Enable Power: Applies power (only) to the EMAC peripheral. This is not
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* an essential step since enabling clocking will also apply power. The
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* only significance is that the EMAC state will be retained if the EMAC
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* clocking is subsequently disabled.
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@ -3653,33 +3920,17 @@ int tiva_ethinitialize(int intf)
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tiva_emac_enablepwr(); /* Ethernet MAC Power Control */
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tiva_emac_enableclk(); /* Ethernet MAC Run Mode Clock Gating Control */
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#ifdef CONFIG_TIVA_PHY_INTERNAL
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/* Integrated PHY:
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*
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* "The Ethernet Controller Module and Integrated PHY receive two clock inputs:
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* - A gated system clock acts as the clock source to the Control and Status
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* registers (CSR) of the Ethernet MAC. The SYSCLK frequency for Run, Sleep
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* and Deep Sleep mode is programmed in the System Control module. ...
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* - The PHY receives the main oscillator (MOSC) which must be 25 MHz ± 50 ppm
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* for proper operation. The MOSC source can be a single-ended source or a
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* crystal."
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*
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* These are currently set up in tiva_clockconfig() before this function runs.
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*
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* MII/RMII Clocking:
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*
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* External PHY support is not yet implemented.
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/* What until the PREMAC register indicates that the EMAC registers are ready
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* to be accessed.
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*/
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/* Enable power and clocking to the Integrated PHY */
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while (!tiva_emac_periphrdy())
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{
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}
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tiva_ephy_enablepwr(); /* Ethernet PHY Power Control */
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tiva_ephy_enableclk(); /* Ethernet PHY Run Mode Clock Gating Control */
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#else
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/* Configure GPIO pins to support Ethernet */
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/* Configure GPIOs to support the internal/eternal PHY */
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tiva_ethgpioconfig(priv);
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#endif
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tiva_phy_gpioconfig(priv);
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/* Attach the IRQ to the driver */
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@ -156,12 +156,24 @@
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#define BUTTON_SW4_BIT (1 << BUTTON_SW4)
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/* Pin Multiplexing Disambiguation **************************************************/
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/* USARTs */
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#define GPIO_UART1_CTS GPIO_UART1_CTS_1
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#define GPIO_UART1_RTS GPIO_UART1_RTS_1
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#define GPIO_UART1_RX GPIO_UART1_RX_1
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#define GPIO_UART1_TX GPIO_UART1_TX_1
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||||
|
||||
/* Ethernet LEDs
|
||||
*
|
||||
* PK4/EN0RXD3/LED0
|
||||
* PK6/EN0TXD2/LED1
|
||||
* PF1/LED2
|
||||
*/
|
||||
|
||||
# define GPIO_EN0_LED0 GPIO_EN0_LED0_2
|
||||
# define GPIO_EN0_LED1 GPIO_EN0_LED1_2
|
||||
# define GPIO_EN0_LED2 GPIO_EN0_LED2_1
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user