TMS570: Flesh out low-level serial console logic
This commit is contained in:
Gregory Nutt
parent
ba0f5467d0
commit
af1504ec4a
@ -9,6 +9,10 @@ comment "TMS570 Configuration Options"
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# Chip Capabilities
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config TMS570_HAVE_SCI2
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bool
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default n
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# Summary Configurations
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# Chip Selection
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@ -32,18 +36,22 @@ config ARCH_CHIP_TMS570LS0432PZ
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config ARCH_CHIP_TMS570LS0714PZ
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bool "TI TMS570LS0714PZ"
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select ARCH_CORTEXR4F
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select TMS570_HAVE_SCI2
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config ARCH_CHIP_TMS570LS0714PGE
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bool "TI TMS570LS0714PGE"
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select ARCH_CORTEXR4F
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select TMS570_HAVE_SCI2
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config ARCH_CHIP_TMS570LS0714ZWT
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bool "TI TMS570LS0714ZWT"
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select ARCH_CORTEXR4F
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select TMS570_HAVE_SCI2
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config ARCH_CHIP_TMS570LS1227ZWT
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bool "TI TMS570LS1227ZWT"
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select ARCH_CORTEXR4F
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select TMS570_HAVE_SCI2
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endchoice # TI TMS570 Chip Selection
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@ -82,6 +90,12 @@ config TMS570_SCI1
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default n
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select ARCH_HAVE_SCI1
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config TMS570_SCI2
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bool "Serial Communication Interface 2 (SCI2)"
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default n
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depends on TMS570_HAVE_SCI2
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select ARCH_HAVE_SCI1
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endmenu # TMS570 Peripheral Support
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config TMS570_SELFTEST
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@ -99,7 +99,7 @@ CHIP_ASRCS =
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# SAMA5-specific C source files
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CHIP_CSRCS = tms570_boot.c tms570_clockconfig.c tms570_irq.c
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CHIP_CSRCS = tms570_boot.c tms570_clockconfig.c tms570_irq.c tms570_lowputc.c
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# Configuration dependent C and assembly language files
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@ -61,7 +61,7 @@
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#define TMS570_SCI_SETINT_OFFSET 0x000c /* SCI Set Interrupt Register */
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#define TMS570_SCI_CLEARINT_OFFSET 0x0010 /* SCI Clear Interrupt Register */
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#define TMS570_SCI_SETINTLVL_OFFSET 0x0014 /* SCI Set Interrupt Level Register */
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#define TMS570_SCI_CLEARINTLVL_OFFSET 0x0018 /* SCI Clear Interrupt Level Register */
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#define TMS570_SCI_CLEARINTLVL_OFFSET 0x0018 /* SCI Clear Interrupt Level Register */
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#define TMS570_SCI_FLR_OFFSET 0x001c /* SCI Flags Register */
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#define TMS570_SCI_INTVECT0_OFFSET 0x0020 /* SCI Interrupt Vector Offset 0 */
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#define TMS570_SCI_INTVECT1_OFFSET 0x0024 /* SCI Interrupt Vector Offset 1 */
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@ -89,6 +89,18 @@
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#define TMS570_SCI_MBRS_OFFSET 0x007c /* Maximum Baud Rate Selection Register */
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#define TMS570_SCI_IODFTCTRL_OFFSET 0x0090 /* Input/Output Error Enable Register */
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/* Friendler register aliases */
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#define TMS570_SCI_FUN_OFFSET TMS570_SCI_PIO0_OFFSET /* Pin Function Register */
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#define TMS570_SCI_DIR_OFFSET TMS570_SCI_PIO1_OFFSET /* Pin Direction Register */
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#define TMS570_SCI_DIN_OFFSET TMS570_SCI_PIO2_OFFSET /* Pin Data In Register */
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#define TMS570_SCI_DOUT_OFFSET TMS570_SCI_PIO3_OFFSET /* Pin Data Out Register */
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#define TMS570_SCI_SET_OFFSET TMS570_SCI_PIO4_OFFSET /* Pin Data Set Register */
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#define TMS570_SCI_CLR_OFFSET TMS570_SCI_PIO5_OFFSET /* Pin Data Clr Register */
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#define TMS570_SCI_ODR_OFFSET TMS570_SCI_PIO6_OFFSET /* Pin Open Drain Output Enable Register */
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#define TMS570_SCI_PD_OFFSET TMS570_SCI_PIO7_OFFSET /* Pin Pullup/Pulldown Disable Register */
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#define TMS570_SCI_PSL_OFFSET TMS570_SCI_PIO8_OFFSET /* Pin Pullup/Pulldown Selection Register */
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/* Register Addresses *******************************************************************************/
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#define TMS570_SCI1_GCR0 (TMS570_SCI1_BASE+TMS570_SCI_GCR0_OFFSET)
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@ -125,6 +137,16 @@
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#define TMS570_SCI1_MBRS (TMS570_SCI1_BASE+TMS570_SCI_MBRS_OFFSET)
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#define TMS570_SCI1_IODFTCTRL (TMS570_SCI1_BASE+TMS570_SCI_IODFTCTRL_OFFSET)
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#define TMS570_SCI1_FUN TMS570_SCI_PIO0 /* Pin Function Register */
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#define TMS570_SCI1_DIR TMS570_SCI_PIO1 /* Pin Direction Register */
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#define TMS570_SCI1_DIN TMS570_SCI_PIO2 /* Pin Data In Register */
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#define TMS570_SCI1_DOUT TMS570_SCI_PIO3 /* Pin Data Out Register */
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#define TMS570_SCI1_SET TMS570_SCI_PIO4 /* Pin Data Set Register */
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#define TMS570_SCI1_CLR TMS570_SCI_PIO5 /* Pin Data Clr Register */
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#define TMS570_SCI1_ODR TMS570_SCI_PIO6 /* Pin Open Drain Output Enable Register */
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#define TMS570_SCI1_PD TMS570_SCI_PIO7 /* Pin Pullup/Pulldown Disable Register */
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#define TMS570_SCI1_PSL TMS570_SCI_PIO8 /* Pin Pullup/Pulldown Selection Register */
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#if TMS570_NSCI > 1
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# define TMS570_SCI2_GCR0 (TMS570_SCI2_BASE+TMS570_SCI_GCR0_OFFSET)
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# define TMS570_SCI2_GCR1 (TMS570_SCI2_BASE+TMS570_SCI_GCR1_OFFSET)
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@ -159,58 +181,150 @@
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# define TMS570_LIN2_TD1 (TMS570_SCI2_BASE+TMS570_LIN_TD1_OFFSET)
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# define TMS570_SCI2_MBRS (TMS570_SCI2_BASE+TMS570_SCI_MBRS_OFFSET)
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# define TMS570_SCI2_IODFTCTRL (TMS570_SCI2_BASE+TMS570_SCI_IODFTCTRL_OFFSET)
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# define TMS570_SCI1_FUN TMS570_SCI_PIO0 /* Pin Function Register */
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# define TMS570_SCI1_DIR TMS570_SCI_PIO1 /* Pin Direction Register */
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# define TMS570_SCI1_DIN TMS570_SCI_PIO2 /* Pin Data In Register */
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# define TMS570_SCI1_DOUT TMS570_SCI_PIO3 /* Pin Data Out Register */
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# define TMS570_SCI1_SET TMS570_SCI_PIO4 /* Pin Data Set Register */
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# define TMS570_SCI1_CLR TMS570_SCI_PIO5 /* Pin Data Clr Register */
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# define TMS570_SCI1_ODR TMS570_SCI_PIO6 /* Pin Open Drain Output Enable Register */
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# define TMS570_SCI1_PD TMS570_SCI_PIO7 /* Pin Pullup/Pulldown Disable Register */
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# define TMS570_SCI1_PSL TMS570_SCI_PIO8 /* Pin Pullup/Pulldown Selection Register */
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#endif
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/* Register Bit-Field Definitions *******************************************************************/
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/* SCI Global Control Register 0 */
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#define SCI_GCR0_
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#define SCI_GCR0_RESET (1 << 0) /* Bit 0: SCI/LIN module is out of reset */
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/* SCI Global Control Register 1 */
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#define SCI_GCR1_
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#define SCI_GCR1_COMM (1 << 0) /* Bit 0: SCI/LIN communication mode */
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#define SCI_GCR1_TIMING (1 << 1) /* Bit 1: SCI timing mode */
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#define SCI_GCR1_PARENA (1 << 2) /* Bit 2: Parity enable */
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#define SCI_GCR1_PARITY (1 << 3) /* Bit 3: SCI parity odd/even selection */
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#define SCI_GCR1_STOP (1 << 4) /* Bit 4: SCI number of stop bits per frame */
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#define SCI_GCR1_CLOCK (1 << 5) /* Bit 5: SCI internal clock enable */
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#define SCI_GCR1_LIN (1 << 6) /* Bit 6: LIN mode */
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#define SCI_GCR1_SWRST (1 << 7) /* Bit 7: Software reset (active low) */
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#define SCI_GCR1_SLEEP (1 << 8) /* Bit 8: SCI sleep */
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#define SCI_GCR1_ADAPT (1 << 9) /* Bit 9: Adapt */
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#define SCI_GCR1_MBUF (1 << 10) /* Bit 10: Multibuffer mode */
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#define SCI_GCR1_CTYPE (1 << 11) /* Bit 11: Checksum type */
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#define SCI_GCR1_HGEN (1 << 12) /* Bit 12: HGEN control */
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#define SCI_GCR1_STOPEXT (1 << 13) /* Bit 13: Stop extended frame communication */
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#define SCI_GCR1_LOOPBACK (1 << 16) /* Bit 16: Loopback bit */
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#define SCI_GCR1_CONT (1 << 17) /* Bit 13: Continue on suspend */
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#define SCI_GCR1_RXENA (1 << 24) /* Bit 24: Receive enable */
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#define SCI_GCR1_TXENA (1 << 25) /* Bit 25: Transmit enable */
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/* SCI Global Control Register 2 */
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#define SCI_GCR2_
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/* SCI Set Interrupt Register */
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#define SCI_SETINT_
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/* SCI Clear Interrupt Register */
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#define SCI_CLEARINT_
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/* SCI Set Interrupt Level Register */
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#define SCI_SETINTLVL_
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/* SCI Clear Interrupt Level Register */
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#define SCI_CLEARINTLVL_
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#define SCI_GCR2_POWERDOWN (1 << 0) /* Bit 0: Power down */
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#define SCI_GCR2_GENWU (1 << 8) /* Bit 8: Generate wakeup signal */
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#define SCI_GCR2_SC (1 << 16) /* Bit 16: Send checksum byte */
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#define SCI_GCR2_CC (1 << 17) /* Bit 17: Compare checksum */
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/* SCI Set Interrupt Register,
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* SCI Clear Interrupt Register,
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( SCI Set Interrupt Level Register, and
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* SCI Clear Interrupt Level Register
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*/
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#define SCI_INT_BRKDT (1 << 0) /* Bit 0: Break detect interrupt */
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#define SCI_INT_WAKEUP (1 << 1) /* Bit 1: Wake-up interrupt */
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#define SCI_INT_TIMEOUT (1 << 4) /* Bit 4: Timeout interrupt */
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#define SCI_INT_TOAWUS (1 << 6) /* Bit 6: Timeout after wakeup signal interrupt */
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#define SCI_INT_TOA3WUS (1 << 7) /* Bit 7: Timeout after 2 Wakeup signls interrupt */
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#define SCI_INT_TX (1 << 8) /* Bit 8: Tranmitter interrupt */
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#define SCI_INT_RX (1 << 9) /* Bit 9: Receiver interrupt */
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#define SCI_INT_ID (1 << 13) /* Bit 13: Identification interrupt */
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#define SCI_INT_PE (1 << 24) /* Bit 24: Parity error interrupt */
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#define SCI_INT_OE (1 << 25) /* Bit 25: Overrun error interrupt */
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#define SCI_INT_FE (1 << 26) /* Bit 26: Framing error interrupt */
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#define SCI_INT_NRE (1 << 27) /* Bit 27: No respose error interrupt */
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#define SCI_INT_ISFE (1 << 28) /* Bit 28: Inconsistene synch field error interrupt */
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#define SCI_INT_CE (1 << 29) /* Bit 29: checksum error interrupt */
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#define SCI_INT_PBE (1 << 30) /* Bit 30: Physical bus error interrupt */
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#define SCI_INT_BE (1 << 31) /* Bit 31: Bit error interrupt */
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#define SCI_INT_ALLERRORS 0xff000000
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#define SCI_INT_ALL 0xff0023d3
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/* SCI Flags Register */
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#define SCI_FLR_
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#define SCI_FLR_BRKDT (1 << 0) /* Bit 0: Break detect flag */
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#define SCI_FLR_WAKEUP (1 << 1) /* Bit 1: Wake-up flag */
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#define SCI_FLR_IDLE (1 << 2) /* Bit 2: SCI receiver in idle state */
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#define SCI_FLR_BUSY (1 << 3) /* Bit 3: Bus busy flag */
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#define SCI_FLR_TIMEOUT (1 << 4) /* Bit 4: Timeout flag */
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#define SCI_FLR_TOAWUS (1 << 6) /* Bit 6: Timeout after wakeup signal flag */
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#define SCI_FLR_TOA3WUS (1 << 7) /* Bit 7: Timeout after 2 Wakeup signls flag */
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#define SCI_FLR_TXRDY (1 << 8) /* Bit 8: Transmitter buffer register ready flag */
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#define SCI_FLR_RXRDY (1 << 9) /* Bit 9: Receiver ready flag */
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#define SCI_FLR_TXWAKE (1 << 10) /* Bit 10: Transmitter wakeup method select */
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#define SCI_FLR_TXEMPTY (1 << 11) /* Bit 11: Transmitter empty flag */
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#define SCI_FLR_RXWAKE (1 << 12) /* Bit 12: Receiver wakeup detect flag */
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#define SCI_FLR_IDTX (1 << 13) /* Bit 13: Identifier on transmit flag */
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#define SCI_FLR_IDRX (1 << 14) /* Bit 14: Identifier on receive flag */
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#define SCI_FLR_PE (1 << 24) /* Bit 24: Parity error flag */
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#define SCI_FLR_OE (1 << 25) /* Bit 25: Overrun error flag */
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#define SCI_FLR_FE (1 << 26) /* Bit 26: Framing error flag */
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#define SCI_FLR_NRE (1 << 27) /* Bit 27: No respose error flag */
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#define SCI_FLR_ISFE (1 << 28) /* Bit 28: Inconsistene synch field error flag */
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#define SCI_FLR_CE (1 << 29) /* Bit 29: checksum error flag */
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#define SCI_FLR_PBE (1 << 30) /* Bit 30: Physical bus error flag */
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#define SCI_FLR_BE (1 << 31) /* Bit 31: Bit error flag */
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/* SCI Interrupt Vector Offset 0 */
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#define SCI_INTVECT0_
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/* SCI Interrupt Vector Offset 1 */
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#define SCI_INTVECT1_
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/* SCI Format Control Register */
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#define SCI_FORMAT_
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#define SCI_FORMAT_CHAR_SHIFT (0) /* Bits 0-2: Frame length control bits */
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#define SCI_FORMAT_CHAR_MASK (7 << SCI_FORMAT_CHAR_SHIFT)
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# define SCI_FORMAT_CHAR(n) ((uint32_t)(n) << SCI_FORMAT_CHAR_SHIFT)
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#define SCI_FORMAT_LENGTH_SHIFT (16) /* Bits 16-18: Character length control bits */
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#define SCI_FORMAT_LENGTH_MASK (7 << SCI_FORMAT_LENGTH_SHIFT)
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# define SCI_FORMAT_LENGTH(n) ((uint32_t)(n) << SCI_FORMAT_LENGTH_SHIFT)
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/* Baud Rate Selection Register */
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#define SCI_BRS_
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#define SCI_BRS_P_SHIFT (0) /* Bits 0-23: Baud integer divider */
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#define SCI_BRS_P_MASK (0x00ffffff << SCI_BRS_P_SHIFT)
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# define SCI_BRS_P(n) ((uint32_t)(n) << SCI_BRS_P_SHIFT)
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#define SCI_BRS_M_SHIFT (24) /* Bits 24-27: SCI/LIN 4-bit fractional divider selection */
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#define SCI_BRS_M_MASK (15 << SCI_BRS_M_SHIFT)
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# define SCI_BRS_M(n) ((uint32_t)(n) << SCI_BRS_M_SHIFT)
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#define SCI_BRS_U_SHIFT (28) /* Bits 28-30: SCI/LIN super fractional divider */
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#define SCI_BRS_U_MASK (7 << SCI_BRS_U_SHIFT)
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# define SCI_BRS_U(n) ((uint32_t)(n) << SCI_BRS_U_SHIFT)
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/* Receiver Emulation Data Buffer */
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#define SCI_ED_
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/* Receiver Data Buffer */
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#define SCI_RD_
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/* Transmit Data Buffer */
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#define SCI_TD_
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/* SCI Pin I/O Control Register 0 */
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#define SCI_PIO0_
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/* SCI Pin I/O Control Register 1 */
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#define SCI_PIO1_
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/* SCI Pin I/O Control Register 2 */
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#define SCI_PIO2_
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/* SCI Pin I/O Control Register 3 */
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#define SCI_PIO3_
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/* SCI Pin I/O Control Register 4 */
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#define SCI_PIO4_
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/* SCI Pin I/O Control Register 5 */
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#define SCI_PIO5_
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/* SCI Pin I/O Control Register 6 */
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#define SCI_PIO6_
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/* SCI Pin I/O Control Register 7 */
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#define SCI_PIO7_
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/* SCI Pin I/O Control Register 8 */
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#define SCI_PIO8_
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/* SCI Pin I/O Control Register 0: Pin Function Register,
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* SCI Pin I/O Control Register 1: Pin Direction Register,
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* SCI Pin I/O Control Register 2: Pin Data In Register,
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* SCI Pin I/O Control Register 3: Pin Data Out Register,
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* SCI Pin I/O Control Register 4: Pin Data Set Register,
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* SCI Pin I/O Control Register 5: Pin Data Clr Register,
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* SCI Pin I/O Control Register 6: Pin Open Drain Output Enable Register,
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* SCI Pin I/O Control Register 7: Pin Pullup/Pulldown Disable Register, and
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* SCI Pin I/O Control Register 8: Pin Pullup/Pulldown Selection Register.
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*/
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#define SCI_PIO_RX (1 << 1) /* Bit 1: RX pin */
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#define SCI_PIO_TX (1 << 2) /* Bit 2: TX pin */
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/* LIN Compare Register */
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#define LIN_COMPARE_
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/* LIN Receive Buffer 0 Register */
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@ -46,6 +46,7 @@
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <errno.h>
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#include <arch/irq.h>
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#include <arch/board/board.h>
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@ -53,10 +54,8 @@
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#include "up_internal.h"
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#include "up_arch.h"
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#include "tms570_config.h"
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#include "tms570_lowputc.h"
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#include "chip/tms570_sci.h"
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#include "tms570_lowputc.h"
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/****************************************************************************
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* Pre-processor Definitions
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@ -64,80 +63,91 @@
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/* Configuration **********************************************************/
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#ifdef HAVE_SERIAL_CONSOLE
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/* BAUD definitions
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*
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* The source clock is selectable and could be one of:
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*
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* - The peripheral clock
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* - A division of the peripheral clock, where the divider is product-
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* dependent, but generally set to 8
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* - A processor/peripheral independent clock source fully programmable
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* provided by PMC (PCK)
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* - The external clock, available on the SCK pin
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*
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* Only the first two options are supported by this driver. The divided
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* peripheral clock is only used for very low BAUD selections.
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*/
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#define FAST_SCI_CLOCK BOARD_MCK_FREQUENCY
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#define SLOW_SCI_CLOCK (BOARD_MCK_FREQUENCY >> 3)
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/* Select SCI parameters for the selected console */
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# if defined(CONFIG_SCI1_SERIAL_CONSOLE)
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# define TMS570_CONSOLE_BASE TMS570_SCI1_BASE
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# define TMS570_CONSOLE_BAUD CONFIG_SCI1_BAUD
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# define TMS570_CONSOLE_BITS CONFIG_SCI1_BITS
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# define TMS570_CONSOLE_PARITY CONFIG_SCI1_PARITY
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# define TMS570_CONSOLE_2STOP CONFIG_SCI1_2STOP
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# elif defined(CONFIG_SCI2_SERIAL_CONSOLE)
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# define TMS570_CONSOLE_BASE TMS570_SCI2_BASE
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# define TMS570_CONSOLE_BAUD CONFIG_SCI2_BAUD
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# define TMS570_CONSOLE_BITS CONFIG_SCI2_BITS
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# define TMS570_CONSOLE_PARITY CONFIG_SCI2_PARITY
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# define TMS570_CONSOLE_2STOP CONFIG_SCI2_2STOP
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# else
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# error "No CONFIG_SCIn_SERIAL_CONSOLE Setting"
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# endif
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#if defined(CONFIG_SCI1_SERIAL_CONSOLE) && defined(CONFIG_TMS570_SCI1)
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# define TMS570_CONSOLE_BASE TMS570_SCI1_BASE
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# define TMS570_CONSOLE_BAUD CONFIG_SCI1_BAUD
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# define TMS570_CONSOLE_BITS CONFIG_SCI1_BITS
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# define TMS570_CONSOLE_PARITY CONFIG_SCI1_PARITY
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# define TMS570_CONSOLE_2STOP CONFIG_SCI1_2STOP
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# define HAVE_SERIAL_CONSOLE 1
|
||||
#elif defined(CONFIG_SCI2_SERIAL_CONSOLE) && defined(CONFIG_TMS570_SCI2)
|
||||
# define TMS570_CONSOLE_BASE TMS570_SCI2_BASE
|
||||
# define TMS570_CONSOLE_BAUD CONFIG_SCI2_BAUD
|
||||
# define TMS570_CONSOLE_BITS CONFIG_SCI2_BITS
|
||||
# define TMS570_CONSOLE_PARITY CONFIG_SCI2_PARITY
|
||||
# define TMS570_CONSOLE_2STOP CONFIG_SCI2_2STOP
|
||||
# define HAVE_SERIAL_CONSOLE 1
|
||||
#else
|
||||
# error "No CONFIG_SCIn_SERIAL_CONSOLE Setting"
|
||||
# undef HAVE_SERIAL_CONSOLE
|
||||
#endif
|
||||
|
||||
/* Select the settings for the mode register */
|
||||
|
||||
# if TMS570_CONSOLE_BITS == 5
|
||||
# define MR_CHRL_VALUE SCI_MR_CHRL_5BITS /* 5 bits */
|
||||
# elif TMS570_CONSOLE_BITS == 6
|
||||
# define MR_CHRL_VALUE SCI_MR_CHRL_6BITS /* 6 bits */
|
||||
# elif TMS570_CONSOLE_BITS == 7
|
||||
# define MR_CHRL_VALUE SCI_MR_CHRL_7BITS /* 7 bits */
|
||||
# elif TMS570_CONSOLE_BITS == 8
|
||||
# define MR_CHRL_VALUE SCI_MR_CHRL_8BITS /* 8 bits */
|
||||
# elif TMS570_CONSOLE_BITS == 9 && !defined(CONFIG_SCI1_SERIAL_CONSOLE) && \
|
||||
!defined(CONFIG_SCI2_SERIAL_CONSOLE)
|
||||
# define MR_CHRL_VALUE SCI_MR_MODE9
|
||||
# else
|
||||
# error "Invalid number of bits"
|
||||
# endif
|
||||
|
||||
# if TMS570_CONSOLE_PARITY == 1
|
||||
# define MR_PAR_VALUE SCI_MR_PAR_ODD
|
||||
# elif TMS570_CONSOLE_PARITY == 2
|
||||
# define MR_PAR_VALUE SCI_MR_PAR_EVEN
|
||||
# else
|
||||
# define MR_PAR_VALUE SCI_MR_PAR_NONE
|
||||
# endif
|
||||
|
||||
# if TMS570_CONSOLE_2STOP != 0
|
||||
# define MR_NBSTOP_VALUE SCI_MR_NBSTOP_2
|
||||
# else
|
||||
# define MR_NBSTOP_VALUE SCI_MR_NBSTOP_1
|
||||
# endif
|
||||
|
||||
# define MR_VALUE (SCI_MR_MODE_NORMAL | SCI_MR_USCLKS_MCK | \
|
||||
MR_CHRL_VALUE | MR_PAR_VALUE | MR_NBSTOP_VALUE)
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef HAVE_SERIAL_CONSOLE
|
||||
static const struct sci_config_s g_console_config =
|
||||
{
|
||||
.baud = TMS570_CONSOLE_BAUD,
|
||||
.parity = TMS570_CONSOLE_PARITY,
|
||||
.bits = TMS570_CONSOLE_BITS,
|
||||
.stopbits2 = TMS570_CONSOLE_2STOP,
|
||||
};
|
||||
#endif /* HAVE_SERIAL_CONSOLE */
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tms570_sci_initialize
|
||||
*
|
||||
* Description:
|
||||
* Perform one-time initialization of the SCI module.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void tms570_sci_initialize(uint32_t base)
|
||||
{
|
||||
/* Bring SCI1 out of reset */
|
||||
|
||||
putreg32(SCI_GCR0_RESET, base + TMS570_SCI_GCR0_OFFSET);
|
||||
|
||||
/* Configure pins */
|
||||
/* Pin Function Register: RX is receive pin, TX is transmit pin. */
|
||||
|
||||
putreg32(SCI_PIO_RX | SCI_PIO_TX, base + TMS570_SCI_FUN_OFFSET);
|
||||
|
||||
/* Pin Data Out Register: Output values are logic low. Irrelevant because
|
||||
* TX FUNC != 0 and RX FUNC != 0
|
||||
*/
|
||||
|
||||
putreg32(0, base + TMS570_SCI_DOUT_OFFSET);
|
||||
|
||||
/* Pin Direction Register: General purpose inputs. Irrelevant because
|
||||
* TX FUNC != 0 and RX FUNC != 0.
|
||||
*/
|
||||
|
||||
putreg32(0, base + TMS570_SCI_DIR_OFFSET);
|
||||
|
||||
/* Set SCI pins open drain enable: ODR functionality disabled. Irrelevant
|
||||
* because TX FUNC != 0 and RX FUNC != 0
|
||||
*/
|
||||
|
||||
putreg32(0, base + TMS570_SCI_ODR_OFFSET);
|
||||
|
||||
/* Set SCI pins pullup/pulldown enable: Pull control enabled */
|
||||
|
||||
putreg32(0, base + TMS570_SCI_PD_OFFSET);
|
||||
|
||||
/* Set SCI pins pullup/pulldown select: Pulled up */
|
||||
|
||||
putreg32(SCI_PIO_RX | SCI_PIO_TX, base + TMS570_SCI_PSL_OFFSET);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
@ -159,20 +169,20 @@ void up_lowputc(char ch)
|
||||
{
|
||||
/* Wait for the transmitter to be available */
|
||||
|
||||
while ((getreg32(TMS570_CONSOLE_BASE + TMS570_SCI_SR_OFFSET) &
|
||||
SCI_INT_TXEMPTY) == 0);
|
||||
while ((getreg32(TMS570_CONSOLE_BASE + TMS570_SCI_FLR_OFFSET) &
|
||||
SCI_FLR_TXRDY) == 0);
|
||||
|
||||
/* Disable interrupts so that the test and the transmission are
|
||||
* atomic.
|
||||
*/
|
||||
|
||||
flags = irqsave();
|
||||
if ((getreg32(TMS570_CONSOLE_BASE + TMS570_SCI_SR_OFFSET) &
|
||||
SCI_INT_TXEMPTY) != 0)
|
||||
if ((getreg32(TMS570_CONSOLE_BASE + TMS570_SCI_FLR_OFFSET) &
|
||||
SCI_FLR_TXRDY) != 0)
|
||||
{
|
||||
/* Send the character */
|
||||
|
||||
putreg32((uint32_t)ch, TMS570_CONSOLE_BASE + TMS570_SCI_THR_OFFSET);
|
||||
putreg32((uint32_t)ch, TMS570_CONSOLE_BASE + TMS570_SCI_TD_OFFSET);
|
||||
irqrestore(flags);
|
||||
return;
|
||||
}
|
||||
@ -219,73 +229,147 @@ int up_putc(int ch)
|
||||
|
||||
void tms570_lowsetup(void)
|
||||
{
|
||||
#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_SCI_CONFIG)
|
||||
uint64_t divb3;
|
||||
uint32_t intpart;
|
||||
uint32_t fracpart;
|
||||
uint32_t regval;
|
||||
#ifdef CONFIG_TMS570_SCI1
|
||||
/* Perform one-time SCI initialization */
|
||||
|
||||
tms570_sci_initialize(TMS570_SCI1_BASE);
|
||||
#endif
|
||||
|
||||
/* Configure the console (only) */
|
||||
#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_SCI_CONFIG)
|
||||
/* Reset and disable receiver and transmitter */
|
||||
#ifdef CONFIG_TMS570_SCI2
|
||||
/* Perform one-time SCI initialization */
|
||||
|
||||
putreg32((SCI_CR_RSTRX | SCI_CR_RSTTX | SCI_CR_RXDIS | SCI_CR_TXDIS),
|
||||
TMS570_CONSOLE_BASE + TMS570_SCI_CR_OFFSET);
|
||||
tms570_sci_initialize(TMS570_SCI2_BASE);
|
||||
#endif
|
||||
|
||||
#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_SCI_CONFIG)
|
||||
/* Configure the console (only) */
|
||||
|
||||
tms570_sci_configure(TMS570_CONSOLE_BASE, &g_console_config);
|
||||
#endif
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: tms570_sci_configure
|
||||
*
|
||||
* Description:
|
||||
* Configure an SCI for non-interrupt driven operation
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int tms570_sci_configure(uint32_t base, FAR const struct sci_config_s *config)
|
||||
{
|
||||
uint64_t divb7;
|
||||
uint64_t intpart;
|
||||
uint64_t frac;
|
||||
uint32_t p;
|
||||
uint32_t m;
|
||||
uint32_t u;
|
||||
uint32_t nbits;
|
||||
uint32_t regval;
|
||||
uint32_t gcr1;
|
||||
|
||||
/* Pre-calculate the baudrate divisor with 7 bits of fraction
|
||||
*
|
||||
* The input clock to the baud rate generator is VCLK.
|
||||
* Asynchronous timing is assumed.
|
||||
*/
|
||||
|
||||
divb7 = ((uint64_t)BOARD_VCLK_FREQUENCY << 7) / (config->baud >> 4);
|
||||
|
||||
/* Break out the integer and fractional parts */
|
||||
|
||||
intpart = divb7 >> 7;
|
||||
if (intpart < 1)
|
||||
{
|
||||
/* Baud cannot be represented */
|
||||
|
||||
DEBUGPANIC();
|
||||
return -ERANGE;
|
||||
}
|
||||
|
||||
if (--intpart > 0x00ffffff)
|
||||
{
|
||||
/* Baud cannot be represented */
|
||||
|
||||
DEBUGPANIC();
|
||||
return -ERANGE;
|
||||
}
|
||||
|
||||
/* Disable all interrupts */
|
||||
|
||||
putreg32(0xffffffff, TMS570_CONSOLE_BASE + TMS570_SCI_IDR_OFFSET);
|
||||
putreg32(SCI_INT_ALL, base + TMS570_SCI_CLEARINT_OFFSET);
|
||||
putreg32(SCI_INT_ALL, base + TMS570_SCI_CLEARINTLVL_OFFSET);
|
||||
|
||||
/* Set up the mode register */
|
||||
|
||||
putreg32(MR_VALUE, TMS570_CONSOLE_BASE + TMS570_SCI_MR_OFFSET);
|
||||
|
||||
/* Configure the console baud:
|
||||
*
|
||||
* Fbaud = SCI_CLOCK / (16 * divisor)
|
||||
* divisor = SCI_CLOCK / (16 * Fbaud)
|
||||
*
|
||||
* NOTE: Oversampling by 8 is not supported. This may limit BAUD rates
|
||||
* for lower SCI clocks.
|
||||
/* Global control 1:
|
||||
* COMM=0 Idle line mode is used.
|
||||
* TIMING=1 Asynchronous timing is used.
|
||||
* PARENA=? Depends on configuration settings
|
||||
* PARITY=? Depends on configuration settings
|
||||
* STOP=? Depends on configuration settings
|
||||
* CLOCK=1 The internal SCICLK is the clock source
|
||||
* LIN=0 LIN mode is disabled
|
||||
* SWRST=0 SCI is initiailized and held in reset state
|
||||
* SLEEP=0 Sleep mode is disabled
|
||||
* ADAPT=0 Automatic baud rate adjustment is disabled
|
||||
* MBUF=0 The multi-buffer mode is disabled.
|
||||
* CTYPE=0 Classic checksum is used.
|
||||
* HGEN=0 (Effective in LIN mode only)
|
||||
* STOPEXT=0 (Effective in LIN mode only)
|
||||
* LOOPBACK=0 Loop back mode is disabled
|
||||
* CONT=0 Freeze SCI when debug mode is entered
|
||||
* RXENA=1 Receiver is enabled
|
||||
* TXENA=1 Transmitter is enabled
|
||||
*/
|
||||
|
||||
divb3 = ((FAST_SCI_CLOCK + (TMS570_CONSOLE_BAUD << 3)) << 3) /
|
||||
(TMS570_CONSOLE_BAUD << 4);
|
||||
intpart = (divb3 >> 3);
|
||||
fracpart = (divb3 & 7);
|
||||
gcr1 = (SCI_GCR1_TIMING | SCI_GCR1_CLOCK | SCI_GCR1_RXENA | SCI_GCR1_TXENA);
|
||||
|
||||
/* Retain the fast MR peripheral clock UNLESS unless using that clock
|
||||
* would result in an excessively large divider.
|
||||
*
|
||||
* REVISIT: The fractional divider is not used.
|
||||
*/
|
||||
|
||||
if ((intpart & ~SCI_BRGR_CD_MASK) != 0)
|
||||
DEBUGASSERT(config->parity >= && config->parity <= 2);
|
||||
if (config->parity == 1)
|
||||
{
|
||||
/* Use the divided SCI clock */
|
||||
|
||||
divb3 = ((SLOW_SCI_CLOCK + (TMS570_CONSOLE_BAUD << 3)) << 3) /
|
||||
(TMS570_CONSOLE_BAUD << 4);
|
||||
intpart = (divb3 >> 3);
|
||||
fracpart = (divb3 & 7);
|
||||
|
||||
/* Re-select the clock source */
|
||||
|
||||
regval = getreg32(TMS570_CONSOLE_BASE + TMS570_SCI_MR_OFFSET);
|
||||
regval &= ~SCI_MR_USCLKS_MASK;
|
||||
regval |= SCI_MR_USCLKS_MCKDIV;
|
||||
putreg32(regval, TMS570_CONSOLE_BASE + TMS570_SCI_MR_OFFSET);
|
||||
gcr1 |= SCI_GCR1_PARENA;
|
||||
}
|
||||
else if (config->parity == 2)
|
||||
{
|
||||
gcr1 |= (SCI_GCR1_PARENA | SCI_GCR1_PARITY);
|
||||
}
|
||||
|
||||
/* Save the BAUD divider (the fractional part is not used for SCIs) */
|
||||
if (config->stopbits2)
|
||||
{
|
||||
gcr1 |= SCI_GCR1_STOP;
|
||||
}
|
||||
|
||||
regval = SCI_BRGR_CD(intpart) | SCI_BRGR_FP(fracpart);
|
||||
putreg32(regval, TMS570_CONSOLE_BASE + TMS570_SCI_BRGR_OFFSET);
|
||||
putreg32(gcr1, base + TMS570_SCI_GCR1_OFFSET);
|
||||
|
||||
/* Enable receiver & transmitter */
|
||||
/* Set baud divisor using the pre-calculated values */
|
||||
|
||||
putreg32((SCI_CR_RXEN | SCI_CR_TXEN),
|
||||
TMS570_CONSOLE_BASE + TMS570_SCI_CR_OFFSET);
|
||||
#endif
|
||||
p = (uint32_t)intpart;
|
||||
frac = (uint32_t)(divb7 & 0x3f);
|
||||
m = frac >> 3;
|
||||
u = frac & 3;
|
||||
|
||||
regval = SCI_BRS_P(p) | SCI_BRS_M(m) | SCI_BRS_U(u);
|
||||
putreg32(regval, base + TMS570_SCI_BRS_OFFSET);
|
||||
|
||||
/* Transmission length */
|
||||
|
||||
nbits = config->bits;
|
||||
DEBUGASSERT(nbits >= 1 && nbits <= 8);
|
||||
|
||||
if (nbits < 1)
|
||||
{
|
||||
nbits = 1;
|
||||
}
|
||||
else if (nbits > 8)
|
||||
{
|
||||
nbits = 8;
|
||||
}
|
||||
|
||||
regval = SCI_FORMAT_CHAR(nbits - 1);
|
||||
putreg32(regval, base + TMS570_SCI_FORMAT_OFFSET);
|
||||
|
||||
/* Put the SCI in its operational state. */
|
||||
|
||||
gcr1 |= SCI_GCR1_SWRST;
|
||||
putreg32(gcr1, base + TMS570_SCI_GCR1_OFFSET);
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -58,6 +58,16 @@
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/* This structure describes the configuration of an SCI UART */
|
||||
|
||||
struct sci_config_s
|
||||
{
|
||||
uint32_t baud; /* Configured baud */
|
||||
uint8_t parity; /* 0=none, 1=odd, 2=even */
|
||||
uint8_t bits; /* Number of bits (5-9) */
|
||||
bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
|
||||
};
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
@ -94,16 +104,14 @@ extern "C"
|
||||
void tms570_lowsetup(void);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: tms570_boardinitialize
|
||||
* Name: tms570_sci_configure
|
||||
*
|
||||
* Description:
|
||||
* All TMS570 architectures must provide the following entry point. This entry
|
||||
* point is called early in the initialization -- after all memory has been
|
||||
* configured and mapped but before any devices have been initialized.
|
||||
* Configure an SCI for non-interrupt driven operation
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void tms570_boardinitialize(void);
|
||||
int tms570_sci_configure(uint32_t base, FAR const struct sci_config_s *config);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
|
||||
@ -62,7 +62,6 @@
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
|
||||
#include "tms570_config.h"
|
||||
#include "chip/tms570_sci.h"
|
||||
|
||||
/****************************************************************************
|
||||
@ -84,11 +83,11 @@
|
||||
# define TTYS0_DEV g_sci2port /* SCI2 is ttyS0 */
|
||||
# define SCI2_ASSIGNED 1
|
||||
#else
|
||||
# undef CONSOLE_DEV /* No console */
|
||||
# if defined(CONFIG_SAMV7_SCI1)
|
||||
# undef CONSOLE_DEV /* No console */
|
||||
# if defined(CONFIG_TMS570_SCI1)
|
||||
# define TTYS0_DEV g_sci1port /* SCI1 is ttyS0 */
|
||||
# define SCI1_ASSIGNED 1
|
||||
# elif defined(CONFIG_SAMV7_SCI2)
|
||||
# elif defined(CONFIG_TMS570_SCI2)
|
||||
# define TTYS0_DEV g_sci2port /* SCI2 is ttyS0 */
|
||||
# define SCI2_ASSIGNED 1
|
||||
# endif
|
||||
@ -98,10 +97,10 @@
|
||||
* SCI.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_SAMV7_SCI1) && !defined(SCI1_ASSIGNED)
|
||||
#if defined(CONFIG_TMS570_SCI1) && !defined(SCI1_ASSIGNED)
|
||||
# define TTYS1_DEV g_sci1port /* SCI1 is ttyS1 */
|
||||
# define SCI1_ASSIGNED 1
|
||||
#elif defined(CONFIG_SAMV7_SCI2) && !defined(SCI2_ASSIGNED)
|
||||
#elif defined(CONFIG_TMS570_SCI2) && !defined(SCI2_ASSIGNED)
|
||||
# define TTYS1_DEV g_sci2port /* SCI2 is ttyS1 */
|
||||
# define SCI2_ASSIGNED 1
|
||||
#endif
|
||||
@ -130,17 +129,11 @@
|
||||
|
||||
struct tms570_dev_s
|
||||
{
|
||||
const uint32_t usartbase; /* Base address of SCI registers */
|
||||
const uint32_t scibase; /* Base address of SCI registers */
|
||||
struct sci_config_s config; /* SCI configuration */
|
||||
xcpt_t handler; /* Interrupt handler */
|
||||
uint32_t baud; /* Configured baud */
|
||||
uint32_t sr; /* Saved status bits */
|
||||
uint8_t irq; /* IRQ associated with this SCI */
|
||||
uint8_t parity; /* 0=none, 1=odd, 2=even */
|
||||
uint8_t bits; /* Number of bits (5-9) */
|
||||
bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
|
||||
#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
|
||||
bool flowc; /* input flow control (RTS) enabled */
|
||||
#endif
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
@ -152,10 +145,10 @@ static void tms570_shutdown(struct sci_dev_s *dev);
|
||||
static int tms570_attach(struct sci_dev_s *dev);
|
||||
static void tms570_detach(struct sci_dev_s *dev);
|
||||
static int tms570_interrupt(struct sci_dev_s *dev);
|
||||
#ifdef CONFIG_SAMV7_SCI1
|
||||
#ifdef CONFIG_TMS570_SCI1
|
||||
static int tms570_sci1_interrupt(int irq, void *context);
|
||||
#endif
|
||||
#ifdef CONFIG_SAMV7_SCI2
|
||||
#ifdef CONFIG_TMS570_SCI2
|
||||
static int tms570_sci2_interrupt(int irq, void *context);
|
||||
#endif
|
||||
static int tms570_ioctl(struct file *filep, int cmd, unsigned long arg);
|
||||
@ -192,27 +185,30 @@ static const struct sci_ops_s g_sci_ops =
|
||||
|
||||
/* I/O buffers */
|
||||
|
||||
#ifdef CONFIG_SAMV7_SCI1
|
||||
#ifdef CONFIG_TMS570_SCI1
|
||||
static char g_sci1rxbuffer[CONFIG_SCI1_RXBUFSIZE];
|
||||
static char g_sci1txbuffer[CONFIG_SCI1_TXBUFSIZE];
|
||||
#endif
|
||||
#ifdef CONFIG_SAMV7_SCI2
|
||||
#ifdef CONFIG_TMS570_SCI2
|
||||
static char g_sci2rxbuffer[CONFIG_SCI2_RXBUFSIZE];
|
||||
static char g_sci2txbuffer[CONFIG_SCI2_TXBUFSIZE];
|
||||
#endif
|
||||
|
||||
/* This describes the state of the SCI1 port. */
|
||||
|
||||
#ifdef CONFIG_SAMV7_SCI1
|
||||
#ifdef CONFIG_TMS570_SCI1
|
||||
static struct tms570_dev_s g_sci1priv =
|
||||
{
|
||||
.usartbase = TMS570_SCI1_BASE,
|
||||
.scibase = TMS570_SCI1_BASE,
|
||||
.config =
|
||||
{
|
||||
.baud = CONFIG_SCI1_BAUD,
|
||||
.parity = CONFIG_SCI1_PARITY,
|
||||
.bits = CONFIG_SCI1_BITS,
|
||||
.stopbit = CONFIG_SCI1_2STOP,
|
||||
}
|
||||
.handler = tms570_sci1_interrupt,
|
||||
.baud = CONFIG_SCI1_BAUD,
|
||||
.irq = TMS570_IRQ_SCI1,
|
||||
.parity = CONFIG_SCI1_PARITY,
|
||||
.bits = CONFIG_SCI1_BITS,
|
||||
.stopbits2 = CONFIG_SCI1_2STOP,
|
||||
};
|
||||
|
||||
static sci_dev_t g_sci1port =
|
||||
@ -234,16 +230,19 @@ static sci_dev_t g_sci1port =
|
||||
|
||||
/* This describes the state of the SCI2 port. */
|
||||
|
||||
#ifdef CONFIG_SAMV7_SCI2
|
||||
#ifdef CONFIG_TMS570_SCI2
|
||||
static struct tms570_dev_s g_sci2priv =
|
||||
{
|
||||
.usartbase = TMS570_SCI2_BASE,
|
||||
.scibase = TMS570_SCI2_BASE,
|
||||
.config =
|
||||
{
|
||||
.baud = CONFIG_SCI2_BAUD,
|
||||
.parity = CONFIG_SCI2_PARITY,
|
||||
.bits = CONFIG_SCI2_BITS,
|
||||
.stopbit = CONFIG_SCI2_2STOP,
|
||||
}
|
||||
.handler = tms570_sci2_interrupt,
|
||||
.baud = CONFIG_SCI2_BAUD,
|
||||
.irq = TMS570_IRQ_SCI2,
|
||||
.parity = CONFIG_SCI2_PARITY,
|
||||
.bits = CONFIG_SCI2_BITS,
|
||||
.stopbits2 = CONFIG_SCI2_2STOP,
|
||||
};
|
||||
|
||||
static sci_dev_t g_sci2port =
|
||||
@ -273,7 +272,7 @@ static sci_dev_t g_sci2port =
|
||||
|
||||
static inline uint32_t tms570_serialin(struct tms570_dev_s *priv, int offset)
|
||||
{
|
||||
return getreg32(priv->usartbase + offset);
|
||||
return getreg32(priv->scibase + offset);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -282,14 +281,14 @@ static inline uint32_t tms570_serialin(struct tms570_dev_s *priv, int offset)
|
||||
|
||||
static inline void tms570_serialout(struct tms570_dev_s *priv, int offset, uint32_t value)
|
||||
{
|
||||
putreg32(value, priv->usartbase + offset);
|
||||
putreg32(value, priv->scibase + offset);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tms570_restoreusartint
|
||||
* Name: tms570_restoresciint
|
||||
****************************************************************************/
|
||||
|
||||
static inline void tms570_restoreusartint(struct tms570_dev_s *priv, uint32_t imr)
|
||||
static inline void tms570_restoresciint(struct tms570_dev_s *priv, uint32_t imr)
|
||||
{
|
||||
/* Restore the previous interrupt state (assuming all interrupts disabled) */
|
||||
|
||||
@ -331,161 +330,15 @@ static void tms570_disableallints(struct tms570_dev_s *priv, uint32_t *imr)
|
||||
|
||||
static int tms570_setup(struct sci_dev_s *dev)
|
||||
{
|
||||
struct tms570_dev_s *priv = (struct tms570_dev_s *)dev->priv;
|
||||
#ifndef CONFIG_SUPPRESS_SCI_CONFIG
|
||||
uint32_t divb3;
|
||||
uint32_t intpart;
|
||||
uint32_t fracpart;
|
||||
uint32_t regval;
|
||||
struct tms570_dev_s *priv = (struct tms570_dev_s *)dev->priv;
|
||||
|
||||
/* Note: The logic here depends on the fact that that the SCI module
|
||||
* was enabled and the pins were configured in tms570_lowsetup().
|
||||
*/
|
||||
|
||||
/* The shutdown method will put the SCI in a known, disabled state */
|
||||
|
||||
tms570_shutdown(dev);
|
||||
|
||||
/* Set up the mode register. Start with normal SCI mode and the MCK
|
||||
* as the timing source
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
|
||||
/* "Setting the SCI to operate with hardware handshaking is performed by
|
||||
* writing the SCI_MODE field in the Mode Register (US_MR) to the value
|
||||
* 0x2. ... Using this mode requires using the PDC or DMAC channel for
|
||||
* reception. The transmitter can handle hardware handshaking in any case."
|
||||
*/
|
||||
|
||||
if (priv->flowc)
|
||||
{
|
||||
/* Enable hardware flow control and MCK as the timing source
|
||||
* (the divided clock source may be reselected below).
|
||||
*/
|
||||
|
||||
regval = (SCI_MR_MODE_HWHS | SCI_MR_USCLKS_MCK);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
/* Set up the mode register. Start with normal SCI mode and the MCK
|
||||
* as the timing source (the divided clock source may be reselected
|
||||
* below).
|
||||
*/
|
||||
|
||||
regval = (SCI_MR_MODE_NORMAL | SCI_MR_USCLKS_MCK);
|
||||
}
|
||||
|
||||
/* OR in settings for the selected number of bits */
|
||||
|
||||
if (priv->bits == 5)
|
||||
{
|
||||
regval |= SCI_MR_CHRL_5BITS; /* 5 bits */
|
||||
}
|
||||
else if (priv->bits == 6)
|
||||
{
|
||||
regval |= SCI_MR_CHRL_6BITS; /* 6 bits */
|
||||
}
|
||||
else if (priv->bits == 7)
|
||||
{
|
||||
regval |= SCI_MR_CHRL_7BITS; /* 7 bits */
|
||||
}
|
||||
#ifdef HAVE_SCI_DEVICE
|
||||
else if (priv->bits == 9
|
||||
#if defined(CONFIG_SAMV7_SCI1)
|
||||
&& priv->usartbase != TMS570_SCI1_BASE
|
||||
#endif
|
||||
#if defined(CONFIG_SAMV7_SCI2)
|
||||
&& priv->usartbase != TMS570_SCI2_BASE
|
||||
#endif
|
||||
)
|
||||
{
|
||||
regval |= SCI_MR_MODE9; /* 9 bits */
|
||||
}
|
||||
#endif
|
||||
else /* if (priv->bits == 8) */
|
||||
{
|
||||
regval |= SCI_MR_CHRL_8BITS; /* 8 bits (default) */
|
||||
}
|
||||
|
||||
/* OR in settings for the selected parity */
|
||||
|
||||
if (priv->parity == 1)
|
||||
{
|
||||
regval |= SCI_MR_PAR_ODD;
|
||||
}
|
||||
else if (priv->parity == 2)
|
||||
{
|
||||
regval |= SCI_MR_PAR_EVEN;
|
||||
}
|
||||
else
|
||||
{
|
||||
regval |= SCI_MR_PAR_NONE;
|
||||
}
|
||||
|
||||
/* OR in settings for the number of stop bits */
|
||||
|
||||
if (priv->stopbits2)
|
||||
{
|
||||
regval |= SCI_MR_NBSTOP_2;
|
||||
}
|
||||
else
|
||||
{
|
||||
regval |= SCI_MR_NBSTOP_1;
|
||||
}
|
||||
|
||||
/* And save the new mode register value */
|
||||
|
||||
tms570_serialout(priv, TMS570_SCI_MR_OFFSET, regval);
|
||||
|
||||
/* Configure the console baud:
|
||||
*
|
||||
* Fbaud = SCI_CLOCK / (16 * divisor)
|
||||
* divisor = SCI_CLOCK / (16 * Fbaud)
|
||||
*
|
||||
* NOTE: Oversampling by 8 is not supported. This may limit BAUD rates
|
||||
* for lower SCI clocks.
|
||||
*/
|
||||
|
||||
divb3 = ((FAST_SCI_CLOCK + (priv->baud << 3)) << 3) /
|
||||
(priv->baud << 4);
|
||||
intpart = divb3 >> 3;
|
||||
fracpart = divb3 & 7;
|
||||
|
||||
/* Retain the fast MR peripheral clock UNLESS unless using that clock
|
||||
* would result in an excessively large divider.
|
||||
*
|
||||
* REVISIT: The fractional divider is not used.
|
||||
*/
|
||||
|
||||
if ((intpart & ~SCI_BRGR_CD_MASK) != 0)
|
||||
{
|
||||
/* Use the divided SCI clock */
|
||||
|
||||
divb3 = ((SLOW_SCI_CLOCK + (priv->baud << 3)) << 3) /
|
||||
(priv->baud << 4);
|
||||
intpart = divb3 >> 3;
|
||||
fracpart = divb3 & 7;
|
||||
|
||||
/* Re-select the clock source */
|
||||
|
||||
regval = tms570_serialin(priv, TMS570_SCI_MR_OFFSET);
|
||||
regval &= ~SCI_MR_USCLKS_MASK;
|
||||
regval |= SCI_MR_USCLKS_MCKDIV;
|
||||
tms570_serialout(priv, TMS570_SCI_MR_OFFSET, regval);
|
||||
}
|
||||
|
||||
/* Save the BAUD divider (the fractional part is not used for SCIs) */
|
||||
|
||||
regval = SCI_BRGR_CD(intpart) | SCI_BRGR_FP(fracpart);
|
||||
tms570_serialout(priv, TMS570_SCI_BRGR_OFFSET, regval);
|
||||
|
||||
/* Enable receiver & transmitter */
|
||||
|
||||
tms570_serialout(priv, TMS570_SCI_CR_OFFSET, (SCI_CR_RXEN | SCI_CR_TXEN));
|
||||
#endif
|
||||
/* Configure baud, number of bits, stop bits, and parity */
|
||||
|
||||
return tms570_sci_configure(priv->base, &priv->config);
|
||||
#else
|
||||
return OK;
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -637,13 +490,13 @@ static int tms570_interrupt(struct sci_dev_s *dev)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAMV7_SCI1
|
||||
#ifdef CONFIG_TMS570_SCI1
|
||||
static int tms570_sci1_interrupt(int irq, void *context)
|
||||
{
|
||||
return tms570_interrupt(&g_sci1port);
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_SAMV7_SCI2
|
||||
#ifdef CONFIG_TMS570_SCI2
|
||||
static int tms570_sci2_interrupt(int irq, void *context)
|
||||
{
|
||||
return tms570_interrupt(&g_sci2port);
|
||||
@ -698,25 +551,20 @@ static int tms570_ioctl(struct file *filep, int cmd, unsigned long arg)
|
||||
|
||||
/* Return baud */
|
||||
|
||||
cfsetispeed(termiosp, priv->baud);
|
||||
cfsetispeed(termiosp, priv->config.baud);
|
||||
|
||||
/* Return parity */
|
||||
|
||||
termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) |
|
||||
((priv->parity == 1) ? PARODD : 0);
|
||||
termiosp->c_cflag = ((priv->config.parity != 0) ? PARENB : 0) |
|
||||
((priv->config.parity == 1) ? PARODD : 0);
|
||||
|
||||
/* Return stop bits */
|
||||
|
||||
termiosp->c_cflag |= (priv->stopbits2) ? CSTOPB : 0;
|
||||
termiosp->c_cflag |= (priv->config.stopbits2) ? CSTOPB : 0;
|
||||
|
||||
/* Return flow control */
|
||||
|
||||
#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
|
||||
termiosp->c_cflag |= (priv->flowc) ? (CCTS_OFLOW | CRTS_IFLOW): 0;
|
||||
#endif
|
||||
/* Return number of bits */
|
||||
|
||||
switch (priv->bits)
|
||||
switch (priv->config.bits)
|
||||
{
|
||||
case 5:
|
||||
termiosp->c_cflag |= CS5;
|
||||
@ -751,9 +599,6 @@ static int tms570_ioctl(struct file *filep, int cmd, unsigned long arg)
|
||||
uint8_t parity;
|
||||
uint8_t nbits;
|
||||
bool stop2;
|
||||
#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
|
||||
bool flowc;
|
||||
#endif
|
||||
|
||||
if (!termiosp)
|
||||
{
|
||||
@ -810,34 +655,27 @@ static int tms570_ioctl(struct file *filep, int cmd, unsigned long arg)
|
||||
|
||||
stop2 = (termiosp->c_cflag & CSTOPB) != 0;
|
||||
|
||||
/* Decode flow control */
|
||||
|
||||
#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
|
||||
flowc = (termiosp->c_cflag & (CCTS_OFLOW | CRTS_IFLOW)) != 0;
|
||||
#endif
|
||||
/* Verify that all settings are valid before committing */
|
||||
|
||||
if (ret == OK)
|
||||
{
|
||||
/* Commit */
|
||||
|
||||
priv->baud = baud;
|
||||
priv->parity = parity;
|
||||
priv->bits = nbits;
|
||||
priv->stopbits2 = stop2;
|
||||
#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
|
||||
priv->flowc = flowc;
|
||||
#endif
|
||||
priv->config.baud = baud;
|
||||
priv->config.parity = parity;
|
||||
priv->config.bits = nbits;
|
||||
priv->config.stopbits2 = stop2;
|
||||
|
||||
/* effect the changes immediately - note that we do not
|
||||
* implement TCSADRAIN / TCSAFLUSH
|
||||
*/
|
||||
|
||||
tms570_disableallints(priv, &imr);
|
||||
ret = tms570_setup(dev);
|
||||
ret = tms570_sci_configure(priv->scibase, &priv->config);
|
||||
|
||||
/* Restore the interrupt state */
|
||||
|
||||
tms570_restoreusartint(priv, imr);
|
||||
tms570_restoresciint(priv, imr);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user