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STM32L4: add support for tickless OS, and incidentally timers, pwm, oneshot, free-running....

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This commit is contained in:
ziggurat29 2016-07-08 17:30:55 -05:00
parent 0207f6699a
commit af236d4784
13 changed files with 8360 additions and 3 deletions
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1
arch/arm/Kconfig
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@ -251,6 +251,7 @@ config ARCH_CHIP_STM32L4
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_TICKLESS
select ARMV7M_HAVE_STACKCHECK
---help---
STMicro STM32 architectures (ARM Cortex-M4).

1845
arch/arm/src/stm32l4/Kconfig
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File diff suppressed because it is too large Load Diff

19
arch/arm/src/stm32l4/Make.defs
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@ -112,9 +112,24 @@ CHIP_CSRCS = stm32l4_allocateheap.c stm32l4_exti_gpio.c stm32l4_gpio.c
CHIP_CSRCS += stm32l4_idle.c stm32l4_irq.c stm32l4_lowputc.c stm32l4_rcc.c
CHIP_CSRCS += stm32l4_serial.c stm32l4_start.c stm32l4_waste.c stm32l4_uid.c
CHIP_CSRCS += stm32l4_spi.c stm32l4_i2c.c stm32l4_lse.c stm32l4_pwr.c
CHIP_CSRCS += stm32l4_tim.c
ifeq ($(CONFIG_TIMER),y)
CHIP_CSRCS += stm32l4_tim_lowerhalf.c
endif
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += stm32l4_timerisr.c
else
CHIP_CSRCS += stm32l4_tickless.c
endif
ifeq ($(CONFIG_STM32L4_ONESHOT),y)
CHIP_CSRCS += stm32l4_oneshot.c
endif
ifeq ($(CONFIG_STM32L4_FREERUN),y)
CHIP_CSRCS += stm32l4_freerun.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
@ -176,6 +191,10 @@ ifeq ($(CONFIG_STM32L4_RNG),y)
CHIP_CSRCS += stm32l4_rng.c
endif
ifeq ($(CONFIG_PWM),y)
CHIP_CSRCS += stm32l4_pwm.c
endif
ifeq ($(CONFIG_STM32L4_QSPI),y)
CHIP_CSRCS += stm32l4_qspi.c
endif

297
arch/arm/src/stm32l4/stm32l4_freerun.c Normal file
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@ -0,0 +1,297 @@
/****************************************************************************
* arch/arm/src/stm32l4/stm32l4_freerun.c
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* dev@ziggurat29.com
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the names NuttX nor Atmel nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#include <errno.h>
#include <nuttx/irq.h>
#include <nuttx/clock.h>
#include "stm32l4_freerun.h"
#ifdef CONFIG_STM32L4_FREERUN
/****************************************************************************
* Private Functions
****************************************************************************/
static struct stm32l4_freerun_s *g_freerun;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_freerun_handler
*
* Description:
* Timer interrupt callback. When the freerun timer counter overflows,
* this interrupt will occur. We will just increment an overflow count.
*
* Input Parameters:
* tch - The handle that represents the timer state
* arg - An opaque argument provided when the interrupt was registered
* sr - The value of the timer interrupt status register at the time
* that the interrupt occurred.
*
* Returned Value:
* None
*
****************************************************************************/
static int stm32_freerun_handler(int irq, void *context)
{
struct stm32l4_freerun_s *freerun = g_freerun;
DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX);
freerun->overflow++;
STM32L4_TIM_ACKINT(freerun->tch, 0);
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32l4_freerun_initialize
*
* Description:
* Initialize the freerun timer wrapper
*
* Input Parameters:
* freerun Caller allocated instance of the freerun state structure
* chan Timer counter channel to be used.
* resolution The required resolution of the timer in units of
* microseconds. NOTE that the range is restricted to the
* range of uint16_t (excluding zero).
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, int chan,
uint16_t resolution)
{
uint32_t frequency;
tmrinfo("chan=%d resolution=%d usec\n", chan, resolution);
DEBUGASSERT(freerun != NULL && resolution > 0);
/* Get the TC frequency the corresponds to the requested resolution */
frequency = USEC_PER_SEC / (uint32_t)resolution;
freerun->frequency = frequency;
freerun->tch = stm32l4_tim_init(chan);
if (!freerun->tch)
{
tmrerr("ERROR: Failed to allocate TIM%d\n", chan);
return -EBUSY;
}
STM32L4_TIM_SETCLOCK(freerun->tch, frequency);
/* Initialize the remaining fields in the state structure and return
* success.
*/
freerun->chan = chan;
freerun->running = false;
freerun->overflow = 0;
g_freerun = freerun;
/* Set up to receive the callback when the counter overflow occurs */
STM32L4_TIM_SETISR(freerun->tch, stm32_freerun_handler, 0);
/* Set timer period */
STM32L4_TIM_SETPERIOD(freerun->tch, UINT32_MAX);
/* Start the counter */
STM32L4_TIM_SETMODE(freerun->tch, STM32L4_TIM_MODE_UP);
STM32L4_TIM_ACKINT(freerun->tch, 0);
STM32L4_TIM_ENABLEINT(freerun->tch, 0);
return OK;
}
/****************************************************************************
* Name: stm32l4_freerun_counter
*
* Description:
* Read the counter register of the free-running timer.
*
* Input Parameters:
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
* stm32_freerun_initialize();
* ts The location in which to return the time from the free-running
* timer.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun,
struct timespec *ts)
{
uint64_t usec;
uint32_t counter;
uint32_t verify;
uint32_t overflow;
uint32_t sec;
int pending;
irqstate_t flags;
DEBUGASSERT(freerun && freerun->tch && ts);
/* Temporarily disable the overflow counter. NOTE that we have to be
* careful here because stm32_tc_getpending() will reset the pending
* interrupt status. If we do not handle the overflow here then, it will
* be lost.
*/
flags = enter_critical_section();
overflow = freerun->overflow;
counter = STM32L4_TIM_GETCOUNTER(freerun->tch);
pending = STM32L4_TIM_CHECKINT(freerun->tch, 0);
verify = STM32L4_TIM_GETCOUNTER(freerun->tch);
/* If an interrupt was pending before we re-enabled interrupts,
* then the overflow needs to be incremented.
*/
if (pending)
{
STM32L4_TIM_ACKINT(freerun->tch, 0);
/* Increment the overflow count and use the value of the
* guaranteed to be AFTER the overflow occurred.
*/
overflow++;
counter = verify;
/* Update freerun overflow counter. */
freerun->overflow = overflow;
}
leave_critical_section(flags);
tmrinfo("counter=%lu (%lu) overflow=%lu, pending=%i\n",
(unsigned long)counter, (unsigned long)verify,
(unsigned long)overflow, pending);
tmrinfo("frequency=%u\n", freerun->frequency);
/* Convert the whole thing to units of microseconds.
*
* frequency = ticks / second
* seconds = ticks * frequency
* usecs = (ticks * USEC_PER_SEC) / frequency;
*/
usec = ((((uint64_t)overflow << 32) + (uint64_t)counter) * USEC_PER_SEC) /
freerun->frequency;
/* And return the value of the timer */
sec = (uint32_t)(usec / USEC_PER_SEC);
ts->tv_sec = sec;
ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC;
tmrinfo("usec=%llu ts=(%u, %lu)\n",
usec, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
return OK;
}
/****************************************************************************
* Name: stm32l4_freerun_uninitialize
*
* Description:
* Stop the free-running timer and release all resources that it uses.
*
* Input Parameters:
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
* stm32_freerun_initialize();
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
int stm32l4_freerun_uninitialize(struct stm32l4_freerun_s *freerun)
{
DEBUGASSERT(freerun && freerun->tch);
/* Now we can disable the timer interrupt and disable the timer. */
STM32L4_TIM_DISABLEINT(freerun->tch, 0);
STM32L4_TIM_SETMODE(freerun->tch, STM32L4_TIM_MODE_DISABLED);
STM32L4_TIM_SETISR(freerun->tch, NULL, 0);
/* Free the timer */
stm32l4_tim_deinit(freerun->tch);
freerun->tch = NULL;
g_freerun = NULL;
return OK;
}
#endif /* CONFIG_STM32L4_FREERUN */

159
arch/arm/src/stm32l4/stm32l4_freerun.h Normal file
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@ -0,0 +1,159 @@
/****************************************************************************
* arch/arm/src/stm32l4/stm32l4_freerun.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* dev@ziggurat29.com
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_FREERUN_H
#define __ARCH_ARM_SRC_STM32L4_FREERUN_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <debug.h>
#include "stm32l4_tim.h"
#ifdef CONFIG_STM32L4_FREERUN
/****************************************************************************
* Public Types
****************************************************************************/
/* The freerun client must allocate an instance of this structure and called
* stm32_freerun_initialize() before using the freerun facilities. The client
* should not access the contents of this structure directly since the
* contents are subject to change.
*/
struct stm32l4_freerun_s
{
uint8_t chan; /* The timer/counter in use */
bool running; /* True: the timer is running */
uint32_t overflow; /* Timer counter overflow */
FAR struct stm32l4_tim_dev_s *tch; /* Handle returned by stm32l4_tim_init() */
uint32_t frequency;
};
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32l4_freerun_initialize
*
* Description:
* Initialize the freerun timer wrapper
*
* Input Parameters:
* freerun Caller allocated instance of the freerun state structure
* chan Timer counter channel to be used.
* resolution The required resolution of the timer in units of
* microseconds. NOTE that the range is restricted to the
* range of uint16_t (excluding zero).
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, int chan,
uint16_t resolution);
/****************************************************************************
* Name: stm32l4_freerun_counter
*
* Description:
* Read the counter register of the free-running timer.
*
* Input Parameters:
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
* stm32_freerun_initialize();
* ts The location in which to return the time remaining on the
* oneshot timer.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun,
struct timespec *ts);
/****************************************************************************
* Name: stm32l4_freerun_uninitialize
*
* Description:
* Stop the free-running timer and release all resources that it uses.
*
* Input Parameters:
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
* stm32_freerun_initialize();
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
int stm32l4_freerun_uninitialize(struct stm32l4_freerun_s *freerun);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* CONFIG_STM32L4_FREERUN */
#endif /* __ARCH_ARM_SRC_STM32L4_FREERUN_H */

416
arch/arm/src/stm32l4/stm32l4_oneshot.c Normal file
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@ -0,0 +1,416 @@
/****************************************************************************
* arch/arm/src/stm32l4/stm32l4_oneshot.c
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* dev@ziggurat29.com
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the names NuttX nor Atmel nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/clock.h>
#include "stm32l4_oneshot.h"
#ifdef CONFIG_STM32L4_ONESHOT
/****************************************************************************
* Private Date
****************************************************************************/
static struct stm32l4_oneshot_s *g_oneshot;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_oneshot_handler
*
* Description:
* Timer interrupt callback. When the oneshot timer interrupt expires,
* this function will be called. It will forward the call to the next
* level up.
*
* Input Parameters:
* tch - The handle that represents the timer state
* arg - An opaque argument provided when the interrupt was registered
* sr - The value of the timer interrupt status register at the time
* that the interrupt occurred.
*
* Returned Value:
* None
*
****************************************************************************/
static int stm32_oneshot_handler(int irq, void *context)
{
struct stm32l4_oneshot_s *oneshot = g_oneshot;
oneshot_handler_t oneshot_handler;
void *oneshot_arg;
tmrinfo("Expired...\n");
DEBUGASSERT(oneshot != NULL && oneshot->handler);
/* The clock was stopped, but not disabled when the RC match occurred.
* Disable the TC now and disable any further interrupts.
*/
STM32L4_TIM_SETMODE(oneshot->tch, STM32L4_TIM_MODE_DISABLED);
STM32L4_TIM_ACKINT(oneshot->tch, 0);
STM32L4_TIM_DISABLEINT(oneshot->tch, 0);
/* The timer is no longer running */
oneshot->running = false;
/* Forward the event, clearing out any vestiges */
oneshot_handler = (oneshot_handler_t)oneshot->handler;
oneshot->handler = NULL;
oneshot_arg = (void *)oneshot->arg;
oneshot->arg = NULL;
oneshot_handler(oneshot_arg);
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32l4_oneshot_initialize
*
* Description:
* Initialize the oneshot timer wrapper
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure
* chan Timer counter channel to be used.
* resolution The required resolution of the timer in units of
* microseconds. NOTE that the range is restricted to the
* range of uint16_t (excluding zero).
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
int stm32l4_oneshot_initialize(struct stm32l4_oneshot_s *oneshot, int chan,
uint16_t resolution)
{
uint32_t frequency;
tmrinfo("chan=%d resolution=%d usec\n", chan, resolution);
DEBUGASSERT(oneshot && resolution > 0);
/* Get the TC frequency the corresponds to the requested resolution */
frequency = USEC_PER_SEC / (uint32_t)resolution;
oneshot->frequency = frequency;
oneshot->tch = stm32l4_tim_init(chan);
if (!oneshot->tch)
{
tmrerr("ERROR: Failed to allocate TIM%d\n", chan);
return -EBUSY;
}
STM32L4_TIM_SETCLOCK(oneshot->tch, frequency);
/* Initialize the remaining fields in the state structure and return
* success.
*/
oneshot->chan = chan;
oneshot->running = false;
oneshot->handler = NULL;
oneshot->arg = NULL;
g_oneshot = oneshot;
return OK;
}
/****************************************************************************
* Name: stm32_oneshot_max_delay
*
* Description:
* Determine the maximum delay of the one-shot timer (in microseconds)
*
****************************************************************************/
int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, uint64_t *usec)
{
DEBUGASSERT(oneshot != NULL && usec != NULL);
*usec = (uint64_t)(UINT32_MAX / oneshot->frequency) *
(uint64_t)USEC_PER_SEC;
return OK;
}
/****************************************************************************
* Name: stm32l4_oneshot_start
*
* Description:
* Start the oneshot timer
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* stm32_oneshot_initialize();
* handler The function to call when when the oneshot timer expires.
* arg An opaque argument that will accompany the callback.
* ts Provides the duration of the one shot timer.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot,
oneshot_handler_t handler, void *arg,
const struct timespec *ts)
{
uint64_t usec;
uint64_t period;
irqstate_t flags;
tmrinfo("handler=%p arg=%p, ts=(%lu, %lu)\n",
handler, arg, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
DEBUGASSERT(oneshot && handler && ts);
DEBUGASSERT(oneshot->tch);
/* Was the oneshot already running? */
flags = enter_critical_section();
if (oneshot->running)
{
/* Yes.. then cancel it */
tmrinfo("Already running... cancelling\n");
(void)stm32l4_oneshot_cancel(oneshot, NULL);
}
/* Save the new handler and its argument */
oneshot->handler = handler;
oneshot->arg = arg;
/* Express the delay in microseconds */
usec = (uint64_t)ts->tv_sec * USEC_PER_SEC +
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
/* Get the timer counter frequency and determine the number of counts need
* to achieve the requested delay.
*
* frequency = ticks / second
* ticks = seconds * frequency
* = (usecs * frequency) / USEC_PER_SEC;
*/
period = (usec * (uint64_t)oneshot->frequency) / USEC_PER_SEC;
tmrinfo("usec=%llu period=%08llx\n", usec, period);
DEBUGASSERT(period <= UINT32_MAX);
/* Set up to receive the callback when the interrupt occurs */
STM32L4_TIM_SETISR(oneshot->tch, stm32_oneshot_handler, 0);
/* Set timer period */
oneshot->period = (uint32_t)period;
STM32L4_TIM_SETPERIOD(oneshot->tch, (uint32_t)period);
/* Start the counter */
STM32L4_TIM_SETMODE(oneshot->tch, STM32L4_TIM_MODE_PULSE);
STM32L4_TIM_ACKINT(oneshot->tch, 0);
STM32L4_TIM_ENABLEINT(oneshot->tch, 0);
/* Enable interrupts. We should get the callback when the interrupt
* occurs.
*/
oneshot->running = true;
leave_critical_section(flags);
return OK;
}
/****************************************************************************
* Name: stm32l4_oneshot_cancel
*
* Description:
* Cancel the oneshot timer and return the time remaining on the timer.
*
* NOTE: This function may execute at a high rate with no timer running (as
* when pre-emption is enabled and disabled).
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* stm32_oneshot_initialize();
* ts The location in which to return the time remaining on the
* oneshot timer. A time of zero is returned if the timer is
* not running. ts may be zero in which case the time remaining
* is not returned.
*
* Returned Value:
* Zero (OK) is returned on success. A call to up_timer_cancel() when
* the timer is not active should also return success; a negated errno
* value is returned on any failure.
*
****************************************************************************/
int stm32l4_oneshot_cancel(struct stm32l4_oneshot_s *oneshot,
struct timespec *ts)
{
irqstate_t flags;
uint64_t usec;
uint64_t sec;
uint64_t nsec;
uint32_t count;
uint32_t period;
/* Was the timer running? */
flags = enter_critical_section();
if (!oneshot->running)
{
/* No.. Just return zero timer remaining and successful cancellation.
* This function may execute at a high rate with no timer running
* (as when pre-emption is enabled and disabled).
*/
ts->tv_sec = 0;
ts->tv_nsec = 0;
leave_critical_section(flags);
return OK;
}
/* Yes.. Get the timer counter and period registers and stop the counter.
* If the counter expires while we are doing this, the counter clock will
* be stopped, but the clock will not be disabled.
*
* The expected behavior is that the the counter register will freezes at
* a value equal to the RC register when the timer expires. The counter
* should have values between 0 and RC in all other cased.
*
* REVISIT: This does not appear to be the case.
*/
tmrinfo("Cancelling...\n");
count = STM32L4_TIM_GETCOUNTER(oneshot->tch);
period = oneshot->period;
/* Now we can disable the interrupt and stop the timer. */
STM32L4_TIM_DISABLEINT(oneshot->tch, 0);
STM32L4_TIM_SETMODE(oneshot->tch, STM32L4_TIM_MODE_DISABLED);
oneshot->running = false;
oneshot->handler = NULL;
oneshot->arg = NULL;
leave_critical_section(flags);
/* Did the caller provide us with a location to return the time
* remaining?
*/
if (ts)
{
/* Yes.. then calculate and return the time remaining on the
* oneshot timer.
*/
tmrinfo("period=%lu count=%lu\n",
(unsigned long)period, (unsigned long)count);
/* REVISIT: I am not certain why the timer counter value sometimes
* exceeds RC. Might be a bug, or perhaps the counter does not stop
* in all cases.
*/
if (count >= period)
{
/* No time remaining (?) */
ts->tv_sec = 0;
ts->tv_nsec = 0;
}
else
{
/* The total time remaining is the difference. Convert the that
* to units of microseconds.
*
* frequency = ticks / second
* seconds = ticks * frequency
* usecs = (ticks * USEC_PER_SEC) / frequency;
*/
usec = (((uint64_t)(period - count)) * USEC_PER_SEC) /
oneshot->frequency;
/* Return the time remaining in the correct form */
sec = usec / USEC_PER_SEC;
nsec = ((usec) - (sec * USEC_PER_SEC)) * NSEC_PER_USEC;
ts->tv_sec = (time_t)sec;
ts->tv_nsec = (unsigned long)nsec;
}
tmrinfo("remaining (%lu, %lu)\n",
(unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
}
return OK;
}
#endif /* CONFIG_STM32L4_ONESHOT */

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/****************************************************************************
* arch/arm/src/stm32l4/stm32l4_oneshot.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* dev@ziggurat29.com
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_ONESHOT_H
#define __ARCH_ARM_SRC_STM32L4_ONESHOT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include "stm32l4_tim.h"
#ifdef CONFIG_STM32L4_ONESHOT
/****************************************************************************
* Public Types
****************************************************************************/
/* This describes the callback function that will be invoked when the oneshot
* timer expires. The oneshot fires, the client will receive:
*
* arg - The opaque argument provided when the interrupt was registered
*/
typedef void (*oneshot_handler_t)(void *arg);
/* The oneshot client must allocate an instance of this structure and called
* stm32_oneshot_initialize() before using the oneshot facilities. The client
* should not access the contents of this structure directly since the
* contents are subject to change.
*/
struct stm32l4_oneshot_s
{
uint8_t chan; /* The timer/counter in use */
volatile bool running; /* True: the timer is running */
FAR struct stm32l4_tim_dev_s *tch; /* Pointer returned by
* stm32l4_tim_init() */
volatile oneshot_handler_t handler; /* Oneshot expiration callback */
volatile void *arg; /* The argument that will accompany
* the callback */
uint32_t frequency;
uint32_t period;
};
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32l4_oneshot_initialize
*
* Description:
* Initialize the oneshot timer wrapper
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure
* chan Timer counter channel to be used.
* resolution The required resolution of the timer in units of
* microseconds. NOTE that the range is restricted to the
* range of uint16_t (excluding zero).
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
int stm32l4_oneshot_initialize(struct stm32l4_oneshot_s *oneshot, int chan,
uint16_t resolution);
/****************************************************************************
* Name: stm32l4_oneshot_max_delay
*
* Description:
* Determine the maximum delay of the one-shot timer (in microseconds)
*
****************************************************************************/
int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, uint64_t *usec);
/****************************************************************************
* Name: stm32l4_oneshot_start
*
* Description:
* Start the oneshot timer
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* stm32_oneshot_initialize();
* handler The function to call when when the oneshot timer expires.
* arg An opaque argument that will accompany the callback.
* ts Provides the duration of the one shot timer.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot,
oneshot_handler_t handler, void *arg,
const struct timespec *ts);
/****************************************************************************
* Name: stm32l4_oneshot_cancel
*
* Description:
* Cancel the oneshot timer and return the time remaining on the timer.
*
* NOTE: This function may execute at a high rate with no timer running (as
* when pre-emption is enabled and disabled).
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* stm32_oneshot_initialize();
* ts The location in which to return the time remaining on the
* oneshot timer. A time of zero is returned if the timer is
* not running.
*
* Returned Value:
* Zero (OK) is returned on success. A call to up_timer_cancel() when
* the timer is not active should also return success; a negated errno
* value is returned on any failure.
*
****************************************************************************/
int stm32l4_oneshot_cancel(struct stm32l4_oneshot_s *oneshot,
struct timespec *ts);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* CONFIG_STM32L4_ONESHOT */
#endif /* __ARCH_ARM_SRC_STM32L4_ONESHOT_H */

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/************************************************************************************
* arch/arm/src/stm32l4/stm32l4_pwm.h
*
* Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_PWM_H
#define __ARCH_ARM_SRC_STM32L4_STM32L4_PWM_H
/* The STM32L4 does not have dedicated PWM hardware. Rather, pulsed output control
* is a capability of the STM32L4 timers. The logic in this file implements the
* lower half of the standard, NuttX PWM interface using the STM32L4 timers. That
* interface is described in include/nuttx/pwm.h.
*/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
/* Timer devices may be used for different purposes. One special purpose is
* to generate modulated outputs for such things as motor control. If CONFIG_STM32L4_TIMn
* is defined then the CONFIG_STM32L4_TIMn_PWM must also be defined to indicate that
* timer "n" is intended to be used for pulsed output signal generation.
*/
#ifndef CONFIG_STM32L4_TIM1
# undef CONFIG_STM32L4_TIM1_PWM
#endif
#ifndef CONFIG_STM32L4_TIM2
# undef CONFIG_STM32L4_TIM2_PWM
#endif
#ifndef CONFIG_STM32L4_TIM3
# undef CONFIG_STM32L4_TIM3_PWM
#endif
#ifndef CONFIG_STM32L4_TIM4
# undef CONFIG_STM32L4_TIM4_PWM
#endif
#ifndef CONFIG_STM32L4_TIM5
# undef CONFIG_STM32L4_TIM5_PWM
#endif
#ifndef CONFIG_STM32L4_TIM8
# undef CONFIG_STM32L4_TIM8_PWM
#endif
#ifndef CONFIG_STM32L4_TIM15
# undef CONFIG_STM32L4_TIM15_PWM
#endif
#ifndef CONFIG_STM32L4_TIM16
# undef CONFIG_STM32L4_TIM16_PWM
#endif
#ifndef CONFIG_STM32L4_TIM17
# undef CONFIG_STM32L4_TIM17_PWM
#endif
/* The basic timers (timer 6 and 7) are not capable of generating output pulses */
#undef CONFIG_STM32L4_TIM6_PWM
#undef CONFIG_STM32L4_TIM7_PWM
/* Check if PWM support for any channel is enabled. */
#if defined(CONFIG_STM32L4_TIM1_PWM) || defined(CONFIG_STM32L4_TIM2_PWM) || \
defined(CONFIG_STM32L4_TIM3_PWM) || defined(CONFIG_STM32L4_TIM4_PWM) || \
defined(CONFIG_STM32L4_TIM5_PWM) || defined(CONFIG_STM32L4_TIM8_PWM) || \
defined(CONFIG_STM32L4_TIM15_PWM) || defined(CONFIG_STM32L4_TIM16_PWM) || \
defined(CONFIG_STM32L4_TIM17_PWM)
#include <arch/board/board.h>
#include "chip/stm32l4_tim.h"
#ifdef CONFIG_PWM_MULTICHAN
#ifdef CONFIG_STM32L4_TIM1_CHANNEL1
# ifdef CONFIG_STM32L4_TIM1_CH1OUT
# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT
# else
# define PWM_TIM1_CH1CFG 0
# endif
# define PWM_TIM1_CHANNEL1 1
#else
# define PWM_TIM1_CHANNEL1 0
#endif
#ifdef CONFIG_STM32L4_TIM1_CHANNEL2
# ifdef CONFIG_STM32L4_TIM1_CH2OUT
# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT
# else
# define PWM_TIM1_CH2CFG 0
# endif
# define PWM_TIM1_CHANNEL2 1
#else
# define PWM_TIM1_CHANNEL2 0
#endif
#ifdef CONFIG_STM32L4_TIM1_CHANNEL3
# ifdef CONFIG_STM32L4_TIM1_CH3OUT
# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT
# else
# define PWM_TIM1_CH3CFG 0
# endif
# define PWM_TIM1_CHANNEL3 1
#else
# define PWM_TIM1_CHANNEL3 0
#endif
#ifdef CONFIG_STM32L4_TIM1_CHANNEL4
# ifdef CONFIG_STM32L4_TIM1_CH4OUT
# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT
# else
# define PWM_TIM1_CH4CFG 0
# endif
# define PWM_TIM1_CHANNEL4 1
#else
# define PWM_TIM1_CHANNEL4 0
#endif
#define PWM_TIM1_NCHANNELS (PWM_TIM1_CHANNEL1 + PWM_TIM1_CHANNEL2 + \
PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4)
#ifdef CONFIG_STM32L4_TIM2_CHANNEL1
# ifdef CONFIG_STM32L4_TIM2_CH1OUT
# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT
# else
# define PWM_TIM2_CH1CFG 0
# endif
# define PWM_TIM2_CHANNEL1 1
#else
# define PWM_TIM2_CHANNEL1 0
#endif
#ifdef CONFIG_STM32L4_TIM2_CHANNEL2
# ifdef CONFIG_STM32L4_TIM2_CH2OUT
# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT
# else
# define PWM_TIM2_CH2CFG 0
# endif
# define PWM_TIM2_CHANNEL2 1
#else
# define PWM_TIM2_CHANNEL2 0
#endif
#ifdef CONFIG_STM32L4_TIM2_CHANNEL3
# ifdef CONFIG_STM32L4_TIM2_CH3OUT
# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT
# else
# define PWM_TIM2_CH3CFG 0
# endif
# define PWM_TIM2_CHANNEL3 1
#else
# define PWM_TIM2_CHANNEL3 0
#endif
#ifdef CONFIG_STM32L4_TIM2_CHANNEL4
# ifdef CONFIG_STM32L4_TIM2_CH4OUT
# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT
# else
# define PWM_TIM2_CH4CFG 0
# endif
# define PWM_TIM2_CHANNEL4 1
#else
# define PWM_TIM2_CHANNEL4 0
#endif
#define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \
PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4)
#ifdef CONFIG_STM32L4_TIM3_CHANNEL1
# ifdef CONFIG_STM32L4_TIM3_CH1OUT
# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT
# else
# define PWM_TIM3_CH1CFG 0
# endif
# define PWM_TIM3_CHANNEL1 1
#else
# define PWM_TIM3_CHANNEL1 0
#endif
#ifdef CONFIG_STM32L4_TIM3_CHANNEL2
# ifdef CONFIG_STM32L4_TIM3_CH2OUT
# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT
# else
# define PWM_TIM3_CH2CFG 0
# endif
# define PWM_TIM3_CHANNEL2 1
#else
# define PWM_TIM3_CHANNEL2 0
#endif
#ifdef CONFIG_STM32L4_TIM3_CHANNEL3
# ifdef CONFIG_STM32L4_TIM3_CH3OUT
# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT
# else
# define PWM_TIM3_CH3CFG 0
# endif
# define PWM_TIM3_CHANNEL3 1
#else
# define PWM_TIM3_CHANNEL3 0
#endif
#ifdef CONFIG_STM32L4_TIM3_CHANNEL4
# ifdef CONFIG_STM32L4_TIM3_CH4OUT
# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT
# else
# define PWM_TIM3_CH4CFG 0
# endif
# define PWM_TIM3_CHANNEL4 1
#else
# define PWM_TIM3_CHANNEL4 0
#endif
#define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \
PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4)
#ifdef CONFIG_STM32L4_TIM4_CHANNEL1
# ifdef CONFIG_STM32L4_TIM4_CH1OUT
# define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT
# else
# define PWM_TIM4_CH1CFG 0
# endif
# define PWM_TIM4_CHANNEL1 1
#else
# define PWM_TIM4_CHANNEL1 0
#endif
#ifdef CONFIG_STM32L4_TIM4_CHANNEL2
# ifdef CONFIG_STM32L4_TIM4_CH2OUT
# define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT
# else
# define PWM_TIM4_CH2CFG 0
# endif
# define PWM_TIM4_CHANNEL2 1
#else
# define PWM_TIM4_CHANNEL2 0
#endif
#ifdef CONFIG_STM32L4_TIM4_CHANNEL3
# ifdef CONFIG_STM32L4_TIM4_CH3OUT
# define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT
# else
# define PWM_TIM4_CH3CFG 0
# endif
# define PWM_TIM4_CHANNEL3 1
#else
# define PWM_TIM4_CHANNEL3 0
#endif
#ifdef CONFIG_STM32L4_TIM4_CHANNEL4
# ifdef CONFIG_STM32L4_TIM4_CH4OUT
# define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT
# else
# define PWM_TIM4_CH4CFG 0
# endif
# define PWM_TIM4_CHANNEL4 1
#else
# define PWM_TIM4_CHANNEL4 0
#endif
#define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \
PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4)
#ifdef CONFIG_STM32L4_TIM5_CHANNEL1
# ifdef CONFIG_STM32L4_TIM5_CH1OUT
# define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT
# else
# define PWM_TIM5_CH1CFG 0
# endif
# define PWM_TIM5_CHANNEL1 1
#else
# define PWM_TIM5_CHANNEL1 0
#endif
#ifdef CONFIG_STM32L4_TIM5_CHANNEL2
# ifdef CONFIG_STM32L4_TIM5_CH2OUT
# define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT
# else
# define PWM_TIM5_CH2CFG 0
# endif
# define PWM_TIM5_CHANNEL2 1
#else
# define PWM_TIM5_CHANNEL2 0
#endif
#ifdef CONFIG_STM32L4_TIM5_CHANNEL3
# ifdef CONFIG_STM32L4_TIM5_CH3OUT
# define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT
# else
# define PWM_TIM5_CH3CFG 0
# endif
# define PWM_TIM5_CHANNEL3 1
#else
# define PWM_TIM5_CHANNEL3 0
#endif
#ifdef CONFIG_STM32L4_TIM5_CHANNEL4
# ifdef CONFIG_STM32L4_TIM5_CH4OUT
# define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT
# else
# define PWM_TIM5_CH4CFG 0
# endif
# define PWM_TIM5_CHANNEL4 1
#else
# define PWM_TIM5_CHANNEL4 0
#endif
#define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \
PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4)
#ifdef CONFIG_STM32L4_TIM8_CHANNEL1
# ifdef CONFIG_STM32L4_TIM8_CH1OUT
# define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT
# else
# define PWM_TIM8_CH1CFG 0
# endif
# define PWM_TIM8_CHANNEL1 1
#else
# define PWM_TIM8_CHANNEL1 0
#endif
#ifdef CONFIG_STM32L4_TIM8_CHANNEL2
# ifdef CONFIG_STM32L4_TIM8_CH2OUT
# define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT
# else
# define PWM_TIM8_CH2CFG 0
# endif
# define PWM_TIM8_CHANNEL2 1
#else
# define PWM_TIM8_CHANNEL2 0
#endif
#ifdef CONFIG_STM32L4_TIM8_CHANNEL3
# ifdef CONFIG_STM32L4_TIM8_CH3OUT
# define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT
# else
# define PWM_TIM8_CH3CFG 0
# endif
# define PWM_TIM8_CHANNEL3 1
#else
# define PWM_TIM8_CHANNEL3 0
#endif
#ifdef CONFIG_STM32L4_TIM8_CHANNEL4
# ifdef CONFIG_STM32L4_TIM8_CH4OUT
# define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT
# else
# define PWM_TIM8_CH4CFG 0
# endif
# define PWM_TIM8_CHANNEL4 1
#else
# define PWM_TIM8_CHANNEL4 0
#endif
#define PWM_TIM8_NCHANNELS (PWM_TIM8_CHANNEL1 + PWM_TIM8_CHANNEL2 + \
PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4)
#ifdef CONFIG_STM32L4_TIM15_CHANNEL1
# ifdef CONFIG_STM32L4_TIM15_CH1OUT
# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT
# else
# define PWM_TIM15_CH1CFG 0
# endif
# define PWM_TIM15_CHANNEL1 1
#else
# define PWM_TIM15_CHANNEL1 0
#endif
#ifdef CONFIG_STM32L4_TIM15_CHANNEL2
# ifdef CONFIG_STM32L4_TIM15_CH2OUT
# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT
# else
# define PWM_TIM15_CH2CFG 0
# endif
# define PWM_TIM15_CHANNEL2 1
#else
# define PWM_TIM15_CHANNEL2 0
#endif
#define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2)
#ifdef CONFIG_STM32L4_TIM16_CHANNEL1
# ifdef CONFIG_STM32L4_TIM16_CH1OUT
# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT
# else
# define PWM_TIM16_CH1CFG 0
# endif
# define PWM_TIM16_CHANNEL1 1
#else
# define PWM_TIM16_CHANNEL1 0
#endif
#define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1
#ifdef CONFIG_STM32L4_TIM17_CHANNEL1
# ifdef CONFIG_STM32L4_TIM17_CH1OUT
# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT
# else
# define PWM_TIM17_CH1CFG 0
# endif
# define PWM_TIM17_CHANNEL1 1
#else
# define PWM_TIM17_CHANNEL1 0
#endif
#define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1
#define PWM_MAX(a, b) ((a) > (b) ? (a) : (b))
#define PWM_NCHANNELS PWM_MAX(PWM_TIM1_NCHANNELS, \
PWM_MAX(PWM_TIM2_NCHANNELS, \
PWM_MAX(PWM_TIM3_NCHANNELS, \
PWM_MAX(PWM_TIM4_NCHANNELS, \
PWM_MAX(PWM_TIM5_NCHANNELS, \
PWM_MAX(PWM_TIM8_NCHANNELS, \
PWM_MAX(PWM_TIM15_NCHANNELS, \
PWM_MAX(PWM_TIM16_NCHANNELS, \
PWM_TIM17_NCHANNELS))))))))))))))
#else
/* For each timer that is enabled for PWM usage, we need the following additional
* configuration settings:
*
* CONFIG_STM32L4_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
* PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h. In the case
* where there are multiple pin selections, the correct setting must be provided
* in the arch/board/board.h file.
*
* NOTE: The STM32L4 timers are each capable of generating different signals on
* each of the four channels with different duty cycles. That capability is
* not supported by this driver: Only one output channel per timer.
*/
#ifdef CONFIG_STM32L4_TIM1_PWM
# if !defined(CONFIG_STM32L4_TIM1_CHANNEL)
# error "CONFIG_STM32L4_TIM1_CHANNEL must be provided"
# elif CONFIG_STM32L4_TIM1_CHANNEL == 1
# define CONFIG_STM32L4_TIM1_CHANNEL1 1
# define CONFIG_STM32L4_TIM1_CH1MODE CONFIG_STM32L4_TIM1_CHMODE
# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT
# elif CONFIG_STM32L4_TIM1_CHANNEL == 2
# define CONFIG_STM32L4_TIM1_CHANNEL2 1
# define CONFIG_STM32L4_TIM1_CH2MODE CONFIG_STM32L4_TIM1_CHMODE
# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT
# elif CONFIG_STM32L4_TIM1_CHANNEL == 3
# define CONFIG_STM32L4_TIM1_CHANNEL3 1
# define CONFIG_STM32L4_TIM1_CH3MODE CONFIG_STM32L4_TIM1_CHMODE
# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT
# elif CONFIG_STM32L4_TIM1_CHANNEL == 4
# define CONFIG_STM32L4_TIM1_CHANNEL4 1
# define CONFIG_STM32L4_TIM1_CH4MODE CONFIG_STM32L4_TIM1_CHMODE
# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32L4_TIM1_CHANNEL"
# endif
#endif
#ifdef CONFIG_STM32L4_TIM2_PWM
# if !defined(CONFIG_STM32L4_TIM2_CHANNEL)
# error "CONFIG_STM32L4_TIM2_CHANNEL must be provided"
# elif CONFIG_STM32L4_TIM2_CHANNEL == 1
# define CONFIG_STM32L4_TIM2_CHANNEL1 1
# define CONFIG_STM32L4_TIM2_CH1MODE CONFIG_STM32L4_TIM2_CHMODE
# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT
# elif CONFIG_STM32L4_TIM2_CHANNEL == 2
# define CONFIG_STM32L4_TIM2_CHANNEL2 1
# define CONFIG_STM32L4_TIM2_CH2MODE CONFIG_STM32L4_TIM2_CHMODE
# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT
# elif CONFIG_STM32L4_TIM2_CHANNEL == 3
# define CONFIG_STM32L4_TIM2_CHANNEL3 1
# define CONFIG_STM32L4_TIM2_CH3MODE CONFIG_STM32L4_TIM2_CHMODE
# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT
# elif CONFIG_STM32L4_TIM2_CHANNEL == 4
# define CONFIG_STM32L4_TIM2_CHANNEL4 1
# define CONFIG_STM32L4_TIM2_CH4MODE CONFIG_STM32L4_TIM2_CHMODE
# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32L4_TIM2_CHANNEL"
# endif
#endif
#ifdef CONFIG_STM32L4_TIM3_PWM
# if !defined(CONFIG_STM32L4_TIM3_CHANNEL)
# error "CONFIG_STM32L4_TIM3_CHANNEL must be provided"
# elif CONFIG_STM32L4_TIM3_CHANNEL == 1
# define CONFIG_STM32L4_TIM3_CHANNEL1 1
# define CONFIG_STM32L4_TIM3_CH1MODE CONFIG_STM32L4_TIM3_CHMODE
# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT
# elif CONFIG_STM32L4_TIM3_CHANNEL == 2
# define CONFIG_STM32L4_TIM3_CHANNEL2 1
# define CONFIG_STM32L4_TIM3_CH2MODE CONFIG_STM32L4_TIM3_CHMODE
# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT
# elif CONFIG_STM32L4_TIM3_CHANNEL == 3
# define CONFIG_STM32L4_TIM3_CHANNEL3 1
# define CONFIG_STM32L4_TIM3_CH3MODE CONFIG_STM32L4_TIM3_CHMODE
# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT
# elif CONFIG_STM32L4_TIM3_CHANNEL == 4
# define CONFIG_STM32L4_TIM3_CHANNEL4 1
# define CONFIG_STM32L4_TIM3_CH4MODE CONFIG_STM32L4_TIM3_CHMODE
# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32L4_TIM3_CHANNEL"
# endif
#endif
#ifdef CONFIG_STM32L4_TIM4_PWM
# if !defined(CONFIG_STM32L4_TIM4_CHANNEL)
# error "CONFIG_STM32L4_TIM4_CHANNEL must be provided"
# elif CONFIG_STM32L4_TIM4_CHANNEL == 1
# define CONFIG_STM32L4_TIM4_CHANNEL1 1
# define CONFIG_STM32L4_TIM4_CH1MODE CONFIG_STM32L4_TIM4_CHMODE
# define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT
# elif CONFIG_STM32L4_TIM4_CHANNEL == 2
# define CONFIG_STM32L4_TIM4_CHANNEL2 1
# define CONFIG_STM32L4_TIM4_CH2MODE CONFIG_STM32L4_TIM4_CHMODE
# define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT
# elif CONFIG_STM32L4_TIM4_CHANNEL == 3
# define CONFIG_STM32L4_TIM4_CHANNEL3 1
# define CONFIG_STM32L4_TIM4_CH3MODE CONFIG_STM32L4_TIM4_CHMODE
# define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT
# elif CONFIG_STM32L4_TIM4_CHANNEL == 4
# define CONFIG_STM32L4_TIM4_CHANNEL4 1
# define CONFIG_STM32L4_TIM4_CH4MODE CONFIG_STM32L4_TIM4_CHMODE
# define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32L4_TIM4_CHANNEL"
# endif
#endif
#ifdef CONFIG_STM32L4_TIM5_PWM
# if !defined(CONFIG_STM32L4_TIM5_CHANNEL)
# error "CONFIG_STM32L4_TIM5_CHANNEL must be provided"
# elif CONFIG_STM32L4_TIM5_CHANNEL == 1
# define CONFIG_STM32L4_TIM5_CHANNEL1 1
# define CONFIG_STM32L4_TIM5_CH1MODE CONFIG_STM32L4_TIM5_CHMODE
# define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT
# elif CONFIG_STM32L4_TIM5_CHANNEL == 2
# define CONFIG_STM32L4_TIM5_CHANNEL2 1
# define CONFIG_STM32L4_TIM5_CH2MODE CONFIG_STM32L4_TIM5_CHMODE
# define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT
# elif CONFIG_STM32L4_TIM5_CHANNEL == 3
# define CONFIG_STM32L4_TIM5_CHANNEL3 1
# define CONFIG_STM32L4_TIM5_CH3MODE CONFIG_STM32L4_TIM5_CHMODE
# define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT
# elif CONFIG_STM32L4_TIM5_CHANNEL == 4
# define CONFIG_STM32L4_TIM5_CHANNEL4 1
# define CONFIG_STM32L4_TIM5_CH4MODE CONFIG_STM32L4_TIM5_CHMODE
# define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32L4_TIM5_CHANNEL"
# endif
#endif
#ifdef CONFIG_STM32L4_TIM8_PWM
# if !defined(CONFIG_STM32L4_TIM8_CHANNEL)
# error "CONFIG_STM32L4_TIM8_CHANNEL must be provided"
# elif CONFIG_STM32L4_TIM8_CHANNEL == 1
# define CONFIG_STM32L4_TIM8_CHANNEL1 1
# define CONFIG_STM32L4_TIM8_CH1MODE CONFIG_STM32L4_TIM8_CHMODE
# define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT
# elif CONFIG_STM32L4_TIM8_CHANNEL == 2
# define CONFIG_STM32L4_TIM8_CHANNEL2 1
# define CONFIG_STM32L4_TIM8_CH2MODE CONFIG_STM32L4_TIM8_CHMODE
# define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT
# elif CONFIG_STM32L4_TIM8_CHANNEL == 3
# define CONFIG_STM32L4_TIM8_CHANNEL3 1
# define CONFIG_STM32L4_TIM8_CH3MODE CONFIG_STM32L4_TIM8_CHMODE
# define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT
# elif CONFIG_STM32L4_TIM8_CHANNEL == 4
# define CONFIG_STM32L4_TIM8_CHANNEL4 1
# define CONFIG_STM32L4_TIM8_CH4MODE CONFIG_STM32L4_TIM8_CHMODE
# define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32L4_TIM8_CHANNEL"
# endif
#endif
#ifdef CONFIG_STM32L4_TIM15_PWM
# if !defined(CONFIG_STM32L4_TIM15_CHANNEL)
# error "CONFIG_STM32L4_TIM15_CHANNEL must be provided"
# elif CONFIG_STM32L4_TIM15_CHANNEL == 1
# define CONFIG_STM32L4_TIM15_CHANNEL1 1
# define CONFIG_STM32L4_TIM15_CH1MODE CONFIG_STM32L4_TIM15_CHMODE
# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT
# elif CONFIG_STM32L4_TIM15_CHANNEL == 2
# define CONFIG_STM32L4_TIM15_CHANNEL2 1
# define CONFIG_STM32L4_TIM15_CH2MODE CONFIG_STM32L4_TIM15_CHMODE
# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT
# else
# error "Unsupported value of CONFIG_STM32L4_TIM15_CHANNEL"
# endif
#endif
#ifdef CONFIG_STM32L4_TIM16_PWM
# if !defined(CONFIG_STM32L4_TIM16_CHANNEL)
# error "CONFIG_STM32L4_TIM16_CHANNEL must be provided"
# elif CONFIG_STM32L4_TIM16_CHANNEL == 1
# define CONFIG_STM32L4_TIM16_CHANNEL1 1
# define CONFIG_STM32L4_TIM16_CH1MODE CONFIG_STM32L4_TIM16_CHMODE
# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT
# else
# error "Unsupported value of CONFIG_STM32L4_TIM16_CHANNEL"
# endif
#endif
#ifdef CONFIG_STM32L4_TIM17_PWM
# if !defined(CONFIG_STM32L4_TIM17_CHANNEL)
# error "CONFIG_STM32L4_TIM17_CHANNEL must be provided"
# elif CONFIG_STM32L4_TIM17_CHANNEL == 1
# define CONFIG_STM32L4_TIM17_CHANNEL1 1
# define CONFIG_STM32L4_TIM17_CH1MODE CONFIG_STM32L4_TIM17_CHMODE
# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT
# else
# error "Unsupported value of CONFIG_STM32L4_TIM17_CHANNEL"
# endif
#endif
#define PWM_NCHANNELS 1
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: stm32l4_pwminitialize
*
* Description:
* Initialize one timer for use with the upper_level PWM driver.
*
* Input Parameters:
* timer - A number identifying the timer use. The number of valid timer
* IDs varies with the STM32 MCU and MCU family but is somewhere in
* the range of {1,..,17}.
*
* Returned Value:
* On success, a pointer to the STM32 lower half PWM driver is returned.
* NULL is returned on any failure.
*
************************************************************************************/
FAR struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32L4_TIMx_PWM */
#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_PWM_H */

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/****************************************************************************
* arch/arm/src/stm32l4/stm32l4_tickless.c
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* dev@ziggurat29.com
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Tickless OS Support.
*
* When CONFIG_SCHED_TICKLESS is enabled, all support for timer interrupts
* is suppressed and the platform specific code is expected to provide the
* following custom functions.
*
* void up_timer_initialize(void): Initializes the timer facilities.
* Called early in the initialization sequence (by up_intialize()).
* int up_timer_gettime(FAR struct timespec *ts): Returns the current
* time from the platform specific time source.
* int up_timer_cancel(void): Cancels the interval timer.
* int up_timer_start(FAR const struct timespec *ts): Start (or re-starts)
* the interval timer.
*
* The RTOS will provide the following interfaces for use by the platform-
* specific interval timer implementation:
*
* void sched_timer_expiration(void): Called by the platform-specific
* logic when the interval timer expires.
*
****************************************************************************/
/****************************************************************************
* STM32L4 Timer Usage
*
* This current implementation uses two timers: A one-shot timer to provide
* the timed events and a free running timer to provide the current time.
* Since timers are a limited resource, that could be an issue on some
* systems.
*
* We could do the job with a single timer if we were to keep the single
* timer in a free-running at all times. The STM32 timer/counters have
* 16-bit/32-bit counters with the capability to generate a compare interrupt
* when the timer matches a compare value but also to continue counting
* without stopping (giving another, different interrupt when the timer
* rolls over from 0xffffffff to zero). So we could potentially just set
* the compare at the number of ticks you want PLUS the current value of
* timer. Then you could have both with a single timer: An interval timer
* and a free-running counter with the same timer!
*
* Patches are welcome!
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <nuttx/arch.h>
#include <debug.h>
#include "stm32l4_oneshot.h"
#include "stm32l4_freerun.h"
#ifdef CONFIG_SCHED_TICKLESS
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef CONFIG_STM32L4_ONESHOT
# error CONFIG_STM32L4_ONESHOT must be selected for the Tickless OS option
#endif
#ifndef CONFIG_STM32L4_FREERUN
# error CONFIG_STM32L4_FREERUN must be selected for the Tickless OS option
#endif
#ifndef CONFIG_STM32L4_TICKLESS_FREERUN
# error CONFIG_STM32L4_TICKLESS_FREERUN must be selected for the Tickless OS option
#endif
#ifndef CONFIG_STM32L4_TICKLESS_ONESHOT
# error CONFIG_STM32L4_TICKLESS_ONESHOT must be selected for the Tickless OS option
#endif
/****************************************************************************
* Private Types
****************************************************************************/
struct stm32_tickless_s
{
struct stm32l4_oneshot_s oneshot;
struct stm32l4_freerun_s freerun;
};
/****************************************************************************
* Private Data
****************************************************************************/
static struct stm32_tickless_s g_tickless;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_oneshot_handler
*
* Description:
* Called when the one shot timer expires
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
* Assumptions:
* Called early in the initialization sequence before any special
* concurrency protections are required.
*
****************************************************************************/
static void stm32_oneshot_handler(void *arg)
{
tmrinfo("Expired...\n");
sched_timer_expiration();
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_timer_initialize
*
* Description:
* Initializes all platform-specific timer facilities. This function is
* called early in the initialization sequence by up_intialize().
* On return, the current up-time should be available from
* up_timer_gettime() and the interval timer is ready for use (but not
* actively timing.
*
* Provided by platform-specific code and called from the architecture-
* specific logic.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
* Assumptions:
* Called early in the initialization sequence before any special
* concurrency protections are required.
*
****************************************************************************/
void up_timer_initialize(void)
{
#ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP
uint64_t max_delay;
#endif
int ret;
/* Initialize the one-shot timer */
ret = stm32l4_oneshot_initialize(&g_tickless.oneshot,
CONFIG_STM32L4_TICKLESS_ONESHOT,
CONFIG_USEC_PER_TICK);
if (ret < 0)
{
tmrerr("ERROR: stm32_oneshot_initialize failed\n");
PANIC();
}
#ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP
/* Get the maximum delay of the one-shot timer in microseconds */
ret = stm32l4_oneshot_max_delay(&g_tickless.oneshot, &max_delay);
if (ret < 0)
{
tmrerr("ERROR: stm32_oneshot_max_delay failed\n");
PANIC();
}
/* Convert this to configured clock ticks for use by the OS timer logic */
max_delay /= CONFIG_USEC_PER_TICK;
if (max_delay > UINT32_MAX)
{
g_oneshot_maxticks = UINT32_MAX;
}
else
{
g_oneshot_maxticks = max_delay;
}
#endif
/* Initialize the free-running timer */
ret = stm32l4_freerun_initialize(&g_tickless.freerun,
CONFIG_STM32L4_TICKLESS_FREERUN,
CONFIG_USEC_PER_TICK);
if (ret < 0)
{
tmrerr("ERROR: stm32_freerun_initialize failed\n");
PANIC();
}
}
/****************************************************************************
* Name: up_timer_gettime
*
* Description:
* Return the elapsed time since power-up (or, more correctly, since
* up_timer_initialize() was called). This function is functionally
* equivalent to:
*
* int clock_gettime(clockid_t clockid, FAR struct timespec *ts);
*
* when clockid is CLOCK_MONOTONIC.
*
* This function provides the basis for reporting the current time and
* also is used to eliminate error build-up from small errors in interval
* time calculations.
*
* Provided by platform-specific code and called from the RTOS base code.
*
* Input Parameters:
* ts - Provides the location in which to return the up-time.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure.
*
* Assumptions:
* Called from the the normal tasking context. The implementation must
* provide whatever mutual exclusion is necessary for correct operation.
* This can include disabling interrupts in order to assure atomic register
* operations.
*
****************************************************************************/
int up_timer_gettime(FAR struct timespec *ts)
{
return stm32l4_freerun_counter(&g_tickless.freerun, ts);
}
/****************************************************************************
* Name: up_timer_cancel
*
* Description:
* Cancel the interval timer and return the time remaining on the timer.
* These two steps need to be as nearly atomic as possible.
* sched_timer_expiration() will not be called unless the timer is
* restarted with up_timer_start().
*
* If, as a race condition, the timer has already expired when this
* function is called, then that pending interrupt must be cleared so
* that up_timer_start() and the remaining time of zero should be
* returned.
*
* NOTE: This function may execute at a high rate with no timer running (as
* when pre-emption is enabled and disabled).
*
* Provided by platform-specific code and called from the RTOS base code.
*
* Input Parameters:
* ts - Location to return the remaining time. Zero should be returned
* if the timer is not active. ts may be zero in which case the
* time remaining is not returned.
*
* Returned Value:
* Zero (OK) is returned on success. A call to up_timer_cancel() when
* the timer is not active should also return success; a negated errno
* value is returned on any failure.
*
* Assumptions:
* May be called from interrupt level handling or from the normal tasking
* level. Interrupts may need to be disabled internally to assure
* non-reentrancy.
*
****************************************************************************/
int up_timer_cancel(FAR struct timespec *ts)
{
return stm32l4_oneshot_cancel(&g_tickless.oneshot, ts);
}
/****************************************************************************
* Name: up_timer_start
*
* Description:
* Start the interval timer. sched_timer_expiration() will be
* called at the completion of the timeout (unless up_timer_cancel
* is called to stop the timing.
*
* Provided by platform-specific code and called from the RTOS base code.
*
* Input Parameters:
* ts - Provides the time interval until sched_timer_expiration() is
* called.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure.
*
* Assumptions:
* May be called from interrupt level handling or from the normal tasking
* level. Interrupts may need to be disabled internally to assure
* non-reentrancy.
*
****************************************************************************/
int up_timer_start(FAR const struct timespec *ts)
{
return stm32l4_oneshot_start(&g_tickless.oneshot, stm32_oneshot_handler, NULL, ts);
}
#endif /* CONFIG_SCHED_TICKLESS */

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/************************************************************************************
* arch/arm/src/stm32l4/stm32l4_tim.h
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
* Author: Uros Platise <uros.platise@isotel.eu>
*
* With modifications and updates by:
*
* Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* dev@ziggurat29.com
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_TIM_H
#define __ARCH_ARM_SRC_STM32L4_STM32L4_TIM_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/stm32l4_tim.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Helpers **************************************************************************/
#define STM32L4_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode))
#define STM32L4_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq))
#define STM32L4_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period))
#define STM32L4_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d))
#define STM32L4_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode))
#define STM32L4_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp))
#define STM32L4_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch))
#define STM32L4_TIM_SETISR(d,hnd,s) ((d)->ops->setisr(d,hnd,s))
#define STM32L4_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s))
#define STM32L4_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s))
#define STM32L4_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s))
#define STM32L4_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s))
/************************************************************************************
* Public Types
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* TIM Device Structure */
struct stm32l4_tim_dev_s
{
struct stm32l4_tim_ops_s *ops;
};
/* TIM Modes of Operation */
typedef enum
{
STM32L4_TIM_MODE_UNUSED = -1,
/* One of the following */
STM32L4_TIM_MODE_MASK = 0x0310,
STM32L4_TIM_MODE_DISABLED = 0x0000,
STM32L4_TIM_MODE_UP = 0x0100,
STM32L4_TIM_MODE_DOWN = 0x0110,
STM32L4_TIM_MODE_UPDOWN = 0x0200,
STM32L4_TIM_MODE_PULSE = 0x0300,
/* One of the following */
STM32L4_TIM_MODE_CK_INT = 0x0000,
//STM32L4_TIM_MODE_CK_INT_TRIG = 0x0400,
//STM32L4_TIM_MODE_CK_EXT = 0x0800,
//STM32L4_TIM_MODE_CK_EXT_TRIG = 0x0C00,
/* Clock sources, OR'ed with CK_EXT */
//STM32L4_TIM_MODE_CK_CHINVALID = 0x0000,
//STM32L4_TIM_MODE_CK_CH1 = 0x0001,
//STM32L4_TIM_MODE_CK_CH2 = 0x0002,
//STM32L4_TIM_MODE_CK_CH3 = 0x0003,
//STM32L4_TIM_MODE_CK_CH4 = 0x0004
/* Todo: external trigger block */
} stm32l4_tim_mode_t;
/* TIM Channel Modes */
typedef enum
{
STM32L4_TIM_CH_DISABLED = 0x00,
/* Common configuration */
STM32L4_TIM_CH_POLARITY_POS = 0x00,
STM32L4_TIM_CH_POLARITY_NEG = 0x01,
/* MODES: */
STM32L4_TIM_CH_MODE_MASK = 0x06,
/* Output Compare Modes */
STM32L4_TIM_CH_OUTPWM = 0x04, /** Enable standard PWM mode, active high when counter < compare */
//STM32L4_TIM_CH_OUTCOMPARE = 0x06,
// TODO other modes ... as PWM capture, ENCODER and Hall Sensor
//STM32L4_TIM_CH_INCAPTURE = 0x10,
//STM32L4_TIM_CH_INPWM = 0x20
//STM32L4_TIM_CH_DRIVE_OC -- open collector mode
} stm32l4_tim_channel_t;
/* TIM Operations */
struct stm32l4_tim_ops_s
{
/* Basic Timers */
int (*setmode)(FAR struct stm32l4_tim_dev_s *dev, stm32l4_tim_mode_t mode);
int (*setclock)(FAR struct stm32l4_tim_dev_s *dev, uint32_t freq);
void (*setperiod)(FAR struct stm32l4_tim_dev_s *dev, uint32_t period);
uint32_t (*getcounter)(FAR struct stm32l4_tim_dev_s *dev);
/* General and Advanced Timers Adds */
int (*setchannel)(FAR struct stm32l4_tim_dev_s *dev, uint8_t channel,
stm32l4_tim_channel_t mode);
int (*setcompare)(FAR struct stm32l4_tim_dev_s *dev, uint8_t channel,
uint32_t compare);
int (*getcapture)(FAR struct stm32l4_tim_dev_s *dev, uint8_t channel);
/* Timer interrupts */
int (*setisr)(FAR struct stm32l4_tim_dev_s *dev,
int (*handler)(int irq, void *context), int source);
void (*enableint)(FAR struct stm32l4_tim_dev_s *dev, int source);
void (*disableint)(FAR struct stm32l4_tim_dev_s *dev, int source);
void (*ackint)(FAR struct stm32l4_tim_dev_s *dev, int source);
int (*checkint)(FAR struct stm32l4_tim_dev_s *dev, int source);
};
/************************************************************************************
* Public Functions
************************************************************************************/
/* Power-up timer and get its structure */
FAR struct stm32l4_tim_dev_s *stm32l4_tim_init(int timer);
/* Power-down timer, mark it as unused */
int stm32l4_tim_deinit(FAR struct stm32l4_tim_dev_s * dev);
/****************************************************************************
* Name: stm32l4_timer_initialize
*
* Description:
* Bind the configuration timer to a timer lower half instance and
* register the timer drivers at 'devpath'
*
* Input Parameters:
* devpath - The full path to the timer device. This should be of the form /dev/timer0
* timer - the timer number.
*
* Returned Values:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
****************************************************************************/
#ifdef CONFIG_TIMER
int stm32l4_timer_initialize(FAR const char *devpath, int timer);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_TIM_H */

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/****************************************************************************
* arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c
*
* Copyright (C) 2015 Wail Khemir. All rights reserved.
* Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved.
* Authors: Wail Khemir <khemirwail@gmail.com>
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
* dev@ziggurat29.com
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <string.h>
#include <errno.h>
#include <nuttx/irq.h>
#include <nuttx/timers/timer.h>
#include <arch/board/board.h>
#include "stm32l4_tim.h"
#if defined(CONFIG_TIMER) && \
(defined(CONFIG_STM32L4_TIM1) || defined(CONFIG_STM32L4_TIM2) || \
defined(CONFIG_STM32L4_TIM3) || defined(CONFIG_STM32L4_TIM4) || \
defined(CONFIG_STM32L4_TIM5) || defined(CONFIG_STM32L4_TIM6) || \
defined(CONFIG_STM32L4_TIM7) || defined(CONFIG_STM32L4_TIM8) || \
defined(CONFIG_STM32L4_TIM15) || defined(CONFIG_STM32L4_TIM16) || \
defined(CONFIG_STM32L4_TIM17))
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define STM32L4_TIM1_RES 16
#define STM32L4_TIM2_RES 32
#define STM32L4_TIM3_RES 16
#define STM32L4_TIM4_RES 16
#define STM32L4_TIM5_RES 32
#define STM32L4_TIM6_RES 16
#define STM32L4_TIM7_RES 16
#define STM32L4_TIM8_RES 16
#define STM32L4_TIM15_RES 16
#define STM32L4_TIM16_RES 16
#define STM32L4_TIM17_RES 16
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure provides the private representation of the "lower-half"
* driver state structure. This structure must be cast-compatible with the
* timer_lowerhalf_s structure.
*/
struct stm32_lowerhalf_s
{
FAR const struct timer_ops_s *ops; /* Lower half operations */
FAR struct stm32l4_tim_dev_s *tim; /* stm32 timer driver */
tccb_t usrhandler; /* Current user interrupt handler */
const xcpt_t timhandler; /* Current timer interrupt handler */
bool started; /* True: Timer has been started */
const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Interrupt handling *******************************************************/
#ifdef CONFIG_STM32L4_TIM1
static int stm32_tim1_interrupt(int irq, FAR void *context);
#endif
#ifdef CONFIG_STM32L4_TIM2
static int stm32_tim2_interrupt(int irq, FAR void *context);
#endif
#ifdef CONFIG_STM32L4_TIM3
static int stm32_tim3_interrupt(int irq, FAR void *context);
#endif
#ifdef CONFIG_STM32L4_TIM4
static int stm32_tim4_interrupt(int irq, FAR void *context);
#endif
#ifdef CONFIG_STM32L4_TIM5
static int stm32_tim5_interrupt(int irq, FAR void *context);
#endif
#ifdef CONFIG_STM32L4_TIM6
static int stm32_tim6_interrupt(int irq, FAR void *context);
#endif
#ifdef CONFIG_STM32L4_TIM7
static int stm32_tim7_interrupt(int irq, FAR void *context);
#endif
#ifdef CONFIG_STM32L4_TIM8
static int stm32_tim8_interrupt(int irq, FAR void *context);
#endif
#ifdef CONFIG_STM32L4_TIM15
static int stm32_tim15_interrupt(int irq, FAR void *context);
#endif
#ifdef CONFIG_STM32L4_TIM16
static int stm32_tim16_interrupt(int irq, FAR void *context);
#endif
#ifdef CONFIG_STM32L4_TIM17
static int stm32_tim17_interrupt(int irq, FAR void *context);
#endif
static int stm32_timer_handler(FAR struct stm32_lowerhalf_s *lower);
/* "Lower half" driver methods **********************************************/
static int stm32_start(FAR struct timer_lowerhalf_s *lower);
static int stm32_stop(FAR struct timer_lowerhalf_s *lower);
static int stm32_settimeout(FAR struct timer_lowerhalf_s *lower,
uint32_t timeout);
static tccb_t stm32_sethandler(FAR struct timer_lowerhalf_s *lower,
tccb_t handler);
/****************************************************************************
* Private Data
****************************************************************************/
/* "Lower half" driver methods */
static const struct timer_ops_s g_timer_ops =
{
.start = stm32_start,
.stop = stm32_stop,
.getstatus = NULL,
.settimeout = stm32_settimeout,
.sethandler = stm32_sethandler,
.ioctl = NULL,
};
#ifdef CONFIG_STM32L4_TIM1
static struct stm32_lowerhalf_s g_tim1_lowerhalf =
{
.ops = &g_timer_ops,
.timhandler = stm32_tim1_interrupt,
.resolution = STM32L4_TIM1_RES,
};
#endif
#ifdef CONFIG_STM32L4_TIM2
static struct stm32_lowerhalf_s g_tim2_lowerhalf =
{
.ops = &g_timer_ops,
.timhandler = stm32_tim2_interrupt,
.resolution = STM32L4_TIM2_RES,
};
#endif
#ifdef CONFIG_STM32L4_TIM3
static struct stm32_lowerhalf_s g_tim3_lowerhalf =
{
.ops = &g_timer_ops,
.timhandler = stm32_tim3_interrupt,
.resolution = STM32L4_TIM3_RES,
};
#endif
#ifdef CONFIG_STM32L4_TIM4
static struct stm32_lowerhalf_s g_tim4_lowerhalf =
{
.ops = &g_timer_ops,
.timhandler = stm32_tim4_interrupt,
.resolution = STM32L4_TIM4_RES,
};
#endif
#ifdef CONFIG_STM32L4_TIM5
static struct stm32_lowerhalf_s g_tim5_lowerhalf =
{
.ops = &g_timer_ops,
.timhandler = stm32_tim5_interrupt,
.resolution = STM32L4_TIM5_RES,
};
#endif
#ifdef CONFIG_STM32L4_TIM6
static struct stm32_lowerhalf_s g_tim6_lowerhalf =
{
.ops = &g_timer_ops,
.timhandler = stm32_tim6_interrupt,
.resolution = STM32L4_TIM6_RES,
};
#endif
#ifdef CONFIG_STM32L4_TIM7
static struct stm32_lowerhalf_s g_tim7_lowerhalf =
{
.ops = &g_timer_ops,
.timhandler = stm32_tim7_interrupt,
.resolution = STM32L4_TIM7_RES,
};
#endif
#ifdef CONFIG_STM32L4_TIM8
static struct stm32_lowerhalf_s g_tim8_lowerhalf =
{
.ops = &g_timer_ops,
.timhandler = stm32_tim8_interrupt,
.resolution = STM32L4_TIM8_RES,
};
#endif
#ifdef CONFIG_STM32L4_TIM15
static struct stm32_lowerhalf_s g_tim15_lowerhalf =
{
.ops = &g_timer_ops,
.timhandler = stm32_tim15_interrupt,
.resolution = STM32L4_TIM15_RES,
};
#endif
#ifdef CONFIG_STM32L4_TIM16
static struct stm32_lowerhalf_s g_tim16_lowerhalf =
{
.ops = &g_timer_ops,
.timhandler = stm32_tim16_interrupt,
.resolution = STM32L4_TIM16_RES,
};
#endif
#ifdef CONFIG_STM32L4_TIM17
static struct stm32_lowerhalf_s g_tim17_lowerhalf =
{
.ops = &g_timer_ops,
.timhandler = stm32_tim17_interrupt,
.resolution = STM32L4_TIM17_RES,
};
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_timN_interrupt, N=1..14
*
* Description:
* Individual interrupt handlers for each timer
*
****************************************************************************/
#ifdef CONFIG_STM32L4_TIM1
static int stm32_tim1_interrupt(int irq, FAR void *context)
{
return stm32_timer_handler(&g_tim1_lowerhalf);
}
#endif
#ifdef CONFIG_STM32L4_TIM2
static int stm32_tim2_interrupt(int irq, FAR void *context)
{
return stm32_timer_handler(&g_tim2_lowerhalf);
}
#endif
#ifdef CONFIG_STM32L4_TIM3
static int stm32_tim3_interrupt(int irq, FAR void *context)
{
return stm32_timer_handler(&g_tim3_lowerhalf);
}
#endif
#ifdef CONFIG_STM32L4_TIM4
static int stm32_tim4_interrupt(int irq, FAR void *context)
{
return stm32_timer_handler(&g_tim4_lowerhalf);
}
#endif
#ifdef CONFIG_STM32L4_TIM5
static int stm32_tim5_interrupt(int irq, FAR void *context)
{
return stm32_timer_handler(&g_tim5_lowerhalf);
}
#endif
#ifdef CONFIG_STM32L4_TIM6
static int stm32_tim6_interrupt(int irq, FAR void *context)
{
return stm32_timer_handler(&g_tim6_lowerhalf);
}
#endif
#ifdef CONFIG_STM32L4_TIM7
static int stm32_tim7_interrupt(int irq, FAR void *context)
{
return stm32_timer_handler(&g_tim7_lowerhalf);
}
#endif
#ifdef CONFIG_STM32L4_TIM8
static int stm32_tim8_interrupt(int irq, FAR void *context)
{
return stm32_timer_handler(&g_tim8_lowerhalf);
}
#endif
#ifdef CONFIG_STM32L4_TIM15
static int stm32_tim15_interrupt(int irq, FAR void *context)
{
return stm32_timer_handler(&g_tim15_lowerhalf);
}
#endif
#ifdef CONFIG_STM32L4_TIM16
static int stm32_tim16_interrupt(int irq, FAR void *context)
{
return stm32_timer_handler(&g_tim16_lowerhalf);
}
#endif
#ifdef CONFIG_STM32L4_TIM17
static int stm32_tim17_interrupt(int irq, FAR void *context)
{
return stm32_timer_handler(&g_tim17_lowerhalf);
}
#endif
/****************************************************************************
* Name: stm32_timer_handler
*
* Description:
* timer interrupt handler
*
* Input Parameters:
*
* Returned Values:
*
****************************************************************************/
static int stm32_timer_handler(FAR struct stm32_lowerhalf_s *lower)
{
uint32_t next_interval_us = 0;
STM32L4_TIM_ACKINT(lower->tim, 0);
if (lower->usrhandler(&next_interval_us))
{
if (next_interval_us > 0)
{
STM32L4_TIM_SETPERIOD(lower->tim, next_interval_us);
}
}
else
{
stm32_stop((struct timer_lowerhalf_s *)lower);
}
return OK;
}
/****************************************************************************
* Name: stm32_start
*
* Description:
* Start the timer, resetting the time to the current timeout,
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
* Returned Values:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int stm32_start(FAR struct timer_lowerhalf_s *lower)
{
FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
if (!priv->started)
{
STM32L4_TIM_SETMODE(priv->tim, STM32L4_TIM_MODE_UP);
if (priv->usrhandler != NULL)
{
STM32L4_TIM_SETISR(priv->tim, priv->timhandler, 0);
STM32L4_TIM_ENABLEINT(priv->tim, 0);
}
priv->started = true;
return OK;
}
/* Return EBUSY to indicate that the timer was already running */
return -EBUSY;
}
/****************************************************************************
* Name: stm32_stop
*
* Description:
* Stop the timer
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
* Returned Values:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int stm32_stop(struct timer_lowerhalf_s *lower)
{
struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower;
if (priv->started)
{
STM32L4_TIM_SETMODE(priv->tim, STM32L4_TIM_MODE_DISABLED);
STM32L4_TIM_DISABLEINT(priv->tim, 0);
STM32L4_TIM_SETISR(priv->tim, 0, 0);
priv->started = false;
return OK;
}
/* Return ENODEV to indicate that the timer was not running */
return -ENODEV;
}
/****************************************************************************
* Name: stm32_settimeout
*
* Description:
* Set a new timeout value (and reset the timer)
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* timeout - The new timeout value in microseconds.
*
* Returned Values:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int stm32_settimeout(FAR struct timer_lowerhalf_s *lower, uint32_t timeout)
{
FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
uint64_t maxtimeout;
if (priv->started)
{
return -EPERM;
}
maxtimeout = (1 << priv->resolution) - 1;
if (timeout > maxtimeout)
{
uint64_t freq = (maxtimeout * 1000000) / timeout;
STM32L4_TIM_SETCLOCK(priv->tim, freq);
STM32L4_TIM_SETPERIOD(priv->tim, maxtimeout);
}
else
{
STM32L4_TIM_SETCLOCK(priv->tim, 1000000);
STM32L4_TIM_SETPERIOD(priv->tim, timeout);
}
return OK;
}
/****************************************************************************
* Name: stm32_sethandler
*
* Description:
* Call this user provided timeout handler.
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* newhandler - The new timer expiration function pointer. If this
* function pointer is NULL, then the reset-on-expiration
* behavior is restored,
*
* Returned Values:
* The previous timer expiration function pointer or NULL is there was
* no previous function pointer.
*
****************************************************************************/
static tccb_t stm32_sethandler(FAR struct timer_lowerhalf_s *lower,
tccb_t newhandler)
{
FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
irqstate_t flags = enter_critical_section();
/* Get the old handler return value */
tccb_t oldhandler = priv->usrhandler;
/* Save the new handler */
priv->usrhandler = newhandler;
if (newhandler != NULL && priv->started)
{
STM32L4_TIM_SETISR(priv->tim, priv->timhandler, 0);
STM32L4_TIM_ENABLEINT(priv->tim, 0);
}
else
{
STM32L4_TIM_DISABLEINT(priv->tim, 0);
STM32L4_TIM_SETISR(priv->tim, 0, 0);
}
leave_critical_section(flags);
return oldhandler;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32l4_timer_initialize
*
* Description:
* Bind the configuration timer to a timer lower half instance and
* register the timer drivers at 'devpath'
*
* Input Parameters:
* devpath - The full path to the timer device. This should be of the
* form /dev/timer0
* timer - the timer's number.
*
* Returned Values:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
****************************************************************************/
int stm32l4_timer_initialize(FAR const char *devpath, int timer)
{
FAR struct stm32_lowerhalf_s *lower;
switch (timer)
{
#ifdef CONFIG_STM32L4_TIM1
case 1:
lower = &g_tim1_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32L4_TIM2
case 2:
lower = &g_tim2_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32L4_TIM3
case 3:
lower = &g_tim3_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32L4_TIM4
case 4:
lower = &g_tim4_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32L4_TIM5
case 5:
lower = &g_tim5_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32L4_TIM6
case 6:
lower = &g_tim6_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32L4_TIM7
case 7:
lower = &g_tim7_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32L4_TIM8
case 8:
lower = &g_tim8_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32L4_TIM15
case 15:
lower = &g_tim15_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32L4_TIM16
case 16:
lower = &g_tim16_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32L4_TIM17
case 17:
lower = &g_tim17_lowerhalf;
break;
#endif
default:
return -ENODEV;
}
/* Initialize the elements of lower half state structure */
lower->started = false;
lower->usrhandler = NULL;
lower->tim = stm32l4_tim_init(timer);
if (lower->tim == NULL)
{
return -EINVAL;
}
/* Register the timer driver as /dev/timerX. The returned value from
* timer_register is a handle that could be used with timer_unregister().
* REVISIT: The returned handle is discard here.
*/
FAR void *drvr = timer_register(devpath,
(FAR struct timer_lowerhalf_s *)lower);
if (drvr == NULL)
{
/* The actual cause of the failure may have been a failure to allocate
* perhaps a failure to register the timer driver (such as if the
* 'depath' were not unique). We know here but we return EEXIST to
* indicate the failure (implying the non-unique devpath).
*/
return -EEXIST;
}
return OK;
}
#endif /* CONFIG_TIMER */