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Add serial method so that lower half driver can provide RX flow control information. From Jussi Kivilinna

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This commit is contained in:
Gregory Nutt 2014-05-08 09:00:33 -06:00
parent 1cc859405e
commit af2bb81ac2
32 changed files with 254 additions and 27 deletions
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3
arch/arm/src/a1x/a1x_serial.c
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@ -157,6 +157,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

3
arch/arm/src/c5471/c5471_serial.c
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@ -133,6 +133,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

3
arch/arm/src/calypso/calypso_serial.c
View File

@ -147,6 +147,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

3
arch/arm/src/dm320/dm320_serial.c
View File

@ -114,6 +114,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

3
arch/arm/src/imx/imx_serial.c
View File

@ -136,6 +136,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

3
arch/arm/src/kinetis/kinetis_serial.c
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@ -280,6 +280,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

3
arch/arm/src/kl/kl_serial.c
View File

@ -196,6 +196,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

3
arch/arm/src/lpc17xx/lpc17_serial.c
View File

@ -129,6 +129,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

3
arch/arm/src/lpc214x/lpc214x_serial.c
View File

@ -113,6 +113,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

3
arch/arm/src/lpc2378/lpc23xx_serial.c
View File

@ -121,6 +121,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

3
arch/arm/src/lpc31xx/lpc31_serial.c
View File

@ -113,6 +113,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

3
arch/arm/src/lpc43xx/lpc43_serial.c
View File

@ -126,6 +126,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

3
arch/arm/src/nuc1xx/nuc_serial.c
View File

@ -126,6 +126,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

3
arch/arm/src/sam34/sam_serial.c
View File

@ -381,6 +381,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

3
arch/arm/src/sama5/sam_dbgu.c
View File

@ -116,6 +116,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = dbgu_receive,
.rxint = dbgu_rxint,
.rxavailable = dbgu_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = dbgu_send,
.txint = dbgu_txint,
.txready = dbgu_txready,

3
arch/arm/src/sama5/sam_serial.c
View File

@ -376,6 +376,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

3
arch/arm/src/samd/sam_serial.c
View File

@ -300,6 +300,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = sam_receive,
.rxint = sam_rxint,
.rxavailable = sam_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = sam_send,
.txint = sam_txint,
.txready = sam_txempty,

186
arch/arm/src/stm32/stm32_serial.c
View File

@ -161,7 +161,7 @@
# if defined(CONFIG_UART4_RXDMA)
# ifndef CONFIG_STM32_DMA2
# error STM32 USART4 receive DMA requires CONFIG_STM32_DMA2
# error STM32 UART4 receive DMA requires CONFIG_STM32_DMA2
# endif
# endif
@ -170,7 +170,7 @@
# define DMAMAP_USART1_RX DMACHAN_USART1_RX
# define DMAMAP_USART2_RX DMACHAN_USART2_RX
# define DMAMAP_USART3_RX DMACHAN_USART3_RX
# define DMAMAP_UART4_RX DMACHAN_USART4_RX
# define DMAMAP_UART4_RX DMACHAN_UART4_RX
# endif
@ -326,6 +326,9 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status);
static void up_rxint(struct uart_dev_s *dev, bool enable);
static bool up_rxavailable(struct uart_dev_s *dev);
#endif
#ifdef CONFIG_SERIAL_IFLOWCONTROL
static bool up_rxflowcontrol(struct uart_dev_s *dev);
#endif
static void up_send(struct uart_dev_s *dev, int ch);
static void up_txint(struct uart_dev_s *dev, bool enable);
static bool up_txready(struct uart_dev_s *dev);
@ -385,6 +388,11 @@ static const struct uart_ops_s g_uart_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = up_rxflowcontrol,
#else
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,
@ -508,21 +516,17 @@ static struct up_dev_s g_usart1priv =
.parity = CONFIG_USART1_PARITY,
.bits = CONFIG_USART1_BITS,
.stopbits2 = CONFIG_USART1_2STOP,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.iflow = false,
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
.oflow = false,
#endif
.baud = CONFIG_USART1_BAUD,
.apbclock = STM32_PCLK2_FREQUENCY,
.usartbase = STM32_USART1_BASE,
.tx_gpio = GPIO_USART1_TX,
.rx_gpio = GPIO_USART1_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART1_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART1_RTS,
#endif
#ifdef CONFIG_USART1_RXDMA
@ -574,21 +578,17 @@ static struct up_dev_s g_usart2priv =
.parity = CONFIG_USART2_PARITY,
.bits = CONFIG_USART2_BITS,
.stopbits2 = CONFIG_USART2_2STOP,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.iflow = false,
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
.oflow = false,
#endif
.baud = CONFIG_USART2_BAUD,
.apbclock = STM32_PCLK1_FREQUENCY,
.usartbase = STM32_USART2_BASE,
.tx_gpio = GPIO_USART2_TX,
.rx_gpio = GPIO_USART2_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART2_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART2_RTS,
#endif
#ifdef CONFIG_USART2_RXDMA
@ -640,21 +640,17 @@ static struct up_dev_s g_usart3priv =
.parity = CONFIG_USART3_PARITY,
.bits = CONFIG_USART3_BITS,
.stopbits2 = CONFIG_USART3_2STOP,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.iflow = false,
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
.oflow = false,
#endif
.baud = CONFIG_USART3_BAUD,
.apbclock = STM32_PCLK1_FREQUENCY,
.usartbase = STM32_USART3_BASE,
.tx_gpio = GPIO_USART3_TX,
.rx_gpio = GPIO_USART3_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART3_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART3_RTS,
#endif
#ifdef CONFIG_USART3_RXDMA
@ -838,21 +834,17 @@ static struct up_dev_s g_usart6priv =
.parity = CONFIG_USART6_PARITY,
.bits = CONFIG_USART6_BITS,
.stopbits2 = CONFIG_USART6_2STOP,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.iflow = false,
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
.oflow = false,
#endif
.baud = CONFIG_USART6_BAUD,
.apbclock = STM32_PCLK2_FREQUENCY,
.usartbase = STM32_USART6_BASE,
.tx_gpio = GPIO_USART6_TX,
.rx_gpio = GPIO_USART6_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART6_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART6_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART6_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART6_RTS,
#endif
#ifdef CONFIG_USART6_RXDMA
@ -910,9 +902,11 @@ static struct up_dev_s g_uart7priv =
.tx_gpio = GPIO_UART7_TX,
.rx_gpio = GPIO_UART7_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART7_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_UART7_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART7_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_UART7_RTS,
#endif
#ifdef CONFIG_UART7_RXDMA
@ -970,9 +964,11 @@ static struct up_dev_s g_uart8priv =
.tx_gpio = GPIO_UART8_TX,
.rx_gpio = GPIO_UART8_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART8_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_UART8_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART8_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_UART8_RTS,
#endif
#ifdef CONFIG_UART8_RXDMA
@ -1308,6 +1304,92 @@ static void up_set_format(struct uart_dev_s *dev)
}
#endif /* CONFIG_SUPPRESS_UART_CONFIG */
/****************************************************************************
* Name: up_set_apb_clock
*
* Description:
* Enable or disable APB clock for the USART peripheral
*
* Input parameters:
* dev - A reference to the UART driver state structure
* on - Enable clock if 'on' is 'true' and disable if 'false'
*
****************************************************************************/
static void up_set_apb_clock(struct uart_dev_s *dev, bool on)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
uint32_t rcc_en;
uint32_t regaddr;
/* Determine which USART to configure */
switch (priv->usartbase)
{
default:
return;
#ifdef CONFIG_STM32_USART1
case STM32_USART1_BASE:
rcc_en = RCC_APB2ENR_USART1EN;
regaddr = STM32_RCC_APB2ENR;
break;
#endif
#ifdef CONFIG_STM32_USART2
case STM32_USART2_BASE:
rcc_en = RCC_APB1ENR_USART2EN;
regaddr = STM32_RCC_APB1ENR;
break;
#endif
#ifdef CONFIG_STM32_USART3
case STM32_USART3_BASE:
rcc_en = RCC_APB1ENR_USART3EN;
regaddr = STM32_RCC_APB1ENR;
break;
#endif
#ifdef CONFIG_STM32_UART4
case STM32_UART4_BASE:
rcc_en = RCC_APB1ENR_UART4EN;
regaddr = STM32_RCC_APB1ENR;
break;
#endif
#ifdef CONFIG_STM32_UART5
case STM32_UART5_BASE:
rcc_en = RCC_APB1ENR_UART5EN;
regaddr = STM32_RCC_APB1ENR;
break;
#endif
#ifdef CONFIG_STM32_USART6
case STM32_USART6_BASE:
rcc_en = RCC_APB2ENR_USART6EN;
regaddr = STM32_RCC_APB2ENR;
break;
#endif
#ifdef CONFIG_STM32_UART7
case STM32_UART7_BASE:
rcc_en = RCC_APB1ENR_USART5EN;
regaddr = STM32_RCC_APB1ENR;
break;
#endif
#ifdef CONFIG_STM32_UART8
case STM32_UART8_BASE:
rcc_en = RCC_APB1ENR_USART5EN;
regaddr = STM32_RCC_APB1ENR;
break;
#endif
}
/* Enable/disable APB 1/2 clock for USART */
if (on)
{
modifyreg32(regaddr, 0, rcc_en);
}
else
{
modifyreg32(regaddr, rcc_en, 0);
}
}
/****************************************************************************
* Name: up_setup
*
@ -1328,6 +1410,10 @@ static int up_setup(struct uart_dev_s *dev)
* was enabled in stm32_lowsetup().
*/
/* Enable USART APB1/2 clock */
up_set_apb_clock(dev, true);
/* Configure pins for USART use */
stm32_configgpio(priv->tx_gpio);
@ -1404,6 +1490,8 @@ static int up_setup(struct uart_dev_s *dev)
regval |= (USART_CR1_UE|USART_CR1_TE|USART_CR1_RE);
up_serialout(priv, STM32_USART_CR1_OFFSET, regval);
#endif /* CONFIG_SUPPRESS_UART_CONFIG */
/* Set up the cached interrupt enables value */
priv->ie = 0;
@ -1490,6 +1578,10 @@ static void up_shutdown(struct uart_dev_s *dev)
up_disableusartint(priv, NULL);
/* Disable USART APB1/2 clock */
up_set_apb_clock(dev, false);
/* Disable Rx, Tx, and the UART */
regval = up_serialin(priv, STM32_USART_CR1_OFFSET);
@ -2006,6 +2098,46 @@ static bool up_rxavailable(struct uart_dev_s *dev)
}
#endif
/****************************************************************************
* Name: up_rxflowcontrol
*
* Description:
* Called when Rx buffer is full. Return true if the Rx interrupt was
* disabled.
*
****************************************************************************/
#ifdef CONFIG_SERIAL_IFLOWCONTROL
static bool up_rxflowcontrol(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
uint16_t ie;
if (priv->iflow)
{
/* Disable Rx interrupt to prevent more data being from peripheral.
* When hardware RTS is enabled, this will prevent more data from
* coming in.
*
* This function is only called when UART recv buffer is full, that
* is: "dev->recv.head + 1 == dev->recv.tail".
*
* Logic in "uart_read" will automatically toggle Rx interrupts when
* buffer is read empty and thus we do not have to re-enable Rx
* interrupts in any other place.
*/
ie = priv->ie;
ie &= ~USART_CR1_RXNEIE;
up_restoreusartint(priv, ie);
return true;
}
return false;
}
#endif
/****************************************************************************
* Name: up_dma_receive
*
@ -2568,6 +2700,8 @@ void stm32_serial_dma_poll(void)
*
****************************************************************************/
#ifdef USE_SERIALDRIVER
int up_putc(int ch)
{
#if CONSOLE_UART > 0

3
arch/arm/src/str71x/str71x_serial.c
View File

@ -279,6 +279,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

3
arch/arm/src/tiva/tiva_serial.c
View File

@ -344,6 +344,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

3
arch/avr/src/at32uc3/at32uc3_serial.c
View File

@ -184,6 +184,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

5
arch/avr/src/at90usb/at90usb_serial.c
View File

@ -107,7 +107,7 @@ static bool usart1_txempty(struct uart_dev_s *dev);
****************************************************************************/
struct uart_ops_s g_uart1_ops =
{
{O
.setup = usart1_setup,
.shutdown = usart1_shutdown,
.attach = usart1_attach,
@ -116,6 +116,9 @@ struct uart_ops_s g_uart1_ops =
.receive = usart1_receive,
.rxint = usart1_rxint,
.rxavailable = usart1_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = usart1_send,
.txint = usart1_txint,
.txready = usart1_txready,

3
arch/avr/src/atmega/atmega_serial.c
View File

@ -158,6 +158,9 @@ struct uart_ops_s g_usart0_ops =
.receive = usart0_receive,
.rxint = usart0_rxint,
.rxavailable = usart0_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = usart0_send,
.txint = usart0_txint,
.txready = usart0_txready,

3
arch/hc/src/m9s12/m9s12_serial.c
View File

@ -146,6 +146,9 @@ struct uart_ops_s g_sci_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

3
arch/mips/src/pic32mx/pic32mx-serial.c
View File

@ -198,6 +198,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

3
arch/rgmp/src/x86/com.c
View File

@ -152,6 +152,9 @@ static struct uart_ops_s g_com_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

3
arch/sh/src/m16c/m16c_serial.c
View File

@ -292,6 +292,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

3
arch/sh/src/sh1/sh1_serial.c
View File

@ -180,6 +180,9 @@ struct uart_ops_s g_sci_ops =
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,

3
arch/z16/src/z16f/z16f_serial.c
View File

@ -121,6 +121,9 @@ static const struct uart_ops_s g_uart_ops =
z16f_receive, /* receive */
z16f_rxint, /* rxint */
z16f_rxavailable, /* rxavailable */
#ifdef CONFIG_SERIAL_IFLOWCONTROL
NULL, /* rxflowcontrol */
#endif
z16f_send, /* send */
z16f_txint, /* txint */
z16f_txready, /* txready */

3
arch/z80/src/ez80/ez80_serial.c
View File

@ -110,6 +110,9 @@ static const struct uart_ops_s g_uart_ops =
ez80_receive, /* receive */
ez80_rxint, /* rxint */
ez80_rxavailable, /* rxavailable */
#ifdef CONFIG_SERIAL_IFLOWCONTROL
NULL, /* rxflowcontrol */
#endif
ez80_send, /* send */
ez80_txint, /* txint */
ez80_txready, /* txready */

3
arch/z80/src/z180/z180_scc.c
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@ -114,6 +114,9 @@ static const struct uart_ops_s g_uart_ops =
z180_receive, /* receive */
z180_rxint, /* rxint */
z180_rxavailable, /* rxavailable */
#ifdef CONFIG_SERIAL_IFLOWCONTROL
NULL, /* rxflowcontrol */
#endif
z180_send, /* send */
z180_txint, /* txint */
z180_txready, /* txready */

3
arch/z80/src/z8/z8_serial.c
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@ -122,6 +122,9 @@ static const struct uart_ops_s g_uart_ops =
z8_receive, /* receive */
z8_rxint, /* rxint */
z8_rxavailable, /* rxavailable */
#ifdef CONFIG_SERIAL_IFLOWCONTROL
NULL, /* rxflowcontrol */
#endif
z8_send, /* send */
z8_txint, /* txint */
z8_txready, /* txready */