From af2bb81ac2f3a93de5da99915bcc6a030faf6bdb Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 8 May 2014 09:00:33 -0600 Subject: [PATCH] Add serial method so that lower half driver can provide RX flow control information. From Jussi Kivilinna --- arch/arm/src/a1x/a1x_serial.c | 3 + arch/arm/src/c5471/c5471_serial.c | 3 + arch/arm/src/calypso/calypso_serial.c | 3 + arch/arm/src/dm320/dm320_serial.c | 3 + arch/arm/src/imx/imx_serial.c | 3 + arch/arm/src/kinetis/kinetis_serial.c | 3 + arch/arm/src/kl/kl_serial.c | 3 + arch/arm/src/lpc17xx/lpc17_serial.c | 3 + arch/arm/src/lpc214x/lpc214x_serial.c | 3 + arch/arm/src/lpc2378/lpc23xx_serial.c | 3 + arch/arm/src/lpc31xx/lpc31_serial.c | 3 + arch/arm/src/lpc43xx/lpc43_serial.c | 3 + arch/arm/src/nuc1xx/nuc_serial.c | 3 + arch/arm/src/sam34/sam_serial.c | 3 + arch/arm/src/sama5/sam_dbgu.c | 3 + arch/arm/src/sama5/sam_serial.c | 3 + arch/arm/src/samd/sam_serial.c | 3 + arch/arm/src/stm32/stm32_serial.c | 186 +++++++++++++++++++++---- arch/arm/src/str71x/str71x_serial.c | 3 + arch/arm/src/tiva/tiva_serial.c | 3 + arch/avr/src/at32uc3/at32uc3_serial.c | 3 + arch/avr/src/at90usb/at90usb_serial.c | 5 +- arch/avr/src/atmega/atmega_serial.c | 3 + arch/hc/src/m9s12/m9s12_serial.c | 3 + arch/mips/src/pic32mx/pic32mx-serial.c | 3 + arch/rgmp/src/x86/com.c | 3 + arch/sh/src/m16c/m16c_serial.c | 3 + arch/sh/src/sh1/sh1_serial.c | 3 + arch/z16/src/z16f/z16f_serial.c | 3 + arch/z80/src/ez80/ez80_serial.c | 3 + arch/z80/src/z180/z180_scc.c | 3 + arch/z80/src/z8/z8_serial.c | 3 + 32 files changed, 254 insertions(+), 27 deletions(-) diff --git a/arch/arm/src/a1x/a1x_serial.c b/arch/arm/src/a1x/a1x_serial.c index 1c93fb1a24..d2cc366425 100644 --- a/arch/arm/src/a1x/a1x_serial.c +++ b/arch/arm/src/a1x/a1x_serial.c @@ -157,6 +157,9 @@ static const struct uart_ops_s g_uart_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/arm/src/c5471/c5471_serial.c b/arch/arm/src/c5471/c5471_serial.c index b993ee8bca..f1b9f7b70b 100644 --- a/arch/arm/src/c5471/c5471_serial.c +++ b/arch/arm/src/c5471/c5471_serial.c @@ -133,6 +133,9 @@ static const struct uart_ops_s g_uart_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/arm/src/calypso/calypso_serial.c b/arch/arm/src/calypso/calypso_serial.c index ddb37201dc..d3f9cf5903 100644 --- a/arch/arm/src/calypso/calypso_serial.c +++ b/arch/arm/src/calypso/calypso_serial.c @@ -147,6 +147,9 @@ static const struct uart_ops_s g_uart_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/arm/src/dm320/dm320_serial.c b/arch/arm/src/dm320/dm320_serial.c index daf711d69a..be74e227f1 100644 --- a/arch/arm/src/dm320/dm320_serial.c +++ b/arch/arm/src/dm320/dm320_serial.c @@ -114,6 +114,9 @@ static const struct uart_ops_s g_uart_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/arm/src/imx/imx_serial.c b/arch/arm/src/imx/imx_serial.c index d5423ff4ac..b5939fad7b 100644 --- a/arch/arm/src/imx/imx_serial.c +++ b/arch/arm/src/imx/imx_serial.c @@ -136,6 +136,9 @@ static const struct uart_ops_s g_uart_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/arm/src/kinetis/kinetis_serial.c b/arch/arm/src/kinetis/kinetis_serial.c index 4cf414fd64..5446ffe803 100644 --- a/arch/arm/src/kinetis/kinetis_serial.c +++ b/arch/arm/src/kinetis/kinetis_serial.c @@ -280,6 +280,9 @@ static const struct uart_ops_s g_uart_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/arm/src/kl/kl_serial.c b/arch/arm/src/kl/kl_serial.c index 2622e0db06..262167e1f0 100644 --- a/arch/arm/src/kl/kl_serial.c +++ b/arch/arm/src/kl/kl_serial.c @@ -196,6 +196,9 @@ static const struct uart_ops_s g_uart_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/arm/src/lpc17xx/lpc17_serial.c b/arch/arm/src/lpc17xx/lpc17_serial.c index 7c0f0e04a3..86e5b2187f 100644 --- a/arch/arm/src/lpc17xx/lpc17_serial.c +++ b/arch/arm/src/lpc17xx/lpc17_serial.c @@ -129,6 +129,9 @@ static const struct uart_ops_s g_uart_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/arm/src/lpc214x/lpc214x_serial.c b/arch/arm/src/lpc214x/lpc214x_serial.c index 5df5264fe8..214eb03477 100644 --- a/arch/arm/src/lpc214x/lpc214x_serial.c +++ b/arch/arm/src/lpc214x/lpc214x_serial.c @@ -113,6 +113,9 @@ static const struct uart_ops_s g_uart_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/arm/src/lpc2378/lpc23xx_serial.c b/arch/arm/src/lpc2378/lpc23xx_serial.c index dcd630eee5..17b6bc0b29 100644 --- a/arch/arm/src/lpc2378/lpc23xx_serial.c +++ b/arch/arm/src/lpc2378/lpc23xx_serial.c @@ -121,6 +121,9 @@ static const struct uart_ops_s g_uart_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/arm/src/lpc31xx/lpc31_serial.c b/arch/arm/src/lpc31xx/lpc31_serial.c index 46e91aba43..e4d6941ca6 100644 --- a/arch/arm/src/lpc31xx/lpc31_serial.c +++ b/arch/arm/src/lpc31xx/lpc31_serial.c @@ -113,6 +113,9 @@ static const struct uart_ops_s g_uart_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/arm/src/lpc43xx/lpc43_serial.c b/arch/arm/src/lpc43xx/lpc43_serial.c index df68c13014..896e1f7381 100644 --- a/arch/arm/src/lpc43xx/lpc43_serial.c +++ b/arch/arm/src/lpc43xx/lpc43_serial.c @@ -126,6 +126,9 @@ static const struct uart_ops_s g_uart_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/arm/src/nuc1xx/nuc_serial.c b/arch/arm/src/nuc1xx/nuc_serial.c index ee774b9ae6..25b7f6060c 100644 --- a/arch/arm/src/nuc1xx/nuc_serial.c +++ b/arch/arm/src/nuc1xx/nuc_serial.c @@ -126,6 +126,9 @@ static const struct uart_ops_s g_uart_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/arm/src/sam34/sam_serial.c b/arch/arm/src/sam34/sam_serial.c index f74d9be719..aa1e56db85 100644 --- a/arch/arm/src/sam34/sam_serial.c +++ b/arch/arm/src/sam34/sam_serial.c @@ -381,6 +381,9 @@ static const struct uart_ops_s g_uart_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/arm/src/sama5/sam_dbgu.c b/arch/arm/src/sama5/sam_dbgu.c index f86cd89a00..9192606167 100644 --- a/arch/arm/src/sama5/sam_dbgu.c +++ b/arch/arm/src/sama5/sam_dbgu.c @@ -116,6 +116,9 @@ static const struct uart_ops_s g_uart_ops = .receive = dbgu_receive, .rxint = dbgu_rxint, .rxavailable = dbgu_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = dbgu_send, .txint = dbgu_txint, .txready = dbgu_txready, diff --git a/arch/arm/src/sama5/sam_serial.c b/arch/arm/src/sama5/sam_serial.c index 4cbcf5f506..26c3b9acb3 100644 --- a/arch/arm/src/sama5/sam_serial.c +++ b/arch/arm/src/sama5/sam_serial.c @@ -376,6 +376,9 @@ static const struct uart_ops_s g_uart_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/arm/src/samd/sam_serial.c b/arch/arm/src/samd/sam_serial.c index 65092a0dbe..d6c448e569 100644 --- a/arch/arm/src/samd/sam_serial.c +++ b/arch/arm/src/samd/sam_serial.c @@ -300,6 +300,9 @@ static const struct uart_ops_s g_uart_ops = .receive = sam_receive, .rxint = sam_rxint, .rxavailable = sam_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = sam_send, .txint = sam_txint, .txready = sam_txempty, diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c index ef624b8703..d5333de90a 100644 --- a/arch/arm/src/stm32/stm32_serial.c +++ b/arch/arm/src/stm32/stm32_serial.c @@ -161,7 +161,7 @@ # if defined(CONFIG_UART4_RXDMA) # ifndef CONFIG_STM32_DMA2 -# error STM32 USART4 receive DMA requires CONFIG_STM32_DMA2 +# error STM32 UART4 receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -170,7 +170,7 @@ # define DMAMAP_USART1_RX DMACHAN_USART1_RX # define DMAMAP_USART2_RX DMACHAN_USART2_RX # define DMAMAP_USART3_RX DMACHAN_USART3_RX -# define DMAMAP_UART4_RX DMACHAN_USART4_RX +# define DMAMAP_UART4_RX DMACHAN_UART4_RX # endif @@ -326,6 +326,9 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); #endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool up_rxflowcontrol(struct uart_dev_s *dev); +#endif static void up_send(struct uart_dev_s *dev, int ch); static void up_txint(struct uart_dev_s *dev, bool enable); static bool up_txready(struct uart_dev_s *dev); @@ -385,6 +388,11 @@ static const struct uart_ops_s g_uart_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = up_rxflowcontrol, +#else + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, @@ -508,21 +516,17 @@ static struct up_dev_s g_usart1priv = .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, -#ifdef CONFIG_SERIAL_IFLOWCONTROL - .iflow = false, -#endif -#ifdef CONFIG_SERIAL_OFLOWCONTROL - .oflow = false, -#endif .baud = CONFIG_USART1_BAUD, .apbclock = STM32_PCLK2_FREQUENCY, .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) + .oflow = true, .cts_gpio = GPIO_USART1_CTS, #endif #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL) + .iflow = true, .rts_gpio = GPIO_USART1_RTS, #endif #ifdef CONFIG_USART1_RXDMA @@ -574,21 +578,17 @@ static struct up_dev_s g_usart2priv = .parity = CONFIG_USART2_PARITY, .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, -#ifdef CONFIG_SERIAL_IFLOWCONTROL - .iflow = false, -#endif -#ifdef CONFIG_SERIAL_OFLOWCONTROL - .oflow = false, -#endif .baud = CONFIG_USART2_BAUD, .apbclock = STM32_PCLK1_FREQUENCY, .usartbase = STM32_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) + .oflow = true, .cts_gpio = GPIO_USART2_CTS, #endif #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL) + .iflow = true, .rts_gpio = GPIO_USART2_RTS, #endif #ifdef CONFIG_USART2_RXDMA @@ -640,21 +640,17 @@ static struct up_dev_s g_usart3priv = .parity = CONFIG_USART3_PARITY, .bits = CONFIG_USART3_BITS, .stopbits2 = CONFIG_USART3_2STOP, -#ifdef CONFIG_SERIAL_IFLOWCONTROL - .iflow = false, -#endif -#ifdef CONFIG_SERIAL_OFLOWCONTROL - .oflow = false, -#endif .baud = CONFIG_USART3_BAUD, .apbclock = STM32_PCLK1_FREQUENCY, .usartbase = STM32_USART3_BASE, .tx_gpio = GPIO_USART3_TX, .rx_gpio = GPIO_USART3_RX, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) + .oflow = true, .cts_gpio = GPIO_USART3_CTS, #endif #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL) + .iflow = true, .rts_gpio = GPIO_USART3_RTS, #endif #ifdef CONFIG_USART3_RXDMA @@ -838,21 +834,17 @@ static struct up_dev_s g_usart6priv = .parity = CONFIG_USART6_PARITY, .bits = CONFIG_USART6_BITS, .stopbits2 = CONFIG_USART6_2STOP, -#ifdef CONFIG_SERIAL_IFLOWCONTROL - .iflow = false, -#endif -#ifdef CONFIG_SERIAL_OFLOWCONTROL - .oflow = false, -#endif .baud = CONFIG_USART6_BAUD, .apbclock = STM32_PCLK2_FREQUENCY, .usartbase = STM32_USART6_BASE, .tx_gpio = GPIO_USART6_TX, .rx_gpio = GPIO_USART6_RX, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART6_OFLOWCONTROL) + .oflow = true, .cts_gpio = GPIO_USART6_CTS, #endif #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART6_IFLOWCONTROL) + .iflow = true, .rts_gpio = GPIO_USART6_RTS, #endif #ifdef CONFIG_USART6_RXDMA @@ -910,9 +902,11 @@ static struct up_dev_s g_uart7priv = .tx_gpio = GPIO_UART7_TX, .rx_gpio = GPIO_UART7_RX, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART7_OFLOWCONTROL) + .oflow = true, .cts_gpio = GPIO_UART7_CTS, #endif #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART7_IFLOWCONTROL) + .iflow = true, .rts_gpio = GPIO_UART7_RTS, #endif #ifdef CONFIG_UART7_RXDMA @@ -970,9 +964,11 @@ static struct up_dev_s g_uart8priv = .tx_gpio = GPIO_UART8_TX, .rx_gpio = GPIO_UART8_RX, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART8_OFLOWCONTROL) + .oflow = true, .cts_gpio = GPIO_UART8_CTS, #endif #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART8_IFLOWCONTROL) + .iflow = true, .rts_gpio = GPIO_UART8_RTS, #endif #ifdef CONFIG_UART8_RXDMA @@ -1308,6 +1304,92 @@ static void up_set_format(struct uart_dev_s *dev) } #endif /* CONFIG_SUPPRESS_UART_CONFIG */ +/**************************************************************************** + * Name: up_set_apb_clock + * + * Description: + * Enable or disable APB clock for the USART peripheral + * + * Input parameters: + * dev - A reference to the UART driver state structure + * on - Enable clock if 'on' is 'true' and disable if 'false' + * + ****************************************************************************/ + +static void up_set_apb_clock(struct uart_dev_s *dev, bool on) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + uint32_t rcc_en; + uint32_t regaddr; + + /* Determine which USART to configure */ + + switch (priv->usartbase) + { + default: + return; +#ifdef CONFIG_STM32_USART1 + case STM32_USART1_BASE: + rcc_en = RCC_APB2ENR_USART1EN; + regaddr = STM32_RCC_APB2ENR; + break; +#endif +#ifdef CONFIG_STM32_USART2 + case STM32_USART2_BASE: + rcc_en = RCC_APB1ENR_USART2EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_USART3 + case STM32_USART3_BASE: + rcc_en = RCC_APB1ENR_USART3EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_UART4 + case STM32_UART4_BASE: + rcc_en = RCC_APB1ENR_UART4EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_UART5 + case STM32_UART5_BASE: + rcc_en = RCC_APB1ENR_UART5EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_USART6 + case STM32_USART6_BASE: + rcc_en = RCC_APB2ENR_USART6EN; + regaddr = STM32_RCC_APB2ENR; + break; +#endif +#ifdef CONFIG_STM32_UART7 + case STM32_UART7_BASE: + rcc_en = RCC_APB1ENR_USART5EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_UART8 + case STM32_UART8_BASE: + rcc_en = RCC_APB1ENR_USART5EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif + } + + /* Enable/disable APB 1/2 clock for USART */ + + if (on) + { + modifyreg32(regaddr, 0, rcc_en); + } + else + { + modifyreg32(regaddr, rcc_en, 0); + } +} + /**************************************************************************** * Name: up_setup * @@ -1328,6 +1410,10 @@ static int up_setup(struct uart_dev_s *dev) * was enabled in stm32_lowsetup(). */ + /* Enable USART APB1/2 clock */ + + up_set_apb_clock(dev, true); + /* Configure pins for USART use */ stm32_configgpio(priv->tx_gpio); @@ -1404,6 +1490,8 @@ static int up_setup(struct uart_dev_s *dev) regval |= (USART_CR1_UE|USART_CR1_TE|USART_CR1_RE); up_serialout(priv, STM32_USART_CR1_OFFSET, regval); +#endif /* CONFIG_SUPPRESS_UART_CONFIG */ + /* Set up the cached interrupt enables value */ priv->ie = 0; @@ -1490,6 +1578,10 @@ static void up_shutdown(struct uart_dev_s *dev) up_disableusartint(priv, NULL); + /* Disable USART APB1/2 clock */ + + up_set_apb_clock(dev, false); + /* Disable Rx, Tx, and the UART */ regval = up_serialin(priv, STM32_USART_CR1_OFFSET); @@ -2006,6 +2098,46 @@ static bool up_rxavailable(struct uart_dev_s *dev) } #endif +/**************************************************************************** + * Name: up_rxflowcontrol + * + * Description: + * Called when Rx buffer is full. Return true if the Rx interrupt was + * disabled. + * + ****************************************************************************/ + +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool up_rxflowcontrol(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + uint16_t ie; + + if (priv->iflow) + { + /* Disable Rx interrupt to prevent more data being from peripheral. + * When hardware RTS is enabled, this will prevent more data from + * coming in. + * + * This function is only called when UART recv buffer is full, that + * is: "dev->recv.head + 1 == dev->recv.tail". + * + * Logic in "uart_read" will automatically toggle Rx interrupts when + * buffer is read empty and thus we do not have to re-enable Rx + * interrupts in any other place. + */ + + ie = priv->ie; + ie &= ~USART_CR1_RXNEIE; + up_restoreusartint(priv, ie); + + return true; + } + + return false; +} +#endif + /**************************************************************************** * Name: up_dma_receive * @@ -2568,6 +2700,8 @@ void stm32_serial_dma_poll(void) * ****************************************************************************/ +#ifdef USE_SERIALDRIVER + int up_putc(int ch) { #if CONSOLE_UART > 0 diff --git a/arch/arm/src/str71x/str71x_serial.c b/arch/arm/src/str71x/str71x_serial.c index a3351eb5f7..d4599574d0 100644 --- a/arch/arm/src/str71x/str71x_serial.c +++ b/arch/arm/src/str71x/str71x_serial.c @@ -279,6 +279,9 @@ static const struct uart_ops_s g_uart_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/arm/src/tiva/tiva_serial.c b/arch/arm/src/tiva/tiva_serial.c index c14edfad03..868976b8ab 100644 --- a/arch/arm/src/tiva/tiva_serial.c +++ b/arch/arm/src/tiva/tiva_serial.c @@ -344,6 +344,9 @@ static const struct uart_ops_s g_uart_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/avr/src/at32uc3/at32uc3_serial.c b/arch/avr/src/at32uc3/at32uc3_serial.c index 1ddb9901be..0425e7e04b 100644 --- a/arch/avr/src/at32uc3/at32uc3_serial.c +++ b/arch/avr/src/at32uc3/at32uc3_serial.c @@ -184,6 +184,9 @@ static const struct uart_ops_s g_uart_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/avr/src/at90usb/at90usb_serial.c b/arch/avr/src/at90usb/at90usb_serial.c index 8d906a915c..854cbb4c3c 100644 --- a/arch/avr/src/at90usb/at90usb_serial.c +++ b/arch/avr/src/at90usb/at90usb_serial.c @@ -107,7 +107,7 @@ static bool usart1_txempty(struct uart_dev_s *dev); ****************************************************************************/ struct uart_ops_s g_uart1_ops = -{ +{O .setup = usart1_setup, .shutdown = usart1_shutdown, .attach = usart1_attach, @@ -116,6 +116,9 @@ struct uart_ops_s g_uart1_ops = .receive = usart1_receive, .rxint = usart1_rxint, .rxavailable = usart1_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = usart1_send, .txint = usart1_txint, .txready = usart1_txready, diff --git a/arch/avr/src/atmega/atmega_serial.c b/arch/avr/src/atmega/atmega_serial.c index ec8a9b6f5b..90bb7f0d83 100644 --- a/arch/avr/src/atmega/atmega_serial.c +++ b/arch/avr/src/atmega/atmega_serial.c @@ -158,6 +158,9 @@ struct uart_ops_s g_usart0_ops = .receive = usart0_receive, .rxint = usart0_rxint, .rxavailable = usart0_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = usart0_send, .txint = usart0_txint, .txready = usart0_txready, diff --git a/arch/hc/src/m9s12/m9s12_serial.c b/arch/hc/src/m9s12/m9s12_serial.c index b83659f3fe..a0ce5a5fcc 100644 --- a/arch/hc/src/m9s12/m9s12_serial.c +++ b/arch/hc/src/m9s12/m9s12_serial.c @@ -146,6 +146,9 @@ struct uart_ops_s g_sci_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/mips/src/pic32mx/pic32mx-serial.c b/arch/mips/src/pic32mx/pic32mx-serial.c index 0a03b98a9c..436a52c439 100644 --- a/arch/mips/src/pic32mx/pic32mx-serial.c +++ b/arch/mips/src/pic32mx/pic32mx-serial.c @@ -198,6 +198,9 @@ static const struct uart_ops_s g_uart_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/rgmp/src/x86/com.c b/arch/rgmp/src/x86/com.c index 5a946db521..99e970e3ff 100644 --- a/arch/rgmp/src/x86/com.c +++ b/arch/rgmp/src/x86/com.c @@ -152,6 +152,9 @@ static struct uart_ops_s g_com_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/sh/src/m16c/m16c_serial.c b/arch/sh/src/m16c/m16c_serial.c index b0afc22fef..4bfeb1194c 100644 --- a/arch/sh/src/m16c/m16c_serial.c +++ b/arch/sh/src/m16c/m16c_serial.c @@ -292,6 +292,9 @@ static const struct uart_ops_s g_uart_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/sh/src/sh1/sh1_serial.c b/arch/sh/src/sh1/sh1_serial.c index 3719e0d5f4..2c8d648886 100644 --- a/arch/sh/src/sh1/sh1_serial.c +++ b/arch/sh/src/sh1/sh1_serial.c @@ -180,6 +180,9 @@ struct uart_ops_s g_sci_ops = .receive = up_receive, .rxint = up_rxint, .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif .send = up_send, .txint = up_txint, .txready = up_txready, diff --git a/arch/z16/src/z16f/z16f_serial.c b/arch/z16/src/z16f/z16f_serial.c index aa3bdcb633..90fbafe9a5 100644 --- a/arch/z16/src/z16f/z16f_serial.c +++ b/arch/z16/src/z16f/z16f_serial.c @@ -121,6 +121,9 @@ static const struct uart_ops_s g_uart_ops = z16f_receive, /* receive */ z16f_rxint, /* rxint */ z16f_rxavailable, /* rxavailable */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + NULL, /* rxflowcontrol */ +#endif z16f_send, /* send */ z16f_txint, /* txint */ z16f_txready, /* txready */ diff --git a/arch/z80/src/ez80/ez80_serial.c b/arch/z80/src/ez80/ez80_serial.c index 06ca2753e7..f071b1e62d 100644 --- a/arch/z80/src/ez80/ez80_serial.c +++ b/arch/z80/src/ez80/ez80_serial.c @@ -110,6 +110,9 @@ static const struct uart_ops_s g_uart_ops = ez80_receive, /* receive */ ez80_rxint, /* rxint */ ez80_rxavailable, /* rxavailable */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + NULL, /* rxflowcontrol */ +#endif ez80_send, /* send */ ez80_txint, /* txint */ ez80_txready, /* txready */ diff --git a/arch/z80/src/z180/z180_scc.c b/arch/z80/src/z180/z180_scc.c index 29d0c52396..d0334258f8 100644 --- a/arch/z80/src/z180/z180_scc.c +++ b/arch/z80/src/z180/z180_scc.c @@ -114,6 +114,9 @@ static const struct uart_ops_s g_uart_ops = z180_receive, /* receive */ z180_rxint, /* rxint */ z180_rxavailable, /* rxavailable */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + NULL, /* rxflowcontrol */ +#endif z180_send, /* send */ z180_txint, /* txint */ z180_txready, /* txready */ diff --git a/arch/z80/src/z8/z8_serial.c b/arch/z80/src/z8/z8_serial.c index 7dcf2f2581..98fa554e6e 100644 --- a/arch/z80/src/z8/z8_serial.c +++ b/arch/z80/src/z8/z8_serial.c @@ -122,6 +122,9 @@ static const struct uart_ops_s g_uart_ops = z8_receive, /* receive */ z8_rxint, /* rxint */ z8_rxavailable, /* rxavailable */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + NULL, /* rxflowcontrol */ +#endif z8_send, /* send */ z8_txint, /* txint */ z8_txready, /* txready */