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ARMv7-R: fix compilation error

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This commit fixes compilation errors on MPU support for ARMv7-R.

Signed-off-by: Heesub Shin <heesub.shin@samsung.com>
This commit is contained in:
Heesub Shin 2016-03-22 15:32:03 +09:00
parent 96a200a71c
commit af6e4f59c6
1 changed files with 12 additions and 10 deletions
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22
arch/arm/src/armv7-r/mpu.h
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@ -49,6 +49,8 @@
# include <debug.h> # include <debug.h>
# include "up_arch.h" # include "up_arch.h"
# include "cache.h"
# include "sctlr.h"
# include "cp15.h" # include "cp15.h"
#endif #endif
@ -66,7 +68,7 @@
/* Region Base Address Register Definitions */ /* Region Base Address Register Definitions */
#define MPU_RBAR_MASK 0xfffffffc #define MPU_RBAR_ADDR_MASK 0xfffffffc
/* Region Size and Enable Register */ /* Region Size and Enable Register */
@ -201,7 +203,7 @@ static inline unsigned int mpu_get_mpuir(void)
unsigned int mpuir; unsigned int mpuir;
__asm__ __volatile__ __asm__ __volatile__
( (
"\tmrc " CP15_MPUIR(%0) "\tmrc p15, 0, %0, c0, c0, 4"
: "=r" (mpuir) : "=r" (mpuir)
: :
: "memory" : "memory"
@ -222,7 +224,7 @@ static inline void mpu_set_drbar(unsigned int drbar)
{ {
__asm__ __volatile__ __asm__ __volatile__
( (
"\tmcr " CP15_DRBAR(%0) "\tmcr p15, 0, %0, c6, c1, 0"
: :
: "r" (drbar) : "r" (drbar)
: "memory" : "memory"
@ -241,7 +243,7 @@ static inline void mpu_set_drsr(unsigned int drsr)
{ {
__asm__ __volatile__ __asm__ __volatile__
( (
"\tmcr " CP15_DRSR(%0) "\tmcr p15, 0, %0, c6, c1, 2"
: :
: "r" (drsr) : "r" (drsr)
: "memory" : "memory"
@ -260,7 +262,7 @@ static inline void mpu_set_dracr(unsigned int dracr)
{ {
__asm__ __volatile__ __asm__ __volatile__
( (
"\tmcr " CP15_DRACR(%0) "\tmcr p15, 0, %0, c6, c1, 4"
: :
: "r" (dracr) : "r" (dracr)
: "memory" : "memory"
@ -280,7 +282,7 @@ static inline void mpu_set_irbar(unsigned int irbar)
{ {
__asm__ __volatile__ __asm__ __volatile__
( (
"\tmcr " CP15_IRBAR(%0) "\tmcr p15, 0, %0, c6, c1, 1"
: :
: "r" (irbar) : "r" (irbar)
: "memory" : "memory"
@ -301,7 +303,7 @@ static inline void mpu_set_irsr(unsigned int irsr)
{ {
__asm__ __volatile__ __asm__ __volatile__
( (
"\tmcr " CP15_IRSR(%0) "\tmcr p15, 0, %0, c6, c1, 3"
: :
: "r" (irsr) : "r" (irsr)
: "memory" : "memory"
@ -322,7 +324,7 @@ static inline void mpu_set_iracr(unsigned int iracr)
{ {
__asm__ __volatile__ __asm__ __volatile__
( (
"\tmcr " CP15_IRACR(%0) "\tmcr p15, 0, %0, c6, c1, 5"
: :
: "r" (iracr) : "r" (iracr)
: "memory" : "memory"
@ -342,7 +344,7 @@ static inline void mpu_set_rgnr(unsigned int rgnr)
{ {
__asm__ __volatile__ __asm__ __volatile__
( (
"\tmcr " CP15_RGNR(%0) "\tmcr p15, 0, %0, c6, c2, 0"
: :
: "r" (rgnr) : "r" (rgnr)
: "memory" : "memory"
@ -422,7 +424,7 @@ static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size)
/* Select the region base address */ /* Select the region base address */
mpu_set_drbar(base & MPU_RBAR_ADDR_MASK) | region | MPU_RBAR_VALID); mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region | MPU_RBAR_VALID);
/* Select the region size and the sub-region map */ /* Select the region size and the sub-region map */