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Fix watchdog stop bit usage. From Lazlo

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This commit is contained in:
Gregory Nutt 2014-10-10 11:36:50 -06:00
parent 994f0c8389
commit afa548a1bc
3 changed files with 21 additions and 7 deletions
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12
arch/arm/src/stm32/chip/stm32_dbgmcu.h
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@ -109,9 +109,9 @@
# define DBGMCU_APB1_TIM12STOP (1 << 6) /* Bit 6: TIM12 stopped when core is halted */
# define DBGMCU_APB1_TIM13STOP (1 << 7) /* Bit 7: TIM13 stopped when core is halted */
# define DBGMCU_APB1_TIM14STOP (1 << 8) /* Bit 7: TIM14 stopped when core is halted */
# define DBGMCU_CR_RTCSTOP (1 << 10) /* Bit 11: RTC stopped when Core is halted */
# define DBGMCU_CR_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */
# define DBGMCU_CR_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */
# define DBGMCU_APB1_RTCSTOP (1 << 10) /* Bit 11: RTC stopped when Core is halted */
# define DBGMCU_APB1_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */
# define DBGMCU_APB1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */
# define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: SMBUS timeout mode stopped when Core is halted */
# define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: SMBUS timeout mode stopped when Core is halted */
# define DBGMCU_APB1_I2C3STOP (1 << 23) /* Bit 23: SMBUS timeout mode stopped when Core is halted */
@ -123,9 +123,9 @@
# define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */
# define DBGMCU_APB1_TIM6STOP (1 << 4) /* Bit 4: TIM6 stopped when core is halted */
# define DBGMCU_APB1_TIM7STOP (1 << 5) /* Bit 5: TIM7 stopped when core is halted */
# define DBGMCU_CR_RTCSTOP (1 << 10) /* Bit 11: RTC stopped when Core is halted */
# define DBGMCU_CR_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */
# define DBGMCU_CR_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */
# define DBGMCU_APB1_RTCSTOP (1 << 10) /* Bit 11: RTC stopped when Core is halted */
# define DBGMCU_APB1_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */
# define DBGMCU_APB1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */
# define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: SMBUS timeout mode stopped when Core is halted */
# define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: SMBUS timeout mode stopped when Core is halted */
# define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */

9
arch/arm/src/stm32/stm32_iwdg.c
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@ -671,7 +671,7 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
priv->lsifreq = lsifreq;
priv->started = false;
/* Make sure that the LSI ocsillator is enabled. NOTE: The LSI oscillator
/* Make sure that the LSI oscillator is enabled. NOTE: The LSI oscillator
* is enabled here but is not disabled by this file (because this file does
* not know the global usage of the oscillator. Any clock management
* logic (say, as part of a power management scheme) needs handle other
@ -701,9 +701,16 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \
defined(CONFIG_STM32_JTAG_SW_ENABLE)
{
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F40XX)
uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ);
cr |= DBGMCU_APB1_IWDGSTOP;
putreg32(cr, STM32_DBGMCU_APB1_FZ);
#else /* if defined(CONFIG_STM32_STM32F10XX) */
uint32_t cr = getreg32(STM32_DBGMCU_CR);
cr |= DBGMCU_CR_IWDGSTOP;
putreg32(cr, STM32_DBGMCU_CR);
#endif
}
#endif
}

7
arch/arm/src/stm32/stm32_wwdg.c
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@ -797,9 +797,16 @@ void stm32_wwdginitialize(FAR const char *devpath)
defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \
defined(CONFIG_STM32_JTAG_SW_ENABLE)
{
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F40XX)
uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ);
cr |= DBGMCU_APB1_WWDGSTOP;
putreg32(cr, STM32_DBGMCU_APB1_FZ);
#else /* if defined(CONFIG_STM32_STM32F10XX) */
uint32_t cr = getreg32(STM32_DBGMCU_CR);
cr |= DBGMCU_CR_WWDGSTOP;
putreg32(cr, STM32_DBGMCU_CR);
#endif
}
#endif
}