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STM32F3 SPI: Fix the number of bit setting for the F3. It works differently than for other parts.

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This commit is contained in:
Gregory Nutt 2016-08-12 18:32:37 -06:00
parent ab16ad7530
commit afb02b56d4
2 changed files with 28 additions and 17 deletions
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36
arch/arm/src/stm32/chip/stm32_spi.h
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@ -135,7 +135,11 @@
#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */
#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */
#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */
#define SPI_CR1_DFF (1 << 11) /* Bit 11: Data Frame Format */
#ifdef CONFIG_STM32_STM32F30XX
# define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */
#else
# define SPI_CR1_DFF (1 << 11) /* Bit 11: Data Frame Format */
#endif
#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */
#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */
#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */
@ -157,21 +161,21 @@
#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */
#ifdef CONFIG_STM32_STM32F30XX
#define SPI_CR1_DS_SHIFT (8) /* Bits 8-11: Data size */
#define SPI_CR1_DS_MASK (15 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_4BIT (3 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_5BIT (4 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_6BIT (5 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_7BIT (6 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_8BIT (7 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_9BIT (8 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_10BIT (9 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_11BIT (10 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_12BIT (11 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_13BIT (12 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_14BIT (13 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_15BIT (14 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_16BIT (15 << SPI_CR1_DS_SHIFT)
#define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */
#define SPI_CR2_DS_MASK (15 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_4BIT (3 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_5BIT (4 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_6BIT (5 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_7BIT (6 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_8BIT (7 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_9BIT (8 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_10BIT (9 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_11BIT (10 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_12BIT (11 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_13BIT (12 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_14BIT (13 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_15BIT (14 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_16BIT (15 << SPI_CR2_DS_SHIFT)
#define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */
#define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */
#define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */

9
arch/arm/src/stm32/stm32_spi.c
View File

@ -1151,6 +1151,13 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
if (nbits != priv->nbits)
{
#ifdef CONFIG_STM32_STM32F30XX
DEBUGASSERT(nbits >= 8 && nbits <= 16)'
spi_modifycr1(priv, 0, SPI_CR1_SPE);
spi_modifycr2(priv, SPI_CR2_DS(nbits), SPI_CR2_DS_MASK);
spi_modifycr1(priv, SPI_CR1_SPE, 0);
#else
/* Yes... Set CR1 appropriately */
switch (nbits)
@ -1172,7 +1179,7 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
spi_modifycr1(priv, 0, SPI_CR1_SPE);
spi_modifycr1(priv, setbits, clrbits);
spi_modifycr1(priv, SPI_CR1_SPE, 0);
#endif
/* Save the selection so the subsequence re-configurations will be faster */
priv->nbits = nbits;