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arch/arm/src/samd2l2, configs/samd20-xplained, samd21-xplained, saml21-xplained: Fix SAMD2L2 arch to use calibrated oscillator value. Now SAMD20 and SAMD21 should work fine without external crystal. Note that SAML21 Xplained board has an external crystal and doesn't need this change, unless you don't want to use the crystal.

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This commit is contained in:
Alexander Vasiliev 2018-12-29 08:36:50 -06:00 committed by Gregory Nutt
parent dffcddd82d
commit b02380c704
7 changed files with 20 additions and 53 deletions
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2
arch/arm/src/samd2l2/chip/samd20_memorymap.h
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@ -70,6 +70,8 @@
# define SAM_AUX1_AREA3 0x00806010 /* Area 3 offset address (reserved, 128 bits) */
# define SAM_AUX1_AREA4 0x00806020 /* Area 4 Software calibration area (256 bits) */
#define SAM_NVMCALIB_AREA SAM_AUX1_AREA4 /* Use same name of SAML21 */
/* AHB-APB Bridge A */
#define SAM_PAC0_BASE 0x40000000 /* Peripheral Access Controller 0 */

2
arch/arm/src/samd2l2/chip/samd21_memorymap.h
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@ -71,6 +71,8 @@
# define SAM_AUX1_AREA3 0x00806010 /* Area 3 offset address (reserved, 128 bits) */
# define SAM_AUX1_AREA4 0x00806020 /* Area 4 Software calibration area (256 bits) */
#define SAM_NVMCALIB_AREA SAM_AUX1_AREA4 /* Use same name of SAML21 */
/* AHB-APB Bridge A */
#define SAM_PAC0_BASE 0x40000000 /* Peripheral Access Controller 0 */

13
arch/arm/src/samd2l2/samd_clockconfig.c
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@ -665,8 +665,6 @@ static inline void sam_dpll_config(void)
* BOARD_DFLL_ENABLECHILLCYCLE - Boolean (defined / not defined)
* BOARD_DFLL_QUICKLOCK - Boolean (defined / not defined)
* BOARD_DFLL_ONDEMAND - Boolean (defined / not defined)
* BOARD_DFLL_COARSEVALUE - Value
* BOARD_DFLL_FINEVALUE - Value
*
* Open Loop mode only:
* BOARD_DFLL_COARSEVALUE - Value
@ -689,8 +687,11 @@ static inline void sam_dpll_config(void)
#ifdef BOARD_DFLL_ENABLE
static inline void sam_dfll_config(void)
{
uint16_t control;
uint32_t regval;
uint16_t control;
uint32_t regval;
uint32_t *nvm_cal = (uint32_t *)SAM_NVMCALIB_AREA;
uint32_t coarse = ((nvm_cal[1]) >> 26) & 0x3f;
uint32_t fine = ((nvm_cal[2]) >> 0) & 0x7ff;
/* Set up the DFLL control register */
@ -737,8 +738,8 @@ static inline void sam_dfll_config(void)
/* Set up the DFLL value register */
regval = SYSCTRL_DFLLVAL_COARSE(BOARD_DFLL_COARSEVALUE) |
SYSCTRL_DFLLVAL_FINE(BOARD_DFLL_FINEVALUE);
regval = SYSCTRL_DFLLVAL_COARSE(coarse) |
SYSCTRL_DFLLVAL_FINE(fine);
putreg32(regval, SAM_SYSCTRL_DFLLVAL);
/* Finally, set the state of the ONDEMAND bit if necessary */

17
arch/arm/src/samd2l2/saml_clockconfig.c
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@ -805,12 +805,6 @@ static inline void sam_osc16m_config(void)
* BOARD_DFLL48M_QUICKLOCK - Boolean (defined / not defined)
* BOARD_DFLL48M_RUNINSTDBY - Boolean (defined / not defined)
* BOARD_DFLL48M_ONDEMAND - Boolean (defined / not defined)
* BOARD_DFLL48M_COARSEVALUE - Value
* BOARD_DFLL48M_FINEVALUE - Value
*
* Open Loop mode only:
* BOARD_DFLL48M_COARSEVALUE - Value
* BOARD_DFLL48M_FINEVALUE - Value
*
* Closed loop mode only:
* BOARD_DFLL48M_REFCLK_CLKGEN - GCLK index in the range {0..8}
@ -829,8 +823,11 @@ static inline void sam_osc16m_config(void)
#ifdef BOARD_DFLL48M_ENABLE
static inline void sam_dfll48m_config(void)
{
uint16_t control;
uint32_t regval;
uint16_t control;
uint32_t regval;
uint32_t *nvm_cal = (uint32_t *)SAM_NVMCALIB_AREA;
uint32_t coarse = ((nvm_cal[1]) >> 26) & 0x3f;
uint32_t fine = ((nvm_cal[2]) >> 0) & 0x7ff;
/* Disable ONDEMAND mode while writing configurations (Errata 9905). This
* is probably not necessary on the first time configuration after reset.
@ -907,8 +904,8 @@ static inline void sam_dfll48m_config(void)
/* Set up the DFLL value register */
regval = OSCCTRL_DFLLVAL_COARSE(BOARD_DFLL48M_COARSEVALUE) |
OSCCTRL_DFLLVAL_FINE(BOARD_DFLL48M_FINEVALUE);
regval = OSCCTRL_DFLLVAL_COARSE(coarse) |
OSCCTRL_DFLLVAL_FINE(fine);
putreg32(regval, SAM_OSCCTRL_DFLLVAL);
}
#else

13
configs/samd20-xplained/include/board.h
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@ -171,12 +171,6 @@
* BOARD_DFLL_ENABLECHILLCYCLE - Boolean (defined / not defined)
* BOARD_DFLL_QUICKLOCK - Boolean (defined / not defined)
* BOARD_DFLL_ONDEMAND - Boolean (defined / not defined)
* BOARD_DFLL_COARSEVALUE - Value
* BOARD_DFLL_FINEVALUE - Value
*
* Open Loop mode only:
* BOARD_DFLL_COARSEVALUE - Value
* BOARD_DFLL_FINEVALUE - Value
*
* Closed loop mode only:
* BOARD_DFLL_GCLKGEN - GCLK index
@ -188,15 +182,10 @@
*/
#define BOARD_DFLL_ENABLE 1
#undef BOARD_DFLL_OPENLOOP
#define BOARD_DFLL_OPENLOOP 1
#undef BOARD_DFLL_ONDEMAND
#undef BOARD_DFLL_RUNINSTANDBY
/* DFLL open loop mode configuration */
#define BOARD_DFLL_COARSEVALUE (0x1f / 4)
#define BOARD_DFLL_FINEVALUE (0xff / 4)
/* DFLL closed loop mode configuration */
#define BOARD_DFLL_SRCGCLKGEN 1

13
configs/samd21-xplained/include/board.h
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@ -171,12 +171,6 @@
* BOARD_DFLL_ENABLECHILLCYCLE - Boolean (defined / not defined)
* BOARD_DFLL_QUICKLOCK - Boolean (defined / not defined)
* BOARD_DFLL_ONDEMAND - Boolean (defined / not defined)
* BOARD_DFLL_COARSEVALUE - Value
* BOARD_DFLL_FINEVALUE - Value
*
* Open Loop mode only:
* BOARD_DFLL_COARSEVALUE - Value
* BOARD_DFLL_FINEVALUE - Value
*
* Closed loop mode only:
* BOARD_DFLL_GCLKGEN - GCLK index
@ -188,15 +182,10 @@
*/
#define BOARD_DFLL_ENABLE 1
#undef BOARD_DFLL_OPENLOOP
#define BOARD_DFLL_OPENLOOP 1
#undef BOARD_DFLL_ONDEMAND
#undef BOARD_DFLL_RUNINSTANDBY
/* DFLL open loop mode configuration */
#define BOARD_DFLL_COARSEVALUE (0x1f / 4)
#define BOARD_DFLL_FINEVALUE (0xff / 4)
/* DFLL closed loop mode configuration */
#define BOARD_DFLL_SRCGCLKGEN 1

13
configs/saml21-xplained/include/board.h
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@ -209,12 +209,6 @@
* BOARD_DFLL48M_QUICKLOCK - Boolean (defined / not defined)
* BOARD_DFLL48M_RUNINSTDBY - Boolean (defined / not defined)
* BOARD_DFLL48M_ONDEMAND - Boolean (defined / not defined)
* BOARD_DFLL48M_COARSEVALUE - Value
* BOARD_DFLL48M_FINEVALUE - Value
*
* Open Loop mode only:
* BOARD_DFLL48M_COARSEVALUE - Value
* BOARD_DFLL48M_FINEVALUE - Value
*
* Closed loop mode only:
* BOARD_DFLL48M_REFCLK_CLKGEN - GCLK index in the range {0..8}
@ -260,11 +254,6 @@
# undef BOARD_DFLL48M_RUNINSTDBY
# undef BOARD_DFLL48M_ONDEMAND
/* DFLL open loop mode configuration */
# define BOARD_DFLL48M_COARSEVALUE (0x1f / 4)
# define BOARD_DFLL48M_FINEVALUE (0xff / 4)
/* DFLL closed loop mode configuration */
# define BOARD_DFLL48M_REFCLK_CLKGEN 1
@ -273,8 +262,6 @@
# define BOARD_DFLL48M_TRACKAFTERFINELOCK 1
# define BOARD_DFLL48M_KEEPLOCKONWAKEUP 1
# define BOARD_DFLL48M_ENABLECHILLCYCLE 1
# define BOARD_DFLL48M_MAXCOARSESTEP (0x1f / 4)
# define BOARD_DFLL48M_MAXFINESTEP (0xff / 4)
# ifdef CONFIG_SAML21_XPLAINED_DFLL_OPENLOOP
# define BOARD_DFLL48M_FREQUENCY (13720000) /* REVISIT: Needs to be measured */