SAMA5 OHCI+EHCI mostly cosmetic changes
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@ -343,14 +343,37 @@ static inline void sam_usbclockconfig(void)
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* value and USB Full-speed accuracy.
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* 4) Enable the OHCI clocks, UHP bit in PMC_SCER register.
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*
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* Steps 2 and 3 are done here. 1 and 2 are performed with the USB device
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* driver is opened.
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* Steps 2 and 3 are done here. 1 and 2 are performed with the OHCI
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* driver is initialized.
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*/
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putreg32(BOARD_OHCI_INPUT | BOARD_OHCI_DIVIDER << PMC_USB_USBDIV_SHIFT,
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SAM_PMC_USB);
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#endif
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#ifdef CONFIG_SAMA5_EHCI
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/* For High-speed operations, the user has to perform the following:
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*
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* 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in
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* PMC_PCER register.
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* 2) Write CKGR_PLLCOUNT field in PMC_UCKR register.
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* 3) Enable UPLL, bit AT91C_CKGR_UPLLEN in PMC_UCKR register.
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* 4) Wait until UTMI_PLL is locked. LOCKU bit in PMC_SR register
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* 5) Enable BIAS, bit AT91C_CKGR_BIASEN in PMC_UCKR register.
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* 6) Select UPLLCK as Input clock of OHCI part, USBS bit in PMC_USB
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* register.
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* 7) Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in
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* PMC_USB register. USBDIV must be 9 (division by 10) if UPLLCK is
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* selected.
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* 8) Enable OHCI clocks, UHP bit in PMC_SCER register.
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*
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* Steps 2 through 7 performed here. 1 and 8 are performed in the EHCI
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* driver is initialized.
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*/
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# warning Missing logic
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#endif
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#if 0 // #ifdef CONFIG_USBDEV
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uint32_t regval;
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@ -186,7 +186,7 @@ struct sam_eplist_s
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struct sam_gtd_s *tail; /* Tail transfer descriptor (TD) */
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};
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/* This structure retins the state of one root hub port */
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/* This structure retains the state of one root hub port */
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struct sam_rhport_s
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{
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@ -2792,9 +2792,6 @@ static int sam_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
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struct sam_ed_s *ed;
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uint32_t dirpid;
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uint32_t regval;
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#if SAM_IOBUFFERS > 0
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uint8_t *origbuf = NULL;
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#endif
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bool in;
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int ret;
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@ -3015,7 +3012,7 @@ FAR struct usbhost_connection_s *sam_ohci_initialize(int controller)
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/* Enable OHCI clocks */
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regval = getreg32(SAM_PMC_SCER);
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regval = getreg32(SAM_PMC_SCER);
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regval |= PMC_UHP;
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putreg32(regval, SAM_PMC_SCER);
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irqrestore(flags);
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@ -3035,7 +3032,7 @@ FAR struct usbhost_connection_s *sam_ohci_initialize(int controller)
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* dedicated function
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*/
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udbg("Initializing Host Stack\n");
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udbg("Initializing OHCI Stack\n");
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/* Initialize all the HCCA to 0 */
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@ -49,6 +49,16 @@
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* General definitions **********************************************************************/
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/* Endpoint speed values as used in endpoint characteristics field */
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#define EHCI_FULL_SPEED (0) /* Full-Speed (12Mbs) */
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#define EHCI_LOW_SPEED (1) /* Low-Speed (1.5Mbs) */
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#define EHCI_HIGH_SPEED (2) /* High-Speed (480 Mb/s) */
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#define EHCI_DIR_IN (1) /* Direction IN: Peripheral to host */
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#define EHCI_DIR_OUT (0) /* Direction OUT: Host to peripheral */
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/* PCI Configuration Space Register Offsets *************************************************/
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/* Paragraph 2.1 */
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@ -456,8 +466,11 @@
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/* siTD Transfer State. Paragraph 3.4.3 */
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#define SITD_XFRSTATE_STATUS_SHIFT (0) /* Bits 0-7: Status */
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#define SITD_XFRSTATE_STATUS_MASK (0xff << SITD_XFRSTATE_STATUS_SHIFT)
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#define SITD_XFRSTATE_CPROGMASK_SHIFT (8) /* Bits 8-15: µFrame Complete-split Progress Mask */
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#define SITD_XFRSTATE_CPROGMASK_MASK (0xff << SITD_XFRSTATE_CPROGMASK_SHIFT)
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#define SITD_XFRSTATE_NBYTES_SHIFT (16) /* Bits 16-25: Total Bytes To Transfer */
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#define SITD_XFRSTATE_NBYTES_MASK (0x3ff << SITD_XFRSTATE_NBYTES_SHIFT)
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/* Bits 26-29: Reserved */
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#define SITD_XFRSTATE_P (1 << 30) /* Bit 30: Page Select */
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#define SITD_XFRSTATE_IOC (1 << 31) /* Bit 31: Interrupt On Complete */
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@ -521,7 +534,8 @@
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#define QTD_TOKEN_CPAGE_SHIFT (12) /* Bits 12-14: Current Page */
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#define QTD_TOKEN_CPAGE_MASK (7 << QTD_TOKEN_CPAGE_SHIFT)
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#define QTD_TOKEN_IOC (1 << 15) /* Bit 15: Interrupt On Complete */
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#define QTD_TOKEN_NBYTES (16) /* Bits 16-30: Total Bytes to Transfer */
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#define QTD_TOKEN_NBYTES_SHIFT (16) /* Bits 16-30: Total Bytes to Transfer */
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#define QTD_TOKEN_NBYTES_MASK (0x7fff << QTD_TOKEN_NBYTES_SHIFT)
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#define QTD_TOKEN_TOGGLE (1 << 13) /* Bit 31: Data Toggle
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/* qTD Buffer Page Pointer List. Paragraph 3.5.4 */
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@ -555,7 +569,7 @@
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#define QH_EPCHAR_DEVADDR_SHIFT (0) /* Bitx 0-6: Device Address */
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#define QH_EPCHAR_DEVADDR_MASK (0x7f << QH_EPCHAR_DEVADDR_SHIFT)
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#define QH_EPCHAR_I (1 << 7) /* Bit 7: Inactivate on Next Transactionl */
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#define QH_EPCHAR_I (1 << 7) /* Bit 7: Inactivate on Next Transaction */
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#define QH_EPCHAR_ENDPT_SHIFT (8) /* Bitx 8-11: Endpoint Number */
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#define QH_EPCHAR_ENDPT_MASK (15 << QH_EPCHAR_ENDPT_SHIFT)
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#define QH_EPCHAR_EPS_SHIFT (12) /* Bitx 12-13: Endpoint Speed */
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@ -634,7 +648,8 @@
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#define QH_TOKEN_CPAGE_SHIFT (12) /* Bits 12-14: Current Page */
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#define QH_TOKEN_CPAGE_MASK (7 << QH_TOKEN_CPAGE_SHIFT)
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#define QH_TOKEN_IOC (1 << 15) /* Bit 15: Interrupt On Complete */
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#define QH_TOKEN_NBYTES (16) /* Bits 16-30: Total Bytes to Transfer */
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#define QH_TOKEN_NBYTES_SHIFT (16) /* Bits 16-30: Total Bytes to Transfer */
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#define QH_TOKEN_NBYTES_MASK (0x7fff << QH_TOKEN_NBYTES_SHIFT)
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#define QH_TOKEN_TOGGLE (1 << 13) /* Bit 31: Data Toggle
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/* Buffer Page Pointer List (NOTE 2)
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