From b0597583da340e7f8559854f1f5fc48e1ccff003 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Mon, 17 Apr 2017 12:48:07 -0600 Subject: [PATCH] Fix System Clock value to 48MHz and remove MCLK definition --- arch/arm/src/stm32f0/stm32f0_clockconfig.c | 4 +- arch/arm/src/stm32f0/stm32f0_timerisr.c | 4 +- configs/stm32f0discovery/include/board.h | 48 +++++++++------------- 3 files changed, 23 insertions(+), 33 deletions(-) diff --git a/arch/arm/src/stm32f0/stm32f0_clockconfig.c b/arch/arm/src/stm32f0/stm32f0_clockconfig.c index 9d54e6133b..20acb55804 100644 --- a/arch/arm/src/stm32f0/stm32f0_clockconfig.c +++ b/arch/arm/src/stm32f0/stm32f0_clockconfig.c @@ -91,11 +91,11 @@ void stm32f0_clockconfig(void) putreg32(regval, STM32F0_RCC_CR); while ((getreg32(STM32F0_RCC_CR) & RCC_CR_PLLRDY) != 0); - /* Configure the PLL. Multiple x6 to get 48MHz */ + /* Configure the PLL. Multiply the HSI to get System Clock */ regval = getreg32(STM32F0_RCC_CFGR); regval &= ~RCC_CFGR_PLLMUL_MASK; - regval |= RCC_CFGR_PLLMUL_CLKx6; + regval |= STM32F0_CFGR_PLLMUL; putreg32(regval, STM32F0_RCC_CFGR); /* Enable the PLL */ diff --git a/arch/arm/src/stm32f0/stm32f0_timerisr.c b/arch/arm/src/stm32f0/stm32f0_timerisr.c index 3887b24a71..d6cb231539 100644 --- a/arch/arm/src/stm32f0/stm32f0_timerisr.c +++ b/arch/arm/src/stm32f0/stm32f0_timerisr.c @@ -63,9 +63,9 @@ */ #if defined(CONFIG_STM32F0_SYSTICK_CORECLK) -# define SYSTICK_CLOCK STM32F0_MCLK /* Core clock */ +# define SYSTICK_CLOCK STM32F0_SYSCLK_FREQUENCY /* Core clock */ #elif defined(CONFIG_STM32F0_SYSTICK_CORECLK_DIV16) -# define SYSTICK_CLOCK (STM32F0_MCLK / 16) /* Core clock divided by 16 */ +# define SYSTICK_CLOCK (STM32F0_SYSCLK_FREQUENCY / 16) /* Core clock divided by 16 */ #endif /* The desired timer interrupt frequency is provided by the definition diff --git a/configs/stm32f0discovery/include/board.h b/configs/stm32f0discovery/include/board.h index 09892bef0d..e2ca4de903 100644 --- a/configs/stm32f0discovery/include/board.h +++ b/configs/stm32f0discovery/include/board.h @@ -75,27 +75,19 @@ #define STM32F0_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ #define STM32F0_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */ +#define STM32F0_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */ +#define STM32F0_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */ #define STM32F0_HSE_FREQUENCY STM32F0_BOARD_XTAL -#define STM32F0_MSI_FREQUENCY 2097000 /* Default is approximately 2.097Mhz */ -#define STM32F0_LSI_FREQUENCY 37000 /* Approximately 37KHz */ +#define STM32F0_LSI_FREQUENCY 40000 /* Approximately 40KHz */ #define STM32F0_LSE_FREQUENCY 32768 /* X2 on board */ -/* This is the clock setup we configure for: - * - * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for source - * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> PLL0 multipler=20, pre-divider=1 - * MCLK = 480MHz / 6 = 80MHz -> MCLK divider = 6 - */ - -#define STM32F0_MCLK 48000000 /* 48Mhz */ - /* PLL Configuration * - * - PLL source is HSI -> 8MHz input (nominal) - * - PLL source pre-divider 2 -> 4MHz divided down PLL VCO clock output - * - PLL multipler is 6 -> 24MHz PLL VCO clock output (for USB) + * - PLL source is HSI -> 8MHz input (nominal) + * - PLL source predivider 2 -> 4MHz divided down PLL VCO clock output + * - PLL multipler is 12 -> 48MHz PLL VCO clock output (for USB) * - * Resulting SYSCLK frequency is 8MHz x 6 / 2 = 24MHz + * Resulting SYSCLK frequency is 8MHz x 12 / 2 = 48MHz * * USB/SDIO: * If the USB or SDIO interface is used in the application, the PLL VCO @@ -112,16 +104,16 @@ * The minimum input clock frequency for PLL is 2 MHz (when using HSE as PLL source). */ -#define STM32F0_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ -#define STM32F0_PLLSRC_FREQUENCY (STM32F0_HSI_FREQUENCY/2) +#define STM32F0_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ +#define STM32F0_PLLSRC_FREQUENCY (STM32F0_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ #ifdef CONFIG_STM32F0_USB -# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */ -# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx6 /* PLLMUL = 6 */ -# define STM32F0_PLL_FREQUENCY (6*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 24MHz */ +# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */ +# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ +# define STM32F0_PLL_FREQUENCY (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ #else -# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */ -# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx6 /* PLLMUL = 6 */ -# define STM32F0_PLL_FREQUENCY (6*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 24MHz */ +# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */ +# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ +# define STM32F0_PLL_FREQUENCY (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ #endif /* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output @@ -131,23 +123,21 @@ #define STM32F0_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ #define STM32F0_SYSCLK_SWS RCC_CFGR_SWS_PLL #ifdef CONFIG_STM32F0_USB -# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 24MHz */ +# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #else -# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 24MHz */ +# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #endif -/* AHB clock (HCLK) is SYSCLK (24MHz) */ - #define STM32F0_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32F0_HCLK_FREQUENCY STM32F0_SYSCLK_FREQUENCY #define STM32F0_BOARD_HCLK STM32F0_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ -/* APB1 clock (PCLK1) is HCLK (24MHz) */ +/* APB1 clock (PCLK1) is HCLK (48MHz) */ #define STM32F0_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK #define STM32F0_PCLK1_FREQUENCY (STM32F0_HCLK_FREQUENCY) -/* APB2 clock (PCLK2) is HCLK (24MHz) */ +/* APB2 clock (PCLK2) is HCLK (48MHz) */ #define STM32F0_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK #define STM32F0_PCLK2_FREQUENCY STM32F0_HCLK_FREQUENCY