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arch: Nxstyle fixes

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Nxstyle fixes to pass CI

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea 2021-04-01 08:20:14 +02:00 committed by Xiang Xiao
parent 9b53451e42
commit b07780d13d
9 changed files with 84 additions and 55 deletions
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2
arch/arm/include/stm32f7/stm32f72xx73xx_irq.h
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@ -18,7 +18,7 @@
*
****************************************************************************/
/*Change Record:
/* Change Record:
* bf20171107 Created file. It's identical to stm32f74xx75xx_irq except for
* the exclusions noted by this tag, and the addition of the
* last IRQ for SDMMC2 (IRQ103).

31
arch/arm/src/am335x/am335x_boot.c
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@ -204,7 +204,9 @@ static inline void am335x_remap(void)
defined(CONFIG_PAGING)
static void am335x_vectorpermissions(uint32_t mmuflags)
{
/* The PTE for the beginning of OCMC0 RAM is at the base of the L2 page table */
/* The PTE for the beginning of OCMC0 RAM is at the base of the L2 page
* table
*/
uint32_t pte = mmu_l2_getentry(PG_L2_VECT_VADDR, 0);
@ -303,8 +305,8 @@ static void am335x_vectormapping(void)
* Description:
* Copy the interrupt block to its final destination. Vectors are already
* positioned at the beginning of the text region and only need to be
* copied in the case where we are using high vectors or where the beginning
* of the text region cannot be remapped to address zero.
* copied in the case where we are using high vectors or where the
* beginning of the text region cannot be remapped to address zero.
*
****************************************************************************/
@ -322,10 +324,11 @@ static void am335x_copyvectorblock(void)
am335x_vectorpermissions(MMU_L2_VECTRWFLAGS);
#endif
/* Copy the vectors into OCMC0 RAM at the address that will be mapped to the vector
* address:
/* Copy the vectors into OCMC0 RAM at the address that will be mapped to
* the vector address:
*
* AM335X_VECTOR_PADDR - Unmapped, physical address of vector table in OCMC0 RAM
* AM335X_VECTOR_PADDR - Unmapped, physical address of vector table in
* OCMC0 RAM
* AM335X_VECTOR_VSRAM - Virtual address of vector table in OCMC0 RAM
* AM335X_VECTOR_VADDR - Virtual address of vector table (0x00000000 or
* 0xffff0000)
@ -377,14 +380,14 @@ static void am335x_copyvectorblock(void)
void arm_boot(void)
{
#ifndef CONFIG_ARCH_ROMPGTABLE
/* __start provided the basic MMU mappings for OCMC0 RAM. Now provide mappings
* for all IO regions (Including the vector region).
/* __start provided the basic MMU mappings for OCMC0 RAM. Now provide
* mappings for all IO regions (Including the vector region).
*/
am335x_setupmappings();
/* Provide a special mapping for the OCMC0 RAM interrupt vector positioned in
* high memory.
/* Provide a special mapping for the OCMC0 RAM interrupt vector positioned
* in high memory.
*/
am335x_vectormapping();
@ -431,10 +434,10 @@ void arm_boot(void)
#endif
#ifdef CONFIG_BOOT_SDRAM_DATA
/* This setting is inappropriate for the AM335x because the code is *always*
* executing from SDRAM. If CONFIG_BOOT_SDRAM_DATA happens to be set,
* let's try to do the right thing and initialize the .data and .bss
* sections.
/* This setting is inappropriate for the AM335x because the code is
* *always* executing from SDRAM. If CONFIG_BOOT_SDRAM_DATA happens
* to be set, let's try to do the right thing and initialize the
* .data and .bss sections.
*/
arm_data_initialize();

56
arch/arm/src/am335x/am335x_can.c
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@ -103,10 +103,10 @@
struct up_dev_s
{
uint8_t port; /* CAN port number */
uint8_t port; /* CAN port number */
uint32_t baud; /* Configured baud */
uint32_t base; /* CAN register base address */
uint8_t irq; /* IRQ associated with this CAN */
uint8_t irq; /* IRQ associated with this CAN */
};
/****************************************************************************
@ -474,9 +474,9 @@ static void can_shutdown(FAR struct can_dev_s *dev)
*
* Description:
* Call to enable or disable RX interrupts.
* This function is called two times: from can_open and can_close. Therefore
* this function enables and disables not only RX interrupts but all message
* objects.
* This function is called two times: from can_open and can_close.
* Therefore this function enables and disables not only RX interrupts
* but all message objects.
*
* Input Parameters:
* dev - An instance of the "upper half" can driver state structure.
@ -627,8 +627,9 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
can_putreg(priv, AM335X_DCAN_IF1MSK_OFFSET, 0xffff);
regval = ((dlc & DCAN_IFMCTL_DLC_MASK) | DCAN_IFMCTL_EOB | DCAN_IFMCTL_TX_RQST
| DCAN_IFMCTL_TX_IE);
regval = ((dlc & DCAN_IFMCTL_DLC_MASK) |
DCAN_IFMCTL_EOB | DCAN_IFMCTL_TX_RQST |
DCAN_IFMCTL_TX_IE);
can_putreg(priv, AM335X_DCAN_IF1MCTL_OFFSET, regval);
/* Write data to IF1 data registers */
@ -642,18 +643,24 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
can_putreg(priv, AM335X_DCAN_IF1DATB_OFFSET, regval);
#ifdef CONFIG_CAN_EXTID
can_putreg(priv, AM335X_DCAN_IF1ARB_OFFSET, DCAN_IFARB_DIR | DCAN_IFARB_MSG_VAL
| DCAN_IFARB_XTD | (id << DCAN_IFARB_ID_SHIFT));
can_putreg(priv,
AM335X_DCAN_IF1ARB_OFFSET,
DCAN_IFARB_DIR | DCAN_IFARB_MSG_VAL |
DCAN_IFARB_XTD | (id << DCAN_IFARB_ID_SHIFT));
#else
can_putreg(priv, AM335X_DCAN_IF1ARB_OFFSET, DCAN_IFARB_DIR | DCAN_IFARB_MSG_VAL
| (id << DCAN_IFARB_ID_SHIFT));
can_putreg(priv,
AM335X_DCAN_IF1ARB_OFFSET,
DCAN_IFARB_DIR | DCAN_IFARB_MSG_VAL |
(id << DCAN_IFARB_ID_SHIFT));
#endif
/* Write to Message RAM */
regval = (DCAN_IFCMD_WR_RD | DCAN_IFCMD_MASK | DCAN_IFCMD_ARB | DCAN_IFCMD_CTL
| DCAN_IFCMD_CLR_INTPND | DCAN_IFCMD_TX_RQST_NEWDAT
| DCAN_IFCMD_DATAA | DCAN_IFCMD_DATAB | DCAN_IFCMD_MSG_NUM(txobj));
regval = (DCAN_IFCMD_WR_RD | DCAN_IFCMD_MASK |
DCAN_IFCMD_ARB | DCAN_IFCMD_CTL |
DCAN_IFCMD_CLR_INTPND | DCAN_IFCMD_TX_RQST_NEWDAT |
DCAN_IFCMD_DATAA | DCAN_IFCMD_DATAB |
DCAN_IFCMD_MSG_NUM(txobj));
can_putreg(priv, AM335X_DCAN_IF1CMD_OFFSET, regval);
#ifdef CONFIG_CAN_TXREADY
@ -748,7 +755,8 @@ static int can_interrupt(int irq, FAR void *context, FAR void *arg)
/* Read CAN interrupt register */
uint32_t interrupt = can_getreg(priv, AM335X_DCAN_INT_OFFSET) & DCAN_INT_LINE0_MASK;
uint32_t interrupt = can_getreg(priv, AM335X_DCAN_INT_OFFSET) &
DCAN_INT_LINE0_MASK;
/* Read CAN status register */
@ -869,7 +877,8 @@ static void can_readobj(struct up_dev_s *priv, uint32_t index)
{
while (can_getreg(priv, AM335X_DCAN_IF2CMD_OFFSET) & DCAN_IFCMD_BUSY);
can_putreg(priv, AM335X_DCAN_IF2CMD_OFFSET, DCAN_IFCMD_MASK | DCAN_IFCMD_ARB |
can_putreg(priv, AM335X_DCAN_IF2CMD_OFFSET,
DCAN_IFCMD_MASK | DCAN_IFCMD_ARB |
DCAN_IFCMD_CTL | DCAN_IFCMD_CLR_INTPND | DCAN_IFCMD_DATAA |
DCAN_IFCMD_DATAB | DCAN_IFCMD_MSG_NUM(index));
}
@ -922,12 +931,14 @@ static void can_setuprxobj(struct up_dev_s *priv)
while (can_getreg(priv, AM335X_DCAN_IF2CMD_OFFSET) & DCAN_IFCMD_BUSY);
can_putreg(priv, AM335X_DCAN_IF2MSK_OFFSET, DCAN_IFMSK_MXTD | DCAN_IFMSK_MDIR);
can_putreg(priv, AM335X_DCAN_IF2MSK_OFFSET,
DCAN_IFMSK_MXTD | DCAN_IFMSK_MDIR);
can_putreg(priv, AM335X_DCAN_IF2MCTL_OFFSET, DCAN_IFMCTL_DLC_MASK |
DCAN_IFMCTL_EOB | DCAN_IFMCTL_RX_IE | DCAN_IFMCTL_UMASK);
#ifdef CONFIG_CAN_EXTID
can_putreg(priv, AM335X_DCAN_IF2ARB_OFFSET, DCAN_IFARB_MSG_VAL | DCAN_IFARB_XTD);
can_putreg(priv, AM335X_DCAN_IF2ARB_OFFSET,
DCAN_IFARB_MSG_VAL | DCAN_IFARB_XTD);
#else
can_putreg(priv, AM335X_DCAN_IF2ARB_OFFSET, DCAN_IFARB_MSG_VAL);
#endif
@ -935,9 +946,12 @@ static void can_setuprxobj(struct up_dev_s *priv)
for (i = CAN_RX_OBJ_FIRST; i <= CAN_RX_OBJ_LAST; ++i)
{
while (can_getreg(priv, AM335X_DCAN_IF2CMD_OFFSET) & DCAN_IFCMD_BUSY);
can_putreg(priv, AM335X_DCAN_IF2CMD_OFFSET, DCAN_IFCMD_WR_RD | DCAN_IFCMD_MASK |
DCAN_IFCMD_ARB | DCAN_IFCMD_CTL | DCAN_IFCMD_CLR_INTPND |
DCAN_IFCMD_DATAA | DCAN_IFCMD_DATAB | DCAN_IFCMD_MSG_NUM(i));
can_putreg(priv, AM335X_DCAN_IF2CMD_OFFSET,
DCAN_IFCMD_WR_RD | DCAN_IFCMD_MASK |
DCAN_IFCMD_ARB | DCAN_IFCMD_CTL |
DCAN_IFCMD_CLR_INTPND |
DCAN_IFCMD_DATAA | DCAN_IFCMD_DATAB |
DCAN_IFCMD_MSG_NUM(i));
}
}

3
arch/arm/src/am335x/am335x_clockconfig.c
View File

@ -547,7 +547,8 @@ static void am335x_peripheral_enable(void)
{
}
while ((getreg32(AM335X_CM_PER_OCPWP_L3_CLKSTCTRL) & per_ocpwp_l3) != per_ocpwp_l3)
while ((getreg32(AM335X_CM_PER_OCPWP_L3_CLKSTCTRL) & per_ocpwp_l3) !=
per_ocpwp_l3)
{
}

1
arch/arm/src/am335x/am335x_irq.c
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@ -116,6 +116,7 @@ void up_irqinitialize(void)
for (i = 0; i < AM335X_IRQ_NINT; i += 32)
{
putreg32(0xffffffff, AM335X_INTC_MIR_SET(i)); /* 1 masks corresponding interrupt */
getreg32(AM335X_INTC_PEND_IRQ(i)); /* Reading status clears pending interrupts */
getreg32(AM335X_INTC_PEND_FIQ(i)); /* Reading status clears pending interrupts */
}

26
arch/arm/src/am335x/am335x_lowputc.c
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@ -37,9 +37,9 @@
#include "am335x_pinmux.h"
#include "hardware/am335x_uart.h"
/**************************************************************************
/****************************************************************************
* Pre-processor Definitions
**************************************************************************/
****************************************************************************/
/* Select UART parameters for the selected console */
@ -133,8 +133,8 @@
#define AM335X_SCLK 48000000
/* The output baud rate is equal to the serial clock (SCLK) frequency divided
* by sixteen times the value of the baud rate divisor, as follows:
/* The output baud rate is equal to the serial clock (SCLK) frequency
* divided by sixteen times the value of the baud rate divisor, as follows:
*
* baud rate = Fsclk / (16 * divisor).
*/
@ -158,14 +158,16 @@ void arm_lowputc(char ch)
#if defined(HAVE_UART_DEVICE) && defined(HAVE_SERIAL_CONSOLE)
/* Wait for the transmitter to be available */
while ((getreg32(CONSOLE_BASE + AM335X_UART_LSR_OFFSET) & UART_LSR_THRE) == 0)
while ((getreg32(CONSOLE_BASE + AM335X_UART_LSR_OFFSET) &
UART_LSR_THRE) == 0)
{
}
/* Send the character */
putreg32((uint32_t)ch, CONSOLE_BASE + AM335X_UART_THR_OFFSET);
while ((getreg32(CONSOLE_BASE + AM335X_UART_LSR_OFFSET) & UART_LSR_THRE) == 0)
while ((getreg32(CONSOLE_BASE + AM335X_UART_LSR_OFFSET) &
UART_LSR_THRE) == 0)
{
}
#endif
@ -219,12 +221,14 @@ void am335x_lowsetup(void)
#if 0
/* Performing Software Reset of the module. */
putreg32(UART_SYSC_SRESET | getreg32(CONSOLE_BASE + AM335X_UART_SYSC_OFFSET),
putreg32(UART_SYSC_SRESET | getreg32(CONSOLE_BASE +
AM335X_UART_SYSC_OFFSET),
CONSOLE_BASE + AM335X_UART_SYSC_OFFSET);
/* Wait until the process of Module Reset is complete. */
while (!(getreg32(CONSOLE_BASE + AM335X_UART_SYSS_OFFSET) & UART_SYSS_RESET_DONE))
while (!(getreg32(CONSOLE_BASE + AM335X_UART_SYSS_OFFSET) &
UART_SYSS_RESET_DONE))
{
}
#endif
@ -261,8 +265,10 @@ void am335x_lowsetup(void)
/* Set the BAUD divisor */
putreg32((CONSOLE_DL >> 8) & UART_DLH_MASK, CONSOLE_BASE + AM335X_UART_DLH_OFFSET);
putreg32(CONSOLE_DL & UART_DLL_MASK, CONSOLE_BASE + AM335X_UART_DLL_OFFSET);
putreg32((CONSOLE_DL >> 8) & UART_DLH_MASK,
CONSOLE_BASE + AM335X_UART_DLH_OFFSET);
putreg32(CONSOLE_DL & UART_DLL_MASK,
CONSOLE_BASE + AM335X_UART_DLL_OFFSET);
/* Clear DLAB */

10
arch/arm/src/am335x/am335x_pinmux.h
View File

@ -30,6 +30,12 @@
#include "hardware/am335x_scm.h"
#include "hardware/am335x_pinmux.h"
#ifndef __ASSEMBLY__
#include <stdint.h>
#endif /* __ASSEMBLY__ */
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@ -93,9 +99,7 @@
#ifndef __ASSEMBLY__
#include <stdint.h>
/* The smallest integer type that can hold the PINMUX encoding */
/* The smallest integer type that can hold the PINMUX encoding */
typedef uint8_t pinmux_pinset_t;

8
arch/arm/src/efm32/efm32_pwm.h
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@ -35,10 +35,6 @@
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* Timer devices may be used for different purposes. One special purpose is
@ -71,6 +67,10 @@
#include <arch/board/board.h>
#include "hardware/efm32_timer.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* For each timer that is enabled for PWM usage, we need the following
* additional configuration settings:
*

2
arch/arm/src/kl/kl_cfmconfig.c
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@ -22,7 +22,7 @@
****************************************************************************/
/****************************************************************************
* Included files
* Included Files
****************************************************************************/
#include <stdint.h>