Fix nuttx coding style
Remove TABs Fix indentation Fix Multi-line comments Fix Comments to the Right of Statements.
This commit is contained in:
simbit18
Xiang Xiao
parent
d8797bde4e
commit
b0965ab963
@ -147,29 +147,29 @@ typedef struct
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uint32_t control; /* Transfer control */
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} dmac_lli_t;
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#define CXD56_DMAC_M2M 0 /**< Memory to memory */
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#define CXD56_DMAC_M2P 1 /**< Memory to peripheral, DMAC controlled */
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#define CXD56_DMAC_P2M 2 /**< Peripheral to memory, DMAC controlled */
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#define CXD56_DMAC_P2P 3 /**< Peripheral to peripheral */
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#define CXD56_DMAC_P2CP 4 /**< P2P destination controlled */
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#define CXD56_DMAC_M2CP 5 /**< M2P peripheral controlled */
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#define CXD56_DMAC_CP2M 6 /**< P2M peripheral controlled */
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#define CXD56_DMAC_CP2P 7 /**< P2P source controlled */
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#define CXD56_DMAC_M2M 0 /* Memory to memory */
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#define CXD56_DMAC_M2P 1 /* Memory to peripheral, DMAC controlled */
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#define CXD56_DMAC_P2M 2 /* Peripheral to memory, DMAC controlled */
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#define CXD56_DMAC_P2P 3 /* Peripheral to peripheral */
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#define CXD56_DMAC_P2CP 4 /* P2P destination controlled */
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#define CXD56_DMAC_M2CP 5 /* M2P peripheral controlled */
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#define CXD56_DMAC_CP2M 6 /* P2M peripheral controlled */
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#define CXD56_DMAC_CP2P 7 /* P2P source controlled */
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#define CXD56_DMAC_BSIZE1 0 /**< 1 burst */
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#define CXD56_DMAC_BSIZE4 1 /**< 4 burst */
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#define CXD56_DMAC_BSIZE8 2 /**< 8 burst */
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#define CXD56_DMAC_BSIZE16 3 /**< 16 burst */
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#define CXD56_DMAC_BSIZE32 4 /**< 32 burst */
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#define CXD56_DMAC_BSIZE64 5 /**< 64 burst */
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#define CXD56_DMAC_BSIZE128 6 /**< 128 burst */
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#define CXD56_DMAC_BSIZE256 7 /**< 256 burst */
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#define CXD56_DMAC_BSIZE1 0 /* 1 burst */
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#define CXD56_DMAC_BSIZE4 1 /* 4 burst */
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#define CXD56_DMAC_BSIZE8 2 /* 8 burst */
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#define CXD56_DMAC_BSIZE16 3 /* 16 burst */
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#define CXD56_DMAC_BSIZE32 4 /* 32 burst */
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#define CXD56_DMAC_BSIZE64 5 /* 64 burst */
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#define CXD56_DMAC_BSIZE128 6 /* 128 burst */
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#define CXD56_DMAC_BSIZE256 7 /* 256 burst */
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#define CXD56_DMAC_LITTLE_ENDIAN 0 /**< Little endian */
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#define CXD56_DMAC_BIG_ENDIAN 1 /**< Bit endian */
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#define CXD56_DMAC_LITTLE_ENDIAN 0 /* Little endian */
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#define CXD56_DMAC_BIG_ENDIAN 1 /* Bit endian */
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#define CXD56_DMAC_MASTER1 0 /**< AHB master 1 */
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#define CXD56_DMAC_MASTER2 1 /**< AHB master 2 */
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#define CXD56_DMAC_MASTER1 0 /* AHB master 1 */
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#define CXD56_DMAC_MASTER2 1 /* AHB master 2 */
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/* max transfer size at a time */
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@ -41,12 +41,12 @@
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#define CXD56_DMA_PERIPHERAL_SPI5_TX (4)
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#define CXD56_DMA_PERIPHERAL_SPI5_RX (5)
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#define CXD56_DMA_INTR_ITC (1u<<0) /**< Terminal count interrupt status */
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#define CXD56_DMA_INTR_ERR (1u<<1) /**< Error interrupt status */
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#define CXD56_DMA_INTR_ITC (1u<<0) /* Terminal count interrupt status */
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#define CXD56_DMA_INTR_ERR (1u<<1) /* Error interrupt status */
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#define CXD56_DMAC_WIDTH8 0 /**< 8 bit width */
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#define CXD56_DMAC_WIDTH16 1 /**< 16 bit width */
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#define CXD56_DMAC_WIDTH32 2 /**< 32 bit width */
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#define CXD56_DMAC_WIDTH8 0 /* 8 bit width */
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#define CXD56_DMAC_WIDTH16 1 /* 16 bit width */
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#define CXD56_DMAC_WIDTH32 2 /* 32 bit width */
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/****************************************************************************
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* Public Types
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@ -92,115 +92,115 @@
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/* Bit fields for RMU CTRL */
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#define _RMU_CTRL_RESETVALUE 0x00000002UL /**< Default value for RMU_CTRL */
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#define _RMU_CTRL_MASK 0x00000003UL /**< Mask for RMU_CTRL */
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#define _RMU_CTRL_RESETVALUE 0x00000002UL /* Default value for RMU_CTRL */
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#define _RMU_CTRL_MASK 0x00000003UL /* Mask for RMU_CTRL */
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#define RMU_CTRL_LOCKUPRDIS (0x1UL << 0) /**< Lockup Reset Disable */
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#define _RMU_CTRL_LOCKUPRDIS_SHIFT 0 /**< Shift value for RMU_LOCKUPRDIS */
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#define _RMU_CTRL_LOCKUPRDIS_MASK 0x1UL /**< Bit mask for RMU_LOCKUPRDIS */
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#define _RMU_CTRL_LOCKUPRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */
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#define RMU_CTRL_LOCKUPRDIS_DEFAULT (_RMU_CTRL_LOCKUPRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CTRL */
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#define RMU_CTRL_BURSTEN (0x1UL << 1) /**< Backup domain reset enable */
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#define _RMU_CTRL_BURSTEN_SHIFT 1 /**< Shift value for RMU_BURSTEN */
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#define _RMU_CTRL_BURSTEN_MASK 0x2UL /**< Bit mask for RMU_BURSTEN */
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#define _RMU_CTRL_BURSTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for RMU_CTRL */
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#define RMU_CTRL_BURSTEN_DEFAULT (_RMU_CTRL_BURSTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for RMU_CTRL */
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#define RMU_CTRL_LOCKUPRDIS (0x1UL << 0) /* Lockup Reset Disable */
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#define _RMU_CTRL_LOCKUPRDIS_SHIFT 0 /* Shift value for RMU_LOCKUPRDIS */
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#define _RMU_CTRL_LOCKUPRDIS_MASK 0x1UL /* Bit mask for RMU_LOCKUPRDIS */
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#define _RMU_CTRL_LOCKUPRDIS_DEFAULT 0x00000000UL /* Mode DEFAULT for RMU_CTRL */
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#define RMU_CTRL_LOCKUPRDIS_DEFAULT (_RMU_CTRL_LOCKUPRDIS_DEFAULT << 0) /* Shifted mode DEFAULT for RMU_CTRL */
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#define RMU_CTRL_BURSTEN (0x1UL << 1) /* Backup domain reset enable */
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#define _RMU_CTRL_BURSTEN_SHIFT 1 /* Shift value for RMU_BURSTEN */
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#define _RMU_CTRL_BURSTEN_MASK 0x2UL /* Bit mask for RMU_BURSTEN */
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#define _RMU_CTRL_BURSTEN_DEFAULT 0x00000001UL /* Mode DEFAULT for RMU_CTRL */
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#define RMU_CTRL_BURSTEN_DEFAULT (_RMU_CTRL_BURSTEN_DEFAULT << 1) /* Shifted mode DEFAULT for RMU_CTRL */
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/* Bit fields for RMU RSTCAUSE */
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#define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */
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#define _RMU_RSTCAUSE_MASK 0x0000FFFFUL /**< Mask for RMU_RSTCAUSE */
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#define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /* Default value for RMU_RSTCAUSE */
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#define _RMU_RSTCAUSE_MASK 0x0000FFFFUL /* Mask for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power On Reset */
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#define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */
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#define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */
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#define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BODUNREGRST (0x1UL << 1) /**< Brown Out Detector Unregulated Domain Reset */
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#define _RMU_RSTCAUSE_BODUNREGRST_SHIFT 1 /**< Shift value for RMU_BODUNREGRST */
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#define _RMU_RSTCAUSE_BODUNREGRST_MASK 0x2UL /**< Bit mask for RMU_BODUNREGRST */
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#define _RMU_RSTCAUSE_BODUNREGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BODUNREGRST_DEFAULT (_RMU_RSTCAUSE_BODUNREGRST_DEFAULT << 1) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BODREGRST (0x1UL << 2) /**< Brown Out Detector Regulated Domain Reset */
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#define _RMU_RSTCAUSE_BODREGRST_SHIFT 2 /**< Shift value for RMU_BODREGRST */
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#define _RMU_RSTCAUSE_BODREGRST_MASK 0x4UL /**< Bit mask for RMU_BODREGRST */
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#define _RMU_RSTCAUSE_BODREGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BODREGRST_DEFAULT (_RMU_RSTCAUSE_BODREGRST_DEFAULT << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_EXTRST (0x1UL << 3) /**< External Pin Reset */
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#define _RMU_RSTCAUSE_EXTRST_SHIFT 3 /**< Shift value for RMU_EXTRST */
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#define _RMU_RSTCAUSE_EXTRST_MASK 0x8UL /**< Bit mask for RMU_EXTRST */
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#define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_WDOGRST (0x1UL << 4) /**< Watchdog Reset */
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#define _RMU_RSTCAUSE_WDOGRST_SHIFT 4 /**< Shift value for RMU_WDOGRST */
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#define _RMU_RSTCAUSE_WDOGRST_MASK 0x10UL /**< Bit mask for RMU_WDOGRST */
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#define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 5) /**< LOCKUP Reset */
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#define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 5 /**< Shift value for RMU_LOCKUPRST */
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#define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x20UL /**< Bit mask for RMU_LOCKUPRST */
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#define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 5) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_SYSREQRST (0x1UL << 6) /**< System Request Reset */
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#define _RMU_RSTCAUSE_SYSREQRST_SHIFT 6 /**< Shift value for RMU_SYSREQRST */
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#define _RMU_RSTCAUSE_SYSREQRST_MASK 0x40UL /**< Bit mask for RMU_SYSREQRST */
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#define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 6) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_EM4RST (0x1UL << 7) /**< EM4 Reset */
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#define _RMU_RSTCAUSE_EM4RST_SHIFT 7 /**< Shift value for RMU_EM4RST */
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#define _RMU_RSTCAUSE_EM4RST_MASK 0x80UL /**< Bit mask for RMU_EM4RST */
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#define _RMU_RSTCAUSE_EM4RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_EM4RST_DEFAULT (_RMU_RSTCAUSE_EM4RST_DEFAULT << 7) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_EM4WURST (0x1UL << 8) /**< EM4 Wake-up Reset */
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#define _RMU_RSTCAUSE_EM4WURST_SHIFT 8 /**< Shift value for RMU_EM4WURST */
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#define _RMU_RSTCAUSE_EM4WURST_MASK 0x100UL /**< Bit mask for RMU_EM4WURST */
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#define _RMU_RSTCAUSE_EM4WURST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_EM4WURST_DEFAULT (_RMU_RSTCAUSE_EM4WURST_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BODAVDD0 (0x1UL << 9) /**< AVDD0 Bod Reset */
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#define _RMU_RSTCAUSE_BODAVDD0_SHIFT 9 /**< Shift value for RMU_BODAVDD0 */
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#define _RMU_RSTCAUSE_BODAVDD0_MASK 0x200UL /**< Bit mask for RMU_BODAVDD0 */
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#define _RMU_RSTCAUSE_BODAVDD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BODAVDD0_DEFAULT (_RMU_RSTCAUSE_BODAVDD0_DEFAULT << 9) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BODAVDD1 (0x1UL << 10) /**< AVDD1 Bod Reset */
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#define _RMU_RSTCAUSE_BODAVDD1_SHIFT 10 /**< Shift value for RMU_BODAVDD1 */
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#define _RMU_RSTCAUSE_BODAVDD1_MASK 0x400UL /**< Bit mask for RMU_BODAVDD1 */
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#define _RMU_RSTCAUSE_BODAVDD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BODAVDD1_DEFAULT (_RMU_RSTCAUSE_BODAVDD1_DEFAULT << 10) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BUBODVDDDREG (0x1UL << 11) /**< Backup Brown Out Detector, VDD_DREG */
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#define _RMU_RSTCAUSE_BUBODVDDDREG_SHIFT 11 /**< Shift value for RMU_BUBODVDDDREG */
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#define _RMU_RSTCAUSE_BUBODVDDDREG_MASK 0x800UL /**< Bit mask for RMU_BUBODVDDDREG */
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#define _RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT (_RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT << 11) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BUBODBUVIN (0x1UL << 12) /**< Backup Brown Out Detector, BU_VIN */
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#define _RMU_RSTCAUSE_BUBODBUVIN_SHIFT 12 /**< Shift value for RMU_BUBODBUVIN */
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#define _RMU_RSTCAUSE_BUBODBUVIN_MASK 0x1000UL /**< Bit mask for RMU_BUBODBUVIN */
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#define _RMU_RSTCAUSE_BUBODBUVIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BUBODBUVIN_DEFAULT (_RMU_RSTCAUSE_BUBODBUVIN_DEFAULT << 12) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BUBODUNREG (0x1UL << 13) /**< Backup Brown Out Detector Unregulated Domain */
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#define _RMU_RSTCAUSE_BUBODUNREG_SHIFT 13 /**< Shift value for RMU_BUBODUNREG */
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#define _RMU_RSTCAUSE_BUBODUNREG_MASK 0x2000UL /**< Bit mask for RMU_BUBODUNREG */
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#define _RMU_RSTCAUSE_BUBODUNREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BUBODUNREG_DEFAULT (_RMU_RSTCAUSE_BUBODUNREG_DEFAULT << 13) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BUBODREG (0x1UL << 14) /**< Backup Brown Out Detector Regulated Domain */
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#define _RMU_RSTCAUSE_BUBODREG_SHIFT 14 /**< Shift value for RMU_BUBODREG */
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#define _RMU_RSTCAUSE_BUBODREG_MASK 0x4000UL /**< Bit mask for RMU_BUBODREG */
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#define _RMU_RSTCAUSE_BUBODREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BUBODREG_DEFAULT (_RMU_RSTCAUSE_BUBODREG_DEFAULT << 14) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BUMODERST (0x1UL << 15) /**< Backup mode reset */
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#define _RMU_RSTCAUSE_BUMODERST_SHIFT 15 /**< Shift value for RMU_BUMODERST */
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#define _RMU_RSTCAUSE_BUMODERST_MASK 0x8000UL /**< Bit mask for RMU_BUMODERST */
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#define _RMU_RSTCAUSE_BUMODERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BUMODERST_DEFAULT (_RMU_RSTCAUSE_BUMODERST_DEFAULT << 15) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_PORST (0x1UL << 0) /* Power On Reset */
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#define _RMU_RSTCAUSE_PORST_SHIFT 0 /* Shift value for RMU_PORST */
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#define _RMU_RSTCAUSE_PORST_MASK 0x1UL /* Bit mask for RMU_PORST */
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#define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /* Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BODUNREGRST (0x1UL << 1) /* Brown Out Detector Unregulated Domain Reset */
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#define _RMU_RSTCAUSE_BODUNREGRST_SHIFT 1 /* Shift value for RMU_BODUNREGRST */
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#define _RMU_RSTCAUSE_BODUNREGRST_MASK 0x2UL /* Bit mask for RMU_BODUNREGRST */
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#define _RMU_RSTCAUSE_BODUNREGRST_DEFAULT 0x00000000UL /* Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BODUNREGRST_DEFAULT (_RMU_RSTCAUSE_BODUNREGRST_DEFAULT << 1) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BODREGRST (0x1UL << 2) /* Brown Out Detector Regulated Domain Reset */
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#define _RMU_RSTCAUSE_BODREGRST_SHIFT 2 /* Shift value for RMU_BODREGRST */
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#define _RMU_RSTCAUSE_BODREGRST_MASK 0x4UL /* Bit mask for RMU_BODREGRST */
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#define _RMU_RSTCAUSE_BODREGRST_DEFAULT 0x00000000UL /* Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BODREGRST_DEFAULT (_RMU_RSTCAUSE_BODREGRST_DEFAULT << 2) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_EXTRST (0x1UL << 3) /* External Pin Reset */
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#define _RMU_RSTCAUSE_EXTRST_SHIFT 3 /* Shift value for RMU_EXTRST */
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#define _RMU_RSTCAUSE_EXTRST_MASK 0x8UL /* Bit mask for RMU_EXTRST */
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#define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /* Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 3) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_WDOGRST (0x1UL << 4) /* Watchdog Reset */
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#define _RMU_RSTCAUSE_WDOGRST_SHIFT 4 /* Shift value for RMU_WDOGRST */
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#define _RMU_RSTCAUSE_WDOGRST_MASK 0x10UL /* Bit mask for RMU_WDOGRST */
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#define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /* Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 4) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 5) /* LOCKUP Reset */
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#define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 5 /* Shift value for RMU_LOCKUPRST */
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#define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x20UL /* Bit mask for RMU_LOCKUPRST */
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#define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /* Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 5) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_SYSREQRST (0x1UL << 6) /* System Request Reset */
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#define _RMU_RSTCAUSE_SYSREQRST_SHIFT 6 /* Shift value for RMU_SYSREQRST */
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#define _RMU_RSTCAUSE_SYSREQRST_MASK 0x40UL /* Bit mask for RMU_SYSREQRST */
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#define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /* Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 6) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_EM4RST (0x1UL << 7) /* EM4 Reset */
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#define _RMU_RSTCAUSE_EM4RST_SHIFT 7 /* Shift value for RMU_EM4RST */
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#define _RMU_RSTCAUSE_EM4RST_MASK 0x80UL /* Bit mask for RMU_EM4RST */
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#define _RMU_RSTCAUSE_EM4RST_DEFAULT 0x00000000UL /* Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_EM4RST_DEFAULT (_RMU_RSTCAUSE_EM4RST_DEFAULT << 7) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_EM4WURST (0x1UL << 8) /* EM4 Wake-up Reset */
|
||||
#define _RMU_RSTCAUSE_EM4WURST_SHIFT 8 /* Shift value for RMU_EM4WURST */
|
||||
#define _RMU_RSTCAUSE_EM4WURST_MASK 0x100UL /* Bit mask for RMU_EM4WURST */
|
||||
#define _RMU_RSTCAUSE_EM4WURST_DEFAULT 0x00000000UL /* Mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_EM4WURST_DEFAULT (_RMU_RSTCAUSE_EM4WURST_DEFAULT << 8) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_BODAVDD0 (0x1UL << 9) /* AVDD0 Bod Reset */
|
||||
#define _RMU_RSTCAUSE_BODAVDD0_SHIFT 9 /* Shift value for RMU_BODAVDD0 */
|
||||
#define _RMU_RSTCAUSE_BODAVDD0_MASK 0x200UL /* Bit mask for RMU_BODAVDD0 */
|
||||
#define _RMU_RSTCAUSE_BODAVDD0_DEFAULT 0x00000000UL /* Mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_BODAVDD0_DEFAULT (_RMU_RSTCAUSE_BODAVDD0_DEFAULT << 9) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_BODAVDD1 (0x1UL << 10) /* AVDD1 Bod Reset */
|
||||
#define _RMU_RSTCAUSE_BODAVDD1_SHIFT 10 /* Shift value for RMU_BODAVDD1 */
|
||||
#define _RMU_RSTCAUSE_BODAVDD1_MASK 0x400UL /* Bit mask for RMU_BODAVDD1 */
|
||||
#define _RMU_RSTCAUSE_BODAVDD1_DEFAULT 0x00000000UL /* Mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_BODAVDD1_DEFAULT (_RMU_RSTCAUSE_BODAVDD1_DEFAULT << 10) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_BUBODVDDDREG (0x1UL << 11) /* Backup Brown Out Detector, VDD_DREG */
|
||||
#define _RMU_RSTCAUSE_BUBODVDDDREG_SHIFT 11 /* Shift value for RMU_BUBODVDDDREG */
|
||||
#define _RMU_RSTCAUSE_BUBODVDDDREG_MASK 0x800UL /* Bit mask for RMU_BUBODVDDDREG */
|
||||
#define _RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT 0x00000000UL /* Mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT (_RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT << 11) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_BUBODBUVIN (0x1UL << 12) /* Backup Brown Out Detector, BU_VIN */
|
||||
#define _RMU_RSTCAUSE_BUBODBUVIN_SHIFT 12 /* Shift value for RMU_BUBODBUVIN */
|
||||
#define _RMU_RSTCAUSE_BUBODBUVIN_MASK 0x1000UL /* Bit mask for RMU_BUBODBUVIN */
|
||||
#define _RMU_RSTCAUSE_BUBODBUVIN_DEFAULT 0x00000000UL /* Mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_BUBODBUVIN_DEFAULT (_RMU_RSTCAUSE_BUBODBUVIN_DEFAULT << 12) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_BUBODUNREG (0x1UL << 13) /* Backup Brown Out Detector Unregulated Domain */
|
||||
#define _RMU_RSTCAUSE_BUBODUNREG_SHIFT 13 /* Shift value for RMU_BUBODUNREG */
|
||||
#define _RMU_RSTCAUSE_BUBODUNREG_MASK 0x2000UL /* Bit mask for RMU_BUBODUNREG */
|
||||
#define _RMU_RSTCAUSE_BUBODUNREG_DEFAULT 0x00000000UL /* Mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_BUBODUNREG_DEFAULT (_RMU_RSTCAUSE_BUBODUNREG_DEFAULT << 13) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_BUBODREG (0x1UL << 14) /* Backup Brown Out Detector Regulated Domain */
|
||||
#define _RMU_RSTCAUSE_BUBODREG_SHIFT 14 /* Shift value for RMU_BUBODREG */
|
||||
#define _RMU_RSTCAUSE_BUBODREG_MASK 0x4000UL /* Bit mask for RMU_BUBODREG */
|
||||
#define _RMU_RSTCAUSE_BUBODREG_DEFAULT 0x00000000UL /* Mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_BUBODREG_DEFAULT (_RMU_RSTCAUSE_BUBODREG_DEFAULT << 14) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_BUMODERST (0x1UL << 15) /* Backup mode reset */
|
||||
#define _RMU_RSTCAUSE_BUMODERST_SHIFT 15 /* Shift value for RMU_BUMODERST */
|
||||
#define _RMU_RSTCAUSE_BUMODERST_MASK 0x8000UL /* Bit mask for RMU_BUMODERST */
|
||||
#define _RMU_RSTCAUSE_BUMODERST_DEFAULT 0x00000000UL /* Mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_BUMODERST_DEFAULT (_RMU_RSTCAUSE_BUMODERST_DEFAULT << 15) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
|
||||
|
||||
/* Bit fields for RMU CMD */
|
||||
|
||||
#define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */
|
||||
#define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */
|
||||
#define _RMU_CMD_RESETVALUE 0x00000000UL /* Default value for RMU_CMD */
|
||||
#define _RMU_CMD_MASK 0x00000001UL /* Mask for RMU_CMD */
|
||||
|
||||
#define RMU_CMD_RCCLR (0x1UL << 0) /**< Reset Cause Clear */
|
||||
#define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */
|
||||
#define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */
|
||||
#define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */
|
||||
#define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */
|
||||
#define RMU_CMD_RCCLR (0x1UL << 0) /* Reset Cause Clear */
|
||||
#define _RMU_CMD_RCCLR_SHIFT 0 /* Shift value for RMU_RCCLR */
|
||||
#define _RMU_CMD_RCCLR_MASK 0x1UL /* Bit mask for RMU_RCCLR */
|
||||
#define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /* Mode DEFAULT for RMU_CMD */
|
||||
#define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /* Shifted mode DEFAULT for RMU_CMD */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_EFM32_HARDWARE_EFM32_RMU_H */
|
||||
|
||||
@ -43,14 +43,14 @@ extern "C"
|
||||
* Pre-processor Macros
|
||||
****************************************************************************/
|
||||
|
||||
#define ESP32C3_ERR_MPI_FILE_IO_ERROR -0x0002 /**< An error occurred while reading from or writing to a file. */
|
||||
#define ESP32C3_ERR_MPI_BAD_INPUT_DATA -0x0004 /**< Bad input parameters to function. */
|
||||
#define ESP32C3_ERR_MPI_INVALID_CHARACTER -0x0006 /**< There is an invalid character in the digit string. */
|
||||
#define ESP32C3_ERR_MPI_BUFFER_TOO_SMALL -0x0008 /**< The buffer is too small to write to. */
|
||||
#define ESP32C3_ERR_MPI_NEGATIVE_VALUE -0x000A /**< The input arguments are negative or result in illegal output. */
|
||||
#define ESP32C3_ERR_MPI_DIVISION_BY_ZERO -0x000C /**< The input argument for division is zero, which is not allowed. */
|
||||
#define ESP32C3_ERR_MPI_NOT_ACCEPTABLE -0x000E /**< The input arguments are not acceptable. */
|
||||
#define ESP32C3_ERR_MPI_ALLOC_FAILED -0x0010 /**< Memory allocation failed. */
|
||||
#define ESP32C3_ERR_MPI_FILE_IO_ERROR -0x0002 /* An error occurred while reading from or writing to a file. */
|
||||
#define ESP32C3_ERR_MPI_BAD_INPUT_DATA -0x0004 /* Bad input parameters to function. */
|
||||
#define ESP32C3_ERR_MPI_INVALID_CHARACTER -0x0006 /* There is an invalid character in the digit string. */
|
||||
#define ESP32C3_ERR_MPI_BUFFER_TOO_SMALL -0x0008 /* The buffer is too small to write to. */
|
||||
#define ESP32C3_ERR_MPI_NEGATIVE_VALUE -0x000A /* The input arguments are negative or result in illegal output. */
|
||||
#define ESP32C3_ERR_MPI_DIVISION_BY_ZERO -0x000C /* The input argument for division is zero, which is not allowed. */
|
||||
#define ESP32C3_ERR_MPI_NOT_ACCEPTABLE -0x000E /* The input arguments are not acceptable. */
|
||||
#define ESP32C3_ERR_MPI_ALLOC_FAILED -0x0010 /* Memory allocation failed. */
|
||||
|
||||
#define ESP32C3_MPI_CHK(f, a) \
|
||||
do \
|
||||
@ -72,7 +72,7 @@ extern "C"
|
||||
/* Maximum size of MPIs allowed in bits and bytes for user-MPIs. */
|
||||
#define ESP32C3_MPI_MAX_SIZE 1024
|
||||
|
||||
/**< Maximum number of bits for usable MPIs. */
|
||||
/* Maximum number of bits for usable MPIs. */
|
||||
#define ESP32C3_MPI_MAX_BITS (8 * ESP32C3_MPI_MAX_SIZE)
|
||||
|
||||
/****************************************************************************
|
||||
|
||||
@ -46,37 +46,37 @@ extern "C"
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */
|
||||
EFUSE_BLK0 = 0, /* Number of eFuse BLOCK0. REPEAT_DATA */
|
||||
|
||||
EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */
|
||||
EFUSE_BLK1 = 1, /* Number of eFuse BLOCK1. MAC_SPI_8M_SYS */
|
||||
|
||||
EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
|
||||
EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
|
||||
EFUSE_BLK2 = 2, /* Number of eFuse BLOCK2. SYS_DATA_PART1 */
|
||||
EFUSE_BLK_SYS_DATA_PART1 = 2, /* Number of eFuse BLOCK2. SYS_DATA_PART1 */
|
||||
|
||||
EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA */
|
||||
EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA */
|
||||
EFUSE_BLK3 = 3, /* Number of eFuse BLOCK3. USER_DATA */
|
||||
EFUSE_BLK_USER_DATA = 3, /* Number of eFuse BLOCK3. USER_DATA */
|
||||
|
||||
EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */
|
||||
EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */
|
||||
EFUSE_BLK4 = 4, /* Number of eFuse BLOCK4. KEY0 */
|
||||
EFUSE_BLK_KEY0 = 4, /* Number of eFuse BLOCK4. KEY0 */
|
||||
|
||||
EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */
|
||||
EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */
|
||||
EFUSE_BLK5 = 5, /* Number of eFuse BLOCK5. KEY1 */
|
||||
EFUSE_BLK_KEY1 = 5, /* Number of eFuse BLOCK5. KEY1 */
|
||||
|
||||
EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */
|
||||
EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */
|
||||
EFUSE_BLK6 = 6, /* Number of eFuse BLOCK6. KEY2 */
|
||||
EFUSE_BLK_KEY2 = 6, /* Number of eFuse BLOCK6. KEY2 */
|
||||
|
||||
EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */
|
||||
EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */
|
||||
EFUSE_BLK7 = 7, /* Number of eFuse BLOCK7. KEY3 */
|
||||
EFUSE_BLK_KEY3 = 7, /* Number of eFuse BLOCK7. KEY3 */
|
||||
|
||||
EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */
|
||||
EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */
|
||||
EFUSE_BLK8 = 8, /* Number of eFuse BLOCK8. KEY4 */
|
||||
EFUSE_BLK_KEY4 = 8, /* Number of eFuse BLOCK8. KEY4 */
|
||||
|
||||
EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */
|
||||
EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */
|
||||
EFUSE_BLK9 = 9, /* Number of eFuse BLOCK9. KEY5 */
|
||||
EFUSE_BLK_KEY5 = 9, /* Number of eFuse BLOCK9. KEY5 */
|
||||
EFUSE_BLK_KEY_MAX = 10,
|
||||
|
||||
EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
|
||||
EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
|
||||
EFUSE_BLK10 = 10, /* Number of eFuse BLOCK10. SYS_DATA_PART2 */
|
||||
EFUSE_BLK_SYS_DATA_PART2 = 10, /* Number of eFuse BLOCK10. SYS_DATA_PART2 */
|
||||
|
||||
EFUSE_BLK_MAX
|
||||
} esp_efuse_block_t;
|
||||
|
||||
@ -46,26 +46,26 @@ extern "C"
|
||||
|
||||
/* RSA Error codes */
|
||||
|
||||
#define ESP32C3_ERR_RSA_BAD_INPUT_DATA -0x4080 /**< Bad input parameters to function. */
|
||||
#define ESP32C3_ERR_RSA_INVALID_PADDING -0x4100 /**< Input data contains invalid padding and is rejected. */
|
||||
#define ESP32C3_ERR_RSA_KEY_GEN_FAILED -0x4180 /**< Something failed during generation of a key. */
|
||||
#define ESP32C3_ERR_RSA_KEY_CHECK_FAILED -0x4200 /**< Key failed to pass the validity check of the library. */
|
||||
#define ESP32C3_ERR_RSA_PUBLIC_FAILED -0x4280 /**< The public key operation failed. */
|
||||
#define ESP32C3_ERR_RSA_PRIVATE_FAILED -0x4300 /**< The private key operation failed. */
|
||||
#define ESP32C3_ERR_RSA_VERIFY_FAILED -0x4380 /**< The PKCS#1 verification failed. */
|
||||
#define ESP32C3_ERR_RSA_OUTPUT_TOO_LARGE -0x4400 /**< The output buffer for decryption is not large enough. */
|
||||
#define ESP32C3_ERR_RSA_RNG_FAILED -0x4480 /**< The random generator failed to generate non-zeros. */
|
||||
#define ESP32C3_ERR_RSA_BAD_INPUT_DATA -0x4080 /* Bad input parameters to function. */
|
||||
#define ESP32C3_ERR_RSA_INVALID_PADDING -0x4100 /* Input data contains invalid padding and is rejected. */
|
||||
#define ESP32C3_ERR_RSA_KEY_GEN_FAILED -0x4180 /* Something failed during generation of a key. */
|
||||
#define ESP32C3_ERR_RSA_KEY_CHECK_FAILED -0x4200 /* Key failed to pass the validity check of the library. */
|
||||
#define ESP32C3_ERR_RSA_PUBLIC_FAILED -0x4280 /* The public key operation failed. */
|
||||
#define ESP32C3_ERR_RSA_PRIVATE_FAILED -0x4300 /* The private key operation failed. */
|
||||
#define ESP32C3_ERR_RSA_VERIFY_FAILED -0x4380 /* The PKCS#1 verification failed. */
|
||||
#define ESP32C3_ERR_RSA_OUTPUT_TOO_LARGE -0x4400 /* The output buffer for decryption is not large enough. */
|
||||
#define ESP32C3_ERR_RSA_RNG_FAILED -0x4480 /* The random generator failed to generate non-zeros. */
|
||||
|
||||
/* RSA constants */
|
||||
|
||||
#define ESP32C3_RSA_PUBLIC 0 /**< Request private key operation. */
|
||||
#define ESP32C3_RSA_PRIVATE 1 /**< Request public key operation. */
|
||||
#define ESP32C3_RSA_PUBLIC 0 /* Request private key operation. */
|
||||
#define ESP32C3_RSA_PRIVATE 1 /* Request public key operation. */
|
||||
|
||||
#define ESP32C3_RSA_PKCS_V15 0 /**< Use PKCS#1 v1.5 encoding. */
|
||||
#define ESP32C3_RSA_PKCS_V21 1 /**< Use PKCS#1 v2.1 encoding. */
|
||||
#define ESP32C3_RSA_PKCS_V15 0 /* Use PKCS#1 v1.5 encoding. */
|
||||
#define ESP32C3_RSA_PKCS_V21 1 /* Use PKCS#1 v2.1 encoding. */
|
||||
|
||||
#define ESP32C3_RSA_SIGN 1 /**< Identifier for RSA signature operations. */
|
||||
#define ESP32C3_RSA_CRYPT 2 /**< Identifier for RSA encryption and decryption operations. */
|
||||
#define ESP32C3_RSA_SIGN 1 /* Identifier for RSA signature operations. */
|
||||
#define ESP32C3_RSA_CRYPT 2 /* Identifier for RSA encryption and decryption operations. */
|
||||
|
||||
#define ESP32C3_RSA_SALT_LEN_ANY -1
|
||||
|
||||
|
||||
@ -31,7 +31,7 @@
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/* @brief Parity */
|
||||
/* Parity */
|
||||
|
||||
typedef enum parity
|
||||
{
|
||||
@ -42,7 +42,7 @@ typedef enum parity
|
||||
parity_always_0,
|
||||
} parity_setting_t;
|
||||
|
||||
/* @brief Stop bits */
|
||||
/* Stop bits */
|
||||
|
||||
typedef enum num_of_stop_bits
|
||||
{
|
||||
@ -51,7 +51,7 @@ typedef enum num_of_stop_bits
|
||||
stop_bits_2,
|
||||
} num_of_stop_bits_t;
|
||||
|
||||
/* @brief Word length */
|
||||
/* Word length */
|
||||
|
||||
typedef enum word_length
|
||||
{
|
||||
@ -61,7 +61,7 @@ typedef enum word_length
|
||||
word_length_8_bits,
|
||||
} word_length_t;
|
||||
|
||||
/* @brief UART fifo trigger levels */
|
||||
/* UART fifo trigger levels */
|
||||
|
||||
typedef enum uart_fifo_trg_lvl
|
||||
{
|
||||
@ -76,14 +76,14 @@ typedef enum uart_fifo_trg_lvl
|
||||
uart_tx_fifo_trg_lt_one_quarter = 3,
|
||||
} uart_fifo_trg_lvl_t;
|
||||
|
||||
/* @brief UART signals */
|
||||
/* UART signals */
|
||||
|
||||
typedef enum uart_signal
|
||||
{
|
||||
uart_signal_rts = UART_MCR_RTS_MASK,
|
||||
} uart_signal_t;
|
||||
|
||||
/* @brief UART signal levels */
|
||||
/* UART signal levels */
|
||||
|
||||
typedef enum uart_signal_level
|
||||
{
|
||||
@ -91,7 +91,7 @@ typedef enum uart_signal_level
|
||||
uart_signal_level_low,
|
||||
} uart_signal_level_t;
|
||||
|
||||
/* @brief UART modem status */
|
||||
/* UART modem status */
|
||||
|
||||
typedef enum uart_modem_stat
|
||||
{
|
||||
@ -99,7 +99,7 @@ typedef enum uart_modem_stat
|
||||
uart_modem_stat_dcts_changed = UART_MSR_DCTS_MASK,
|
||||
} uart_modem_stat_t;
|
||||
|
||||
/* @brief UART interrupt enable masks */
|
||||
/* UART interrupt enable masks */
|
||||
|
||||
typedef enum uart_intr_enable
|
||||
{
|
||||
@ -112,7 +112,7 @@ typedef enum uart_intr_enable
|
||||
#endif
|
||||
} uart_intr_enable_t;
|
||||
|
||||
/* @brief UART interrupt IDs */
|
||||
/* UART interrupt IDs */
|
||||
|
||||
typedef enum uart_intr_id
|
||||
{
|
||||
@ -123,7 +123,7 @@ typedef enum uart_intr_id
|
||||
uart_intr_id_rx_timeout = 0xc,
|
||||
} uart_intr_id_t;
|
||||
|
||||
/* @brief UART status */
|
||||
/* UART status */
|
||||
|
||||
typedef enum uart_stat
|
||||
{
|
||||
@ -137,55 +137,49 @@ typedef enum uart_stat
|
||||
uart_stat_rx_fifo_error = UART_LSR_ERRF_MASK,
|
||||
} uart_stat_t;
|
||||
|
||||
/**
|
||||
* @brief UART modem config
|
||||
*/
|
||||
/* UART modem config */
|
||||
|
||||
typedef struct uart_modem_config
|
||||
{
|
||||
bool auto_flow_ctrl_en; /**< Auto flow control enable flag */
|
||||
bool loop_back_en; /**< Loop back enable flag */
|
||||
bool set_rts_high; /**< Set signal RTS level high flag */
|
||||
bool auto_flow_ctrl_en; /* Auto flow control enable flag */
|
||||
bool loop_back_en; /* Loop back enable flag */
|
||||
bool set_rts_high; /* Set signal RTS level high flag */
|
||||
} uart_modem_config_t;
|
||||
|
||||
#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1)
|
||||
/**
|
||||
* @brief UART RX Line Idle detection conditions
|
||||
*/
|
||||
/* UART RX Line Idle detection conditions */
|
||||
|
||||
typedef enum hpm_uart_rxline_idle_cond
|
||||
{
|
||||
uart_rxline_idle_cond_rxline_logic_one = 0, /**< Treat as idle if the RX Line high duration exceeds threshold */
|
||||
uart_rxline_idle_cond_state_machine_idle = 1 /**< Treat as idle if the RX state machine idle state duration exceeds threshold */
|
||||
uart_rxline_idle_cond_rxline_logic_one = 0, /* Treat as idle if the RX Line high duration exceeds threshold */
|
||||
uart_rxline_idle_cond_state_machine_idle = 1 /* Treat as idle if the RX state machine idle state duration exceeds threshold */
|
||||
} uart_rxline_idle_cond_t;
|
||||
|
||||
typedef struct hpm_uart_rxline_idle_detect_config
|
||||
{
|
||||
bool detect_enable; /**< RX Line Idle detection flag */
|
||||
bool detect_irq_enable; /**< Enable RX Line Idle detection interrupt */
|
||||
uart_rxline_idle_cond_t idle_cond; /**< RX Line Idle detection condition */
|
||||
uint8_t threshold; /**< UART RX Line Idle detection threshold, in terms of bits */
|
||||
bool detect_enable; /* RX Line Idle detection flag */
|
||||
bool detect_irq_enable; /* Enable RX Line Idle detection interrupt */
|
||||
uart_rxline_idle_cond_t idle_cond; /* RX Line Idle detection condition */
|
||||
uint8_t threshold; /* UART RX Line Idle detection threshold, in terms of bits */
|
||||
} uart_rxline_idle_config_t;
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief UART config
|
||||
*/
|
||||
/* UART config */
|
||||
|
||||
typedef struct hpm_uart_config
|
||||
{
|
||||
uint32_t src_freq_in_hz; /**< Source clock frequency in Hz */
|
||||
uint32_t baudrate; /**< Baudrate */
|
||||
uint8_t num_of_stop_bits; /**< Number of stop bits */
|
||||
uint8_t word_length; /**< Word length */
|
||||
uint8_t parity; /**< Parity */
|
||||
uint8_t tx_fifo_level; /**< TX Fifo level */
|
||||
uint8_t rx_fifo_level; /**< RX Fifo level */
|
||||
bool dma_enable; /**< DMA Enable flag */
|
||||
bool fifo_enable; /**< Fifo Enable flag */
|
||||
uart_modem_config_t modem_config; /**< Modem config */
|
||||
uint32_t src_freq_in_hz; /* Source clock frequency in Hz */
|
||||
uint32_t baudrate; /* Baudrate */
|
||||
uint8_t num_of_stop_bits; /* Number of stop bits */
|
||||
uint8_t word_length; /* Word length */
|
||||
uint8_t parity; /* Parity */
|
||||
uint8_t tx_fifo_level; /* TX Fifo level */
|
||||
uint8_t rx_fifo_level; /* RX Fifo level */
|
||||
bool dma_enable; /* DMA Enable flag */
|
||||
bool fifo_enable; /* Fifo Enable flag */
|
||||
uart_modem_config_t modem_config; /* Modem config */
|
||||
#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1)
|
||||
uart_rxline_idle_config_t rxidle_config; /**< RX Idle configuration */
|
||||
uart_rxline_idle_config_t rxidle_config; /* RX Idle configuration */
|
||||
#endif
|
||||
} uart_config_t;
|
||||
|
||||
|
||||
@ -46,37 +46,37 @@ extern "C"
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */
|
||||
EFUSE_BLK0 = 0, /* Number of eFuse BLOCK0. REPEAT_DATA */
|
||||
|
||||
EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */
|
||||
EFUSE_BLK1 = 1, /* Number of eFuse BLOCK1. MAC_SPI_8M_SYS */
|
||||
|
||||
EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
|
||||
EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
|
||||
EFUSE_BLK2 = 2, /* Number of eFuse BLOCK2. SYS_DATA_PART1 */
|
||||
EFUSE_BLK_SYS_DATA_PART1 = 2, /* Number of eFuse BLOCK2. SYS_DATA_PART1 */
|
||||
|
||||
EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA */
|
||||
EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA */
|
||||
EFUSE_BLK3 = 3, /* Number of eFuse BLOCK3. USER_DATA */
|
||||
EFUSE_BLK_USER_DATA = 3, /* Number of eFuse BLOCK3. USER_DATA */
|
||||
|
||||
EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */
|
||||
EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */
|
||||
EFUSE_BLK4 = 4, /* Number of eFuse BLOCK4. KEY0 */
|
||||
EFUSE_BLK_KEY0 = 4, /* Number of eFuse BLOCK4. KEY0 */
|
||||
|
||||
EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */
|
||||
EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */
|
||||
EFUSE_BLK5 = 5, /* Number of eFuse BLOCK5. KEY1 */
|
||||
EFUSE_BLK_KEY1 = 5, /* Number of eFuse BLOCK5. KEY1 */
|
||||
|
||||
EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */
|
||||
EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */
|
||||
EFUSE_BLK6 = 6, /* Number of eFuse BLOCK6. KEY2 */
|
||||
EFUSE_BLK_KEY2 = 6, /* Number of eFuse BLOCK6. KEY2 */
|
||||
|
||||
EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */
|
||||
EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */
|
||||
EFUSE_BLK7 = 7, /* Number of eFuse BLOCK7. KEY3 */
|
||||
EFUSE_BLK_KEY3 = 7, /* Number of eFuse BLOCK7. KEY3 */
|
||||
|
||||
EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */
|
||||
EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */
|
||||
EFUSE_BLK8 = 8, /* Number of eFuse BLOCK8. KEY4 */
|
||||
EFUSE_BLK_KEY4 = 8, /* Number of eFuse BLOCK8. KEY4 */
|
||||
|
||||
EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */
|
||||
EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */
|
||||
EFUSE_BLK9 = 9, /* Number of eFuse BLOCK9. KEY5 */
|
||||
EFUSE_BLK_KEY5 = 9, /* Number of eFuse BLOCK9. KEY5 */
|
||||
EFUSE_BLK_KEY_MAX = 10,
|
||||
|
||||
EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
|
||||
EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
|
||||
EFUSE_BLK10 = 10, /* Number of eFuse BLOCK10. SYS_DATA_PART2 */
|
||||
EFUSE_BLK_SYS_DATA_PART2 = 10, /* Number of eFuse BLOCK10. SYS_DATA_PART2 */
|
||||
|
||||
EFUSE_BLK_MAX
|
||||
} esp_efuse_block_t;
|
||||
|
||||
@ -46,37 +46,37 @@ extern "C"
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */
|
||||
EFUSE_BLK0 = 0, /* Number of eFuse BLOCK0. REPEAT_DATA */
|
||||
|
||||
EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */
|
||||
EFUSE_BLK1 = 1, /* Number of eFuse BLOCK1. MAC_SPI_8M_SYS */
|
||||
|
||||
EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
|
||||
EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
|
||||
EFUSE_BLK2 = 2, /* Number of eFuse BLOCK2. SYS_DATA_PART1 */
|
||||
EFUSE_BLK_SYS_DATA_PART1 = 2, /* Number of eFuse BLOCK2. SYS_DATA_PART1 */
|
||||
|
||||
EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA */
|
||||
EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA */
|
||||
EFUSE_BLK3 = 3, /* Number of eFuse BLOCK3. USER_DATA */
|
||||
EFUSE_BLK_USER_DATA = 3, /* Number of eFuse BLOCK3. USER_DATA */
|
||||
|
||||
EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */
|
||||
EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */
|
||||
EFUSE_BLK4 = 4, /* Number of eFuse BLOCK4. KEY0 */
|
||||
EFUSE_BLK_KEY0 = 4, /* Number of eFuse BLOCK4. KEY0 */
|
||||
|
||||
EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */
|
||||
EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */
|
||||
EFUSE_BLK5 = 5, /* Number of eFuse BLOCK5. KEY1 */
|
||||
EFUSE_BLK_KEY1 = 5, /* Number of eFuse BLOCK5. KEY1 */
|
||||
|
||||
EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */
|
||||
EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */
|
||||
EFUSE_BLK6 = 6, /* Number of eFuse BLOCK6. KEY2 */
|
||||
EFUSE_BLK_KEY2 = 6, /* Number of eFuse BLOCK6. KEY2 */
|
||||
|
||||
EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */
|
||||
EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */
|
||||
EFUSE_BLK7 = 7, /* Number of eFuse BLOCK7. KEY3 */
|
||||
EFUSE_BLK_KEY3 = 7, /* Number of eFuse BLOCK7. KEY3 */
|
||||
|
||||
EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */
|
||||
EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */
|
||||
EFUSE_BLK8 = 8, /* Number of eFuse BLOCK8. KEY4 */
|
||||
EFUSE_BLK_KEY4 = 8, /* Number of eFuse BLOCK8. KEY4 */
|
||||
|
||||
EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */
|
||||
EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */
|
||||
EFUSE_BLK9 = 9, /* Number of eFuse BLOCK9. KEY5 */
|
||||
EFUSE_BLK_KEY5 = 9, /* Number of eFuse BLOCK9. KEY5 */
|
||||
EFUSE_BLK_KEY_MAX = 10,
|
||||
|
||||
EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
|
||||
EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
|
||||
EFUSE_BLK10 = 10, /* Number of eFuse BLOCK10. SYS_DATA_PART2 */
|
||||
EFUSE_BLK_SYS_DATA_PART2 = 10, /* Number of eFuse BLOCK10. SYS_DATA_PART2 */
|
||||
|
||||
EFUSE_BLK_MAX
|
||||
} esp_efuse_block_t;
|
||||
|
||||
@ -448,7 +448,7 @@
|
||||
#define ETS_WMAC_INUM 0
|
||||
#define ETS_BT_HOST_INUM 1
|
||||
#define ETS_WBB_INUM 4
|
||||
#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
|
||||
#define ETS_TG0_T1_INUM 10 /* use edge interrupt*/
|
||||
#define ETS_FRC1_INUM 22
|
||||
#define ETS_T1_WDT_INUM 24
|
||||
#define ETS_CACHEERR_INUM 25
|
||||
|
||||
@ -51,20 +51,20 @@ extern "C"
|
||||
* Pin floating, pull up, pull down definitions
|
||||
*/
|
||||
|
||||
#define PIN_FLOAT (0) /**< Floating */
|
||||
#define PIN_PULLUP (1) /**< Internal Weak Pull Up */
|
||||
#define PIN_PULLDOWN (2) /**< Internal Weak Pull Down */
|
||||
#define PIN_BUSKEEPER (3) /**< Internal Bus-Keeper */
|
||||
#define PIN_FLOAT (0) /* Floating */
|
||||
#define PIN_PULLUP (1) /* Internal Weak Pull Up */
|
||||
#define PIN_PULLDOWN (2) /* Internal Weak Pull Down */
|
||||
#define PIN_BUSKEEPER (3) /* Internal Bus-Keeper */
|
||||
|
||||
/* GPIO Interrupt Setting
|
||||
* GPIO interrupt level and edge trigger types
|
||||
*/
|
||||
|
||||
#define INT_HIGH_LEVEL (2) /**< High Level */
|
||||
#define INT_LOW_LEVEL (3) /**< Low Level */
|
||||
#define INT_RISING_EDGE (4) /**< Rising Edge */
|
||||
#define INT_FALLING_EDGE (5) /**< Falling Edge */
|
||||
#define INT_BOTH_EDGE (7) /**< Both Edge */
|
||||
#define INT_HIGH_LEVEL (2) /* High Level */
|
||||
#define INT_LOW_LEVEL (3) /* Low Level */
|
||||
#define INT_RISING_EDGE (4) /* Rising Edge */
|
||||
#define INT_FALLING_EDGE (5) /* Falling Edge */
|
||||
#define INT_BOTH_EDGE (7) /* Both Edge */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
|
||||
@ -188,23 +188,23 @@
|
||||
#endif
|
||||
|
||||
#if CONFIG_SPIFI_LIBRARY
|
||||
# define SPIFI_DEVICE_ALL 0 /**< Enables all devices in family */
|
||||
# define SPIFI_DEVICE_S25FL016K 0 /**< Enables Spansion S25FL016K device */
|
||||
# define SPIFI_DEVICE_S25FL032P 0 /**< Enables Spansion S25FL032P device */
|
||||
# define SPIFI_DEVICE_S25FL064P 0 /**< Enables Spansion S25FL064P device */
|
||||
# define SPIFI_DEVICE_S25FL129P_64K 0 /**< Enables Spansion S25FL129P (64K block) device */
|
||||
# define SPIFI_DEVICE_S25FL129P_256K 0 /**< Enables Spansion S25FL129P (256K block) device */
|
||||
# define SPIFI_DEVICE_S25FL164K 0 /**< Enables Spansion S25FL164K device */
|
||||
# define SPIFI_DEVICE_S25FL256S_64K 0 /**< Enables Spansion S25FL256S (64K block) device */
|
||||
# define SPIFI_DEVICE_S25FL256S_256K 0 /**< Enables Spansion S25FL256S (256K block) device */
|
||||
# define SPIFI_DEVICE_S25FL512S 0 /**< Enables Spansion S25FL512S device */
|
||||
# define SPIFI_DEVICE_MX25L1635E 0 /**< Enables Macronix MX25L1635E device */
|
||||
# define SPIFI_DEVICE_MX25L3235E 0 /**< Enables Macronix MX25L3235E device */
|
||||
# define SPIFI_DEVICE_MX25L8035E 0 /**< Enables Macronix MX25L8035E device */
|
||||
# define SPIFI_DEVICE_MX25L6435E 0 /**< Enables Macronix MX25L6435E device */
|
||||
# define SPIFI_DEVICE_W25Q32FV 0 /**< Enables Winbond W25Q32FV device */
|
||||
# define SPIFI_DEVICE_W25Q64FV 0 /**< Enables Winbond W25Q32V device */
|
||||
# define SPIFI_DEVICE_W25Q80BV 1 /**< Enables Winbond W25Q80BV device */
|
||||
# define SPIFI_DEVICE_ALL 0 /* Enables all devices in family */
|
||||
# define SPIFI_DEVICE_S25FL016K 0 /* Enables Spansion S25FL016K device */
|
||||
# define SPIFI_DEVICE_S25FL032P 0 /* Enables Spansion S25FL032P device */
|
||||
# define SPIFI_DEVICE_S25FL064P 0 /* Enables Spansion S25FL064P device */
|
||||
# define SPIFI_DEVICE_S25FL129P_64K 0 /* Enables Spansion S25FL129P (64K block) device */
|
||||
# define SPIFI_DEVICE_S25FL129P_256K 0 /* Enables Spansion S25FL129P (256K block) device */
|
||||
# define SPIFI_DEVICE_S25FL164K 0 /* Enables Spansion S25FL164K device */
|
||||
# define SPIFI_DEVICE_S25FL256S_64K 0 /* Enables Spansion S25FL256S (64K block) device */
|
||||
# define SPIFI_DEVICE_S25FL256S_256K 0 /* Enables Spansion S25FL256S (256K block) device */
|
||||
# define SPIFI_DEVICE_S25FL512S 0 /* Enables Spansion S25FL512S device */
|
||||
# define SPIFI_DEVICE_MX25L1635E 0 /* Enables Macronix MX25L1635E device */
|
||||
# define SPIFI_DEVICE_MX25L3235E 0 /* Enables Macronix MX25L3235E device */
|
||||
# define SPIFI_DEVICE_MX25L8035E 0 /* Enables Macronix MX25L8035E device */
|
||||
# define SPIFI_DEVICE_MX25L6435E 0 /* Enables Macronix MX25L6435E device */
|
||||
# define SPIFI_DEVICE_W25Q32FV 0 /* Enables Winbond W25Q32FV device */
|
||||
# define SPIFI_DEVICE_W25Q64FV 0 /* Enables Winbond W25Q32V device */
|
||||
# define SPIFI_DEVICE_W25Q80BV 1 /* Enables Winbond W25Q80BV device */
|
||||
# define SPIFI_DEVICE_REQUENCY_DIVIDER 2 /* PLL1 clock divider */
|
||||
#endif
|
||||
|
||||
|
||||
@ -183,23 +183,23 @@
|
||||
#endif
|
||||
|
||||
#if CONFIG_SPIFI_LIBRARY
|
||||
# define SPIFI_DEVICE_ALL 0 /**< Enables all devices in family */
|
||||
# define SPIFI_DEVICE_S25FL016K 0 /**< Enables Spansion S25FL016K device */
|
||||
# define SPIFI_DEVICE_S25FL032P 0 /**< Enables Spansion S25FL032P device */
|
||||
# define SPIFI_DEVICE_S25FL064P 0 /**< Enables Spansion S25FL064P device */
|
||||
# define SPIFI_DEVICE_S25FL129P_64K 0 /**< Enables Spansion S25FL129P (64K block) device */
|
||||
# define SPIFI_DEVICE_S25FL129P_256K 0 /**< Enables Spansion S25FL129P (256K block) device */
|
||||
# define SPIFI_DEVICE_S25FL164K 0 /**< Enables Spansion S25FL164K device */
|
||||
# define SPIFI_DEVICE_S25FL256S_64K 0 /**< Enables Spansion S25FL256S (64K block) device */
|
||||
# define SPIFI_DEVICE_S25FL256S_256K 0 /**< Enables Spansion S25FL256S (256K block) device */
|
||||
# define SPIFI_DEVICE_S25FL512S 0 /**< Enables Spansion S25FL512S device */
|
||||
# define SPIFI_DEVICE_MX25L1635E 0 /**< Enables Macronix MX25L1635E device */
|
||||
# define SPIFI_DEVICE_MX25L3235E 0 /**< Enables Macronix MX25L3235E device */
|
||||
# define SPIFI_DEVICE_MX25L8035E 0 /**< Enables Macronix MX25L8035E device */
|
||||
# define SPIFI_DEVICE_MX25L6435E 0 /**< Enables Macronix MX25L6435E device */
|
||||
# define SPIFI_DEVICE_W25Q32FV 0 /**< Enables Winbond W25Q32FV device */
|
||||
# define SPIFI_DEVICE_W25Q64FV 0 /**< Enables Winbond W25Q32V device */
|
||||
# define SPIFI_DEVICE_W25Q80BV 1 /**< Enables Winbond W25Q80BV device */
|
||||
# define SPIFI_DEVICE_ALL 0 /* Enables all devices in family */
|
||||
# define SPIFI_DEVICE_S25FL016K 0 /* Enables Spansion S25FL016K device */
|
||||
# define SPIFI_DEVICE_S25FL032P 0 /* Enables Spansion S25FL032P device */
|
||||
# define SPIFI_DEVICE_S25FL064P 0 /* Enables Spansion S25FL064P device */
|
||||
# define SPIFI_DEVICE_S25FL129P_64K 0 /* Enables Spansion S25FL129P (64K block) device */
|
||||
# define SPIFI_DEVICE_S25FL129P_256K 0 /* Enables Spansion S25FL129P (256K block) device */
|
||||
# define SPIFI_DEVICE_S25FL164K 0 /* Enables Spansion S25FL164K device */
|
||||
# define SPIFI_DEVICE_S25FL256S_64K 0 /* Enables Spansion S25FL256S (64K block) device */
|
||||
# define SPIFI_DEVICE_S25FL256S_256K 0 /* Enables Spansion S25FL256S (256K block) device */
|
||||
# define SPIFI_DEVICE_S25FL512S 0 /* Enables Spansion S25FL512S device */
|
||||
# define SPIFI_DEVICE_MX25L1635E 0 /* Enables Macronix MX25L1635E device */
|
||||
# define SPIFI_DEVICE_MX25L3235E 0 /* Enables Macronix MX25L3235E device */
|
||||
# define SPIFI_DEVICE_MX25L8035E 0 /* Enables Macronix MX25L8035E device */
|
||||
# define SPIFI_DEVICE_MX25L6435E 0 /* Enables Macronix MX25L6435E device */
|
||||
# define SPIFI_DEVICE_W25Q32FV 0 /* Enables Winbond W25Q32FV device */
|
||||
# define SPIFI_DEVICE_W25Q64FV 0 /* Enables Winbond W25Q32V device */
|
||||
# define SPIFI_DEVICE_W25Q80BV 1 /* Enables Winbond W25Q80BV device */
|
||||
# define SPIFI_DEVICE_REQUENCY_DIVIDER 2 /* PLL1 clock divider */
|
||||
#endif
|
||||
|
||||
|
||||
@ -51,9 +51,9 @@
|
||||
#define ALTCOM_RX_PKT_SIZE_MAX (ALTCOM_PAYLOAD_SIZE_MAX_V4 \
|
||||
+ sizeof(struct altcom_cmdhdr_s))
|
||||
|
||||
#define LTE_RESULT_OK (0) /**< Result code on success */
|
||||
#define LTE_RESULT_ERROR (1) /**< Result code on failure */
|
||||
#define LTE_RESULT_CANCEL (2) /**< Result code on cancel */
|
||||
#define LTE_RESULT_OK (0) /* Result code on success */
|
||||
#define LTE_RESULT_ERROR (1) /* Result code on failure */
|
||||
#define LTE_RESULT_CANCEL (2) /* Result code on cancel */
|
||||
|
||||
#define ALTCOM_CMD_POWER_ON_REPLY_SIZE (1)
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user