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xtensa: Add initial support for ESP32-S3

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Co-authored-by: Alan Carvalho de Assis <alan.carvalho@espressif.com>
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
This commit is contained in:
Gustavo Henrique Nihei 2022-01-07 14:44:06 -03:00 committed by Alan Carvalho de Assis
parent f8ba016d72
commit b0d24f53c4
69 changed files with 45740 additions and 3 deletions
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39
arch/xtensa/Kconfig
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@ -70,6 +70,34 @@ config ARCH_CHIP_ESP32S2
Based on an Xtensa single-core 32-bit LX7 processor, it can be clocked
at up to 240 MHz.
config ARCH_CHIP_ESP32S3
bool "Espressif ESP32-S3"
select ARCH_FAMILY_LX7
select XTENSA_HAVE_INTERRUPTS
select ARCH_HAVE_MULTICPU
select ARCH_HAVE_TEXT_HEAP
select ARCH_HAVE_SDRAM
select ARCH_HAVE_RESET
select ARCH_HAVE_BOOTLOADER
select ARCH_VECNOTIRQ
select LIBC_ARCH_MEMCPY
select LIBC_ARCH_MEMCHR
select LIBC_ARCH_MEMCMP
select LIBC_ARCH_MEMMOVE
select LIBC_ARCH_MEMSET
select LIBC_ARCH_STRCHR
select LIBC_ARCH_STRCMP
select LIBC_ARCH_STRCPY
select LIBC_ARCH_STRLCPY
select LIBC_ARCH_STRNCPY
select LIBC_ARCH_STRLEN
select LIBC_ARCH_STRNLEN
---help---
ESP32-S3 is a dual-core Xtensa LX7 MCU, capable of running at 240 MHz.
Apart from its 512 KB of internal SRAM, it also comes with integrated 2.4 GHz,
802.11 b/g/n Wi-Fi and Bluetooth 5 (LE) connectivity that provides long-range
support.
config ARCH_CHIP_XTENSA_CUSTOM
bool "Custom XTENSA chip"
select ARCH_CHIP_CUSTOM
@ -145,8 +173,9 @@ config ARCH_FAMILY_LX7
config ARCH_CHIP
string
default "esp32" if ARCH_CHIP_ESP32
default "esp32s2" if ARCH_CHIP_ESP32S2
default "esp32" if ARCH_CHIP_ESP32
default "esp32s2" if ARCH_CHIP_ESP32S2
default "esp32s3" if ARCH_CHIP_ESP32S3
config XTENSA_CP_LAZY
bool "Lazy co-processor state restoration"
@ -267,13 +296,19 @@ config XTENSA_TOOLCHAIN_ESP
endchoice
source "arch/xtensa/src/lx6/Kconfig"
if ARCH_CHIP_ESP32
source "arch/xtensa/src/esp32/Kconfig"
endif
source "arch/xtensa/src/lx7/Kconfig"
if ARCH_CHIP_ESP32S2
source "arch/xtensa/src/esp32s2/Kconfig"
endif
if ARCH_CHIP_ESP32S3
source "arch/xtensa/src/esp32s3/Kconfig"
endif
endif # ARCH_XTENSA

66
arch/xtensa/include/esp32s3/chip.h Normal file
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@ -0,0 +1,66 @@
/****************************************************************************
* arch/xtensa/include/esp32s3/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_INCLUDE_ESP32S3_CHIP_H
#define __ARCH_XTENSA_INCLUDE_ESP32S3_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define ESP32S3_NGPIOS 45 /* GPIO0-44 */
/* Characterize each supported ESP32-S3 part */
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_INCLUDE_ESP32S3_CHIP_H */

695
arch/xtensa/include/esp32s3/core-isa.h Normal file
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@ -0,0 +1,695 @@
/****************************************************************************
* arch/xtensa/include/esp32s3/core-isa.h
* Xtensa processor core configuration information.
*
* Customer ID=15128; Build=0x90f1f; Copyright (c) 1999-2021 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_INCLUDE_ESP32S3_CORE_ISA_H
#define __ARCH_XTENSA_INCLUDE_ESP32S3_CORE_ISA_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Parameters Useful for Any Code, USER or PRIVILEGED
****************************************************************************/
/* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option
* is configured, and a value of 0 otherwise. These macros are always
* defined.
*/
/****************************************************************************
* ISA
****************************************************************************/
#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */
#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
#define XCHAL_MAX_INSTRUCTION_SIZE 4 /* max instr bytes (3..8) */
#define XCHAL_HAVE_DEBUG 1 /* debug option */
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
#define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
#define XCHAL_HAVE_L32R 1 /* L32R instruction */
#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
/* #define XCHAL_HAVE_POPC 0 */ /* POPC instruction */
/* #define XCHAL_HAVE_CRC 0 */ /* CRC instruction */
#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
#define XCHAL_NUM_CONTEXTS 1 /* */
#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
#define XCHAL_HAVE_PRID 1 /* processor ID register */
#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
#define XCHAL_HAVE_FUSION 0 /* Fusion*/
#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */
#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
#define XCHAL_HAVE_HIFI5 0 /* HiFi5 Audio Engine pkg */
#define XCHAL_HAVE_HIFI5_NN_MAC 0 /* HiFi5 Audio Engine NN-MAC option */
#define XCHAL_HAVE_HIFI5_VFPU 0 /* HiFi5 Audio Engine Single-Precision VFPU option */
#define XCHAL_HAVE_HIFI5_HP_VFPU 0 /* HiFi5 Audio Engine Half-Precision VFPU option */
#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */
#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */
#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
#define XCHAL_HAVE_HIFI_MINI 0
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
#define XCHAL_HAVE_USER_SPFPU 0 /* user SP floating-point pkg */
#define XCHAL_HAVE_FP 1 /* single prec floating point */
#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */
#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */
#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */
#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */
#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
#define XCHAL_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */
#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
#define XCHAL_HAVE_FUSIONG 0 /* FusionG */
#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */
#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */
#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */
#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */
#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */
#define XCHAL_HAVE_PDX 0 /* PDX */
#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */
#define XCHAL_HAVE_PDX4 0 /* PDX4 */
#define XCHAL_HAVE_PDX8 0 /* PDX8 */
#define XCHAL_HAVE_PDX16 0 /* PDX16 */
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 Dual LoadStore Flix */
#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 vector recip sqrt */
#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 vector divide */
#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 despread */
#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */
#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 transpose32x32 */
#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 viterbi */
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */
#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */
#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */
#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, or P3 */
#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */
#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */
#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6 */
#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6 */
#define XCHAL_HAVE_VISIONC 0 /* Vision C */
/****************************************************************************
* MISC
****************************************************************************/
#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */
#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
#define XCHAL_DATA_WIDTH 16 /* data width in bytes */
#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay (1 = 5-stage, 2 = 7-stage) */
#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
/* In T1050, applies to selected core load
* and store instructions (see ISA)
*/
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */
#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/
#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */
#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/
#define XCHAL_SW_VERSION 1200012 /* sw version of this header */
#define XCHAL_CORE_ID "LX7_ESP32_S3_MP" /* alphanum core name
* (CoreID) set in the Xtensa
* Processor Generator
*/
#define XCHAL_BUILD_UNIQUE_ID 0x00090F1F /* 22-bit sw build ID */
/* These definitions describe the hardware targeted by this software. */
#define XCHAL_HW_CONFIGID0 0xC2F0FFFE /* ConfigID hi 32 bits*/
#define XCHAL_HW_CONFIGID1 0x23090F1F /* ConfigID lo 32 bits*/
#define XCHAL_HW_VERSION_NAME "LX7.0.12" /* full version name */
#define XCHAL_HW_VERSION_MAJOR 2700 /* major ver# of targeted hw */
#define XCHAL_HW_VERSION_MINOR 12 /* minor ver# of targeted hw */
#define XCHAL_HW_VERSION 270012 /* major*100+minor */
#define XCHAL_HW_REL_LX7 1
#define XCHAL_HW_REL_LX7_0 1
#define XCHAL_HW_REL_LX7_0_12 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
/* If software targets a range of hardware versions, these are the bounds: */
#define XCHAL_HW_MIN_VERSION_MAJOR 2700 /* major v of earliest tgt hw */
#define XCHAL_HW_MIN_VERSION_MINOR 12 /* minor v of earliest tgt hw */
#define XCHAL_HW_MIN_VERSION 270012 /* earliest targeted hw */
#define XCHAL_HW_MAX_VERSION_MAJOR 2700 /* major v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION_MINOR 12 /* minor v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION 270012 /* latest targeted hw */
/****************************************************************************
* CACHE
****************************************************************************/
#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */
#define XCHAL_DCACHE_LINESIZE 16 /* D-cache line size in bytes */
#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */
#define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */
#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */
#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */
#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */
#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */
#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
/****************************************************************************
* Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
****************************************************************************/
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
/****************************************************************************
* CACHE
****************************************************************************/
#define XCHAL_HAVE_PIF 1 /* any outbound bus present */
#define XCHAL_HAVE_AXI 0 /* AXI bus */
#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */
#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */
#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */
#define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
/* Number of cache sets in log2(lines per way): */
#define XCHAL_ICACHE_SETWIDTH 0
#define XCHAL_DCACHE_SETWIDTH 0
/* Cache set associativity (number of ways): */
#define XCHAL_ICACHE_WAYS 1
#define XCHAL_DCACHE_WAYS 1
/* Cache features: */
#define XCHAL_ICACHE_LINE_LOCKABLE 0
#define XCHAL_DCACHE_LINE_LOCKABLE 0
#define XCHAL_ICACHE_ECC_PARITY 0
#define XCHAL_DCACHE_ECC_PARITY 0
#define XCHAL_ICACHE_ECC_WIDTH 1
#define XCHAL_DCACHE_ECC_WIDTH 1
/* Cache access size in bytes (affects operation of SICW instruction): */
#define XCHAL_ICACHE_ACCESS_SIZE 1
#define XCHAL_DCACHE_ACCESS_SIZE 1
#define XCHAL_DCACHE_BANKS 0 /* number of banks */
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits) */
#define XCHAL_CA_BITS 4
/****************************************************************************
* INTERNAL I/D RAM/ROMs and XLMI
****************************************************************************/
#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
/* Instruction RAM 0: */
#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */
#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */
#define XCHAL_INSTRAM0_SIZE 67108864 /* size in bytes */
#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_HAVE_INSTRAM0 1
#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */
/* Data RAM 0: */
#define XCHAL_DATARAM0_VADDR 0x3C000000 /* virtual address */
#define XCHAL_DATARAM0_PADDR 0x3C000000 /* physical address */
#define XCHAL_DATARAM0_SIZE 67108864 /* size in bytes */
#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
#define XCHAL_HAVE_DATARAM0 1
#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */
#define XCHAL_HAVE_IDMA 0
#define XCHAL_HAVE_IDMA_TRANSPOSE 0
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM */
/****************************************************************************
* INTERRUPTS and TIMERS
****************************************************************************/
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
#define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
* (not including level zero)
*/
#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
/* Masks of interrupts at each interrupt level: */
#define XCHAL_INTLEVEL1_MASK 0x000637FF
#define XCHAL_INTLEVEL2_MASK 0x00380000
#define XCHAL_INTLEVEL3_MASK 0x28C08800
#define XCHAL_INTLEVEL4_MASK 0x53000000
#define XCHAL_INTLEVEL5_MASK 0x84010000
#define XCHAL_INTLEVEL6_MASK 0x00000000
#define XCHAL_INTLEVEL7_MASK 0x00004000
/* Masks of interrupts at each range 1..n of interrupt levels: */
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000637FF
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x003E37FF
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFFF
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF
/* Level of each interrupt: */
#define XCHAL_INT0_LEVEL 1
#define XCHAL_INT1_LEVEL 1
#define XCHAL_INT2_LEVEL 1
#define XCHAL_INT3_LEVEL 1
#define XCHAL_INT4_LEVEL 1
#define XCHAL_INT5_LEVEL 1
#define XCHAL_INT6_LEVEL 1
#define XCHAL_INT7_LEVEL 1
#define XCHAL_INT8_LEVEL 1
#define XCHAL_INT9_LEVEL 1
#define XCHAL_INT10_LEVEL 1
#define XCHAL_INT11_LEVEL 3
#define XCHAL_INT12_LEVEL 1
#define XCHAL_INT13_LEVEL 1
#define XCHAL_INT14_LEVEL 7
#define XCHAL_INT15_LEVEL 3
#define XCHAL_INT16_LEVEL 5
#define XCHAL_INT17_LEVEL 1
#define XCHAL_INT18_LEVEL 1
#define XCHAL_INT19_LEVEL 2
#define XCHAL_INT20_LEVEL 2
#define XCHAL_INT21_LEVEL 2
#define XCHAL_INT22_LEVEL 3
#define XCHAL_INT23_LEVEL 3
#define XCHAL_INT24_LEVEL 4
#define XCHAL_INT25_LEVEL 4
#define XCHAL_INT26_LEVEL 5
#define XCHAL_INT27_LEVEL 3
#define XCHAL_INT28_LEVEL 4
#define XCHAL_INT29_LEVEL 3
#define XCHAL_INT30_LEVEL 4
#define XCHAL_INT31_LEVEL 5
#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
* EXCSAVE/EPS/EPC_n, RFI n)
*/
/* Type of each interrupt: */
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_PROFILING
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
#define XCHAL_INT15_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT16_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT29_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
/* Masks of interrupts for each type of interrupt: */
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x20000080
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x50400400
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x8FBE333F
#define XCHAL_INTTYPE_MASK_TIMER 0x00018040
#define XCHAL_INTTYPE_MASK_NMI 0x00004000
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
#define XCHAL_INTTYPE_MASK_PROFILING 0x00000800
#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000
#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000
#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000
/* Interrupt numbers assigned to specific interrupt sources: */
#define XTHAL_TIMER_UNCONFIGURED -1
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
#define XCHAL_TIMER1_INTERRUPT 15 /* CCOMPARE1 */
#define XCHAL_TIMER2_INTERRUPT 16 /* CCOMPARE2 */
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
#define XCHAL_PROFILING_INTERRUPT 11
/* Interrupt numbers for levels at which only one interrupt is configured: */
#define XCHAL_INTLEVEL7_NUM 14
/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */
/* External interrupt mapping.
* These macros describe how Xtensa processor interrupt numbers
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
* map to external BInterrupt<n> pins, for those interrupts
* configured as external (level-triggered, edge-triggered, or NMI).
* See the Xtensa processor databook for more details.
*/
/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
#define XCHAL_EXTINT6_NUM 8 /* (intlevel 1) */
#define XCHAL_EXTINT7_NUM 9 /* (intlevel 1) */
#define XCHAL_EXTINT8_NUM 10 /* (intlevel 1) */
#define XCHAL_EXTINT9_NUM 12 /* (intlevel 1) */
#define XCHAL_EXTINT10_NUM 13 /* (intlevel 1) */
#define XCHAL_EXTINT11_NUM 14 /* (intlevel 7) */
#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
#define XCHAL_EXTINT14_NUM 19 /* (intlevel 2) */
#define XCHAL_EXTINT15_NUM 20 /* (intlevel 2) */
#define XCHAL_EXTINT16_NUM 21 /* (intlevel 2) */
#define XCHAL_EXTINT17_NUM 22 /* (intlevel 3) */
#define XCHAL_EXTINT18_NUM 23 /* (intlevel 3) */
#define XCHAL_EXTINT19_NUM 24 /* (intlevel 4) */
#define XCHAL_EXTINT20_NUM 25 /* (intlevel 4) */
#define XCHAL_EXTINT21_NUM 26 /* (intlevel 5) */
#define XCHAL_EXTINT22_NUM 27 /* (intlevel 3) */
#define XCHAL_EXTINT23_NUM 28 /* (intlevel 4) */
#define XCHAL_EXTINT24_NUM 30 /* (intlevel 4) */
#define XCHAL_EXTINT25_NUM 31 /* (intlevel 5) */
/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
#define XCHAL_INT8_EXTNUM 6 /* (intlevel 1) */
#define XCHAL_INT9_EXTNUM 7 /* (intlevel 1) */
#define XCHAL_INT10_EXTNUM 8 /* (intlevel 1) */
#define XCHAL_INT12_EXTNUM 9 /* (intlevel 1) */
#define XCHAL_INT13_EXTNUM 10 /* (intlevel 1) */
#define XCHAL_INT14_EXTNUM 11 /* (intlevel 7) */
#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */
#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */
#define XCHAL_INT19_EXTNUM 14 /* (intlevel 2) */
#define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */
#define XCHAL_INT21_EXTNUM 16 /* (intlevel 2) */
#define XCHAL_INT22_EXTNUM 17 /* (intlevel 3) */
#define XCHAL_INT23_EXTNUM 18 /* (intlevel 3) */
#define XCHAL_INT24_EXTNUM 19 /* (intlevel 4) */
#define XCHAL_INT25_EXTNUM 20 /* (intlevel 4) */
#define XCHAL_INT26_EXTNUM 21 /* (intlevel 5) */
#define XCHAL_INT27_EXTNUM 22 /* (intlevel 3) */
#define XCHAL_INT28_EXTNUM 23 /* (intlevel 4) */
#define XCHAL_INT30_EXTNUM 24 /* (intlevel 4) */
#define XCHAL_INT31_EXTNUM 25 /* (intlevel 5) */
/****************************************************************************
* EXCEPTIONS and VECTORS
****************************************************************************/
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
* number: 1 == XEA1 (old)
* 2 == XEA2 (new)
* 0 == XEAX (extern) or TX
*/
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
#define XCHAL_HAVE_HALT 0 /* halt architecture option */
#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
#define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */
#define XCHAL_VECBASE_RESET_PADDR 0x40000000
#define XCHAL_RESET_VECBASE_OVERLAP 0
#define XCHAL_RESET_VECTOR0_VADDR 0x50000000
#define XCHAL_RESET_VECTOR0_PADDR 0x50000000
#define XCHAL_RESET_VECTOR1_VADDR 0x40000400
#define XCHAL_RESET_VECTOR1_PADDR 0x40000400
#define XCHAL_RESET_VECTOR_VADDR 0x40000400
#define XCHAL_RESET_VECTOR_PADDR 0x40000400
#define XCHAL_USER_VECOFS 0x00000340
#define XCHAL_USER_VECTOR_VADDR 0x40000340
#define XCHAL_USER_VECTOR_PADDR 0x40000340
#define XCHAL_KERNEL_VECOFS 0x00000300
#define XCHAL_KERNEL_VECTOR_VADDR 0x40000300
#define XCHAL_KERNEL_VECTOR_PADDR 0x40000300
#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000
#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000
#define XCHAL_INTLEVEL2_VECOFS 0x00000180
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180
#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0
#define XCHAL_INTLEVEL4_VECOFS 0x00000200
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200
#define XCHAL_INTLEVEL5_VECOFS 0x00000240
#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240
#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240
#define XCHAL_INTLEVEL6_VECOFS 0x00000280
#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280
#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
#define XCHAL_NMI_VECOFS 0x000002C0
#define XCHAL_NMI_VECTOR_VADDR 0x400002C0
#define XCHAL_NMI_VECTOR_PADDR 0x400002C0
#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
/****************************************************************************
* DEBUG MODULE
****************************************************************************/
/* Misc */
#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */
#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
/* On-Chip Debug (OCD) */
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
/* TRAX (in core) */
#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */
#define XCHAL_TRAX_MEM_SIZE 16384 /* TRAX memory size in bytes */
#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */
#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
/* Perf counters */
#define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */
/****************************************************************************
* MMU
****************************************************************************/
/* See core-matmap.h header file for more details. */
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
* [autorefill] and protection)
* usable for an MMU-based OS
*/
/* If none of the above last 5 are set, it's a custom TLB configuration. */
#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
/****************************************************************************
* MPU
****************************************************************************/
#define XCHAL_HAVE_MPU 0
#define XCHAL_MPU_ENTRIES 0
#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */
#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/
#define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */
#define XCHAL_MPU_ALIGN_BITS 0
#define XCHAL_MPU_ALIGN 0
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
#endif /* __ARCH_XTENSA_INCLUDE_ESP32S3_CORE_ISA_H */

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/****************************************************************************
* arch/xtensa/include/esp32s3/irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directly but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_XTENSA_INCLUDE_ESP32S3_IRQ_H
#define __ARCH_XTENSA_INCLUDE_ESP32S3_IRQ_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define ESP32S3_INT_PRIO_DEF 1
/* Interrupt Matrix
*
* The Interrupt Matrix embedded in the ESP32-S3 independently allocates
* peripheral interrupt sources to the two CPUs’ peripheral interrupts, to
* timely inform CPU0 or CPU1 to process the interrupts once the interrupt
* signals are generated.
* Peripheral interrupt sources must be routed to CPU0/CPU1 peripheral
* interrupts via this interrupt matrix due to the following considerations:
* - ESP32-S3 has 99 peripheral interrupt sources. To map them to 32 CPU0
* interrupts or 32 CPU1 interrupts, this matrix is needed.
* - Through this matrix, one peripheral interrupt source can be mapped to
* multiple CPU0 interrupts or CPU1 interrupts according to application
* requirements.
*
* Features:
* - Accept 99 peripheral interrupt sources as input.
* - Generate 26 peripheral interrupts to CPU0 and 26 peripheral interrupts
* to CPU1 as output. Note that the remaining 6 CPU0 interrupts and 6 CPU1
* interrupts are internal interrupts.
* - Support disabling CPU non-maskable interrupt (NMI) sources.
* - Support querying current interrupt status of peripheral interrupt
* sources.
*/
#define ESP32S3_PERIPH_MAC 0
#define ESP32S3_PERIPH_MAC_NMI 1
#define ESP32S3_PERIPH_PWR 2
#define ESP32S3_PERIPH_BB 3
#define ESP32S3_PERIPH_BT_MAC 4
#define ESP32S3_PERIPH_BT_BB 5
#define ESP32S3_PERIPH_BT_BB_NMI 6
#define ESP32S3_PERIPH_RWBT 7
#define ESP32S3_PERIPH_RWBLE 8
#define ESP32S3_PERIPH_RWBT_NMI 9
/* RESERVED interrupts: 12, 13, 15, 18, 19 */
#define ESP32S3_PERIPH_RWBLE_NMI 10
#define ESP32S3_PERIPH_I2C_MST 11
#define ESP32S3_PERIPH_UHCI0 14
#define ESP32S3_PERIPH_GPIO_INT_CPU 16
#define ESP32S3_PERIPH_GPIO_INT_CPU_NMI 17
/* RESERVED interrupts: 23 */
#define ESP32S3_PERIPH_SPI1 20
#define ESP32S3_PERIPH_SPI2 21
#define ESP32S3_PERIPH_SPI3 22
#define ESP32S3_PERIPH_LCD_CAM 24
#define ESP32S3_PERIPH_I2S0 25
#define ESP32S3_PERIPH_I2S1 26
#define ESP32S3_PERIPH_UART0 27
#define ESP32S3_PERIPH_UART1 28
#define ESP32S3_PERIPH_UART2 29
/* RESERVED interrupts: 33, 34 */
#define ESP32S3_PERIPH_SDIO_HOST 30
#define ESP32S3_PERIPH_PWM0 31
#define ESP32S3_PERIPH_PWM1 32
#define ESP32S3_PERIPH_LEDC 35
#define ESP32S3_PERIPH_EFUSE 36
#define ESP32S3_PERIPH_CAN 37
#define ESP32S3_PERIPH_USB 38
#define ESP32S3_PERIPH_RTC_CORE 39
/* RESERVED interrupts: 44, 45, 46, 47, 48, 49 */
#define ESP32S3_PERIPH_RMT 40
#define ESP32S3_PERIPH_PCNT 41
#define ESP32S3_PERIPH_I2C_EXT0 42
#define ESP32S3_PERIPH_I2C_EXT1 43
#define ESP32S3_PERIPH_TG_T0_LEVEL 50
#define ESP32S3_PERIPH_TG_T1_LEVEL 51
#define ESP32S3_PERIPH_TG_WDT_LEVEL 52
#define ESP32S3_PERIPH_TG1_T0_LEVEL 53
#define ESP32S3_PERIPH_TG1_T1_LEVEL 54
#define ESP32S3_PERIPH_TG1_WDT_LEVEL 55
#define ESP32S3_PERIPH_CACHE_IA 56
#define ESP32S3_PERIPH_SYSTIMER_TARGET0 57
#define ESP32S3_PERIPH_SYSTIMER_TARGET1 58
#define ESP32S3_PERIPH_SYSTIMER_TARGET2 59
#define ESP32S3_PERIPH_SPI_MEM_REJECT 60
#define ESP32S3_PERIPH_DCACHE_PRELOAD 61
#define ESP32S3_PERIPH_ICACHE_PRELOAD 62
#define ESP32S3_PERIPH_DCACHE_SYNC 63
#define ESP32S3_PERIPH_ICACHE_SYNC 64
#define ESP32S3_PERIPH_APB_ADC 65
#define ESP32S3_PERIPH_DMA_IN_CH0 66
#define ESP32S3_PERIPH_DMA_IN_CH1 67
#define ESP32S3_PERIPH_DMA_IN_CH2 68
#define ESP32S3_PERIPH_DMA_IN_CH3 69
#define ESP32S3_PERIPH_DMA_IN_CH4 70
#define ESP32S3_PERIPH_DMA_OUT_CH0 71
#define ESP32S3_PERIPH_DMA_OUT_CH1 72
#define ESP32S3_PERIPH_DMA_OUT_CH2 73
#define ESP32S3_PERIPH_DMA_OUT_CH3 74
#define ESP32S3_PERIPH_DMA_OUT_CH4 75
#define ESP32S3_PERIPH_RSA 76
#define ESP32S3_PERIPH_AES 77
#define ESP32S3_PERIPH_SHA 78
#define ESP32S3_PERIPH_INT_FROM_CPU0 79
#define ESP32S3_PERIPH_INT_FROM_CPU1 80
#define ESP32S3_PERIPH_INT_FROM_CPU2 81
#define ESP32S3_PERIPH_INT_FROM_CPU3 82
#define ESP32S3_PERIPH_ASSIST_DEBUG 83
#define ESP32S3_PERIPH_DMA_APB_PMS_MONITOR_VIOLATE 84
#define ESP32S3_PERIPH_CORE_0_IRAM0_PMS_MONITOR_VIOLATE 85
#define ESP32S3_PERIPH_CORE_0_DRAM0_PMS_MONITOR_VIOLATE 86
#define ESP32S3_PERIPH_CORE_0_PIF_PMS_MONITOR_VIOLATE 87
#define ESP32S3_PERIPH_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE 88
#define ESP32S3_PERIPH_CORE_1_IRAM0_PMS_MONITOR_VIOLATE 89
#define ESP32S3_PERIPH_CORE_1_DRAM0_PMS_MONITOR_VIOLATE 90
#define ESP32S3_PERIPH_CORE_1_PIF_PMS_MONITOR_VIOLATE 91
#define ESP32S3_PERIPH_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE 92
#define ESP32S3_PERIPH_BACKUP_PMS_VIOLATE 93
#define ESP32S3_PERIPH_CACHE_CORE0_ACS 94
#define ESP32S3_PERIPH_CACHE_CORE1_ACS 95
#define ESP32S3_PERIPH_USB_DEVICE 96
#define ESP32S3_PERIPH_PERIPH_BACKUP 97
#define ESP32S3_PERIPH_DMA_EXTMEM_REJECT 98
/* Total number of peripherals */
#define ESP32S3_NPERIPHERALS 99
/* Exceptions
*
* IRAM Offset Description
* 0x0000 Windows
* 0x0180 Level 2 interrupt
* 0x01c0 Level 3 interrupt
* 0x0200 Level 4 interrupt
* 0x0240 Level 5 interrupt
* 0x0280 Debug exception
* 0x02c0 NMI exception
* 0x0300 Kernel exception
* 0x0340 User exception
* 0x03c0 Double exception
*/
/* IRQ numbers for internal interrupts that are dispatched like peripheral
* interrupts.
*/
#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */
#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */
#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */
#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_NIRQ_INTERNAL 4 /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_FIRSTPERIPH 4 /* First peripheral IRQ number */
/* IRQ numbers for peripheral interrupts coming through the Interrupt
* Matrix.
*/
#define ESP32S3_IRQ2PERIPH(irq) ((irq) - XTENSA_IRQ_FIRSTPERIPH)
#define ESP32S3_PERIPH2IRQ(id) ((id) + XTENSA_IRQ_FIRSTPERIPH)
#define ESP32S3_IRQ_MAC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_MAC)
#define ESP32S3_IRQ_MAC_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_MAC_NMI)
#define ESP32S3_IRQ_PWR (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_PWR)
#define ESP32S3_IRQ_BB (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_BB)
#define ESP32S3_IRQ_BT_MAC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_BT_MAC)
#define ESP32S3_IRQ_BT_BB (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_BB)
#define ESP32S3_IRQ_BT_BB_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_BB_NMI)
#define ESP32S3_IRQ_RWBT (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RWBT)
#define ESP32S3_IRQ_RWBLE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RWBLE)
#define ESP32S3_IRQ_RWBT_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RWBT_NMI)
#define ESP32S3_IRQ_RWBLE_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RWBLE_NMI)
#define ESP32S3_IRQ_I2C_MST (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_I2C_MST)
#define ESP32S3_IRQ_UHCI0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_UHCI0)
#define ESP32S3_IRQ_GPIO_INT_CPU (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_GPIO_INT_CPU)
#define ESP32S3_IRQ_GPIO_INT_CPU_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_GPIO_INT_CPU_NMI)
#define ESP32S3_IRQ_SPI1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SPI1)
#define ESP32S3_IRQ_SPI2 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SPI2)
#define ESP32S3_IRQ_SPI3 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SPI3)
#define ESP32S3_IRQ_LCD_CAM (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_LCD_CAM)
#define ESP32S3_IRQ_I2S0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_I2S0)
#define ESP32S3_IRQ_I2S1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_I2S1)
#define ESP32S3_IRQ_UART0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_UART0)
#define ESP32S3_IRQ_UART1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_UART1)
#define ESP32S3_IRQ_UART2 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_UART2)
#define ESP32S3_IRQ_SDIO_HOST (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SDIO_HOST)
#define ESP32S3_IRQ_PWM0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_PWM0)
#define ESP32S3_IRQ_SREG0 ESP32S3_IRQ_MAC
#define ESP32S3_NIRQS_SREG0 32
#define ESP32S3_IRQ_PWM1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_PWM1)
#define ESP32S3_IRQ_LEDC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_LEDC)
#define ESP32S3_IRQ_EFUSE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_EFUSE)
#define ESP32S3_IRQ_CAN (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CAN)
#define ESP32S3_IRQ_USB (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_USB)
#define ESP32S3_IRQ_RTC_CORE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RTC_CORE)
#define ESP32S3_IRQ_RMT (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RMT)
#define ESP32S3_IRQ_PCNT (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_PCNT)
#define ESP32S3_IRQ_I2C_EXT0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_I2C_EXT0)
#define ESP32S3_IRQ_I2C_EXT1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_I2C_EXT1)
#define ESP32S3_IRQ_TG_T0_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_TG_T0_LEVEL)
#define ESP32S3_IRQ_TG_T1_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_TG_T1_LEVEL)
#define ESP32S3_IRQ_TG_WDT_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_TG_WDT_LEVEL)
#define ESP32S3_IRQ_TG1_T0_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_TG1_T0_LEVEL)
#define ESP32S3_IRQ_TG1_T1_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_TG1_T1_LEVEL)
#define ESP32S3_IRQ_TG1_WDT_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_TG1_WDT_LEVEL)
#define ESP32S3_IRQ_CACHE_IA (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CACHE_IA)
#define ESP32S3_IRQ_SYSTIMER_TARGET0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SYSTIMER_TARGET0)
#define ESP32S3_IRQ_SYSTIMER_TARGET1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SYSTIMER_TARGET1)
#define ESP32S3_IRQ_SYSTIMER_TARGET2 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SYSTIMER_TARGET2)
#define ESP32S3_IRQ_SPI_MEM_REJECT (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SPI_MEM_REJECT)
#define ESP32S3_IRQ_DCACHE_PRELOAD (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DCACHE_PRELOAD)
#define ESP32S3_IRQ_ICACHE_PRELOAD (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_ICACHE_PRELOAD)
#define ESP32S3_IRQ_DCACHE_SYNC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DCACHE_SYNC)
#define ESP32S3_IRQ_SREG1 ESP32S3_IRQ_PWM1
#define ESP32S3_NIRQS_SREG1 32
#define ESP32S3_IRQ_ICACHE_SYNC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_ICACHE_SYNC)
#define ESP32S3_IRQ_APB_ADC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_APB_ADC)
#define ESP32S3_IRQ_DMA_IN_CH0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_IN_CH0)
#define ESP32S3_IRQ_DMA_IN_CH1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_IN_CH1)
#define ESP32S3_IRQ_DMA_IN_CH2 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_IN_CH2)
#define ESP32S3_IRQ_DMA_IN_CH3 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_IN_CH3)
#define ESP32S3_IRQ_DMA_IN_CH4 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_IN_CH4)
#define ESP32S3_IRQ_DMA_OUT_CH0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_OUT_CH0)
#define ESP32S3_IRQ_DMA_OUT_CH1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_OUT_CH1)
#define ESP32S3_IRQ_DMA_OUT_CH2 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_OUT_CH2)
#define ESP32S3_IRQ_DMA_OUT_CH3 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_OUT_CH3)
#define ESP32S3_IRQ_DMA_OUT_CH4 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_OUT_CH4)
#define ESP32S3_IRQ_RSA (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RSA)
#define ESP32S3_IRQ_AES (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_AES)
#define ESP32S3_IRQ_SHA (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SHA)
#define ESP32S3_IRQ_INT_FROM_CPU0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_INT_FROM_CPU0)
#define ESP32S3_IRQ_INT_FROM_CPU1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_INT_FROM_CPU1)
#define ESP32S3_IRQ_INT_FROM_CPU2 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_INT_FROM_CPU2)
#define ESP32S3_IRQ_INT_FROM_CPU3 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_INT_FROM_CPU3)
#define ESP32S3_IRQ_ASSIST_DEBUG (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_ASSIST_DEBUG)
#define ESP32S3_IRQ_DMA_APB_PMS_MONITOR_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_APB_PMS_MONITOR_VIOLATE)
#define ESP32S3_IRQ_CORE_0_IRAM0_PMS_MONITOR_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_0_IRAM0_PMS_MONITOR_VIOLATE)
#define ESP32S3_IRQ_CORE_0_DRAM0_PMS_MONITOR_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_0_DRAM0_PMS_MONITOR_VIOLATE)
#define ESP32S3_IRQ_CORE_0_PIF_PMS_MONITOR_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_0_PIF_PMS_MONITOR_VIOLATE)
#define ESP32S3_IRQ_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE)
#define ESP32S3_IRQ_CORE_1_IRAM0_PMS_MONITOR_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_1_IRAM0_PMS_MONITOR_VIOLATE)
#define ESP32S3_IRQ_CORE_1_DRAM0_PMS_MONITOR_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_1_DRAM0_PMS_MONITOR_VIOLATE)
#define ESP32S3_IRQ_CORE_1_PIF_PMS_MONITOR_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_1_PIF_PMS_MONITOR_VIOLATE)
#define ESP32S3_IRQ_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE)
#define ESP32S3_IRQ_BACKUP_PMS_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_BACKUP_PMS_VIOLATE)
#define ESP32S3_IRQ_CACHE_CORE0_ACS (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CACHE_CORE0_ACS)
#define ESP32S3_IRQ_CACHE_CORE1_ACS (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CACHE_CORE1_ACS)
#define ESP32S3_IRQ_SREG2 ESP32S3_IRQ_ICACHE_SYNC
#define ESP32S3_NIRQS_SREG2 32
#define ESP32S3_IRQ_USB_DEVICE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_USB_DEVICE)
#define ESP32S3_IRQ_PERIPH_BACKUP (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_PERIPH_BACKUP)
#define ESP32S3_IRQ_DMA_EXTMEM_REJECT (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_EXTMEM_REJECT)
#define ESP32S3_IRQ_SREG3 ESP32S3_IRQ_USB_DEVICE
#define ESP32S3_NIRQS_SREG3 3
#define ESP32S3_NIRQ_PERIPH ESP32S3_NPERIPHERALS
/* Second level GPIO interrupts. GPIO interrupts are decoded and dispatched
* as a second level of decoding: The first level dispatches to the GPIO
* interrupt handler. The second to the decoded GPIO interrupt handler.
*/
#ifdef CONFIG_ESP32S3_GPIO_IRQ
# define ESP32S3_NIRQ_GPIO 40
# define ESP32S3_FIRST_GPIOIRQ (XTENSA_NIRQ_INTERNAL + ESP32S3_NIRQ_PERIPH)
# define ESP32S3_LAST_GPIOIRQ (ESP32S3_FIRST_GPIOIRQ + ESP32S3_NIRQ_GPIO - 1)
# define ESP32S3_PIN2IRQ(p) ((p) + ESP32S3_FIRST_GPIOIRQ)
# define ESP32S3_IRQ2PIN(i) ((i) - ESP32S3_FIRST_GPIOIRQ)
#else
# define ESP32S3_NIRQ_GPIO 0
#endif
/* Total number of interrupts */
#define NR_IRQS (XTENSA_NIRQ_INTERNAL + ESP32S3_NIRQ_PERIPH + ESP32S3_NIRQ_GPIO)
/* Xtensa CPU Interrupts.
*
* Each of the two CPUs (PRO and APP) have 32 interrupts each, of which
* 26 can be mapped to peripheral interrupts:
*
* Level triggered peripherals (21 total):
* 0-5, 8-9, 12-13, 17-18 - Priority 1
* 19-21 - Priority 2
* 23, 27 - Priority 3
* 24-25 - Priority 4
* 26, 31 - Priority 5
* Edge triggered peripherals (4 total):
* 10 - Priority 1
* 22 - Priority 3
* 28, 30 - Priority 4
* NMI (1 total):
* 14 - NMI
*
* CPU peripheral interrupts can be a assigned to a CPU interrupt using the
* PRO_*_MAP_REG or APP_*_MAP_REG. There are a pair of these registers for
* each peripheral source. Multiple peripheral interrupt sources can be
* mapped to the same CPU interrupt.
*
* The remaining, six, internal CPU interrupts are:
*
* 6 Timer0 - Priority 1
* 7 Software - Priority 1
* 11 Profiling - Priority 3
* 15 Timer1 - Priority 3
* 16 Timer2 - Priority 5
* 29 Software - Priority 3
*
* A peripheral interrupt can be disabled
*/
#define ESP32S3_CPUINT_LEVELPERIPH_0 0
#define ESP32S3_CPUINT_LEVELPERIPH_1 1
#define ESP32S3_CPUINT_LEVELPERIPH_2 2
#define ESP32S3_CPUINT_LEVELPERIPH_3 3
#define ESP32S3_CPUINT_LEVELPERIPH_4 4
#define ESP32S3_CPUINT_LEVELPERIPH_5 5
#define ESP32S3_CPUINT_LEVELPERIPH_6 8
#define ESP32S3_CPUINT_LEVELPERIPH_7 9
#define ESP32S3_CPUINT_LEVELPERIPH_8 12
#define ESP32S3_CPUINT_LEVELPERIPH_9 13
#define ESP32S3_CPUINT_LEVELPERIPH_10 17
#define ESP32S3_CPUINT_LEVELPERIPH_11 18
#define ESP32S3_CPUINT_LEVELPERIPH_12 19
#define ESP32S3_CPUINT_LEVELPERIPH_13 20
#define ESP32S3_CPUINT_LEVELPERIPH_14 21
#define ESP32S3_CPUINT_LEVELPERIPH_15 23
#define ESP32S3_CPUINT_LEVELPERIPH_16 24
#define ESP32S3_CPUINT_LEVELPERIPH_17 25
#define ESP32S3_CPUINT_LEVELPERIPH_18 26
#define ESP32S3_CPUINT_LEVELPERIPH_19 27
#define ESP32S3_CPUINT_LEVELPERIPH_20 31
#define ESP32S3_CPUINT_NLEVELPERIPHS 21
#define ESP32S3_CPUINT_LEVELSET 0x8fbe333f
#define ESP32S3_CPUINT_EDGEPERIPH_0 10
#define ESP32S3_CPUINT_EDGEPERIPH_1 22
#define ESP32S3_CPUINT_EDGEPERIPH_2 28
#define ESP32S3_CPUINT_EDGEPERIPH_3 30
#define ESP32S3_CPUINT_NEDGEPERIPHS 4
#define ESP32S3_CPUINT_EDGESET 0x50400400
#define ESP32S3_CPUINT_NNMIPERIPHS 1
#define ESP32S3_CPUINT_NMISET 0x00004000
#define ESP32S3_CPUINT_MAC 0
#define ESP32S3_CPUINT_TIMER0 6
#define ESP32S3_CPUINT_SOFTWARE0 7
#define ESP32S3_CPUINT_PROFILING 11
#define ESP32S3_CPUINT_TIMER1 15
#define ESP32S3_CPUINT_TIMER2 16
#define ESP32S3_CPUINT_SOFTWARE1 29
#define ESP32S3_CPUINT_NINTERNAL 6
#define ESP32S3_NCPUINTS 32
#define ESP32S3_CPUINT_MAX (ESP32S3_NCPUINTS - 1)
#define ESP32S3_CPUINT_PERIPHSET 0xdffe773f
#define ESP32S3_CPUINT_INTERNALSET 0x200188c0
/* Priority 1: 0-10, 12-13, 17-18 (15)
* Priority 2: 19-21 (3)
* Priority 3: 11, 15, 22-23, 27, 29 (6)
* Priority 4: 24-25, 28, 30 (4)
* Priority 5: 16, 26, 31 (3)
* Priority NMI: 14 (1)
*/
#define ESP32S3_INTPRI1_MASK 0x000637ff
#define ESP32S3_INTPRI2_MASK 0x00380000
#define ESP32S3_INTPRI3_MASK 0x28c08800
#define ESP32S3_INTPRI4_MASK 0x53000000
#define ESP32S3_INTPRI5_MASK 0x84010000
#define ESP32S3_INTNMI_MASK 0x00004000
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_INCLUDE_ESP32S3_IRQ_H */

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arch/xtensa/include/esp32s3/tie-asm.h Normal file
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/****************************************************************************
* arch/xtensa/include/esp32s3/tie-asm.h
* Compile-time HAL assembler definitions dependent on CORE & TIE
* configuration
*
* NOTE: This header file is not meant to be included directly.
*
* This header file contains assembly-language definitions (assembly
* macros, etc.) for this specific Xtensa processor's TIE extensions
* and options. It is customized to this Xtensa processor configuration.
*
* Customer ID=15128; Build=0x90f1f;
* Copyright (c) 1999-2021 Cadence Design Systems Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_ASM_H
#define __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_ASM_H
/* Selection parameter values for save-area save/restore macros: */
/* Option vs. TIE: */
#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
/* Whether used automatically by compiler: */
#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
/* ABI handling across function calls: */
#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
/* Misc */
#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
| ((ccuse) & XTHAL_SAS_ANYCC) \
| ((abi) & XTHAL_SAS_ANYABI) )
/*
* Macro to store all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers).
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 4 byte aligned address).
* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
* registers are clobbered, the remaining are unused).
* Optional parameters:
* continue If macro invoked as part of a larger store sequence, set to 1
* if this is not the first in the sequence. Defaults to 0.
* ofs Offset from start of larger sequence (from value of first ptr
* in sequence) at which to store. Defaults to next available space
* (or 0 if <continue> is 0).
* select Select what category(ies) of registers to store, as a bitmask
* (see XTHAL_SAS_xxx constants). Defaults to all registers.
* alloc Select what category(ies) of registers to allocate; if any
* category is selected here that is not in <select>, space for
* the corresponding registers is skipped without doing any store.
*/
.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Optional global registers used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
xchal_sa_align \ptr, 0, 1016, 4, 4
rur.THREADPTR \at1 // threadptr option
s32i \at1, \ptr, .Lxchal_ofs_+0
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1016, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.endif
// Optional caller-saved registers used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1012, 4, 4
rsr.ACCLO \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+0
rsr.ACCHI \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1012, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.endif
// Optional caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 996, 4, 4
rsr.BR \at1 // boolean option
s32i \at1, \ptr, .Lxchal_ofs_+0
rsr.SCOMPARE1 \at1 // conditional store option
s32i \at1, \ptr, .Lxchal_ofs_+4
rsr.M0 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+8
rsr.M1 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+12
rsr.M2 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+16
rsr.M3 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+20
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 996, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.endif
.endm // xchal_ncp_store
/*
* Macro to load all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers).
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 4 byte aligned address).
* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
* registers are clobbered, the remaining are unused).
* Optional parameters:
* continue If macro invoked as part of a larger load sequence, set to 1
* if this is not the first in the sequence. Defaults to 0.
* ofs Offset from start of larger sequence (from value of first ptr
* in sequence) at which to load. Defaults to next available space
* (or 0 if <continue> is 0).
* select Select what category(ies) of registers to load, as a bitmask
* (see XTHAL_SAS_xxx constants). Defaults to all registers.
* alloc Select what category(ies) of registers to allocate; if any
* category is selected here that is not in <select>, space for
* the corresponding registers is skipped without doing any load.
*/
.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Optional global registers used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
xchal_sa_align \ptr, 0, 1016, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wur.THREADPTR \at1 // threadptr option
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1016, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.endif
// Optional caller-saved registers used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1012, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wsr.ACCLO \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_+4
wsr.ACCHI \at1 // MAC16 option
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1012, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.endif
// Optional caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 996, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wsr.BR \at1 // boolean option
l32i \at1, \ptr, .Lxchal_ofs_+4
wsr.SCOMPARE1 \at1 // conditional store option
l32i \at1, \ptr, .Lxchal_ofs_+8
wsr.M0 \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_+12
wsr.M1 \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_+16
wsr.M2 \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_+20
wsr.M3 \at1 // MAC16 option
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 996, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.endif
.endm // xchal_ncp_load
#define XCHAL_NCP_NUM_ATMPS 1
/*
* Macro to store the state of TIE coprocessor FPU.
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 4 byte aligned address).
* at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
* registers are clobbered, the remaining are unused).
* Optional parameters are the same as for xchal_ncp_store.
*/
#define xchal_cp_FPU_store xchal_cp0_store
.macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 948, 4, 4
rur.FCR \at1 // ureg 232
s32i \at1, \ptr, .Lxchal_ofs_+0
rur.FSR \at1 // ureg 233
s32i \at1, \ptr, .Lxchal_ofs_+4
ssi f0, \ptr, .Lxchal_ofs_+8
ssi f1, \ptr, .Lxchal_ofs_+12
ssi f2, \ptr, .Lxchal_ofs_+16
ssi f3, \ptr, .Lxchal_ofs_+20
ssi f4, \ptr, .Lxchal_ofs_+24
ssi f5, \ptr, .Lxchal_ofs_+28
ssi f6, \ptr, .Lxchal_ofs_+32
ssi f7, \ptr, .Lxchal_ofs_+36
ssi f8, \ptr, .Lxchal_ofs_+40
ssi f9, \ptr, .Lxchal_ofs_+44
ssi f10, \ptr, .Lxchal_ofs_+48
ssi f11, \ptr, .Lxchal_ofs_+52
ssi f12, \ptr, .Lxchal_ofs_+56
ssi f13, \ptr, .Lxchal_ofs_+60
ssi f14, \ptr, .Lxchal_ofs_+64
ssi f15, \ptr, .Lxchal_ofs_+68
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 948, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
.endif
.endm // xchal_cp0_store
/*
* Macro to load the state of TIE coprocessor FPU.
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 4 byte aligned address).
* at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
* registers are clobbered, the remaining are unused).
* Optional parameters are the same as for xchal_ncp_load.
*/
#define xchal_cp_FPU_load xchal_cp0_load
.macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 948, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wur.FCR \at1 // ureg 232
l32i \at1, \ptr, .Lxchal_ofs_+4
wur.FSR \at1 // ureg 233
lsi f0, \ptr, .Lxchal_ofs_+8
lsi f1, \ptr, .Lxchal_ofs_+12
lsi f2, \ptr, .Lxchal_ofs_+16
lsi f3, \ptr, .Lxchal_ofs_+20
lsi f4, \ptr, .Lxchal_ofs_+24
lsi f5, \ptr, .Lxchal_ofs_+28
lsi f6, \ptr, .Lxchal_ofs_+32
lsi f7, \ptr, .Lxchal_ofs_+36
lsi f8, \ptr, .Lxchal_ofs_+40
lsi f9, \ptr, .Lxchal_ofs_+44
lsi f10, \ptr, .Lxchal_ofs_+48
lsi f11, \ptr, .Lxchal_ofs_+52
lsi f12, \ptr, .Lxchal_ofs_+56
lsi f13, \ptr, .Lxchal_ofs_+60
lsi f14, \ptr, .Lxchal_ofs_+64
lsi f15, \ptr, .Lxchal_ofs_+68
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 948, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
.endif
.endm // xchal_cp0_load
#define XCHAL_CP0_NUM_ATMPS 1
/*
* Macro to store the state of TIE coprocessor cop_ai.
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 16 byte aligned address).
* at1..at4 Four temporary address registers (first XCHAL_CP3_NUM_ATMPS
* registers are clobbered, the remaining are unused).
* Optional parameters are the same as for xchal_ncp_store.
*/
#define xchal_cp_cop_ai_store xchal_cp3_store
.macro xchal_cp3_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 0, 16, 16
rur.ACCX_0 \at1 // ureg 0
s32i \at1, \ptr, .Lxchal_ofs_+0
rur.ACCX_1 \at1 // ureg 1
s32i \at1, \ptr, .Lxchal_ofs_+4
rur.QACC_H_0 \at1 // ureg 2
s32i \at1, \ptr, .Lxchal_ofs_+8
rur.QACC_H_1 \at1 // ureg 3
s32i \at1, \ptr, .Lxchal_ofs_+12
rur.QACC_H_2 \at1 // ureg 4
s32i \at1, \ptr, .Lxchal_ofs_+16
rur.QACC_H_3 \at1 // ureg 5
s32i \at1, \ptr, .Lxchal_ofs_+20
rur.QACC_H_4 \at1 // ureg 6
s32i \at1, \ptr, .Lxchal_ofs_+24
rur.QACC_L_0 \at1 // ureg 7
s32i \at1, \ptr, .Lxchal_ofs_+28
rur.QACC_L_1 \at1 // ureg 8
s32i \at1, \ptr, .Lxchal_ofs_+32
rur.QACC_L_2 \at1 // ureg 9
s32i \at1, \ptr, .Lxchal_ofs_+36
rur.QACC_L_3 \at1 // ureg 10
s32i \at1, \ptr, .Lxchal_ofs_+40
rur.QACC_L_4 \at1 // ureg 11
s32i \at1, \ptr, .Lxchal_ofs_+44
rur.SAR_BYTE \at1 // ureg 13
s32i \at1, \ptr, .Lxchal_ofs_+48
rur.FFT_BIT_WIDTH \at1 // ureg 14
s32i \at1, \ptr, .Lxchal_ofs_+52
rur.UA_STATE_0 \at1 // ureg 15
s32i \at1, \ptr, .Lxchal_ofs_+56
rur.UA_STATE_1 \at1 // ureg 16
s32i \at1, \ptr, .Lxchal_ofs_+60
rur.UA_STATE_2 \at1 // ureg 17
s32i \at1, \ptr, .Lxchal_ofs_+64
rur.UA_STATE_3 \at1 // ureg 18
s32i \at1, \ptr, .Lxchal_ofs_+68
st.qr q0, \ptr, .Lxchal_ofs_+80
st.qr q1, \ptr, .Lxchal_ofs_+96
st.qr q2, \ptr, .Lxchal_ofs_+112
addi \ptr, \ptr, 128
st.qr q3, \ptr, .Lxchal_ofs_+0
st.qr q4, \ptr, .Lxchal_ofs_+16
st.qr q5, \ptr, .Lxchal_ofs_+32
st.qr q6, \ptr, .Lxchal_ofs_+48
st.qr q7, \ptr, .Lxchal_ofs_+64
.set .Lxchal_pofs_, .Lxchal_pofs_ + 128
.set .Lxchal_ofs_, .Lxchal_ofs_ + 80
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 0, 16, 16
.set .Lxchal_ofs_, .Lxchal_ofs_ + 208
.endif
.endm // xchal_cp3_store
/*
* Macro to load the state of TIE coprocessor cop_ai.
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 16 byte aligned address).
* at1..at4 Four temporary address registers (first XCHAL_CP3_NUM_ATMPS
* registers are clobbered, the remaining are unused).
* Optional parameters are the same as for xchal_ncp_load.
*/
#define xchal_cp_cop_ai_load xchal_cp3_load
.macro xchal_cp3_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 0, 16, 16
l32i \at1, \ptr, .Lxchal_ofs_+0
wur.ACCX_0 \at1 // ureg 0
l32i \at1, \ptr, .Lxchal_ofs_+4
wur.ACCX_1 \at1 // ureg 1
l32i \at1, \ptr, .Lxchal_ofs_+8
wur.QACC_H_0 \at1 // ureg 2
l32i \at1, \ptr, .Lxchal_ofs_+12
wur.QACC_H_1 \at1 // ureg 3
l32i \at1, \ptr, .Lxchal_ofs_+16
wur.QACC_H_2 \at1 // ureg 4
l32i \at1, \ptr, .Lxchal_ofs_+20
wur.QACC_H_3 \at1 // ureg 5
l32i \at1, \ptr, .Lxchal_ofs_+24
wur.QACC_H_4 \at1 // ureg 6
l32i \at1, \ptr, .Lxchal_ofs_+28
wur.QACC_L_0 \at1 // ureg 7
l32i \at1, \ptr, .Lxchal_ofs_+32
wur.QACC_L_1 \at1 // ureg 8
l32i \at1, \ptr, .Lxchal_ofs_+36
wur.QACC_L_2 \at1 // ureg 9
l32i \at1, \ptr, .Lxchal_ofs_+40
wur.QACC_L_3 \at1 // ureg 10
l32i \at1, \ptr, .Lxchal_ofs_+44
wur.QACC_L_4 \at1 // ureg 11
l32i \at1, \ptr, .Lxchal_ofs_+48
wur.SAR_BYTE \at1 // ureg 13
l32i \at1, \ptr, .Lxchal_ofs_+52
wur.FFT_BIT_WIDTH \at1 // ureg 14
l32i \at1, \ptr, .Lxchal_ofs_+56
wur.UA_STATE_0 \at1 // ureg 15
l32i \at1, \ptr, .Lxchal_ofs_+60
wur.UA_STATE_1 \at1 // ureg 16
l32i \at1, \ptr, .Lxchal_ofs_+64
wur.UA_STATE_2 \at1 // ureg 17
l32i \at1, \ptr, .Lxchal_ofs_+68
wur.UA_STATE_3 \at1 // ureg 18
ld.qr q0, \ptr, .Lxchal_ofs_+80
ld.qr q1, \ptr, .Lxchal_ofs_+96
ld.qr q2, \ptr, .Lxchal_ofs_+112
addi \ptr, \ptr, 128
ld.qr q3, \ptr, .Lxchal_ofs_+0
ld.qr q4, \ptr, .Lxchal_ofs_+16
ld.qr q5, \ptr, .Lxchal_ofs_+32
ld.qr q6, \ptr, .Lxchal_ofs_+48
ld.qr q7, \ptr, .Lxchal_ofs_+64
.set .Lxchal_pofs_, .Lxchal_pofs_ + 128
.set .Lxchal_ofs_, .Lxchal_ofs_ + 80
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 0, 16, 16
.set .Lxchal_ofs_, .Lxchal_ofs_ + 208
.endif
.endm // xchal_cp3_load
#define XCHAL_CP3_NUM_ATMPS 1
#define XCHAL_SA_NUM_ATMPS 1
/* Empty macros for unconfigured coprocessors: */
.macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
#endif /* __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_ASM_H */

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/****************************************************************************
* arch/xtensa/include/esp32s3/tie.h
* Compile-time HAL definitions dependent on CORE & TIE configuration
*
* NOTE: This header file is not meant to be included directly.
*
* This header file describes this specific Xtensa processor's TIE extensions
* that extend basic Xtensa core functionality. It is customized to this
* Xtensa processor configuration.
*
* Customer ID=15128; Build=0x90f1f;
* Copyright (c) 1999-2021 Cadence Design Systems Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_H
#define __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_H
#define XCHAL_CP_NUM 2 /* number of coprocessors */
#define XCHAL_CP_MAX 4 /* max CP ID + 1 (0 if none) */
#define XCHAL_CP_MASK 0x09 /* bitmask of all CPs by ID */
#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
/* Basic parameters of each coprocessor: */
#define XCHAL_CP0_NAME "FPU"
#define XCHAL_CP0_IDENT FPU
#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */
#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */
#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */
#define XCHAL_CP3_NAME "cop_ai"
#define XCHAL_CP3_IDENT cop_ai
#define XCHAL_CP3_SA_SIZE 208 /* size of state save area */
#define XCHAL_CP3_SA_ALIGN 16 /* min alignment of save area */
#define XCHAL_CP_ID_COP_AI 3 /* coprocessor ID (0..7) */
/* Filler info for unassigned coprocessors, to simplify arrays etc: */
#define XCHAL_CP1_SA_SIZE 0
#define XCHAL_CP1_SA_ALIGN 1
#define XCHAL_CP2_SA_SIZE 0
#define XCHAL_CP2_SA_ALIGN 1
#define XCHAL_CP4_SA_SIZE 0
#define XCHAL_CP4_SA_ALIGN 1
#define XCHAL_CP5_SA_SIZE 0
#define XCHAL_CP5_SA_ALIGN 1
#define XCHAL_CP6_SA_SIZE 0
#define XCHAL_CP6_SA_ALIGN 1
#define XCHAL_CP7_SA_SIZE 0
#define XCHAL_CP7_SA_ALIGN 1
/* Save area for non-coprocessor optional and custom (TIE) state: */
#define XCHAL_NCP_SA_SIZE 36
#define XCHAL_NCP_SA_ALIGN 4
/* Total save area for optional and custom state (NCP + CPn): */
#define XCHAL_TOTAL_SA_SIZE 336 /* with 16-byte align padding */
#define XCHAL_TOTAL_SA_ALIGN 16 /* actual minimum alignment */
/* Detailed contents of save areas.
* NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
* before expanding the XCHAL_xxx_SA_LIST() macros.
*
* XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
* dbnum,base,regnum,bitsz,gapsz,reset,x...)
*
* s = passed from XCHAL_*_LIST(s), eg. to select how to expand
* ccused = set if used by compiler without special options or code
* abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
* kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
* opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
* name = lowercase reg name (no quotes)
* galign = group byte alignment (power of 2) (galign >= align)
* align = register byte alignment (power of 2)
* asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
* (not including any pad bytes required to galign this or next reg)
* dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
* base = reg shortname w/o index (or sr=special, ur=TIE user reg)
* regnum = reg index in regfile, or special/TIE-user reg number
* bitsz = number of significant bits (regfile width, or ur/sr mask bits)
* gapsz = intervening bits, if bitsz bits not stored contiguously
* (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
* reset = register reset value (or 0 if undefined at reset)
* x = reserved for future use (0 until then)
*
* To filter out certain registers, e.g. to expand only the non-global
* registers used by the compiler, you can do something like this:
*
* #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
* #define SELCC0(p...)
* #define SELCC1(abikind,p...) SELAK##abikind(p)
* #define SELAK0(p...) REG(p)
* #define SELAK1(p...) REG(p)
* #define SELAK2(p...)
* #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
* ...what you want to expand...
*/
#define XCHAL_NCP_SA_NUM 9
#define XCHAL_NCP_SA_LIST(s) \
XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0)
#define XCHAL_CP0_SA_NUM 18
#define XCHAL_CP0_SA_LIST(s) \
XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, fsr, 4, 4, 4,0x03E9, ur,233, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f0, 4, 4, 4,0x0030, f,0 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f1, 4, 4, 4,0x0031, f,1 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f2, 4, 4, 4,0x0032, f,2 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f3, 4, 4, 4,0x0033, f,3 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f4, 4, 4, 4,0x0034, f,4 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f5, 4, 4, 4,0x0035, f,5 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f6, 4, 4, 4,0x0036, f,6 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f7, 4, 4, 4,0x0037, f,7 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f8, 4, 4, 4,0x0038, f,8 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f9, 4, 4, 4,0x0039, f,9 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f10, 4, 4, 4,0x003A, f,10 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f11, 4, 4, 4,0x003B, f,11 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f12, 4, 4, 4,0x003C, f,12 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f13, 4, 4, 4,0x003D, f,13 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f14, 4, 4, 4,0x003E, f,14 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f15, 4, 4, 4,0x003F, f,15 , 32,0,0,0)
#define XCHAL_CP1_SA_NUM 0
#define XCHAL_CP1_SA_LIST(s) /* empty */
#define XCHAL_CP2_SA_NUM 0
#define XCHAL_CP2_SA_LIST(s) /* empty */
#define XCHAL_CP3_SA_NUM 26
#define XCHAL_CP3_SA_LIST(s) \
XCHAL_SA_REG(s,0,0,1,0, accx_0,16, 4, 4,0x0300, ur,0 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, accx_1, 4, 4, 4,0x0301, ur,1 , 8,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, qacc_h_0, 4, 4, 4,0x0302, ur,2 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, qacc_h_1, 4, 4, 4,0x0303, ur,3 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, qacc_h_2, 4, 4, 4,0x0304, ur,4 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, qacc_h_3, 4, 4, 4,0x0305, ur,5 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, qacc_h_4, 4, 4, 4,0x0306, ur,6 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, qacc_l_0, 4, 4, 4,0x0307, ur,7 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, qacc_l_1, 4, 4, 4,0x0308, ur,8 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, qacc_l_2, 4, 4, 4,0x0309, ur,9 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, qacc_l_3, 4, 4, 4,0x030A, ur,10 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, qacc_l_4, 4, 4, 4,0x030B, ur,11 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, sar_byte, 4, 4, 4,0x030D, ur,13 , 4,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, fft_bit_width, 4, 4, 4,0x030E, ur,14 , 4,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, ua_state_0, 4, 4, 4,0x030F, ur,15 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, ua_state_1, 4, 4, 4,0x0310, ur,16 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, ua_state_2, 4, 4, 4,0x0311, ur,17 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, ua_state_3, 4, 4, 4,0x0312, ur,18 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, q0,16,16,16,0x1008, q,0 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, q1,16,16,16,0x1009, q,1 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, q2,16,16,16,0x100A, q,2 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, q3,16,16,16,0x100B, q,3 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, q4,16,16,16,0x100C, q,4 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, q5,16,16,16,0x100D, q,5 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, q6,16,16,16,0x100E, q,6 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, q7,16,16,16,0x100F, q,7 ,128,0,0,0)
#define XCHAL_CP4_SA_NUM 0
#define XCHAL_CP4_SA_LIST(s) /* empty */
#define XCHAL_CP5_SA_NUM 0
#define XCHAL_CP5_SA_LIST(s) /* empty */
#define XCHAL_CP6_SA_NUM 0
#define XCHAL_CP6_SA_LIST(s) /* empty */
#define XCHAL_CP7_SA_NUM 0
#define XCHAL_CP7_SA_LIST(s) /* empty */
/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4
/* Byte length of instruction from its first byte, per FLIX. */
#define XCHAL_BYTE0_FORMAT_LENGTHS \
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4
#endif /* __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_H */

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/****************************************************************************
* arch/xtensa/include/lx7/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_INCLUDE_LX7_CHIP_H
#define __ARCH_XTENSA_INCLUDE_LX7_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_INCLUDE_LX7_CHIP_H */

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/esp-nuttx-bootloader

88
arch/xtensa/src/esp32s3/Bootloader.mk Normal file
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############################################################################
# arch/xtensa/src/esp32s3/Bootloader.mk
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
ifeq ($(CONFIG_ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE),y)
CHIPDIR = $(TOPDIR)/arch/xtensa/src/chip
BOOTLOADER_SRCDIR = $(CHIPDIR)/esp-nuttx-bootloader
BOOTLOADER_VERSION = main
BOOTLOADER_URL = https://github.com/espressif/esp-nuttx-bootloader
BOOTLOADER_OUTDIR = out
BOOTLOADER_CONFIG = $(CHIPDIR)/bootloader.conf
$(BOOTLOADER_SRCDIR):
$(Q) git clone $(BOOTLOADER_URL) $(BOOTLOADER_SRCDIR) -b $(BOOTLOADER_VERSION)
# Helpers for creating the configuration file
cfg_en = echo "$(1)=y";
cfg_val = echo "$(1)=$(2)";
$(BOOTLOADER_CONFIG): $(TOPDIR)/.config
$(Q) echo "Creating Bootloader configuration"
$(Q) { \
$(if $(CONFIG_ESP32S3_FLASH_4M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_4MB)) \
$(if $(CONFIG_ESP32S3_FLASH_8M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_8MB)) \
$(if $(CONFIG_ESP32S3_FLASH_16M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_16MB)) \
$(if $(CONFIG_ESP32S3_FLASH_MODE_DIO),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_DIO)) \
$(if $(CONFIG_ESP32S3_FLASH_MODE_DOUT),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_DOUT)) \
$(if $(CONFIG_ESP32S3_FLASH_MODE_QIO),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_QIO)) \
$(if $(CONFIG_ESP32S3_FLASH_MODE_QOUT),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_QOUT)) \
$(if $(CONFIG_ESP32S3_FLASH_FREQ_120M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_120M)) \
$(if $(CONFIG_ESP32S3_FLASH_FREQ_80M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_80M)) \
$(if $(CONFIG_ESP32S3_FLASH_FREQ_40M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_40M)) \
$(if $(CONFIG_ESP32S3_FLASH_FREQ_20M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_20M)) \
} > $(BOOTLOADER_CONFIG)
ifeq ($(CONFIG_ESP32S3_APP_FORMAT_LEGACY),y)
$(Q) { \
$(call cfg_en,CONFIG_PARTITION_TABLE_CUSTOM) \
$(call cfg_val,CONFIG_PARTITION_TABLE_CUSTOM_FILENAME,\"partitions.csv\") \
$(call cfg_val,CONFIG_PARTITION_TABLE_OFFSET,$(CONFIG_ESP32S3_PARTITION_TABLE_OFFSET)) \
} >> $(BOOTLOADER_CONFIG)
endif
bootloader: $(BOOTLOADER_SRCDIR) $(BOOTLOADER_CONFIG)
$(Q) echo "Building Bootloader binaries"
$(Q) $(BOOTLOADER_SRCDIR)/build_idfboot.sh -c esp32s3 -s -f $(BOOTLOADER_CONFIG)
$(call COPYFILE,$(BOOTLOADER_SRCDIR)/$(BOOTLOADER_OUTDIR)/bootloader-esp32s3.bin,$(TOPDIR))
$(call COPYFILE,$(BOOTLOADER_SRCDIR)/$(BOOTLOADER_OUTDIR)/partition-table-esp32s3.bin,$(TOPDIR))
clean_bootloader:
$(call DELDIR,$(BOOTLOADER_SRCDIR))
$(call DELFILE,$(BOOTLOADER_CONFIG))
$(call DELFILE,$(TOPDIR)/bootloader-esp32s3.bin)
$(call DELFILE,$(TOPDIR)/partition-table-esp32s3.bin)
else ifeq ($(CONFIG_ESP32S3_BOOTLOADER_DOWNLOAD_PREBUILT),y)
BOOTLOADER_VERSION = latest
BOOTLOADER_URL = https://github.com/espressif/esp-nuttx-bootloader/releases/download/$(BOOTLOADER_VERSION)
bootloader:
$(Q) echo "Downloading Bootloader binaries"
$(Q) curl -L $(BOOTLOADER_URL)/bootloader-esp32s3.bin -o $(TOPDIR)/bootloader-esp32s3.bin
$(Q) curl -L $(BOOTLOADER_URL)/partition-table-esp32s3.bin -o $(TOPDIR)/partition-table-esp32s3.bin
clean_bootloader:
$(call DELFILE,$(TOPDIR)/bootloader-esp32s3.bin)
$(call DELFILE,$(TOPDIR)/partition-table-esp32s3.bin)
endif

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#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_CHIP_ESP32S3
comment "ESP32-S3 Configuration Options"
choice
prompt "ESP32-S3 Chip Selection"
default ARCH_CHIP_ESP32S3WROOM1
config ARCH_CHIP_ESP32S3WROOM1
bool "ESP32-S3-WROOM-1"
select ESP32S3_FLASH_4M
---help---
Generic module with an embedded ESP32-S3.
config ARCH_CHIP_ESP32S3WROOM2
bool "ESP32-S3-WROOM-2"
select ESP32S3_FLASH_16M
select ESP32S3_PSRAM_8M
---help---
Generic module with an embedded ESP32-S3.
config ARCH_CHIP_ESP32S3MINI1
bool "ESP32-S3-MINI-1"
select ESP32S3_FLASH_8M
---help---
Generic module with an embedded ESP32-S3.
endchoice # ESP32-S3 Chip Selection
choice ESP32S3_DEFAULT_CPU_FREQ
prompt "CPU frequency"
default ESP32S3_DEFAULT_CPU_FREQ_240
---help---
CPU frequency to be set on application startup.
config ESP32S3_DEFAULT_CPU_FREQ_80
bool "80 MHz"
config ESP32S3_DEFAULT_CPU_FREQ_160
bool "160 MHz"
config ESP32S3_DEFAULT_CPU_FREQ_240
bool "240 MHz"
endchoice # CPU frequency
config ESP32S3_DEFAULT_CPU_FREQ_MHZ
int
default 80 if ESP32S3_DEFAULT_CPU_FREQ_80
default 160 if ESP32S3_DEFAULT_CPU_FREQ_160
default 240 if ESP32S3_DEFAULT_CPU_FREQ_240
menu "Cache config"
choice
prompt "Instruction cache size"
default ESP32S3_INSTRUCTION_CACHE_16KB
---help---
Instruction cache size to be set on application startup.
If you use 16KB instruction cache rather than 32KB instruction cache,
then the other 16KB will be managed by heap allocator.
config ESP32S3_INSTRUCTION_CACHE_16KB
bool "16KB"
---help---
Use 16KB of SRAM as Instruction Cache
config ESP32S3_INSTRUCTION_CACHE_32KB
bool "32KB"
---help---
Use 32KB of SRAM as Instruction Cache
endchoice # Instruction cache size
config ESP32S3_INSTRUCTION_CACHE_SIZE
hex
default 0x4000 if ESP32S3_INSTRUCTION_CACHE_16KB
default 0x8000 if ESP32S3_INSTRUCTION_CACHE_32KB
choice ESP32S3_ICACHE_ASSOCIATED_WAYS
prompt "Instruction cache associated ways"
default ESP32S3_INSTRUCTION_CACHE_8WAYS
---help---
Instruction cache associated ways to be set on application startup.
config ESP32S3_INSTRUCTION_CACHE_4WAYS
bool "4 ways"
config ESP32S3_INSTRUCTION_CACHE_8WAYS
bool "8 ways"
endchoice
config ESP32S3_ICACHE_ASSOCIATED_WAYS
int
default 4 if ESP32S3_INSTRUCTION_CACHE_4WAYS
default 8 if ESP32S3_INSTRUCTION_CACHE_8WAYS
choice ESP32S3_INSTRUCTION_CACHE_LINE_SIZE
prompt "Instruction cache line size"
default ESP32S3_INSTRUCTION_CACHE_LINE_32B
---help---
Instruction cache line size to be set on application startup.
config ESP32S3_INSTRUCTION_CACHE_LINE_16B
bool "16 Bytes"
depends on ESP32S3_INSTRUCTION_CACHE_16KB
config ESP32S3_INSTRUCTION_CACHE_LINE_32B
bool "32 Bytes"
endchoice
config ESP32S3_INSTRUCTION_CACHE_LINE_SIZE
int
default 16 if ESP32S3_INSTRUCTION_CACHE_LINE_16B
default 32 if ESP32S3_INSTRUCTION_CACHE_LINE_32B
choice
prompt "Data cache size"
default ESP32S3_DATA_CACHE_32KB
---help---
Data cache size to be set on application startup.
If you use 32KB data cache rather than 64KB data cache,
the other 32KB will be added to the heap.
config ESP32S3_DATA_CACHE_16KB
bool "16KB"
---help---
Use 16KB of SRAM as Data Cache
config ESP32S3_DATA_CACHE_32KB
bool "32KB"
---help---
Use 32KB of SRAM as Data Cache
config ESP32S3_DATA_CACHE_64KB
bool "64KB"
---help---
Use 64KB of SRAM as Data Cache
endchoice # Data cache size
config ESP32S3_DATA_CACHE_SIZE
hex
# For 16KB the actual configuration is 32kb cache, but 16kb will be reserved for heap at startup
default 0x8000 if ESP32S3_DATA_CACHE_16KB
default 0x8000 if ESP32S3_DATA_CACHE_32KB
default 0x10000 if ESP32S3_DATA_CACHE_64KB
choice ESP32S3_DCACHE_ASSOCIATED_WAYS
prompt "Data cache associated ways"
default ESP32S3_DATA_CACHE_8WAYS
---help---
Data cache associated ways to be set on application startup.
config ESP32S3_DATA_CACHE_4WAYS
bool "4 ways"
config ESP32S3_DATA_CACHE_8WAYS
bool "8 ways"
endchoice
config ESP32S3_DCACHE_ASSOCIATED_WAYS
int
default 4 if ESP32S3_DATA_CACHE_4WAYS
default 8 if ESP32S3_DATA_CACHE_8WAYS
choice ESP32S3_DATA_CACHE_LINE_SIZE
prompt "Data cache line size"
default ESP32S3_DATA_CACHE_LINE_32B
---help---
Data cache line size to be set on application startup.
config ESP32S3_DATA_CACHE_LINE_16B
bool "16 Bytes"
depends on ESP32S3_DATA_CACHE_16KB || ESP32S3_DATA_CACHE_32KB
config ESP32S3_DATA_CACHE_LINE_32B
bool "32 Bytes"
config ESP32S3_DATA_CACHE_LINE_64B
bool "64 Bytes"
endchoice
config ESP32S3_DATA_CACHE_LINE_SIZE
int
default 16 if ESP32S3_DATA_CACHE_LINE_16B
default 32 if ESP32S3_DATA_CACHE_LINE_32B
default 64 if ESP32S3_DATA_CACHE_LINE_64B
endmenu # Cache config
config ESP32S3_ULP_COPROC_ENABLED
bool "Enable Ultra Low Power (ULP) Coprocessor"
default n
---help---
Set to 'y' if you plan to load a firmware for the coprocessor.
config ESP32S3_ULP_COPROC_RESERVE_MEM
int
prompt "RTC slow memory reserved for coprocessor" if ESP32S3_ULP_COPROC_ENABLED
default 512 if ESP32S3_ULP_COPROC_ENABLED
range 32 8176 if ESP32S3_ULP_COPROC_ENABLED
default 0 if !ESP32S3_ULP_COPROC_ENABLED
range 0 0 if !ESP32S3_ULP_COPROC_ENABLED
help
Bytes of memory to reserve for ULP coprocessor firmware & data.
Data is reserved at the beginning of RTC slow memory.
config ESP32S3_FLASH_4M
bool
default n
config ESP32S3_FLASH_8M
bool
default n
config ESP32S3_FLASH_16M
bool
default n
config ESP32S3_ESPTOOLPY_NO_STUB
bool "Disable download stub"
default n
---help---
The flasher tool sends a precompiled download stub first by default.
That stub allows things like compressed downloads and more.
Usually you should not need to disable that feature.
It is only required to be disabled in certain scenarios when either
Secure Boot V2 or Flash Encryption is enabled.
config ESP32S3_FLASH_DETECT
bool "Auto-detect FLASH size"
default y
---help---
Auto detect flash size when flashing.
config ESP32S3_PSRAM_8M
bool
default n
choice ESP32S3_FLASH_MODE
prompt "SPI FLASH mode"
default ESP32S3_FLASH_MODE_DIO
---help---
These options control how many I/O pins are used for communication
with the attached SPI flash chip.
The option selected here is then used by esptool when flashing.
config ESP32S3_FLASH_MODE_DIO
bool "Dual IO (DIO)"
config ESP32S3_FLASH_MODE_DOUT
bool "Dual Output (DOUT)"
config ESP32S3_FLASH_MODE_QIO
bool "Quad IO (QIO)"
config ESP32S3_FLASH_MODE_QOUT
bool "Quad Output (QOUT)"
endchoice # ESP32S3_FLASH_MODE
choice ESP32S3_FLASH_FREQ
prompt "SPI FLASH frequency"
default ESP32S3_FLASH_FREQ_40M
---help---
SPI FLASH frequency
config ESP32S3_FLASH_FREQ_120M
bool "120 MHz"
config ESP32S3_FLASH_FREQ_80M
bool "80 MHz"
config ESP32S3_FLASH_FREQ_40M
bool "40 MHz"
config ESP32S3_FLASH_FREQ_20M
bool "20 MHz"
endchoice # ESP32S3_FLASH_FREQ
config ESP32S3_RUN_IRAM
bool "Run from IRAM"
default n
---help---
This loads all of NuttX inside IRAM. Used to test somewhat small
images that can fit entirely in IRAM.
menu "ESP32-S3 Peripheral Selection"
config ESP32S3_UART
bool
default n
config ESP32S3_UART0
bool "UART 0"
default n
select ESP32S3_UART
select UART0_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config ESP32S3_UART1
bool "UART 1"
default n
select ESP32S3_UART
select UART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config ESP32S3_UART2
bool "UART 2"
default n
select ESP32S3_UART
select UART2_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
endmenu # ESP32S3 Peripheral Selection
menu "UART configuration"
depends on ESP32S3_UART
if ESP32S3_UART0
config ESP32S3_UART0_TXPIN
int "UART0 Tx Pin"
default 43
range 0 48
config ESP32S3_UART0_RXPIN
int "UART0 Rx Pin"
default 44
range 0 48
config ESP32S3_UART0_RTSPIN
int "UART0 RTS Pin"
depends on SERIAL_IFLOWCONTROL
default 15
range 0 48
config ESP32S3_UART0_CTSPIN
int "UART0 CTS Pin"
depends on SERIAL_OFLOWCONTROL
default 16
range 0 48
endif # ESP32S3_UART0
if ESP32S3_UART1
config ESP32S3_UART1_TXPIN
int "UART1 Tx Pin"
default 17
range 0 48
config ESP32S3_UART1_RXPIN
int "UART1 Rx Pin"
default 18
range 0 48
config ESP32S3_UART1_RTSPIN
int "UART1 RTS Pin"
depends on SERIAL_IFLOWCONTROL
default 19
range 0 48
config ESP32S3_UART1_CTSPIN
int "UART1 CTS Pin"
depends on SERIAL_OFLOWCONTROL
default 20
range 0 48
endif # ESP32S3_UART1
if ESP32S3_UART2
config ESP32S3_UART2_TXPIN
int "UART2 Tx Pin"
default 17
range 0 48
config ESP32S3_UART2_RXPIN
int "UART2 Rx Pin"
default 16
range 0 48
config ESP32S3_UART2_RTSPIN
int "UART2 RTS Pin"
depends on SERIAL_IFLOWCONTROL
default 35
range 0 48
config ESP32S3_UART2_CTSPIN
int "UART2 CTS Pin"
depends on SERIAL_OFLOWCONTROL
default 36
range 0 48
endif # ESP32S3_UART2
endmenu # UART configuration
menu "Application Image Configuration"
choice
prompt "Application Image Format"
default ESP32S3_APP_FORMAT_LEGACY
---help---
Depending on the chosen 2nd stage bootloader, the application may
be required to be perform a specific startup routine. Furthermore,
the image binary must be formatted according to the definition from
the 2nd stage bootloader.
config ESP32S3_APP_FORMAT_LEGACY
bool "Legacy format"
---help---
This is the legacy application image format, as supported by the ESP-IDF
2nd stage bootloader.
endchoice # Application Image Format
choice
prompt "Source for bootloader binaries"
default ESP32S3_BOOTLOADER_DOWNLOAD_PREBUILT
---help---
Select the action to be taken by the build system for the
"make bootloader" target.
config ESP32S3_BOOTLOADER_DOWNLOAD_PREBUILT
bool "Download prebuilt binaries"
---help---
The build system will download the prebuilt binaries from
https://github.com/espressif/esp-nuttx-bootloader according to the chosen
Application Image Format (ESP32S3_APP_FORMAT_LEGACY or ESP32S3_APP_FORMAT_MCUBOOT)
config ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE
bool "Build binaries from source"
---help---
The build system will build all the required binaries from source. It will clone
the https://github.com/espressif/esp-nuttx-bootloader repository and build a
custom bootloader according to the chosen Application Image Format
(ESP32S3_APP_FORMAT_LEGACY or ESP32S3_APP_FORMAT_MCUBOOT) and partition information.
endchoice
config ESP32S3_PARTITION_TABLE_OFFSET
hex "Partition Table offset"
default 0x8000
depends on ESP32S3_APP_FORMAT_LEGACY
endmenu # Application Image Configuration
endif # ARCH_CHIP_ESP32S3

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############################################################################
# arch/xtensa/src/esp32s3/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include chip/Bootloader.mk
# The start-up, "head", file. May be either a .S or a .c file.
HEAD_ASRC = xtensa_vectors.S xtensa_window_vector.S xtensa_windowspill.S
HEAD_ASRC += xtensa_int_handlers.S xtensa_user_handler.S
HEAD_CSRC = esp32s3_start.c
# Common XTENSA files (arch/xtensa/src/common)
CMN_ASRCS = xtensa_context.S xtensa_coproc.S xtensa_cpuint.S xtensa_panic.S
CMN_ASRCS += xtensa_sigtramp.S
CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c
CMN_CSRCS += xtensa_cpenable.c xtensa_createstack.c xtensa_exit.c
CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c xtensa_interruptcontext.c
CMN_CSRCS += xtensa_irqdispatch.c xtensa_lowputs.c xtensa_mdelay.c
CMN_CSRCS += xtensa_modifyreg8.c xtensa_modifyreg16.c xtensa_modifyreg32.c
CMN_CSRCS += xtensa_puts.c xtensa_releasepending.c xtensa_releasestack.c
CMN_CSRCS += xtensa_reprioritizertr.c xtensa_schedsigaction.c
CMN_CSRCS += xtensa_sigdeliver.c xtensa_stackframe.c xtensa_udelay.c
CMN_CSRCS += xtensa_unblocktask.c xtensa_usestack.c
# Configuration-dependent common XTENSA files
ifeq ($(CONFIG_DEBUG_ALERT),y)
CMN_CSRCS += xtensa_dumpstate.c
endif
ifeq ($(CONFIG_SPINLOCK),y)
CMN_CSRCS += xtensa_testset.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += xtensa_checkstack.c
endif
ifeq ($(CONFIG_XTENSA_SEMIHOSTING_HOSTFS),y)
CMN_ASRCS += xtensa_simcall.S
CMN_CSRCS += xtensa_hostfs.c
endif
# Required ESP32-S3 files (arch/xtensa/src/esp32s3)
CHIP_CSRCS = esp32s3_irq.c esp32s3_clockconfig.c esp32s3_region.c
CHIP_CSRCS += esp32s3_timerisr.c esp32s3_user.c esp32s3_allocateheap.c
CHIP_CSRCS += esp32s3_wdt.c esp32s3_gpio.c esp32s3_lowputc.c esp32s3_serial.c
CHIP_CSRCS += esp32s3_systemreset.c
# Configuration-dependent ESP32-S3 files
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CHIP_CSRCS += esp32s3_idle.c
endif

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/****************************************************************************
* arch/xtensa/src/esp32s3/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_CHIP_H
#define __ARCH_XTENSA_SRC_ESP32S3_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip_macros.h"
#include "chip_memory.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32S3_CHIP_H */

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/****************************************************************************
* arch/xtensa/src/esp32s3/chip_macros.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_CHIP_MACROS_H
#define __ARCH_XTENSA_SRC_ESP32S3_CHIP_MACROS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* This is the name of the section containing the Xtensa low level handlers
* that is used by the board linker scripts.
*/
#define HANDLER_SECTION .iram1
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Assembly Language Macros
****************************************************************************/
#ifdef __ASSEMBLY__
/* Macro to get the current core ID. Only uses the reg given as an argument.
* Reading PRID on the ESP108 architecture gives us 0xcdcd on the PRO
* processor and 0xabab on the APP CPU. We distinguish between the two by
* simply checking bit 1: it's 1 on the APP and 0 on the PRO processor.
*/
.macro getcoreid reg
rsr.prid \reg
bbci \reg, 1, 1f
movi \reg, 1
j 2f
1:
movi \reg, 0
2:
.endm
#endif /* __ASSEMBLY */
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32S3_CHIP_MACROS_H */

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/****************************************************************************
* arch/xtensa/src/esp32s3/chip_memory.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_CHIP_MEMORY_H
#define __ARCH_XTENSA_SRC_ESP32S3_CHIP_MEMORY_H
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ASSEMBLY__
#include <stdbool.h>
#include <stdint.h>
#include "hardware/esp32s3_soc.h"
#endif
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: xtensa_sp_sane
****************************************************************************/
static inline bool xtensa_sp_sane(uint32_t sp)
{
return (esp32s3_sp_dram(sp) && ((sp & 0x0f) == 0));
}
/****************************************************************************
* Name: xtensa_ptr_extram
****************************************************************************/
static inline bool xtensa_ptr_exec(const void *p)
{
return esp32s3_ptr_exec(p);
}
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32S3_CHIP_MEMORY_H */

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/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_allocateheap.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <debug.h>
#include <nuttx/mm/mm.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "xtensa.h"
#include "hardware/esp32s3_rom_layout.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_allocate_heap
*
* Description:
* This function will be called to dynamically set aside the heap region.
*
* For the kernel build (CONFIG_BUILD_KERNEL=y) with both kernel- and
* user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
* size of the unprotected, user-space heap.
*
* If a protected kernel-space heap is provided, the kernel heap must be
* allocated (and protected) by an analogous up_allocate_kheap().
*
****************************************************************************/
void up_allocate_heap(void **heap_start, size_t *heap_size)
{
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (void *)&_sheap;
*heap_size = (size_t)(ets_rom_layout_p->dram0_rtos_reserved_start -
(uintptr_t)&_sheap);
}
/****************************************************************************
* Name: xtensa_add_region
*
* Description:
* RAM may be added in non-contiguous chunks. This routine adds all chunks
* that may be used for heap.
*
****************************************************************************/
#if CONFIG_MM_REGIONS > 1
void xtensa_add_region(void)
{
}
#endif

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/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_clockconfig.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "hardware/esp32s3_soc.h"
#include "hardware/esp32s3_uart.h"
#include "hardware/esp32s3_system.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef MIN
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#define DEFAULT_CPU_FREQ 80
/****************************************************************************
* Private Types
****************************************************************************/
enum cpu_freq_e
{
CPU_80M = 0,
CPU_160M = 1,
CPU_240M = 2,
};
enum cpu_clksrc_e
{
XTAL_CLK,
PLL_CLK,
FOSC_CLK
};
enum pll_freq_e
{
PLL_320,
PLL_480
};
/****************************************************************************
* ROM Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: ets_update_cpu_frequency
*
* Description:
* Set the real CPU ticks per us to the ets, so that ets_delay_us will be
* accurate. Call this function when CPU frequency is changed.
*
* Input Parameters:
* ticks_per_us - CPU ticks per us.
*
* Returned Value:
* None
*
****************************************************************************/
extern void ets_update_cpu_frequency(uint32_t ticks_per_us);
/****************************************************************************
* Name: ets_get_cpu_frequency
*
* Description:
* Get the real CPU ticks per us to the ets.
* This function do not return real CPU ticks per us, just the record in
* ets. It can be used to check with the real CPU frequency.
*
* Input Parameters:
* None.
*
* Returned Value:
* CPU ticks per us record in ets.
*
****************************************************************************/
extern uint32_t ets_get_cpu_frequency(void);
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s3_cpuclksrc
*
* Description:
* Select a clock source for CPU clock.
*
* Input Parameters:
* src - Any source from cpu_clksrc_e.
*
* Returned Value:
* None
*
****************************************************************************/
static inline void esp32s3_cpuclksrc(enum cpu_clksrc_e src)
{
uint32_t value;
value = VALUE_TO_FIELD(src, SYSTEM_SOC_CLK_SEL);
modifyreg32(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL_M, value);
}
/****************************************************************************
* Name: esp32s3_cpudiv
*
* Description:
* Select a divider for the CPU clk.
* NOTE: The divider is not necessarily the real divisor. See TRM for the
* equivalences.
*
* Input Parameters:
* divider - A value between 0 to 2.
*
* Returned Value:
* None
*
****************************************************************************/
static inline void esp32s3_cpudiv(uint8_t divider)
{
uint32_t value;
value = VALUE_TO_FIELD(divider, SYSTEM_CPUPERIOD_SEL);
modifyreg32(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL_M, value);
}
/****************************************************************************
* Name: esp32s3_pllfreqsel
*
* Description:
* Select the PLL frequency.
*
* Input Parameters:
* freq - Any clock from enum pll_freq_e
*
* Returned Value:
* None
****************************************************************************/
static inline void esp32s3_pllfreqsel(enum pll_freq_e freq)
{
uint32_t value;
value = VALUE_TO_FIELD(freq, SYSTEM_PLL_FREQ_SEL);
modifyreg32(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL_M, value);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s3_update_cpu_freq
*
* Description:
* Set the real CPU ticks per us to the ets, so that ets_delay_us
* will be accurate. Call this function when CPU frequency is changed.
*
* Input Parameters:
* ticks_per_us - CPU ticks per us
*
* Returned Value:
* None
*
****************************************************************************/
void IRAM_ATTR esp32s3_update_cpu_freq(uint32_t ticks_per_us)
{
/* Update scale factors used by esp_rom_delay_us */
ets_update_cpu_frequency(ticks_per_us);
}
/****************************************************************************
* Name: esp32s3_set_cpu_freq
*
* Description:
* Switch to one of PLL-based frequencies.
*
* Input Parameters:
* cpu_freq_mhz - Target CPU frequency
*
* Returned Value:
* None
*
****************************************************************************/
void IRAM_ATTR esp32s3_set_cpu_freq(int cpu_freq_mhz)
{
switch (cpu_freq_mhz)
{
case 80:
/* 80 MHz is obtained from the 480 MHz PLL.
* In this case CPU_CLK = PLL_CLK / 6. Config the PLL as 480 MHz
* with a 6 divider and set the source clock as PLL_CLK.
*/
esp32s3_cpudiv(0);
break;
case 160:
/* 160 MHz is obtained from the 480 MHz PLL.
* In this case CPU_CLK = PLL_CLK / 3. Config the PLL as 480 MHz
* with a 3 divider and set the source clock as PLL_CLK.
*/
esp32s3_cpudiv(1);
break;
case 240:
/* 240 MHz is obtained from the 480 MHz PLL.
* In this case CPU_CLK = PLL_CLK / 2. Config the PLL as 480 MHz
* with a 2 divider and set the source clock as PLL_CLK.
*/
esp32s3_cpudiv(2);
break;
default:
/* Unsupported clock config. */
return;
}
esp32s3_pllfreqsel(PLL_480);
esp32s3_cpuclksrc(PLL_CLK);
esp32s3_update_cpu_freq(cpu_freq_mhz);
}
/****************************************************************************
* Name: esp32s3_clockconfig
*
* Description:
* Called to initialize the ESP32-S3. This does whatever setup is needed to
* put the SoC in a usable state. This includes the initialization of
* clocking using the settings in board.h.
*
****************************************************************************/
void esp32s3_clockconfig(void)
{
/* Configure the CPU frequency */
esp32s3_set_cpu_freq(CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ);
}
/****************************************************************************
* Name: esp_clk_cpu_freq
*
* Description:
* Get CPU frequency
*
* Input Parameters:
* None
*
* Returned Value:
* CPU frequency
*
****************************************************************************/
int IRAM_ATTR esp_clk_cpu_freq(void)
{
return (int)ets_get_cpu_frequency() * MHZ;
}
/****************************************************************************
* Name: esp_clk_apb_freq
*
* Description:
* Return current APB clock frequency.
*
* Input Parameters:
* None
*
* Returned Value:
* APB clock frequency, in Hz
*
****************************************************************************/
int IRAM_ATTR esp_clk_apb_freq(void)
{
return MIN(ets_get_cpu_frequency(), 80) * MHZ;
}

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/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_clockconfig.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_CLOCKCONFIG_H
#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_CLOCKCONFIG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s3_update_cpu_freq
*
* Description:
* Set the real CPU ticks per us to the ets, so that ets_delay_us
* will be accurate. Call this function when CPU frequency is changed.
*
* Input Parameters:
* ticks_per_us - CPU ticks per us
*
* Returned Value:
* None.
*
****************************************************************************/
void esp32s3_update_cpu_freq(uint32_t ticks_per_us);
/****************************************************************************
* Name: esp32s3_set_cpu_freq
*
* Description:
* Switch to one of PLL-based frequencies.
* Current frequency can be XTAL or PLL.
*
* Input Parameters:
* cpu_freq_mhz - new CPU frequency
*
* Returned Value:
* None.
*
****************************************************************************/
void esp32s3_set_cpu_freq(int cpu_freq_mhz);
/****************************************************************************
* Name: esp32s3_clockconfig
*
* Description:
* Called to initialize the ESP32-S3. This does whatever setup is needed to
* put the SoC in a usable state. This includes the initialization of
* clocking using the settings in board.h.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
void esp32s3_clockconfig(void);
/****************************************************************************
* Name: esp_clk_cpu_freq
*
* Description:
* Get the current CPU frequency.
*
* Input Parameters:
* None.
*
* Returned Value:
* CPU frequency in Hz.
*
****************************************************************************/
int esp_clk_cpu_freq(void);
/****************************************************************************
* Name: esp_clk_apb_freq
*
* Description:
* Return current APB clock frequency.
*
* Input Parameters:
* None.
*
* Returned Value:
* APB clock frequency in Hz.
*
****************************************************************************/
int esp_clk_apb_freq(void);
#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_CLOCKCONFIG_H */

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/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_config.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_CONFIG_H
#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_CONFIG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/chip/chip.h>
#include <arch/board/board.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* UARTs ********************************************************************/
/* Are any UARTs enabled? */
#undef HAVE_UART_DEVICE
#ifdef CONFIG_ESP32S3_UART
# define HAVE_UART_DEVICE 1
#endif
/* Serial Console ***********************************************************/
/* Is there a serial console? There should be no more than one defined. It
* could be on any UARTn. n E {0,1}
*/
#undef CONSOLE_UART
#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_ESP32S3_UART0)
# undef CONFIG_UART1_SERIAL_CONSOLE
# define CONSOLE_UART 1
#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_ESP32S3_UART1)
# undef CONFIG_UART0_SERIAL_CONSOLE
# define CONSOLE_UART 1
#else
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
#endif
#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_CONFIG_H */

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/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_gpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <arch/irq.h>
#include <arch/esp32s3/chip.h>
#include "xtensa.h"
#include "esp32s3_irq.h"
#include "hardware/esp32s3_iomux.h"
#include "hardware/esp32s3_gpio.h"
#include "esp32s3_gpio.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s3_configgpio
*
* Description:
* Configure a GPIO pin based on encoded pin attributes.
*
****************************************************************************/
int esp32s3_configgpio(int pin, gpio_pinattr_t attr)
{
uintptr_t regaddr;
uint32_t func;
uint32_t cntrl;
uint32_t pin2func;
DEBUGASSERT(pin >= 0 && pin <= ESP32S3_NGPIOS);
func = 0;
cntrl = 0;
/* Handle input pins */
if ((attr & INPUT) != 0)
{
putreg32((1ul << pin), GPIO_ENABLE_W1TC_REG);
/* Input enable */
func |= FUN_IE;
if ((attr & PULLUP) != 0)
{
func |= FUN_PU;
}
else if ((attr & PULLDOWN) != 0)
{
func |= FUN_PD;
}
}
/* Handle output pins */
if ((attr & OUTPUT) != 0)
{
putreg32((1ul << pin), GPIO_ENABLE_W1TS_REG);
}
/* Add drivers */
func |= (uint32_t)(2ul << FUN_DRV_S);
/* Select the pad's function. If no function was given, consider it a
* normal input or output (i.e. function1).
*/
if ((attr & FUNCTION_MASK) != 0)
{
func |= (uint32_t)(((attr >> FUNCTION_SHIFT) - 1) << MCU_SEL_S);
}
else
{
func |= (uint32_t)(PIN_FUNC_GPIO << MCU_SEL_S);
}
if ((attr & OPEN_DRAIN) != 0)
{
cntrl |= (1 << GPIO_PIN_PAD_DRIVER_S);
}
/* Set the pin function to its register */
pin2func = (pin + 1) * 4;
regaddr = REG_IO_MUX_BASE + pin2func;
putreg32(func, regaddr);
regaddr = GPIO_REG(pin);
putreg32(cntrl, regaddr);
return OK;
}
/****************************************************************************
* Name: esp32s3_gpio_matrix_in
*
* Description:
* Set gpio input to a signal
* NOTE: one gpio can input to several signals
* If gpio == 0x3c, cancel input to the signal, input 0 to signal.
* If gpio == 0x3a, input nothing to signal.
* If gpio == 0x38, cancel input to the signal, input 1 to signal.
*
****************************************************************************/
void esp32s3_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv)
{
uint32_t regaddr = GPIO_FUNC0_IN_SEL_CFG_REG + (signal_idx * 4);
uint32_t regval = (gpio << GPIO_FUNC0_IN_SEL_S);
if (inv)
{
regval |= GPIO_FUNC0_IN_INV_SEL;
}
if (gpio != 0x3a)
{
regval |= GPIO_SIG0_IN_SEL;
}
putreg32(regval, regaddr);
}
/****************************************************************************
* Name: esp32s3_gpio_matrix_out
*
* Description:
* Set signal output to gpio
* NOTE: one signal can output to several gpios
* If signal_idx == 0x100, cancel output put to the gpio
*
****************************************************************************/
void esp32s3_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx,
bool out_inv, bool oen_inv)
{
uint32_t regaddr = GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio * 4);
uint32_t regval = signal_idx << GPIO_FUNC0_OUT_SEL_S;
if (gpio >= ESP32S3_NGPIOS)
{
return;
}
putreg32(1ul << gpio, GPIO_ENABLE_W1TS_REG);
if (out_inv)
{
regval |= GPIO_FUNC0_OUT_INV_SEL;
}
if (oen_inv)
{
regval |= GPIO_FUNC0_OEN_INV_SEL;
}
putreg32(regval, regaddr);
}

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/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_GPIO_H
#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define MATRIX_DETACH_OUT_SIG 0x100 /* Detach an OUTPUT signal */
#define MATRIX_DETACH_IN_LOW_PIN 0x3c /* Detach non-inverted INPUT signal */
#define MATRIX_DETACH_IN_LOW_HIGH 0x38 /* Detach inverted INPUT signal */
/* Bit-encoded input to esp32s3_configgpio() ********************************/
/* Encoded pin attributes used with esp32s3_configgpio()
*
* 8 7 6 5 4 3 2 1 0
* -- -- -- -- -- -- -- -- --
* FN FN FN OD PD PU F O I
*/
#define PINMODE_SHIFT 0
#define PINMODE_MASK (7 << PINMODE_SHIFT)
# define INPUT (1 << 0)
# define OUTPUT (1 << 1)
# define FUNCTION (1 << 2)
#define PULLUP (1 << 3)
#define PULLDOWN (1 << 4)
#define OPEN_DRAIN (1 << 5)
#define FUNCTION_SHIFT 6
#define FUNCTION_MASK (7 << FUNCTION_SHIFT)
# define FUNCTION_0 (1 << FUNCTION_SHIFT)
# define FUNCTION_1 (2 << FUNCTION_SHIFT)
# define FUNCTION_2 (3 << FUNCTION_SHIFT)
# define FUNCTION_3 (4 << FUNCTION_SHIFT)
# define FUNCTION_4 (5 << FUNCTION_SHIFT)
#define INPUT_PULLUP (INPUT | PULLUP)
#define INPUT_PULLDOWN (INPUT | PULLDOWN)
#define OUTPUT_OPEN_DRAIN (OUTPUT | OPEN_DRAIN)
#define INPUT_FUNCTION (INPUT | FUNCTION)
# define INPUT_FUNCTION_0 (INPUT_FUNCTION | FUNCTION_0)
# define INPUT_FUNCTION_1 (INPUT_FUNCTION | FUNCTION_1)
# define INPUT_FUNCTION_2 (INPUT_FUNCTION | FUNCTION_2)
# define INPUT_FUNCTION_3 (INPUT_FUNCTION | FUNCTION_3)
# define INPUT_FUNCTION_4 (INPUT_FUNCTION | FUNCTION_4)
#define OUTPUT_FUNCTION (OUTPUT | FUNCTION)
# define OUTPUT_FUNCTION_0 (OUTPUT_FUNCTION | FUNCTION_0)
# define OUTPUT_FUNCTION_1 (OUTPUT_FUNCTION | FUNCTION_1)
# define OUTPUT_FUNCTION_2 (OUTPUT_FUNCTION | FUNCTION_2)
# define OUTPUT_FUNCTION_3 (OUTPUT_FUNCTION | FUNCTION_3)
# define OUTPUT_FUNCTION_4 (OUTPUT_FUNCTION | FUNCTION_4)
/* Interrupt type used with esp32s3_gpioirqenable() */
#define DISABLED 0x00
#define RISING 0x01
#define FALLING 0x02
#define CHANGE 0x03
#define ONLOW 0x04
#define ONHIGH 0x05
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/* Must be big enough to hold the above encodings */
typedef uint16_t gpio_pinattr_t;
typedef uint8_t gpio_intrtype_t;
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s3_configgpio
*
* Description:
* Configure a GPIO pin based on encoded pin attributes.
*
****************************************************************************/
int esp32s3_configgpio(int pin, gpio_pinattr_t attr);
/****************************************************************************
* Name: esp32s3_gpio_matrix_in
*
* Description:
* Set gpio input to a signal
* NOTE: one gpio can input to several signals
* If gpio == 0x3c, cancel input to the signal, input 0 to signal.
* If gpio == 0x3a, input nothing to signal.
* If gpio == 0x38, cancel input to the signal, input 1 to signal.
*
****************************************************************************/
void esp32s3_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
/****************************************************************************
* Name: esp32s3_gpio_matrix_out
*
* Description:
* Set signal output to gpio
* NOTE: one signal can output to several gpios
* If signal_idx == 0x100, cancel output put to the gpio
*
****************************************************************************/
void esp32s3_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx,
bool out_inv, bool oen_inv);
#ifdef __cplusplus
}
#endif
#undef EXTERN
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_GPIO_H */

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/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_idle.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/board/board.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include "xtensa.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_idle
*
* Description:
* up_idle() is the logic that will be executed when their is no other
* ready-to-run task. This is processor idle time and will continue until
* some interrupt occurs to cause a context switch from the idle task.
*
* Processing in this state may be processor-specific. e.g., this is where
* power management operations might be performed.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
nxsched_process_timer();
#else
/* This would be an appropriate place to put some MCU-specific logic to
* sleep in a reduced power mode until an interrupt occurs to save power
*/
#if XCHAL_HAVE_INTERRUPTS
__asm__ __volatile__ ("waiti 0");
#endif
#endif
}

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/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_irq.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <string.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <arch/irq.h>
#include <arch/board/board.h>
#include "xtensa.h"
#include "hardware/esp32s3_soc.h"
#include "hardware/esp32s3_system.h"
#include "hardware/esp32s3_interrupt_core0.h"
#include "esp32s3_irq.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ to CPU and CPU interrupts mapping:
*
* Encoding: CIIIIIII
* C: CPU that enabled the interrupt (0 = PRO, 1 = APP).
* I: Associated CPU interrupt.
*/
#define IRQ_UNMAPPED 0xff
#define IRQ_GETCPU(m) (((m) & 0x80) >> 0x07)
#define IRQ_GETCPUINT(m) ((m) & 0x7f)
#define IRQ_MKMAP(c, i) (((c) << 0x07) | (i))
/* CPU interrupts to peripheral mapping:
*
* Encoding: EPPPPPPP
* E: CPU interrupt status (0 = Disabled, 1 = Enabled).
* P: Attached peripheral.
*/
#define CPUINT_UNASSIGNED 0x7f
#define CPUINT_GETEN(m) (((m) & 0x80) >> 0x07)
#define CPUINT_GETIRQ(m) ((m) & 0x7f)
#define CPUINT_ASSIGN(c) (((c) & 0x7f) | 0x80)
#define CPUINT_DISABLE(m) ((m) & 0x7f)
#define CPUINT_ENABLE(m) ((m) | 0x80)
/* Mapping Peripheral IDs to map register addresses. */
#define CORE0_MAP_REGADDR(n) (DR_REG_INTERRUPT_CORE0_BASE + ((n) << 2))
/* CPU interrupts can be detached from any peripheral source by setting the
* map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29).
*/
#define NO_CPUINT ESP32S3_CPUINT_TIMER0
/* Priority range is 1-5 */
#define ESP32S3_MIN_PRIORITY 1
#define ESP32S3_MAX_PRIORITY 5
#define ESP32S3_PRIO_INDEX(p) ((p) - ESP32S3_MIN_PRIORITY)
/****************************************************************************
* Public Data
****************************************************************************/
/* g_current_regs[] holds a reference to the current interrupt level
* register storage structure. It is non-NULL only during interrupt
* processing. Access to g_current_regs[] must be through the macro
* CURRENT_REGS for portability.
*/
volatile uint32_t *g_current_regs[1];
/****************************************************************************
* Private Data
****************************************************************************/
/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */
static uint8_t g_cpu0_intmap[ESP32S3_NCPUINTS];
static volatile uint8_t g_irqmap[NR_IRQS];
/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register
* content.
*/
static uint32_t g_intenable[1];
/* Bitsets for free, unallocated CPU interrupts available to peripheral
* devices.
*/
static uint32_t g_cpu0_freeints = ESP32S3_CPUINT_PERIPHSET;
/* Bitsets for each interrupt priority 1-5 */
static const uint32_t g_priority[5] =
{
ESP32S3_INTPRI1_MASK,
ESP32S3_INTPRI2_MASK,
ESP32S3_INTPRI3_MASK,
ESP32S3_INTPRI4_MASK,
ESP32S3_INTPRI5_MASK
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s3_intinfo
*
* Description:
* Return the CPU interrupt map of the given CPU and the register map
* of the given peripheral.
*
****************************************************************************/
static void esp32s3_intinfo(int cpu, int periphid,
uintptr_t *regaddr, uint8_t **intmap)
{
*regaddr = CORE0_MAP_REGADDR(periphid);
*intmap = g_cpu0_intmap;
}
/****************************************************************************
* Name: esp32s3_getcpuint
*
* Description:
* Get a free CPU interrupt for a peripheral device. This function will
* not ignore all of the pre-allocated CPU interrupts for internal
* devices.
*
* Input Parameters:
* intmask - mask of candidate CPU interrupts. The CPU interrupt will be
* be allocated from free interrupts within this set
*
* Returned Value:
* On success, a CPU interrupt number is returned.
* A negated errno is returned on failure.
*
****************************************************************************/
static int esp32s3_getcpuint(uint32_t intmask)
{
uint32_t *freeints;
uint32_t bitmask;
uint32_t intset;
int cpuint;
int ret = -ENOMEM;
int cpu = 0;
/* Check if there are CPU interrupts with the requested properties
* available.
*/
cpu = up_cpu_index();
freeints = &g_cpu0_freeints;
intset = *freeints & intmask;
if (intset != 0)
{
/* Skip over initial unavailable CPU interrupts quickly in groups
* of 8 interrupt.
*/
for (cpuint = 0, bitmask = 0xff;
cpuint <= ESP32S3_CPUINT_MAX && (intset & bitmask) == 0;
cpuint += 8, bitmask <<= 8);
/* Search for an unallocated CPU interrupt number in the remaining
* intset.
*/
for (; cpuint <= ESP32S3_CPUINT_MAX; cpuint++)
{
/* If the bit corresponding to the CPU interrupt is '1', then
* that CPU interrupt is available.
*/
bitmask = 1ul << cpuint;
if ((intset & bitmask) != 0)
{
/* Got it! */
*freeints &= ~bitmask;
ret = cpuint;
break;
}
}
}
/* Enable the CPU interrupt now. The interrupt is still not attached
* to any peripheral and thus has no effect.
*/
if (ret >= 0)
{
xtensa_enable_cpuint(&g_intenable[cpu], 1ul << ret);
}
return ret;
}
/****************************************************************************
* Name: esp32s3_alloc_cpuint
*
* Description:
* Allocate a level CPU interrupt
*
* Input Parameters:
* priority - Priority of the CPU interrupt (1-5)
* type - Interrupt type (level or edge).
*
* Returned Value:
* On success, the allocated CPU interrupt number is returned.
* A negated errno is returned on failure. The only possible failure
* is that all CPU interrupts of the requested type have already been
* allocated.
*
****************************************************************************/
static int esp32s3_alloc_cpuint(int priority, int type)
{
uint32_t mask;
DEBUGASSERT(priority >= ESP32S3_MIN_PRIORITY &&
priority <= ESP32S3_MAX_PRIORITY);
DEBUGASSERT(type == ESP32S3_CPUINT_LEVEL ||
type == ESP32S3_CPUINT_EDGE);
if (type == ESP32S3_CPUINT_LEVEL)
{
/* Check if there are any level CPU interrupts available at the
* requested interrupt priority.
*/
mask = g_priority[ESP32S3_PRIO_INDEX(priority)] &
ESP32S3_CPUINT_LEVELSET;
}
else
{
/* Check if there are any edge CPU interrupts available at the
* requested interrupt priority.
*/
mask = g_priority[ESP32S3_PRIO_INDEX(priority)] &
ESP32S3_CPUINT_EDGESET;
}
return esp32s3_getcpuint(mask);
}
/****************************************************************************
* Name: esp32s3_free_cpuint
*
* Description:
* Free a previously allocated CPU interrupt
*
* Input Parameters:
* The CPU interrupt number to be freed
*
* Returned Value:
* None
*
****************************************************************************/
static void esp32s3_free_cpuint(int cpuint)
{
uint32_t *freeints;
uint32_t bitmask;
DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX);
/* Mark the CPU interrupt as available */
bitmask = 1ul << cpuint;
freeints = &g_cpu0_freeints;
DEBUGASSERT((*freeints & bitmask) == 0);
*freeints |= bitmask;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_irqinitialize
****************************************************************************/
void up_irqinitialize(void)
{
int i;
for (i = 0; i < NR_IRQS; i++)
{
g_irqmap[i] = IRQ_UNMAPPED;
}
/* Hard code special cases. */
g_irqmap[XTENSA_IRQ_TIMER0] = IRQ_MKMAP(0, ESP32S3_CPUINT_TIMER0);
/* Initialize CPU interrupts */
esp32s3_cpuint_initialize();
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* And finally, enable interrupts. Also clears PS.EXCM */
up_irq_enable();
#endif
}
/****************************************************************************
* Name: up_disable_irq
*
* Description:
* Disable the IRQ specified by 'irq'
*
****************************************************************************/
void up_disable_irq(int irq)
{
int cpu = IRQ_GETCPU(g_irqmap[irq]);
int cpuint = IRQ_GETCPUINT(g_irqmap[irq]);
if (g_irqmap[irq] == IRQ_UNMAPPED)
{
/* This interrupt is already disabled. */
return;
}
DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX);
DEBUGASSERT(cpu == 0);
if (irq < XTENSA_NIRQ_INTERNAL)
{
/* This is an internal CPU interrupt, it cannot be disabled using
* the Interrupt Matrix.
*/
xtensa_disable_cpuint(&g_intenable[cpu], 1ul << cpuint);
}
else
{
/* A peripheral interrupt, use the Interrupt Matrix to disable it. */
int periph = ESP32S3_IRQ2PERIPH(irq);
uintptr_t regaddr;
uint8_t *intmap;
DEBUGASSERT(periph >= 0 && periph < ESP32S3_NPERIPHERALS);
esp32s3_intinfo(cpu, periph, &regaddr, &intmap);
intmap[cpuint] = CPUINT_DISABLE(intmap[cpuint]);
putreg32(NO_CPUINT, regaddr);
}
}
/****************************************************************************
* Name: up_enable_irq
*
* Description:
* Enable the IRQ specified by 'irq'
*
****************************************************************************/
void up_enable_irq(int irq)
{
int cpu = IRQ_GETCPU(g_irqmap[irq]);
int cpuint = IRQ_GETCPUINT(g_irqmap[irq]);
DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX);
DEBUGASSERT(cpu == 0);
if (irq < XTENSA_NIRQ_INTERNAL)
{
/* Enable the CPU interrupt now for internal CPU. */
xtensa_enable_cpuint(&g_intenable[cpu], 1ul << cpuint);
}
else
{
/* For peripheral interrupts, attach the interrupt to the peripheral;
* the CPU interrupt was already enabled when allocated.
*/
int periph = ESP32S3_IRQ2PERIPH(irq);
uintptr_t regaddr;
uint8_t *intmap;
DEBUGASSERT(periph >= 0 && periph < ESP32S3_NPERIPHERALS);
esp32s3_intinfo(cpu, periph, &regaddr, &intmap);
intmap[cpuint] = CPUINT_ENABLE(intmap[cpuint]);
putreg32(cpuint, regaddr);
}
}
/****************************************************************************
* Name: esp32s3_cpuint_initialize
*
* Description:
* Initialize CPU interrupts
*
* Input Parameters:
* None
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned on
* any failure.
*
****************************************************************************/
int esp32s3_cpuint_initialize(void)
{
uintptr_t regaddr;
uint8_t *intmap;
int i;
/* Disable all CPU interrupts on this CPU */
xtensa_disable_all();
/* Detach all peripheral sources PRO CPU interrupts */
for (i = 0; i < ESP32S3_NPERIPHERALS; i++)
{
regaddr = CORE0_MAP_REGADDR(i);
putreg32(NO_CPUINT, regaddr);
}
/* Initialize CPU interrupt-to-IRQ mapping table */
intmap = g_cpu0_intmap;
/* Indicate that no peripheral interrupts are assigned to CPU interrupts */
memset(intmap, CPUINT_UNASSIGNED, ESP32S3_NCPUINTS);
/* Special case the 6 internal interrupts.
*
* CPU interrupt bit IRQ number
* --------------------------- ---------------------
* ESP32S3_CPUINT_TIMER0 6 XTENSA_IRQ_TIMER0 0
* ESP32S3_CPUINT_SOFTWARE0 7 Not yet defined
* ESP32S3_CPUINT_PROFILING 11 Not yet defined
* ESP32S3_CPUINT_TIMER1 15 XTENSA_IRQ_TIMER1 1
* ESP32S3_CPUINT_TIMER2 16 XTENSA_IRQ_TIMER2 2
* ESP32S3_CPUINT_SOFTWARE1 29 Not yet defined
*/
intmap[ESP32S3_CPUINT_TIMER0] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER0);
intmap[ESP32S3_CPUINT_TIMER1] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER1);
intmap[ESP32S3_CPUINT_TIMER2] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER2);
return OK;
}
/****************************************************************************
* Name: esp32s3_setup_irq
*
* Description:
* This function sets up the IRQ. It allocates a CPU interrupt of the given
* priority and type and attaches it to the given peripheral.
*
* Input Parameters:
* cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
* periphid - The peripheral number from irq.h to be assigned to
* a CPU interrupt.
* priority - Interrupt's priority (1 - 5).
* type - Interrupt's type (level or edge).
*
* Returned Value:
* The allocated CPU interrupt on success, a negated errno value on
* failure.
*
****************************************************************************/
int esp32s3_setup_irq(int cpu, int periphid, int priority, int type)
{
irqstate_t irqstate;
uintptr_t regaddr;
uint8_t *intmap;
int irq;
int cpuint;
irqstate = enter_critical_section();
/* Setting up an IRQ includes the following steps:
* 1. Allocate a CPU interrupt.
* 2. Attach that CPU interrupt to the peripheral.
* 3. Map the CPU interrupt to the IRQ to ease searching later.
*/
cpuint = esp32s3_alloc_cpuint(priority, type);
if (cpuint < 0)
{
irqerr("Unable to allocate CPU interrupt for priority=%d and type=%d",
priority, type);
leave_critical_section(irqstate);
return cpuint;
}
irq = ESP32S3_PERIPH2IRQ(periphid);
DEBUGASSERT(periphid >= 0 && periphid < ESP32S3_NPERIPHERALS);
DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX);
esp32s3_intinfo(cpu, periphid, &regaddr, &intmap);
DEBUGASSERT(intmap[cpuint] == CPUINT_UNASSIGNED);
intmap[cpuint] = CPUINT_ASSIGN(periphid + XTENSA_IRQ_FIRSTPERIPH);
g_irqmap[irq] = IRQ_MKMAP(cpu, cpuint);
putreg32(cpuint, regaddr);
leave_critical_section(irqstate);
return cpuint;
}
/****************************************************************************
* Name: esp32s3_teardown_irq
*
* Description:
* This function undoes the operations done by esp32s3_setup_irq.
* It detaches a peripheral interrupt from a CPU interrupt and frees the
* CPU interrupt.
*
* Input Parameters:
* cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
* periphid - The peripheral number from irq.h to be detached from the
* CPU interrupt.
* cpuint - The CPU interrupt from which the peripheral interrupt will
* be detached.
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s3_teardown_irq(int cpu, int periphid, int cpuint)
{
irqstate_t irqstate;
uintptr_t regaddr;
uint8_t *intmap;
int irq;
irqstate = enter_critical_section();
/* Tearing down an IRQ includes the following steps:
* 1. Free the previously allocated CPU interrupt.
* 2. Detach the interrupt from the peripheral.
* 3. Unmap the IRQ from the IRQ-to-cpuint map.
*/
esp32s3_free_cpuint(cpuint);
irq = ESP32S3_PERIPH2IRQ(periphid);
DEBUGASSERT(periphid >= 0 && periphid < ESP32S3_NPERIPHERALS);
esp32s3_intinfo(cpu, periphid, &regaddr, &intmap);
DEBUGASSERT(intmap[cpuint] != CPUINT_UNASSIGNED);
intmap[cpuint] = CPUINT_UNASSIGNED;
g_irqmap[irq] = IRQ_UNMAPPED;
putreg32(NO_CPUINT, regaddr);
leave_critical_section(irqstate);
}
/****************************************************************************
* Name: xtensa_int_decode
*
* Description:
* Determine the peripheral that generated the interrupt and dispatch
* handling to the registered interrupt handler via xtensa_irq_dispatch().
*
* Input Parameters:
* cpuints - Set of pending interrupts valid for this level
* regs - Saves processor state on the stack
*
* Returned Value:
* Normally the same value as regs is returned. But, in the event of an
* interrupt level context switch, the returned value will, instead point
* to the saved processor state in the TCB of the newly started task.
*
****************************************************************************/
uint32_t *xtensa_int_decode(uint32_t cpuints, uint32_t *regs)
{
uint8_t *intmap;
uint32_t mask;
int bit;
#ifdef CONFIG_ARCH_LEDS_CPU_ACTIVITY
board_autoled_on(LED_CPU);
#endif
intmap = g_cpu0_intmap;
/* Skip over zero bits, eight at a time */
for (bit = 0, mask = 0xff;
bit < ESP32S3_NCPUINTS && (cpuints & mask) == 0;
bit += 8, mask <<= 8);
/* Process each pending CPU interrupt */
for (; bit < ESP32S3_NCPUINTS && cpuints != 0; bit++)
{
mask = 1 << bit;
if ((cpuints & mask) != 0)
{
/* Extract the IRQ number from the mapping table */
uint8_t irq = CPUINT_GETIRQ(intmap[bit]);
DEBUGASSERT(CPUINT_GETEN(intmap[bit]));
DEBUGASSERT(irq != CPUINT_UNASSIGNED);
/* Clear software or edge-triggered interrupt */
xtensa_intclear(mask);
/* Dispatch the CPU interrupt.
*
* NOTE that regs may be altered in the case of an interrupt
* level context switch.
*/
regs = xtensa_irq_dispatch((int)irq, regs);
/* Clear the bit in the pending interrupt so that perhaps
* we can exit the look early.
*/
cpuints &= ~mask;
}
}
return regs;
}

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/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_IRQ_H
#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/irq.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* CPU interrupt types. */
#define ESP32S3_CPUINT_LEVEL 0
#define ESP32S3_CPUINT_EDGE 1
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s3_cpuint_initialize
*
* Description:
* Initialize CPU interrupts
*
* Input Parameters:
* None
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned on
* any failure.
*
****************************************************************************/
int esp32s3_cpuint_initialize(void);
/****************************************************************************
* Name: esp32s3_setup_irq
*
* Description:
* This function sets up the IRQ. It allocates a CPU interrupt of the given
* priority and type and attaches it to the given peripheral.
*
* Input Parameters:
* cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
* periphid - The peripheral number from irq.h to be assigned to
* a CPU interrupt.
* priority - Interrupt's priority (1 - 5).
* type - Interrupt's type (level or edge).
*
* Returned Value:
* The allocated CPU interrupt on success, a negated errno value on
* failure.
*
****************************************************************************/
int esp32s3_setup_irq(int cpu, int periphid, int priority, int type);
/****************************************************************************
* Name: esp32s3_teardown_irq
*
* Description:
* This function undoes the operations done by esp32s3_setup_irq.
* It detaches a peripheral interrupt from a CPU interrupt and frees the
* CPU interrupt.
*
* Input Parameters:
* cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
* periphid - The peripheral number from irq.h to be detached from the
* CPU interrupt.
* cpuint - The CPU interrupt from which the peripheral interrupt will
* be detached.
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s3_teardown_irq(int cpu, int periphid, int cpuint);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_IRQ_H */

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/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_lowputc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <unistd.h>
#include <string.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <arch/irq.h>
#include "chip.h"
#include "xtensa.h"
#include "hardware/esp32s3_system.h"
#include "hardware/esp32s3_uart.h"
#include "hardware/esp32s3_soc.h"
#include "esp32s3_clockconfig.h"
#include "esp32s3_config.h"
#include "esp32s3_gpio.h"
#include "esp32s3_lowputc.h"
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef HAVE_UART_DEVICE
#ifdef CONFIG_ESP32S3_UART0
struct esp32s3_uart_s g_uart0_config =
{
.periph = ESP32S3_PERIPH_UART0,
.id = 0,
.cpuint = -ENOMEM,
.irq = ESP32S3_IRQ_UART0,
.baud = CONFIG_UART0_BAUD,
.bits = CONFIG_UART0_BITS,
.parity = CONFIG_UART0_PARITY,
.stop_b2 = CONFIG_UART0_2STOP,
.int_pri = ESP32S3_INT_PRIO_DEF,
.txpin = CONFIG_ESP32S3_UART0_TXPIN,
.txsig = U0TXD_OUT_IDX,
.rxpin = CONFIG_ESP32S3_UART0_RXPIN,
.rxsig = U0RXD_IN_IDX,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rtspin = CONFIG_ESP32S3_UART0_RTSPIN,
.rtssig = U0RTS_OUT_IDX,
#ifdef CONFIG_UART0_IFLOWCONTROL
.iflow = true, /* input flow control (RTS) enabled */
#else
.iflow = false, /* input flow control (RTS) disabled */
#endif
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
.ctspin = CONFIG_ESP32S3_UART0_CTSPIN,
.ctssig = U0CTS_IN_IDX,
#ifdef CONFIG_UART0_OFLOWCONTROL
.oflow = true, /* output flow control (CTS) enabled */
#else
.oflow = false, /* output flow control (CTS) disabled */
#endif
#endif
};
#endif /* CONFIG_ESP32S3_UART0 */
#ifdef CONFIG_ESP32S3_UART1
struct esp32s3_uart_s g_uart1_config =
{
.periph = ESP32S3_PERIPH_UART1,
.id = 1,
.cpuint = -ENOMEM,
.irq = ESP32S3_IRQ_UART1,
.baud = CONFIG_UART1_BAUD,
.bits = CONFIG_UART1_BITS,
.parity = CONFIG_UART1_PARITY,
.stop_b2 = CONFIG_UART1_2STOP,
.int_pri = ESP32S3_INT_PRIO_DEF,
.txpin = CONFIG_ESP32S3_UART1_TXPIN,
.txsig = U1TXD_OUT_IDX,
.rxpin = CONFIG_ESP32S3_UART1_RXPIN,
.rxsig = U1RXD_IN_IDX,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rtspin = CONFIG_ESP32S3_UART1_RTSPIN,
.rtssig = U1RTS_OUT_IDX,
#ifdef CONFIG_UART1_IFLOWCONTROL
.iflow = true, /* input flow control (RTS) enabled */
#else
.iflow = false, /* input flow control (RTS) disabled */
#endif
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
.ctspin = CONFIG_ESP32S3_UART1_CTSPIN,
.ctssig = U1CTS_IN_IDX,
#ifdef CONFIG_UART1_OFLOWCONTROL
.oflow = true, /* output flow control (CTS) enabled */
#else
.oflow = false, /* output flow control (CTS) disabled */
#endif
#endif
};
#endif /* CONFIG_ESP32S3_UART1 */
#endif /* HAVE_UART_DEVICE */
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s3_lowputc_set_iflow
*
* Description:
* Configure the input hardware flow control.
*
* Parameters:
* priv - Pointer to the private driver struct.
* threshold - RX FIFO value from which RST will automatically be
* asserted.
* enable - true = enable, false = disable
*
****************************************************************************/
void esp32s3_lowputc_set_iflow(const struct esp32s3_uart_s *priv,
uint8_t threshold, bool enable)
{
uint32_t mask;
if (enable)
{
/* Enable RX flow control */
modifyreg32(UART_CONF1_REG(priv->id), 0, UART_RX_FLOW_EN);
/* Configure the threshold */
mask = VALUE_TO_FIELD(threshold, UART_RX_FLOW_THRHD);
modifyreg32(UART_MEM_CONF_REG(priv->id), UART_RX_FLOW_THRHD_M, mask);
}
else
{
/* Disable RX flow control */
modifyreg32(UART_CONF1_REG(priv->id), UART_RX_FLOW_EN, 0);
}
}
/****************************************************************************
* Name: esp32s3_lowputc_set_oflow
*
* Description:
* Configure the output hardware flow control.
*
* Parameters:
* priv - Pointer to the private driver struct.
* enable - true = enable, false = disable
*
****************************************************************************/
void esp32s3_lowputc_set_oflow(const struct esp32s3_uart_s *priv,
bool enable)
{
if (enable)
{
/* Enable TX flow control */
modifyreg32(UART_CONF0_REG(priv->id), 0, UART_TX_FLOW_EN);
}
else
{
/* Disable TX flow control */
modifyreg32(UART_CONF0_REG(priv->id), UART_TX_FLOW_EN, 0);
}
}
/****************************************************************************
* Name: esp32s3_lowputc_reset_core
*
* Description:
* Reset both TX and RX cores.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_reset_cores(const struct esp32s3_uart_s *priv)
{
uint32_t set_bit = 1 << UART_RST_CORE_S;
modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RST_CORE_M, set_bit);
modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RST_CORE_M, 0);
}
/****************************************************************************
* Name: esp32s3_lowputc_rst_tx
*
* Description:
* Reset TX core.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_rst_tx(const struct esp32s3_uart_s *priv)
{
uint32_t set_bit = 1 << UART_TX_RST_CORE_S;
modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_RST_CORE_M, set_bit);
modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_RST_CORE_M, 0);
}
/****************************************************************************
* Name: esp32s3_lowputc_rst_rx
*
* Description:
* Reset RX core.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_rst_rx(const struct esp32s3_uart_s *priv)
{
uint32_t set_bit = 1 << UART_RX_RST_CORE_S;
modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_RST_CORE_M, set_bit);
modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_RST_CORE_M, 0);
}
/****************************************************************************
* Name: esp32s3_lowputc_enable_sclk
*
* Description:
* Enable clock for whole core.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_enable_sclk(const struct esp32s3_uart_s *priv)
{
modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_EN_M,
1 << UART_SCLK_EN_S);
modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_SCLK_EN_M,
1 << UART_RX_SCLK_EN_S);
modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_SCLK_EN_M,
1 << UART_TX_SCLK_EN_S);
}
/****************************************************************************
* Name: esp32s3_lowputc_disable_sclk
*
* Description:
* Disable clock for whole core.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_disable_sclk(const struct esp32s3_uart_s *priv)
{
modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_EN_M, 0);
modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_SCLK_EN_M, 0);
modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_SCLK_EN_M, 0);
}
/****************************************************************************
* Name: esp32s3_lowputc_set_sclk
*
* Description:
* Set a source clock for UART.
*
* Parameters:
* priv - Pointer to the private driver struct.
* source - APB_CLK = 1 80 MHz
* CLK_8 = 2 8 MHz
* XTAL_CLK = 3
*
****************************************************************************/
void esp32s3_lowputc_set_sclk(const struct esp32s3_uart_s *priv,
enum uart_sclk source)
{
uint32_t clk = (uint32_t)source << UART_SCLK_SEL_S;
modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_SEL_M, clk);
}
/****************************************************************************
* Name: esp32s3_lowputc_get_sclk
*
* Description:
* Get the source clock for UART.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
* Returned Value:
* The frequency of the clock in Hz.
*
****************************************************************************/
uint32_t esp32s3_lowputc_get_sclk(const struct esp32s3_uart_s * priv)
{
uint32_t clk_conf_reg;
uint32_t ret = -ENODATA;
clk_conf_reg = getreg32(UART_CLK_CONF_REG(priv->id));
clk_conf_reg &= UART_SCLK_SEL_M;
clk_conf_reg >>= UART_SCLK_SEL_S;
switch (clk_conf_reg)
{
case 1:
ret = esp_clk_apb_freq();
break;
case 2:
ret = RTC_CLK_FREQ;
break;
case 3:
ret = XTAL_CLK_FREQ;
break;
}
return ret;
}
/****************************************************************************
* Name: esp32s3_lowputc_baud
*
* Description:
* Set the baud rate according to the value in the private driver
* struct.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_baud(const struct esp32s3_uart_s * priv)
{
int sclk_div;
uint32_t sclk_freq;
uint32_t clk_div;
uint32_t int_part;
uint32_t frag_part;
/* Get serial clock */
sclk_freq = esp32s3_lowputc_get_sclk(priv);
/* Calculate integral part of the frequency divider factor.
* For low baud rates, the sclk must be less than half.
* For high baud rates, the sclk must be the higher.
*/
sclk_div = DIV_UP(sclk_freq, MAX_UART_CLKDIV * priv->baud);
/* Calculate the clock divisor to achieve the baud rate.
* baud = f/clk_div
* f = sclk_freq/sclk_div
* clk_div = 16*int_part + frag_part
* 16*int_part + frag_part = 16*(sclk_freq/sclk_div)/baud
*/
clk_div = (sclk_freq << 4) / (priv->baud * sclk_div);
/* Get the integer part of it. */
int_part = clk_div >> 4;
/* Get the frag part of it. */
frag_part = clk_div & 0xf;
/* Set integer part of the clock divisor for baud rate. */
modifyreg32(UART_CLKDIV_REG(priv->id), UART_CLKDIV_M, int_part);
/* Set decimal part of the clock divisor for baud rate. */
modifyreg32(UART_CLKDIV_REG(priv->id), UART_CLKDIV_FRAG_M,
(frag_part & UART_CLKDIV_FRAG_V) << UART_CLKDIV_FRAG_S);
/* Set the the integral part of the frequency divider factor. */
modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_DIV_NUM_M,
(sclk_div - 1) << UART_SCLK_DIV_NUM_S);
}
/****************************************************************************
* Name: esp32s3_lowputc_normal_mode
*
* Description:
* Set the UART to operate in normal mode, i.e., disable the RS485 mode and
* IRDA mode.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_normal_mode(const struct esp32s3_uart_s * priv)
{
/* Disable RS485 mode */
modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485_EN_M, 0);
modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485TX_RX_EN_M, 0);
modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485RXBY_TX_EN_M, 0);
/* Disable IRDA mode */
modifyreg32(UART_CONF0_REG(priv->id), UART_IRDA_EN_M, 0);
}
/****************************************************************************
* Name: esp32s3_lowputc_parity
*
* Description:
* Set the parity, according to the value in the private driver
* struct.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_parity(const struct esp32s3_uart_s * priv)
{
if (priv->parity == UART_PARITY_DISABLE)
{
modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_EN_M, 0);
}
else
{
modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_M,
(priv->parity & 0x1) << UART_PARITY_S);
modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_EN_M,
1 << UART_PARITY_EN_S);
}
}
/****************************************************************************
* Name: esp32s3_lowputc_data_length
*
* Description:
* Set the data bits length, according to the value in the private driver
* struct.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
int esp32s3_lowputc_data_length(const struct esp32s3_uart_s * priv)
{
int ret = OK;
uint32_t length = priv->bits - 5;
/* If it is the allowed range */
if (length >= UART_DATA_5_BITS && length <= UART_DATA_8_BITS)
{
modifyreg32(UART_CONF0_REG(priv->id), UART_BIT_NUM_M,
length << UART_BIT_NUM_S);
}
else
{
ret = -EINVAL;
}
return ret;
}
/****************************************************************************
* Name: esp32s3_lowputc_stop_length
*
* Description:
* Set the stop bits length, according to the value in the private driver
* struct.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_stop_length(const struct esp32s3_uart_s *priv)
{
if (priv->stop_b2 == 0)
{
modifyreg32(UART_CONF0_REG(priv->id), UART_STOP_BIT_NUM_M,
UART_STOP_BITS_1 << UART_STOP_BIT_NUM_S);
}
else
{
modifyreg32(UART_CONF0_REG(priv->id), UART_STOP_BIT_NUM_M,
UART_STOP_BITS_2 << UART_STOP_BIT_NUM_S);
}
}
/****************************************************************************
* Name: esp32s3_lowputc_set_tx_idle_time
*
* Description:
* Set the idle time between transfers.
*
* Parameters:
* priv - Pointer to the private driver struct.
* time - Desired time interval between the transfers.
*
****************************************************************************/
void esp32s3_lowputc_set_tx_idle_time(const struct esp32s3_uart_s *priv,
uint32_t time)
{
time = time << UART_TX_IDLE_NUM_S;
time = time & UART_TX_IDLE_NUM_M; /* Just in case value overloads */
modifyreg32(UART_IDLE_CONF_REG(priv->id), UART_TX_IDLE_NUM_M,
time);
}
/****************************************************************************
* Name: esp32s3_lowputc_send_byte
*
* Description:
* Send one byte.
*
* Parameters:
* priv - Pointer to the private driver struct.
* byte - Byte to be sent.
*
****************************************************************************/
void esp32s3_lowputc_send_byte(const struct esp32s3_uart_s * priv,
char byte)
{
putreg32((uint32_t) byte, UART_FIFO_REG(priv->id));
}
/****************************************************************************
* Name: esp32s3_lowputc_is_tx_fifo_full
*
* Description:
* Verify if TX FIFO is full.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
* Returned Value:
* True if it is full, otherwise false.
*
****************************************************************************/
bool esp32s3_lowputc_is_tx_fifo_full(const struct esp32s3_uart_s *priv)
{
uint32_t reg;
reg = getreg32(UART_STATUS_REG(priv->id));
reg = reg >> UART_TXFIFO_CNT_S;
reg = reg & UART_TXFIFO_CNT_V;
return !(reg < (UART_TX_FIFO_SIZE - 1));
}
/****************************************************************************
* Name: esp32s3_lowputc_rst_peripheral
*
* Description:
* Reset the UART peripheral by using System reg.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_rst_peripheral(const struct esp32s3_uart_s *priv)
{
if (priv->id == 0)
{
modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_UART_RST_M,
SYSTEM_UART_RST_M);
modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_UART_RST_M, 0);
}
else
{
modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_UART1_RST_M,
SYSTEM_UART1_RST_M);
modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_UART1_RST_M, 0);
}
}
/****************************************************************************
* Name: esp32s3_lowputc_rst_txfifo
*
* Description:
* Reset TX FIFO.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_rst_txfifo(const struct esp32s3_uart_s *priv)
{
modifyreg32(UART_CONF0_REG(priv->id), UART_TXFIFO_RST_M,
UART_TXFIFO_RST_M);
modifyreg32(UART_CONF0_REG(priv->id), UART_TXFIFO_RST_M, 0);
}
/****************************************************************************
* Name: esp32s3_lowputc_rst_rxfifo
*
* Description:
* Reset RX FIFO.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_rst_rxfifo(const struct esp32s3_uart_s *priv)
{
modifyreg32(UART_CONF0_REG(priv->id), UART_RXFIFO_RST_M,
UART_RXFIFO_RST_M);
modifyreg32(UART_CONF0_REG(priv->id), UART_RXFIFO_RST_M, 0);
}
/****************************************************************************
* Name: esp32s3_lowputc_disable_all_uart_int
*
* Description:
* Disable all UART interrupts.
*
* Parameters:
* priv - Pointer to the private driver struct.
* current_status - Pointer to a variable to store the current status of
* the interrupt enable register before disabling
* UART interrupts.
*
****************************************************************************/
void esp32s3_lowputc_disable_all_uart_int(const struct esp32s3_uart_s *priv,
uint32_t *current_status)
{
irqstate_t flags;
flags = enter_critical_section();
if (current_status != NULL)
{
/* Save current status */
*current_status = getreg32(UART_INT_ENA_REG(priv->id));
}
/* Disable all UART int */
putreg32(0, UART_INT_ENA_REG(priv->id));
/* Clear all ints */
putreg32(0xffffffff, UART_INT_CLR_REG(priv->id));
leave_critical_section(flags);
}
/****************************************************************************
* Name: esp32s3_lowputc_restore_all_uart_int
*
* Description:
* Restore all UART interrupts.
*
* Parameters:
* priv - Pointer to the private driver struct.
* last_status - Pointer to a variable that stored the last state of the
* interrupt enable register.
*
****************************************************************************/
void esp32s3_lowputc_restore_all_uart_int(const struct esp32s3_uart_s *priv,
uint32_t *last_status)
{
/* Restore the previous behaviour */
putreg32(*last_status, UART_INT_ENA_REG(priv->id));
}
/****************************************************************************
* Name: esp32s3_lowputc_config_pins
*
* Description:
* Configure TX and RX UART pins.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_config_pins(const struct esp32s3_uart_s *priv)
{
/* Configure the pins */
esp32s3_gpio_matrix_out(priv->txpin, priv->txsig, 0, 0);
esp32s3_configgpio(priv->txpin, OUTPUT_FUNCTION_1);
esp32s3_configgpio(priv->rxpin, INPUT_FUNCTION_1);
esp32s3_gpio_matrix_in(priv->rxpin, priv->rxsig, 0);
#ifdef CONFIG_SERIAL_IFLOWCONTROL
if (priv->iflow)
{
esp32s3_configgpio(priv->rtspin, OUTPUT_FUNCTION_1);
esp32s3_gpio_matrix_out(priv->rtspin, priv->rtssig,
0, 0);
}
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
if (priv->oflow)
{
esp32s3_configgpio(priv->ctspin, INPUT_FUNCTION_1);
esp32s3_gpio_matrix_in(priv->ctspin, priv->ctssig, 0);
}
#endif
}
/****************************************************************************
* Name: esp32s3_lowputc_restore_pins
*
* Description:
* Configure both pins back to INPUT mode and detach the TX pin from the
* output signal and the RX pin from the input signal.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_restore_pins(const struct esp32s3_uart_s *priv)
{
/* Configure the pins */
esp32s3_configgpio(priv->txpin, INPUT);
esp32s3_gpio_matrix_out(priv->txpin, MATRIX_DETACH_OUT_SIG, false, false);
esp32s3_configgpio(priv->rxpin, INPUT);
esp32s3_gpio_matrix_in(priv->rxpin, MATRIX_DETACH_IN_LOW_PIN, false);
}
/****************************************************************************
* Name: up_lowputc
*
* Description:
* Output one byte on the serial console.
*
* Parameters:
* ch - Byte to be sent.
*
****************************************************************************/
void up_lowputc(char ch)
{
#ifdef CONSOLE_UART
# if defined(CONFIG_UART0_SERIAL_CONSOLE)
struct esp32s3_uart_s *priv = &g_uart0_config;
#elif defined (CONFIG_UART1_SERIAL_CONSOLE)
struct esp32s3_uart_s *priv = &g_uart1_config;
#endif
/* Wait until the TX FIFO has space to insert new char */
while (esp32s3_lowputc_is_tx_fifo_full(priv));
/* Then send the character */
esp32s3_lowputc_send_byte(priv, ch);
#elif defined (CONFIG_ESP32S3_USBSERIAL)
esp32s3_usbserial_write(ch);
#endif /* CONSOLE_UART */
}
/****************************************************************************
* Name: esp32s3_lowsetup
*
* Description:
* This performs only the basic configuration for UART pins.
*
****************************************************************************/
void esp32s3_lowsetup(void)
{
#ifndef CONFIG_SUPPRESS_UART_CONFIG
#ifdef CONFIG_ESP32S3_UART0
esp32s3_lowputc_config_pins(&g_uart0_config);
#endif
#ifdef CONFIG_ESP32S3_UART1
esp32s3_lowputc_config_pins(&g_uart1_config);
#endif
#endif /* !CONFIG_SUPPRESS_UART_CONFIG */
}

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/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_lowputc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_LOWPUTC_H
#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_LOWPUTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <unistd.h>
#include <string.h>
#include <errno.h>
#include <debug.h>
#include "chip.h"
#include "hardware/esp32s3_uart.h"
#include "hardware/esp32s3_gpio_sigmap.h"
#include "esp32s3_irq.h"
/****************************************************************************
* Public Types
****************************************************************************/
enum uart_sclk
{
APB_CLK = 1, /* 80 MHz */
CLK_8, /* 8 MHz */
XTAL_CLK
};
enum uart_parity
{
UART_PARITY_DISABLE,
UART_PARITY_ODD,
UART_PARITY_EVEN
};
enum uart_data_length
{
UART_DATA_5_BITS,
UART_DATA_6_BITS,
UART_DATA_7_BITS,
UART_DATA_8_BITS
};
enum uart_stop_length
{
UART_STOP_BITS_1 = 0x1, /* Stop bit: 1 bit */
UART_STOP_BITS_2 = 0x3, /* Stop bit: 2 bits */
};
/* Default FIFOs size */
#define UART_TX_FIFO_SIZE 128
#define UART_RX_FIFO_SIZE 128
/* Maximum serial clock divisor for integer part */
#define MAX_UART_CLKDIV (BIT(12) - 1)
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
/* Struct used to store uart driver information and to
* manipulate uart driver
*/
struct esp32s3_uart_s
{
uint8_t periph; /* UART peripheral ID */
int cpuint; /* CPU interrupt assigned to this UART */
uint8_t id; /* UART ID */
uint8_t irq; /* IRQ associated with this UART */
uint8_t cpu; /* CPU ID */
uint32_t baud; /* Configured baud rate */
uint8_t bits; /* Data length (5 to 8 bits). */
uint8_t parity; /* 0=no parity, 1=odd parity, 2=even parity */
uint8_t stop_b2; /* Use 2 stop bits? 0 = no (use 1) 1 = yes (use 2) */
uint8_t int_pri; /* UART Interrupt Priority */
uint8_t txpin; /* TX pin */
uint8_t txsig; /* TX signal */
uint8_t rxpin; /* RX pin */
uint8_t rxsig; /* RX signal */
#ifdef CONFIG_SERIAL_IFLOWCONTROL
uint8_t rtspin; /* RTS pin number */
uint8_t rtssig; /* RTS signal */
bool iflow; /* Input flow control (RTS) enabled */
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
uint8_t ctspin; /* CTS pin number */
uint8_t ctssig; /* CTS signal */
bool oflow; /* Output flow control (CTS) enabled */
#endif
};
extern struct esp32s3_uart_s g_uart0_config;
extern struct esp32s3_uart_s g_uart1_config;
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s3_lowputc_set_iflow
*
* Description:
* Configure the input hardware flow control.
*
* Parameters:
* priv - Pointer to the private driver struct.
* threshold - RX FIFO value from which RST will automatically be
* asserted.
* enable - true = enable, false = disable
*
****************************************************************************/
void esp32s3_lowputc_set_iflow(const struct esp32s3_uart_s *priv,
uint8_t threshold, bool enable);
/****************************************************************************
* Name: esp32s3_lowputc_set_oflow
*
* Description:
* Configure the output hardware flow control.
*
* Parameters:
* priv - Pointer to the private driver struct.
* enable - true = enable, false = disable
*
****************************************************************************/
void esp32s3_lowputc_set_oflow(const struct esp32s3_uart_s *priv,
bool enable);
/****************************************************************************
* Name: esp32s3_lowputc_reset_core
*
* Description:
* Reset both TX and RX cores.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_reset_cores(const struct esp32s3_uart_s *priv);
/****************************************************************************
* Name: esp32s3_lowputc_rst_tx
*
* Description:
* Reset TX core.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_rst_tx(const struct esp32s3_uart_s *priv);
/****************************************************************************
* Name: esp32s3_lowputc_rst_rx
*
* Description:
* Reset RX core.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_rst_rx(const struct esp32s3_uart_s *priv);
/****************************************************************************
* Name: esp32s3_lowputc_enable_sclk
*
* Description:
* Enable clock for whole core.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_enable_sclk(const struct esp32s3_uart_s *priv);
/****************************************************************************
* Name: esp32s3_lowputc_disable_sclk
*
* Description:
* Disable clock for whole core.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_disable_sclk(const struct esp32s3_uart_s *priv);
/****************************************************************************
* Name: esp32s3_lowputc_set_sclk
*
* Description:
* Set a source clock for UART.
*
* Parameters:
* priv - Pointer to the private driver struct.
* source - APB_CLK = 1 80 MHz
* CLK_8 = 2 8 MHz
* XTAL_CLK = 3
*
****************************************************************************/
void esp32s3_lowputc_set_sclk(const struct esp32s3_uart_s *priv,
enum uart_sclk source);
/****************************************************************************
* Name: esp32s3_lowputc_get_sclk
*
* Description:
* Get the source clock for UART.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
* Returned Value:
* The frequency of the clock in Hz.
*
****************************************************************************/
uint32_t esp32s3_lowputc_get_sclk(const struct esp32s3_uart_s *priv);
/****************************************************************************
* Name: esp32s3_lowputc_baud
*
* Description:
* Set the baud rate according to the value in the private driver
* struct.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_baud(const struct esp32s3_uart_s *priv);
/****************************************************************************
* Name: esp32s3_lowputc_normal_mode
*
* Description:
* Set the UART to operate in normal mode, i.e., disable the RS485 mode and
* IRDA mode.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_normal_mode(const struct esp32s3_uart_s *priv);
/****************************************************************************
* Name: esp32s3_lowputc_parity
*
* Description:
* Set the parity, according to the value in the private driver
* struct.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_parity(const struct esp32s3_uart_s *priv);
/****************************************************************************
* Name: esp32s3_lowputc_data_length
*
* Description:
* Set the data bits length, according to the value in the private driver
* struct.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
int esp32s3_lowputc_data_length(const struct esp32s3_uart_s *priv);
/****************************************************************************
* Name: esp32s3_lowputc_stop_length
*
* Description:
* Set the stop bits length, according to the value in the private driver
* struct.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_stop_length(const struct esp32s3_uart_s *priv);
/****************************************************************************
* Name: esp32s3_lowputc_set_tx_idle_time
*
* Description:
* Set the idle time between transfers.
*
* Parameters:
* priv - Pointer to the private driver struct.
* time - Desired time interval between the transfers.
*
****************************************************************************/
void esp32s3_lowputc_set_tx_idle_time(const struct esp32s3_uart_s *priv,
uint32_t time);
/****************************************************************************
* Name: esp32s3_lowputc_send_byte
*
* Description:
* Send one byte.
*
* Parameters:
* priv - Pointer to the private driver struct.
* byte - Byte to be sent.
*
****************************************************************************/
void esp32s3_lowputc_send_byte(const struct esp32s3_uart_s *priv,
char byte);
/****************************************************************************
* Name: esp32s3_lowputc_is_tx_fifo_full
*
* Description:
* Verify if TX FIFO is full.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
* Returned Value:
* True if it is full, otherwise false.
*
****************************************************************************/
bool esp32s3_lowputc_is_tx_fifo_full(const struct esp32s3_uart_s *priv);
/****************************************************************************
* Name: esp32s3_lowputc_rst_peripheral
*
* Description:
* Reset the UART peripheral by using System reg.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_rst_peripheral(const struct esp32s3_uart_s *priv);
/****************************************************************************
* Name: esp32s3_lowputc_rst_txfifo
*
* Description:
* Reset TX FIFO.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_rst_txfifo(const struct esp32s3_uart_s *priv);
/****************************************************************************
* Name: esp32s3_lowputc_rst_rxfifo
*
* Description:
* Reset RX FIFO.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_rst_rxfifo(const struct esp32s3_uart_s *priv);
/****************************************************************************
* Name: esp32s3_lowputc_disable_all_uart_int
*
* Description:
* Disable all UART interrupts.
*
* Parameters:
* priv - Pointer to the private driver struct.
* current_status - Pointer to a variable to store the current status of
* the interrupt enable register before disabling
* UART interrupts.
*
****************************************************************************/
void esp32s3_lowputc_disable_all_uart_int(const struct esp32s3_uart_s *priv,
uint32_t *current_status);
/****************************************************************************
* Name: esp32s3_lowputc_restore_all_uart_int
*
* Description:
* Restore all UART interrupts.
*
* Parameters:
* priv - Pointer to the private driver struct.
* last_status - Pointer to a variable that stored the last state of the
* interrupt enable register.
*
****************************************************************************/
void esp32s3_lowputc_restore_all_uart_int(const struct esp32s3_uart_s *priv,
uint32_t * last_status);
/****************************************************************************
* Name: esp32s3_lowputc_config_pins
*
* Description:
* Configure TX and RX UART pins.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_config_pins(const struct esp32s3_uart_s *priv);
/****************************************************************************
* Name: esp32s3_lowputc_restore_pins
*
* Description:
* Configure both pins back to INPUT mode and detach the TX pin from the
* output signal and the RX pin from the input signal.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s3_lowputc_restore_pins(const struct esp32s3_uart_s *priv);
/****************************************************************************
* Name: esp32s3_lowsetup
*
* Description:
* This performs basic initialization of the UART used for the serial
* console. Its purpose is to get the console output available as soon
* as possible.
*
****************************************************************************/
void esp32s3_lowsetup(void);
#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_LOWPUTC_H */

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/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_region.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
/****************************************************************************
* Private Data
****************************************************************************/
static const uint32_t g_protected_pages[] =
{
0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000
};
#define NPROTECTED_PAGES (sizeof(g_protected_pages)/sizeof(uint32_t))
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: xtensa_write_dtlb and xtensa_write_itlb
*
* Description:
* Functions to set page attributes for Region Protection option in the
* CPU. See Xtensa ISA Reference manual for explanation of arguments
* (section 4.6.3.2).
*
****************************************************************************/
static inline void xtensa_write_dtlb(uint32_t vpn, uint32_t attr)
{
__asm__ __volatile__
(
"wdtlb %1, %0\n"
"dsync\n"
: : "r" (vpn), "r" (attr)
);
}
static inline void xtensa_write_itlb(uint32_t vpn, uint32_t attr)
{
__asm__ __volatile__
(
"witlb %1, %0\n"
"isync\n"
: : "r" (vpn), "r" (attr)
);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s3_region_protection
*
* Description:
* Make page 0 access raise an exception. Also protect some other unused
* pages so we can catch weirdness.
*
* Useful attribute values:
* 0 — cached, RW
* 2 — bypass cache, RWX (default value after CPU reset)
* 15 — no access, raise exception
*
****************************************************************************/
void esp32s3_region_protection(void)
{
int i;
for (i = 0; i < NPROTECTED_PAGES; ++i)
{
xtensa_write_dtlb(g_protected_pages[i], 0xf);
xtensa_write_itlb(g_protected_pages[i], 0xf);
}
xtensa_write_dtlb(0x20000000, 0);
xtensa_write_itlb(0x20000000, 0);
}

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/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_region.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_REGION_H
#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_REGION_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Name: esp32s3_region_protection
*
* Description:
* Make page 0 access raise an exception. Also protect some other unused
* pages so we can catch weirdness.
*
* Useful attribute values:
* 0 — cached, RW
* 2 — bypass cache, RWX (default value after CPU reset)
* 15 — no access, raise exception
*
****************************************************************************/
void esp32s3_region_protection(void);
#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_REGION_H */

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/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_start.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <string.h>
#include <nuttx/init.h>
#include <nuttx/irq.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "esp32s3_start.h"
#include "esp32s3_lowputc.h"
#include "esp32s3_clockconfig.h"
#include "esp32s3_region.h"
#include "esp32s3_wdt.h"
#include "hardware/esp32s3_cache_memory.h"
#include "hardware/esp32s3_system.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
# define showprogress(c) up_lowputc(c)
#else
# define showprogress(c)
#endif
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* ROM Function Prototypes
****************************************************************************/
extern void rom_config_instruction_cache_mode(uint32_t cfg_cache_size,
uint8_t cfg_cache_ways,
uint8_t cfg_cache_line_size);
extern void rom_config_data_cache_mode(uint32_t cfg_cache_size,
uint8_t cfg_cache_ways,
uint8_t cfg_cache_line_size);
extern uint32_t cache_suspend_dcache(void);
extern void cache_resume_dcache(uint32_t val);
extern uint32_t cache_set_idrom_mmu_size(uint32_t irom_size,
uint32_t drom_size);
extern void cache_set_idrom_mmu_info(uint32_t instr_page_num,
uint32_t rodata_page_num,
uint32_t rodata_start,
uint32_t rodata_end,
int i_off,
int ro_off);
#ifdef CONFIG_ESP32S3_DATA_CACHE_16KB
extern void cache_invalidate_dcache_all(void);
extern int cache_occupy_addr(uint32_t addr, uint32_t size);
#endif
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
extern int _rodata_reserved_start;
extern int _rodata_reserved_end;
/* Address of the CPU0 IDLE thread */
uint32_t g_idlestack[IDLETHREAD_STACKWORDS]
aligned_data(16) locate_data(".noinit");
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: configure_cpu_caches
*
* Description:
* Configure the Instruction and Data CPU caches.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
static void IRAM_ATTR configure_cpu_caches(void)
{
int s_instr_flash2spiram_off = 0;
int s_rodata_flash2spiram_off = 0;
/* Configure the mode of instruction cache: cache size, cache line size. */
rom_config_instruction_cache_mode(CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE,
CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS,
CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE);
/* If we need to use SPIRAM, we should use data cache.
* Configure the mode of data cache: cache size, cache line size.
*/
cache_suspend_dcache();
rom_config_data_cache_mode(CONFIG_ESP32S3_DATA_CACHE_SIZE,
CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS,
CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE);
cache_resume_dcache(0);
/* Configure the Cache MMU size for instruction and rodata in flash. */
uint32_t rodata_reserved_start_align =
(uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1);
uint32_t cache_mmu_irom_size =
((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) *
sizeof(uint32_t);
uint32_t cache_mmu_drom_size =
(((uint32_t)&_rodata_reserved_end - rodata_reserved_start_align +
MMU_PAGE_SIZE - 1) /
MMU_PAGE_SIZE) * sizeof(uint32_t);
cache_set_idrom_mmu_size(cache_mmu_irom_size,
CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
cache_set_idrom_mmu_info(cache_mmu_irom_size / sizeof(uint32_t),
cache_mmu_drom_size / sizeof(uint32_t),
(uint32_t)&_rodata_reserved_start,
(uint32_t)&_rodata_reserved_end,
s_instr_flash2spiram_off,
s_rodata_flash2spiram_off);
#ifdef CONFIG_ESP32S3_DATA_CACHE_16KB
cache_invalidate_dcache_all();
cache_occupy_addr(SOC_DROM_LOW, 0x4000);
#endif
}
/****************************************************************************
* Name: disable_app_cpu
*
* Description:
* Disable the APP CPU (Core 1).
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
static void IRAM_ATTR disable_app_cpu(void)
{
uint32_t regval;
regval = getreg32(SYSTEM_CORE_1_CONTROL_0_REG);
regval &= ~SYSTEM_CONTROL_CORE_1_CLKGATE_EN;
putreg32(regval, SYSTEM_CORE_1_CONTROL_0_REG);
/* The clock gating signal of the App core is invalid.
* We use RUNSTALL and RESETING signals to ensure that the App core stops
* running in single-core mode.
*/
regval = getreg32(SYSTEM_CORE_1_CONTROL_0_REG);
regval |= SYSTEM_CONTROL_CORE_1_RUNSTALL;
putreg32(regval, SYSTEM_CORE_1_CONTROL_0_REG);
regval = getreg32(SYSTEM_CORE_1_CONTROL_0_REG);
regval &= ~SYSTEM_CONTROL_CORE_1_RESETING;
putreg32(regval, SYSTEM_CORE_1_CONTROL_0_REG);
}
/****************************************************************************
* Name: __esp32s3_start
*
* Description:
* Perform base configuration of the chip for code execution.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
void noreturn_function IRAM_ATTR __esp32s3_start(void)
{
uint32_t sp;
/* Make sure that normal interrupts are disabled. This is really only an
* issue when we are started in un-usual ways (such as from IRAM). In this
* case, we can at least defer some unexpected interrupts left over from
* the last program execution.
*/
up_irq_disable();
/* Move the stack to a known location. Although we were given a stack
* pointer at start-up, we don't know where that stack pointer is
* positioned with respect to our memory map. The only safe option is to
* switch to a well-known IDLE thread stack.
*/
sp = (uint32_t)g_idlestack + IDLETHREAD_STACKSIZE;
__asm__ __volatile__("mov sp, %0\n" : : "r"(sp));
/* Raise an exception in case page 0 is accessed */
esp32s3_region_protection();
/* Move CPU0 exception vectors to IRAM */
__asm__ __volatile__ ("wsr %0, vecbase\n"::"r" (&_init_start));
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
* certain that there are no issues with the state of global variables.
*/
for (uint32_t *dest = &_sbss; dest < &_ebss; dest++)
{
*dest = 0;
}
/* Make sure that the APP_CPU is disabled for now */
disable_app_cpu();
/* The 2nd stage bootloader enables RTC WDT to check on startup sequence
* related issues in application. Hence disable that as we are about to
* start the NuttX environment.
*/
esp32s3_wdt_early_deinit();
/* Set CPU frequency configured in board.h */
esp32s3_clockconfig();
#ifndef CONFIG_SUPPRESS_UART_CONFIG
/* Configure the UART so we can get debug output */
esp32s3_lowsetup();
#endif
#ifdef USE_EARLYSERIALINIT
/* Perform early serial initialization */
xtensa_earlyserialinit();
#endif
showprogress('A');
/* Initialize onboard resources */
esp32s3_board_initialize();
showprogress('B');
/* Bring up NuttX */
nx_start();
for (; ; ); /* Should not return */
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: __start
*
* Description:
* We arrive here after the bootloader finished loading the program from
* flash. The hardware is mostly uninitialized, and the app CPU is in
* reset. We do have a stack, so we can do the initialization in C.
*
* The app CPU will remain in reset unless CONFIG_SMP is selected and
* up_cpu_start() is called later in the bring-up sequence.
*
****************************************************************************/
void IRAM_ATTR __start(void)
{
configure_cpu_caches();
__esp32s3_start();
while (true); /* Should not return */
}

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/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_start.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_START_H
#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_START_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Name: esp32s3_board_initialize
*
* Description:
* Board-specific logic is initialized by calling this function. This
* entry point is called early in the initialization -- after all memory
* has been configured but before any devices have been initialized.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s3_board_initialize(void);
#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_START_H */

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/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_systemreset.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include "xtensa.h"
#include "hardware/esp32s3_rtccntl.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_systemreset
*
* Description:
* Internal reset logic.
*
****************************************************************************/
void up_systemreset(void)
{
putreg32(RTC_CNTL_SW_SYS_RST, RTC_CNTL_RTC_OPTIONS0_REG);
/* Wait for the reset */
for (; ; );
}

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/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_timerisr.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <time.h>
#include <arch/board/board.h>
#include <arch/irq.h>
#include <nuttx/arch.h>
#include "chip.h"
#include "esp32s3_irq.h"
#include "hardware/esp32s3_system.h"
#include "hardware/esp32s3_systimer.h"
#include "xtensa.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define ESP32S3_SYSTIMER_TICKS_PER_SEC (16 * 1000 * 1000)
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: systimer_isr
*
* Description:
* The timer ISR will perform a variety of services for various portions
* of the systems.
*
* Input Parameters:
* irq - CPU interrupt index.
* context - Context data from the ISR.
* arg - Opaque pointer to the internal driver state structure.
*
* Returned Value:
* Zero (OK) is returned on success. A negated errno value is returned on
* failure.
*
****************************************************************************/
static int systimer_isr(int irq, void *context, void *arg)
{
modifyreg32(SYSTIMER_INT_CLR_REG, 0, SYSTIMER_TARGET0_INT_CLR);
/* Process timer interrupt */
nxsched_process_timer();
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_timer_initialize
*
* Description:
* This function is called during start-up to initialize the timer
* interrupt.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
void up_timer_initialize(void)
{
uint32_t regval;
int cpuint;
cpuint = esp32s3_setup_irq(0, ESP32S3_PERIPH_SYSTIMER_TARGET0, 1,
ESP32S3_CPUINT_LEVEL);
DEBUGASSERT(cpuint >= 0);
/* Attach the timer interrupt. */
irq_attach(ESP32S3_IRQ_SYSTIMER_TARGET0, systimer_isr, NULL);
/* Enable the allocated CPU interrupt. */
up_enable_irq(ESP32S3_IRQ_SYSTIMER_TARGET0);
/* Enable timer clock */
modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, 0, SYSTEM_SYSTIMER_CLK_EN);
modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_SYSTIMER_RST, 0);
modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_CLK_EN);
/* Configure alarm0 (Comparator 0) */
regval = SYSTIMER_TARGET0_PERIOD_MODE |
((ESP32S3_SYSTIMER_TICKS_PER_SEC / CLOCKS_PER_SEC) <<
SYSTIMER_TARGET0_PERIOD_S);
putreg32(regval, SYSTIMER_TARGET0_CONF_REG);
putreg32(SYSTIMER_TIMER_COMP0_LOAD, SYSTIMER_COMP0_LOAD_REG);
/* Stall systimer 0 when CPU stalls, e.g., when using JTAG to debug */
modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN);
/* Enable interrupt */
modifyreg32(SYSTIMER_INT_CLR_REG, 0, SYSTIMER_TARGET0_INT_CLR);
modifyreg32(SYSTIMER_INT_ENA_REG, 0, SYSTIMER_TARGET0_INT_ENA);
modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TARGET0_WORK_EN);
/* Start alarm0 counter0 */
modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TIMER_UNIT0_WORK_EN);
}

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/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_user.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "xtensa.h"
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: xtensa_user
*
* Description:
* ESP32-S3-specific user exception handler.
*
* Input Parameters:
* exccause - Identifies the EXCCAUSE of the user exception.
* regs - The register save are at the time of the interrupt.
*
* Returned Value:
* Does not return.
*
****************************************************************************/
uint32_t *xtensa_user(int exccause, uint32_t *regs)
{
/* xtensa_user_panic never returns. */
xtensa_user_panic(exccause, regs);
while (1)
{
}
}

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/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_wdt.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include "xtensa.h"
#include "esp32s3_wdt.h"
#include "hardware/esp32s3_rtccntl.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s3_wdt_early_deinit
*
* Description:
* Disable the WDT(s) that was/were enabled by the bootloader.
*
****************************************************************************/
void esp32s3_wdt_early_deinit(void)
{
uint32_t regval;
putreg32(RTC_CNTL_WDT_WKEY_VALUE, RTC_CNTL_RTC_WDTWPROTECT_REG);
regval = getreg32(RTC_CNTL_RTC_WDTCONFIG0_REG);
regval &= ~RTC_CNTL_WDT_EN;
putreg32(regval, RTC_CNTL_RTC_WDTCONFIG0_REG);
putreg32(0, RTC_CNTL_RTC_WDTWPROTECT_REG);
}

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/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_wdt.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_WDT_H
#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_WDT_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
void esp32s3_wdt_early_deinit(void);
#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_WDT_H */

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/****************************************************************************
* arch/xtensa/src/esp32s3/hardware/esp32s3_cache_memory.h
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_CACHE_MEMORY_H
#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_CACHE_MEMORY_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#include "esp32s3_soc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRAM0 is connected with Cache IBUS0 */
#define IRAM0_ADDRESS_LOW 0x40000000
#define IRAM0_ADDRESS_HIGH 0x44000000
#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
#define IRAM0_CACHE_ADDRESS_HIGH 0x44000000
/* DRAM0 is connected with Cache DBUS0 */
#define DRAM0_ADDRESS_LOW 0x3c000000
#define DRAM0_ADDRESS_HIGH 0x40000000
#define DRAM0_CACHE_ADDRESS_LOW 0x3c000000
#define DRAM0_CACHE_ADDRESS_HIGH 0x3e000000
#define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH
#define ESP_CACHE_TEMP_ADDR 0x3c800000
#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - \
bus_name##_ADDRESS_LOW)
#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW \
&& (vaddr) < \
bus_name##_ADDRESS_HIGH)
#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
#define CACHE_IBUS 0
#define CACHE_IBUS_MMU_START 0
#define CACHE_IBUS_MMU_END 0x800
#define CACHE_DBUS 1
#define CACHE_DBUS_MMU_START 0
#define CACHE_DBUS_MMU_END 0x800
#define CACHE_IROM_MMU_START 0
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
#define CACHE_DROM_MMU_MAX_END 0x400
#define ICACHE_MMU_SIZE 0x800
#define DCACHE_MMU_SIZE 0x800
#define MMU_BUS_START(i) 0
#define MMU_BUS_SIZE(i) 0x800
#define MMU_INVALID BIT(14)
#define MMU_TYPE BIT(15)
#define MMU_ACCESS_FLASH 0
#define MMU_ACCESS_SPIRAM BIT(15)
#define CACHE_MAX_SYNC_NUM 0x400000
#define CACHE_MAX_LOCK_NUM 0x8000
#define FLASH_MMU_TABLE ((volatile uint32_t *)DR_REG_MMU_TABLE)
#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE / sizeof(uint32_t))
#define MMU_TABLE_INVALID_VAL 0x4000
#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
#define MMU_ADDRESS_MASK 0x3fff
#define MMU_PAGE_SIZE 0x10000
#define INVALID_PHY_PAGE 0xffff
#define BUS_ADDR_SIZE 0x200000
#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
#define CACHE_ICACHE_LOW_SHIFT 0
#define CACHE_ICACHE_HIGH_SHIFT 2
#define CACHE_DCACHE_LOW_SHIFT 4
#define CACHE_DCACHE_HIGH_SHIFT 6
#define CACHE_MEMORY_IBANK0_ADDR 0x40370000
#define CACHE_MEMORY_IBANK1_ADDR 0x40374000
#define CACHE_MEMORY_DBANK0_ADDR 0x3fcf0000
#define CACHE_MEMORY_DBANK1_ADDR 0x3fcf8000
#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_CACHE_MEMORY_H */

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/****************************************************************************
* arch/xtensa/src/esp32s3/hardware/esp32s3_gpio_sigmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_GPIO_SIGMAP_H
#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_GPIO_SIGMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#define SPIQ_IN_IDX 0
#define SPIQ_OUT_IDX 0
#define SPID_IN_IDX 1
#define SPID_OUT_IDX 1
#define SPIHD_IN_IDX 2
#define SPIHD_OUT_IDX 2
#define SPIWP_IN_IDX 3
#define SPIWP_OUT_IDX 3
#define SPICLK_OUT_IDX 4
#define SPICS0_OUT_IDX 5
#define SPICS1_OUT_IDX 6
#define SPID4_IN_IDX 7
#define SPID4_OUT_IDX 7
#define SPID5_IN_IDX 8
#define SPID5_OUT_IDX 8
#define SPID6_IN_IDX 9
#define SPID6_OUT_IDX 9
#define SPID7_IN_IDX 10
#define SPID7_OUT_IDX 10
#define SPIDQS_IN_IDX 11
#define SPIDQS_OUT_IDX 11
#define U0RXD_IN_IDX 12
#define U0TXD_OUT_IDX 12
#define U0CTS_IN_IDX 13
#define U0RTS_OUT_IDX 13
#define U0DSR_IN_IDX 14
#define U0DTR_OUT_IDX 14
#define U1RXD_IN_IDX 15
#define U1TXD_OUT_IDX 15
#define U1CTS_IN_IDX 16
#define U1RTS_OUT_IDX 16
#define U1DSR_IN_IDX 17
#define U1DTR_OUT_IDX 17
#define U2RXD_IN_IDX 18
#define U2TXD_OUT_IDX 18
#define U2CTS_IN_IDX 19
#define U2RTS_OUT_IDX 19
#define U2DSR_IN_IDX 20
#define U2DTR_OUT_IDX 20
#define I2S1_MCLK_IN_IDX 21
#define I2S1_MCLK_OUT_IDX 21
#define I2S0O_BCK_IN_IDX 22
#define I2S0O_BCK_OUT_IDX 22
#define I2S0_MCLK_IN_IDX 23
#define I2S0_MCLK_OUT_IDX 23
#define I2S0O_WS_IN_IDX 24
#define I2S0O_WS_OUT_IDX 24
#define I2S0I_SD_IN_IDX 25
#define I2S0O_SD_OUT_IDX 25
#define I2S0I_BCK_IN_IDX 26
#define I2S0I_BCK_OUT_IDX 26
#define I2S0I_WS_IN_IDX 27
#define I2S0I_WS_OUT_IDX 27
#define I2S1O_BCK_IN_IDX 28
#define I2S1O_BCK_OUT_IDX 28
#define I2S1O_WS_IN_IDX 29
#define I2S1O_WS_OUT_IDX 29
#define I2S1I_SD_IN_IDX 30
#define I2S1O_SD_OUT_IDX 30
#define I2S1I_BCK_IN_IDX 31
#define I2S1I_BCK_OUT_IDX 31
#define I2S1I_WS_IN_IDX 32
#define I2S1I_WS_OUT_IDX 32
#define PCNT_SIG_CH0_IN0_IDX 33
#define GPIO_WLAN_PRIO_IDX 33
#define PCNT_SIG_CH1_IN0_IDX 34
#define GPIO_WLAN_ACTIVE_IDX 34
#define PCNT_CTRL_CH0_IN0_IDX 35
#define BB_DIAG0_IDX 35
#define PCNT_CTRL_CH1_IN0_IDX 36
#define BB_DIAG1_IDX 36
#define PCNT_SIG_CH0_IN1_IDX 37
#define BB_DIAG2_IDX 37
#define PCNT_SIG_CH1_IN1_IDX 38
#define BB_DIAG3_IDX 38
#define PCNT_CTRL_CH0_IN1_IDX 39
#define BB_DIAG4_IDX 39
#define PCNT_CTRL_CH1_IN1_IDX 40
#define BB_DIAG5_IDX 40
#define PCNT_SIG_CH0_IN2_IDX 41
#define BB_DIAG6_IDX 41
#define PCNT_SIG_CH1_IN2_IDX 42
#define BB_DIAG7_IDX 42
#define PCNT_CTRL_CH0_IN2_IDX 43
#define BB_DIAG8_IDX 43
#define PCNT_CTRL_CH1_IN2_IDX 44
#define BB_DIAG9_IDX 44
#define PCNT_SIG_CH0_IN3_IDX 45
#define BB_DIAG10_IDX 45
#define PCNT_SIG_CH1_IN3_IDX 46
#define BB_DIAG11_IDX 46
#define PCNT_CTRL_CH0_IN3_IDX 47
#define BB_DIAG12_IDX 47
#define PCNT_CTRL_CH1_IN3_IDX 48
#define BB_DIAG13_IDX 48
#define GPIO_BT_ACTIVE_IDX 49
#define BB_DIAG14_IDX 49
#define GPIO_BT_PRIORITY_IDX 50
#define BB_DIAG15_IDX 50
#define I2S0I_SD1_IN_IDX 51
#define BB_DIAG16_IDX 51
#define I2S0I_SD2_IN_IDX 52
#define BB_DIAG17_IDX 52
#define I2S0I_SD3_IN_IDX 53
#define BB_DIAG18_IDX 53
#define BB_DIAG19_IDX 54
#define USB_EXTPHY_VP_IDX 55
#define USB_EXTPHY_OEN_IDX 55
#define USB_EXTPHY_VM_IDX 56
#define USB_EXTPHY_SPEED_IDX 56
#define USB_EXTPHY_RCV_IDX 57
#define USB_EXTPHY_VPO_IDX 57
#define USB_OTG_IDDIG_IN_IDX 58
#define USB_EXTPHY_VMO_IDX 58
#define USB_OTG_AVALID_IN_IDX 59
#define USB_EXTPHY_SUSPND_IDX 59
#define USB_SRP_BVALID_IN_IDX 60
#define USB_OTG_IDPULLUP_IDX 60
#define USB_OTG_VBUSVALID_IN_IDX 61
#define USB_OTG_DPPULLDOWN_IDX 61
#define USB_SRP_SESSEND_IN_IDX 62
#define USB_OTG_DMPULLDOWN_IDX 62
#define USB_OTG_DRVVBUS_IDX 63
#define USB_SRP_CHRGVBUS_IDX 64
#define USB_SRP_DISCHRGVBUS_IDX 65
#define SPI3_CLK_IN_IDX 66
#define SPI3_CLK_OUT_IDX 66
#define SPI3_Q_IN_IDX 67
#define SPI3_Q_OUT_IDX 67
#define SPI3_D_IN_IDX 68
#define SPI3_D_OUT_IDX 68
#define SPI3_HD_IN_IDX 69
#define SPI3_HD_OUT_IDX 69
#define SPI3_WP_IN_IDX 70
#define SPI3_WP_OUT_IDX 70
#define SPI3_CS0_IN_IDX 71
#define SPI3_CS0_OUT_IDX 71
#define SPI3_CS1_OUT_IDX 72
#define EXT_ADC_START_IDX 73
#define LEDC_LS_SIG_OUT0_IDX 73
#define LEDC_LS_SIG_OUT1_IDX 74
#define LEDC_LS_SIG_OUT2_IDX 75
#define LEDC_LS_SIG_OUT3_IDX 76
#define LEDC_LS_SIG_OUT4_IDX 77
#define LEDC_LS_SIG_OUT5_IDX 78
#define LEDC_LS_SIG_OUT6_IDX 79
#define LEDC_LS_SIG_OUT7_IDX 80
#define RMT_SIG_IN0_IDX 81
#define RMT_SIG_OUT0_IDX 81
#define RMT_SIG_IN1_IDX 82
#define RMT_SIG_OUT1_IDX 82
#define RMT_SIG_IN2_IDX 83
#define RMT_SIG_OUT2_IDX 83
#define RMT_SIG_IN3_IDX 84
#define RMT_SIG_OUT3_IDX 84
#define I2CEXT0_SCL_IN_IDX 89
#define I2CEXT0_SCL_OUT_IDX 89
#define I2CEXT0_SDA_IN_IDX 90
#define I2CEXT0_SDA_OUT_IDX 90
#define I2CEXT1_SCL_IN_IDX 91
#define I2CEXT1_SCL_OUT_IDX 91
#define I2CEXT1_SDA_IN_IDX 92
#define I2CEXT1_SDA_OUT_IDX 92
#define GPIO_SD0_OUT_IDX 93
#define GPIO_SD1_OUT_IDX 94
#define GPIO_SD2_OUT_IDX 95
#define GPIO_SD3_OUT_IDX 96
#define GPIO_SD4_OUT_IDX 97
#define GPIO_SD5_OUT_IDX 98
#define GPIO_SD6_OUT_IDX 99
#define GPIO_SD7_OUT_IDX 100
#define FSPICLK_IN_IDX 101
#define FSPICLK_OUT_IDX 101
#define FSPIQ_IN_IDX 102
#define FSPIQ_OUT_IDX 102
#define FSPID_IN_IDX 103
#define FSPID_OUT_IDX 103
#define FSPIHD_IN_IDX 104
#define FSPIHD_OUT_IDX 104
#define FSPIWP_IN_IDX 105
#define FSPIWP_OUT_IDX 105
#define FSPIIO4_IN_IDX 106
#define FSPIIO4_OUT_IDX 106
#define FSPIIO5_IN_IDX 107
#define FSPIIO5_OUT_IDX 107
#define FSPIIO6_IN_IDX 108
#define FSPIIO6_OUT_IDX 108
#define FSPIIO7_IN_IDX 109
#define FSPIIO7_OUT_IDX 109
#define FSPICS0_IN_IDX 110
#define FSPICS0_OUT_IDX 110
#define FSPICS1_OUT_IDX 111
#define FSPICS2_OUT_IDX 112
#define FSPICS3_OUT_IDX 113
#define FSPICS4_OUT_IDX 114
#define FSPICS5_OUT_IDX 115
#define TWAI_RX_IDX 116
#define TWAI_TX_IDX 116
#define TWAI_BUS_OFF_ON_IDX 117
#define TWAI_CLKOUT_IDX 118
#define SUBSPICLK_OUT_IDX 119
#define SUBSPIQ_IN_IDX 120
#define SUBSPIQ_OUT_IDX 120
#define SUBSPID_IN_IDX 121
#define SUBSPID_OUT_IDX 121
#define SUBSPIHD_IN_IDX 122
#define SUBSPIHD_OUT_IDX 122
#define SUBSPIWP_IN_IDX 123
#define SUBSPIWP_OUT_IDX 123
#define SUBSPICS0_OUT_IDX 124
#define SUBSPICS1_OUT_IDX 125
#define FSPIDQS_OUT_IDX 126
#define SPI3_CS2_OUT_IDX 127
#define LCD_CS_IDX 132
#define CAM_DATA_IN0_IDX 133
#define LCD_DATA_OUT0_IDX 133
#define CAM_DATA_IN1_IDX 134
#define LCD_DATA_OUT1_IDX 134
#define CAM_DATA_IN2_IDX 135
#define LCD_DATA_OUT2_IDX 135
#define CAM_DATA_IN3_IDX 136
#define LCD_DATA_OUT3_IDX 136
#define CAM_DATA_IN4_IDX 137
#define LCD_DATA_OUT4_IDX 137
#define CAM_DATA_IN5_IDX 138
#define LCD_DATA_OUT5_IDX 138
#define CAM_DATA_IN6_IDX 139
#define LCD_DATA_OUT6_IDX 139
#define CAM_DATA_IN7_IDX 140
#define LCD_DATA_OUT7_IDX 140
#define CAM_DATA_IN8_IDX 141
#define LCD_DATA_OUT8_IDX 141
#define CAM_DATA_IN9_IDX 142
#define LCD_DATA_OUT9_IDX 142
#define CAM_DATA_IN10_IDX 143
#define LCD_DATA_OUT10_IDX 143
#define CAM_DATA_IN11_IDX 144
#define LCD_DATA_OUT11_IDX 144
#define CAM_DATA_IN12_IDX 145
#define LCD_DATA_OUT12_IDX 145
#define CAM_DATA_IN13_IDX 146
#define LCD_DATA_OUT13_IDX 146
#define CAM_DATA_IN14_IDX 147
#define LCD_DATA_OUT14_IDX 147
#define CAM_DATA_IN15_IDX 148
#define LCD_DATA_OUT15_IDX 148
#define CAM_PCLK_IDX 149
#define CAM_CLK_IDX 149
#define CAM_H_ENABLE_IDX 150
#define LCD_H_ENABLE_IDX 150
#define CAM_H_SYNC_IDX 151
#define LCD_H_SYNC_IDX 151
#define CAM_V_SYNC_IDX 152
#define LCD_V_SYNC_IDX 152
#define LCD_DC_IDX 153
#define LCD_PCLK_IDX 154
#define SUBSPID4_IN_IDX 155
#define SUBSPID4_OUT_IDX 155
#define SUBSPID5_IN_IDX 156
#define SUBSPID5_OUT_IDX 156
#define SUBSPID6_IN_IDX 157
#define SUBSPID6_OUT_IDX 157
#define SUBSPID7_IN_IDX 158
#define SUBSPID7_OUT_IDX 158
#define SUBSPIDQS_IN_IDX 159
#define SUBSPIDQS_OUT_IDX 159
#define PWM0_SYNC0_IN_IDX 160
#define PWM0_OUT0A_IDX 160
#define PWM0_SYNC1_IN_IDX 161
#define PWM0_OUT0B_IDX 161
#define PWM0_SYNC2_IN_IDX 162
#define PWM0_OUT1A_IDX 162
#define PWM0_F0_IN_IDX 163
#define PWM0_OUT1B_IDX 163
#define PWM0_F1_IN_IDX 164
#define PWM0_OUT2A_IDX 164
#define PWM0_F2_IN_IDX 165
#define PWM0_OUT2B_IDX 165
#define PWM0_CAP0_IN_IDX 166
#define PWM1_OUT0A_IDX 166
#define PWM0_CAP1_IN_IDX 167
#define PWM1_OUT0B_IDX 167
#define PWM0_CAP2_IN_IDX 168
#define PWM1_OUT1A_IDX 168
#define PWM1_SYNC0_IN_IDX 169
#define PWM1_OUT1B_IDX 169
#define PWM1_SYNC1_IN_IDX 170
#define PWM1_OUT2A_IDX 170
#define PWM1_SYNC2_IN_IDX 171
#define PWM1_OUT2B_IDX 171
#define PWM1_F0_IN_IDX 172
#define SDHOST_CCLK_OUT_1_IDX 172
#define PWM1_F1_IN_IDX 173
#define SDHOST_CCLK_OUT_2_IDX 173
#define PWM1_F2_IN_IDX 174
#define SDHOST_RST_N_1_IDX 174
#define PWM1_CAP0_IN_IDX 175
#define SDHOST_RST_N_2_IDX 175
#define PWM1_CAP1_IN_IDX 176
#define SDHOST_CCMD_OD_PULLUP_EN_N_IDX176
#define PWM1_CAP2_IN_IDX 177
#define SDIO_TOHOST_INT_OUT_IDX 177
#define SDHOST_CCMD_IN_1_IDX 178
#define SDHOST_CCMD_OUT_1_IDX 178
#define SDHOST_CCMD_IN_2_IDX 179
#define SDHOST_CCMD_OUT_2_IDX 179
#define SDHOST_CDATA_IN_10_IDX 180
#define SDHOST_CDATA_OUT_10_IDX 180
#define SDHOST_CDATA_IN_11_IDX 181
#define SDHOST_CDATA_OUT_11_IDX 181
#define SDHOST_CDATA_IN_12_IDX 182
#define SDHOST_CDATA_OUT_12_IDX 182
#define SDHOST_CDATA_IN_13_IDX 183
#define SDHOST_CDATA_OUT_13_IDX 183
#define SDHOST_CDATA_IN_14_IDX 184
#define SDHOST_CDATA_OUT_14_IDX 184
#define SDHOST_CDATA_IN_15_IDX 185
#define SDHOST_CDATA_OUT_15_IDX 185
#define SDHOST_CDATA_IN_16_IDX 186
#define SDHOST_CDATA_OUT_16_IDX 186
#define SDHOST_CDATA_IN_17_IDX 187
#define SDHOST_CDATA_OUT_17_IDX 187
#define PCMFSYNC_IN_IDX 188
#define BT_AUDIO0_IRQ_IDX 188
#define PCMCLK_IN_IDX 189
#define BT_AUDIO1_IRQ_IDX 189
#define PCMDIN_IDX 190
#define BT_AUDIO2_IRQ_IDX 190
#define RW_WAKEUP_REQ_IDX 191
#define BLE_AUDIO0_IRQ_IDX 191
#define SDHOST_DATA_STROBE_1_IDX 192
#define BLE_AUDIO1_IRQ_IDX 192
#define SDHOST_DATA_STROBE_2_IDX 193
#define BLE_AUDIO2_IRQ_IDX 193
#define SDHOST_CARD_DETECT_N_1_IDX 194
#define PCMFSYNC_OUT_IDX 194
#define SDHOST_CARD_DETECT_N_2_IDX 195
#define PCMCLK_OUT_IDX 195
#define SDHOST_CARD_WRITE_PRT_1_IDX 196
#define PCMDOUT_IDX 196
#define SDHOST_CARD_WRITE_PRT_2_IDX 197
#define BLE_AUDIO_SYNC0_P_IDX 197
#define SDHOST_CARD_INT_N_1_IDX 198
#define BLE_AUDIO_SYNC1_P_IDX 198
#define SDHOST_CARD_INT_N_2_IDX 199
#define BLE_AUDIO_SYNC2_P_IDX 199
#define ANT_SEL0_IDX 200
#define ANT_SEL1_IDX 201
#define ANT_SEL2_IDX 202
#define ANT_SEL3_IDX 203
#define ANT_SEL4_IDX 204
#define ANT_SEL5_IDX 205
#define ANT_SEL6_IDX 206
#define ANT_SEL7_IDX 207
#define SIG_IN_FUNC_223_IDX 208
#define SIG_IN_FUNC223_IDX 208
#define SIG_IN_FUNC_224_IDX 209
#define SIG_IN_FUNC224_IDX 209
#define SIG_IN_FUNC_225_IDX 210
#define SIG_IN_FUNC225_IDX 210
#define SIG_IN_FUNC_226_IDX 211
#define SIG_IN_FUNC226_IDX 211
#define SIG_IN_FUNC_227_IDX 212
#define SIG_IN_FUNC227_IDX 212
#define SDHOST_CDATA_IN_20_IDX 213
#define SDHOST_CDATA_OUT_20_IDX 213
#define SDHOST_CDATA_IN_21_IDX 214
#define SDHOST_CDATA_OUT_21_IDX 214
#define SDHOST_CDATA_IN_22_IDX 215
#define SDHOST_CDATA_OUT_22_IDX 215
#define SDHOST_CDATA_IN_23_IDX 216
#define SDHOST_CDATA_OUT_23_IDX 216
#define SDHOST_CDATA_IN_24_IDX 217
#define SDHOST_CDATA_OUT_24_IDX 217
#define SDHOST_CDATA_IN_25_IDX 218
#define SDHOST_CDATA_OUT_25_IDX 218
#define SDHOST_CDATA_IN_26_IDX 219
#define SDHOST_CDATA_OUT_26_IDX 219
#define SDHOST_CDATA_IN_27_IDX 220
#define SDHOST_CDATA_OUT_27_IDX 220
#define PRO_ALONEGPIO_IN0_IDX 221
#define PRO_ALONEGPIO_OUT0_IDX 221
#define PRO_ALONEGPIO_IN1_IDX 222
#define PRO_ALONEGPIO_OUT1_IDX 222
#define PRO_ALONEGPIO_IN2_IDX 223
#define PRO_ALONEGPIO_OUT2_IDX 223
#define PRO_ALONEGPIO_IN3_IDX 224
#define PRO_ALONEGPIO_OUT3_IDX 224
#define PRO_ALONEGPIO_IN4_IDX 225
#define PRO_ALONEGPIO_OUT4_IDX 225
#define PRO_ALONEGPIO_IN5_IDX 226
#define PRO_ALONEGPIO_OUT5_IDX 226
#define PRO_ALONEGPIO_IN6_IDX 227
#define PRO_ALONEGPIO_OUT6_IDX 227
#define PRO_ALONEGPIO_IN7_IDX 228
#define PRO_ALONEGPIO_OUT7_IDX 228
#define SYNCERR_IDX 229
#define SYNCFOUND_FLAG_IDX 230
#define EVT_CNTL_IMMEDIATE_ABORT_IDX 231
#define LINKLBL_IDX 232
#define DATA_EN_IDX 233
#define DATA_IDX 234
#define PKT_TX_ON_IDX 235
#define PKT_RX_ON_IDX 236
#define RW_TX_ON_IDX 237
#define RW_RX_ON_IDX 238
#define EVT_REQ_P_IDX 239
#define EVT_STOP_P_IDX 240
#define BT_MODE_ON_IDX 241
#define GPIO_LC_DIAG0_IDX 242
#define GPIO_LC_DIAG1_IDX 243
#define GPIO_LC_DIAG2_IDX 244
#define CH_IDX_IDX 245
#define RX_WINDOW_IDX 246
#define UPDATE_RX_IDX 247
#define RX_STATUS_IDX 248
#define CLK_GPIO_IDX 249
#define NBT_BLE_IDX 250
#define SIG_GPIO_OUT_IDX 256
#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_GPIO_SIGMAP_H */

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/****************************************************************************
* arch/xtensa/src/esp32s3/hardware/esp32s3_iomux.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_IOMUX_H
#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_IOMUX_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "esp32s3_soc.h"
/****************************************************************************
* Pre-preprocessor Definitions
****************************************************************************/
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
/* Output enable in sleep mode */
#define SLP_OE (BIT(0))
#define SLP_OE_M (BIT(0))
#define SLP_OE_V 1
#define SLP_OE_S 0
/* Pin used for wakeup from sleep */
#define SLP_SEL (BIT(1))
#define SLP_SEL_M (BIT(1))
#define SLP_SEL_V 1
#define SLP_SEL_S 1
/* Pulldown enable in sleep mode */
#define SLP_PD (BIT(2))
#define SLP_PD_M (BIT(2))
#define SLP_PD_V 1
#define SLP_PD_S 2
/* Pullup enable in sleep mode */
#define SLP_PU (BIT(3))
#define SLP_PU_M (BIT(3))
#define SLP_PU_V 1
#define SLP_PU_S 3
/* Input enable in sleep mode */
#define SLP_IE (BIT(4))
#define SLP_IE_M (BIT(4))
#define SLP_IE_V 1
#define SLP_IE_S 4
/* Drive strength in sleep mode */
#define SLP_DRV 0x3
#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
#define SLP_DRV_V 0x3
#define SLP_DRV_S 5
/* Pulldown enable */
#define FUN_PD (BIT(7))
#define FUN_PD_M (BIT(7))
#define FUN_PD_V 1
#define FUN_PD_S 7
/* Pullup enable */
#define FUN_PU (BIT(8))
#define FUN_PU_M (BIT(8))
#define FUN_PU_V 1
#define FUN_PU_S 8
/* Input enable */
#define FUN_IE (BIT(9))
#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
#define FUN_IE_V 1
#define FUN_IE_S 9
/* Drive strength */
#define FUN_DRV 0x3
#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
#define FUN_DRV_V 0x3
#define FUN_DRV_S 10
/* Function select (possible values are defined for each pin as
* FUNC_pinname_function below)
*/
#define MCU_SEL 0x7
#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
#define MCU_SEL_V 0x7
#define MCU_SEL_S 12
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_GPIO1_U
#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U
#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U
#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_GPIO4_U
#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_GPIO5_U
#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_GPIO6_U
#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_GPIO7_U
#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U
#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U
#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U
#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_GPIO11_U
#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U
#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_GPIO13_U
#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_GPIO14_U
#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_XTAL_32K_P_U
#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_XTAL_32K_N_U
#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_DAC_1_U
#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_DAC_2_U
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_GPIO20_U
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_GPIO21_U
#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_SPICS1_U
#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_SPIHD_U
#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_SPIWP_U
#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_SPICS0_U
#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_SPICLK_U
#define IO_MUX_GPIO31_REG PERIPHS_IO_MUX_SPIQ_U
#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_SPID_U
#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_GPIO33_U
#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_GPIO34_U
#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_GPIO35_U
#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_GPIO36_U
#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_GPIO37_U
#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_GPIO38_U
#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_MTCK_U
#define IO_MUX_GPIO40_REG PERIPHS_IO_MUX_MTDO_U
#define IO_MUX_GPIO41_REG PERIPHS_IO_MUX_MTDI_U
#define IO_MUX_GPIO42_REG PERIPHS_IO_MUX_MTMS_U
#define IO_MUX_GPIO43_REG PERIPHS_IO_MUX_U0TXD_U
#define IO_MUX_GPIO44_REG PERIPHS_IO_MUX_U0RXD_U
#define IO_MUX_GPIO45_REG PERIPHS_IO_MUX_GPIO45_U
#define IO_MUX_GPIO46_REG PERIPHS_IO_MUX_GPIO46_U
#define IO_MUX_GPIO47_REG PERIPHS_IO_MUX_SPICLK_P_U
#define IO_MUX_GPIO48_REG PERIPHS_IO_MUX_SPICLK_N_U
#define FUNC_GPIO_GPIO 1
#define PIN_FUNC_GPIO 1
#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define U1RXD_GPIO_NUM 18
#define U1TXD_GPIO_NUM 17
#define U0RXD_GPIO_NUM 44
#define U0TXD_GPIO_NUM 43
#define SPI_CS1_GPIO_NUM 26
#define SPI_HD_GPIO_NUM 27
#define SPI_WP_GPIO_NUM 28
#define SPI_CS0_GPIO_NUM 29
#define SPI_CLK_GPIO_NUM 30
#define SPI_Q_GPIO_NUM 31
#define SPI_D_GPIO_NUM 32
#define SPI_D4_GPIO_NUM 33
#define SPI_D5_GPIO_NUM 34
#define SPI_D6_GPIO_NUM 35
#define SPI_D7_GPIO_NUM 36
#define SPI_DQS_GPIO_NUM 37
#define SD_CLK_GPIO_NUM 12
#define SD_CMD_GPIO_NUM 11
#define SD_DATA0_GPIO_NUM 13
#define SD_DATA1_GPIO_NUM 14
#define SD_DATA2_GPIO_NUM 9
#define SD_DATA3_GPIO_NUM 10
#define MAX_RTC_GPIO_NUM 21
#define MAX_PAD_GPIO_NUM 48
#define MAX_GPIO_NUM 53
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE + 0x00)
#define PAD_POWER_SEL BIT(15)
#define PAD_POWER_SEL_V 0x1
#define PAD_POWER_SEL_M BIT(15)
#define PAD_POWER_SEL_S 15
#define PAD_POWER_SWITCH_DELAY 0x7
#define PAD_POWER_SWITCH_DELAY_V 0x7
#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
#define PAD_POWER_SWITCH_DELAY_S 12
#define CLK_OUT3 0xf
#define CLK_OUT3_V CLK_OUT3
#define CLK_OUT3_S 8
#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S)
#define CLK_OUT2 0xf
#define CLK_OUT2_V CLK_OUT2
#define CLK_OUT2_S 4
#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S)
#define CLK_OUT1 0xf
#define CLK_OUT1_V CLK_OUT1
#define CLK_OUT1_S 0
#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S)
#define PERIPHS_IO_MUX_GPIO0_U (REG_IO_MUX_BASE + 0x04)
#define FUNC_GPIO0_GPIO0 1
#define FUNC_GPIO0_GPIO0_0 0
#define PERIPHS_IO_MUX_GPIO1_U (REG_IO_MUX_BASE + 0x08)
#define FUNC_GPIO1_GPIO1 1
#define FUNC_GPIO1_GPIO1_0 0
#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE + 0x0c)
#define FUNC_GPIO2_GPIO2 1
#define FUNC_GPIO2_GPIO2_0 0
#define PERIPHS_IO_MUX_GPIO3_U (REG_IO_MUX_BASE + 0x10)
#define FUNC_GPIO3_GPIO3 1
#define FUNC_GPIO3_GPIO3_0 0
#define PERIPHS_IO_MUX_GPIO4_U (REG_IO_MUX_BASE + 0x14)
#define FUNC_GPIO4_GPIO4 1
#define FUNC_GPIO4_GPIO4_0 0
#define PERIPHS_IO_MUX_GPIO5_U (REG_IO_MUX_BASE + 0x18)
#define FUNC_GPIO5_GPIO5 1
#define FUNC_GPIO5_GPIO5_0 0
#define PERIPHS_IO_MUX_GPIO6_U (REG_IO_MUX_BASE + 0x1c)
#define FUNC_GPIO6_GPIO6 1
#define FUNC_GPIO6_GPIO6_0 0
#define PERIPHS_IO_MUX_GPIO7_U (REG_IO_MUX_BASE + 0x20)
#define FUNC_GPIO7_GPIO7 1
#define FUNC_GPIO7_GPIO7_0 0
#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE + 0x24)
#define FUNC_GPIO8_SUBSPICS1 3
#define FUNC_GPIO8_GPIO8 1
#define FUNC_GPIO8_GPIO8_0 0
#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE + 0x28)
#define FUNC_GPIO9_FSPIHD 4
#define FUNC_GPIO9_SUBSPIHD 3
#define FUNC_GPIO9_GPIO9 1
#define FUNC_GPIO9_GPIO9_0 0
#define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE + 0x2c)
#define FUNC_GPIO10_FSPICS0 4
#define FUNC_GPIO10_SUBSPICS0 3
#define FUNC_GPIO10_FSPIIO4 2
#define FUNC_GPIO10_GPIO10 1
#define FUNC_GPIO10_GPIO10_0 0
#define PERIPHS_IO_MUX_GPIO11_U (REG_IO_MUX_BASE + 0x30)
#define FUNC_GPIO11_FSPID 4
#define FUNC_GPIO11_SUBSPID 3
#define FUNC_GPIO11_FSPIIO5 2
#define FUNC_GPIO11_GPIO11 1
#define FUNC_GPIO11_GPIO11_0 0
#define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE + 0x34)
#define FUNC_GPIO12_FSPICLK 4
#define FUNC_GPIO12_SUBSPICLK 3
#define FUNC_GPIO12_FSPIIO6 2
#define FUNC_GPIO12_GPIO12 1
#define FUNC_GPIO12_GPIO12_0 0
#define PERIPHS_IO_MUX_GPIO13_U (REG_IO_MUX_BASE + 0x38)
#define FUNC_GPIO13_FSPIQ 4
#define FUNC_GPIO13_SUBSPIQ 3
#define FUNC_GPIO13_FSPIIO7 2
#define FUNC_GPIO13_GPIO13 1
#define FUNC_GPIO13_GPIO13_0 0
#define PERIPHS_IO_MUX_GPIO14_U (REG_IO_MUX_BASE + 0x3c)
#define FUNC_GPIO14_FSPIWP 4
#define FUNC_GPIO14_SUBSPIWP 3
#define FUNC_GPIO14_FSPIDQS 2
#define FUNC_GPIO14_GPIO14 1
#define FUNC_GPIO14_GPIO14_0 0
#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE + 0x40)
#define FUNC_XTAL_32K_P_U0RTS 2
#define FUNC_XTAL_32K_P_GPIO15 1
#define FUNC_XTAL_32K_P_GPIO15_0 0
#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE + 0x44)
#define FUNC_XTAL_32K_N_U0CTS 2
#define FUNC_XTAL_32K_N_GPIO16 1
#define FUNC_XTAL_32K_N_GPIO16_0 0
#define PERIPHS_IO_MUX_DAC_1_U (REG_IO_MUX_BASE + 0x48)
#define FUNC_DAC_1_U1TXD 2
#define FUNC_DAC_1_GPIO17 1
#define FUNC_DAC_1_GPIO17_0 0
#define PERIPHS_IO_MUX_DAC_2_U (REG_IO_MUX_BASE + 0x4c)
#define FUNC_DAC_2_CLK_OUT3 3
#define FUNC_DAC_2_U1RXD 2
#define FUNC_DAC_2_GPIO18 1
#define FUNC_DAC_2_GPIO18_0 0
#define PERIPHS_IO_MUX_GPIO19_U (REG_IO_MUX_BASE + 0x50)
#define FUNC_GPIO19_CLK_OUT2 3
#define FUNC_GPIO19_U1RTS 2
#define FUNC_GPIO19_GPIO19 1
#define FUNC_GPIO19_GPIO19_0 0
#define PERIPHS_IO_MUX_GPIO20_U (REG_IO_MUX_BASE + 0x54)
#define FUNC_GPIO20_CLK_OUT1 3
#define FUNC_GPIO20_U1CTS 2
#define FUNC_GPIO20_GPIO20 1
#define FUNC_GPIO20_GPIO20_0 0
#define PERIPHS_IO_MUX_GPIO21_U (REG_IO_MUX_BASE + 0x58)
#define FUNC_GPIO21_GPIO21 1
#define FUNC_GPIO21_GPIO21_0 0
#define PERIPHS_IO_MUX_SPICS1_U (REG_IO_MUX_BASE + 0x6c)
#define FUNC_SPICS1_GPIO26 1
#define FUNC_SPICS1_SPICS1 0
#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE + 0x70)
#define FUNC_SPIHD_GPIO27 1
#define FUNC_SPIHD_SPIHD 0
#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE + 0x74)
#define FUNC_SPIWP_GPIO28 1
#define FUNC_SPIWP_SPIWP 0
#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE + 0x78)
#define FUNC_SPICS0_GPIO29 1
#define FUNC_SPICS0_SPICS0 0
#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE + 0x7c)
#define FUNC_SPICLK_GPIO30 1
#define FUNC_SPICLK_SPICLK 0
#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE + 0x80)
#define FUNC_SPIQ_GPIO31 1
#define FUNC_SPIQ_SPIQ 0
#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE + 0x84)
#define FUNC_SPID_GPIO32 1
#define FUNC_SPID_SPID 0
#define PERIPHS_IO_MUX_GPIO33_U (REG_IO_MUX_BASE + 0x88)
#define FUNC_GPIO33_SPIIO4 4
#define FUNC_GPIO33_SUBSPIHD 3
#define FUNC_GPIO33_FSPIHD 2
#define FUNC_GPIO33_GPIO33 1
#define FUNC_GPIO33_GPIO33_0 0
#define PERIPHS_IO_MUX_GPIO34_U (REG_IO_MUX_BASE + 0x8c)
#define FUNC_GPIO34_SPIIO5 4
#define FUNC_GPIO34_SUBSPICS0 3
#define FUNC_GPIO34_FSPICS0 2
#define FUNC_GPIO34_GPIO34 1
#define FUNC_GPIO34_GPIO34_0 0
#define PERIPHS_IO_MUX_GPIO35_U (REG_IO_MUX_BASE + 0x90)
#define FUNC_GPIO35_SPIIO6 4
#define FUNC_GPIO35_SUBSPID 3
#define FUNC_GPIO35_FSPID 2
#define FUNC_GPIO35_GPIO35 1
#define FUNC_GPIO35_GPIO35_0 0
#define PERIPHS_IO_MUX_GPIO36_U (REG_IO_MUX_BASE + 0x94)
#define FUNC_GPIO36_SPIIO7 4
#define FUNC_GPIO36_SUBSPICLK 3
#define FUNC_GPIO36_FSPICLK 2
#define FUNC_GPIO36_GPIO36 1
#define FUNC_GPIO36_GPIO36_0 0
#define PERIPHS_IO_MUX_GPIO37_U (REG_IO_MUX_BASE + 0x98)
#define FUNC_GPIO37_SPIDQS 4
#define FUNC_GPIO37_SUBSPIQ 3
#define FUNC_GPIO37_FSPIQ 2
#define FUNC_GPIO37_GPIO37 1
#define FUNC_GPIO37_GPIO37_0 0
#define PERIPHS_IO_MUX_GPIO38_U (REG_IO_MUX_BASE + 0x9c)
#define FUNC_GPIO38_SUBSPIWP 3
#define FUNC_GPIO38_FSPIWP 2
#define FUNC_GPIO38_GPIO38 1
#define FUNC_GPIO38_GPIO38_0 0
#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE + 0xa0)
#define FUNC_MTCK_SUBSPICS1 3
#define FUNC_MTCK_CLK_OUT3 2
#define FUNC_MTCK_GPIO39 1
#define FUNC_MTCK_MTCK 0
#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE + 0xa4)
#define FUNC_MTDO_CLK_OUT2 2
#define FUNC_MTDO_GPIO40 1
#define FUNC_MTDO_MTDO 0
#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE + 0xa8)
#define FUNC_MTDI_CLK_OUT1 2
#define FUNC_MTDI_GPIO41 1
#define FUNC_MTDI_MTDI 0
#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE + 0xac)
#define FUNC_MTMS_GPIO42 1
#define FUNC_MTMS_MTMS 0
#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE + 0xb0)
#define FUNC_U0TXD_CLK_OUT1 2
#define FUNC_U0TXD_GPIO43 1
#define FUNC_U0TXD_U0TXD 0
#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE + 0xb4)
#define FUNC_U0RXD_CLK_OUT2 2
#define FUNC_U0RXD_GPIO44 1
#define FUNC_U0RXD_U0RXD 0
#define PERIPHS_IO_MUX_GPIO45_U (REG_IO_MUX_BASE + 0xb8)
#define FUNC_GPIO45_GPIO45 1
#define FUNC_GPIO45_GPIO45_0 0
#define PERIPHS_IO_MUX_GPIO46_U (REG_IO_MUX_BASE + 0xbc)
#define FUNC_GPIO46_GPIO46 1
#define FUNC_GPIO46_GPIO46_0 0
#define PERIPHS_IO_MUX_SPICLK_P_U (REG_IO_MUX_BASE + 0xc0)
#define FUNC_SPICLK_P_SUBSPICLK_DIFF 2
#define FUNC_SPICLK_P_GPIO47 1
#define FUNC_SPICLK_P_SPICLK_DIFF 0
#define PERIPHS_IO_MUX_SPICLK_N_U (REG_IO_MUX_BASE + 0xc4)
#define FUNC_SPICLK_N_SUBSPICLK_DIFF 2
#define FUNC_SPICLK_N_GPIO48 1
#define FUNC_SPICLK_N_SPICLK_DIFF 0
#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
#define IO_MUX_DATE 0xFFFFFFFF
#define IO_MUX_DATE_S 0
#define IO_MUX_DATE_VERSION 0x1907160
#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_IOMUX_H */

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/****************************************************************************
* arch/xtensa/src/esp32s3/hardware/esp32s3_rom_layout.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_ROM_LAYOUT_H
#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_ROM_LAYOUT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Structure and functions for returning ROM global layout
*
* This is for address symbols defined in the linker script,
* which may change during ECOs.
*/
struct esp32s3_rom_layout_s
{
uintptr_t dram0_stack_shared_mem_start;
uintptr_t dram0_rtos_reserved_start;
uintptr_t stack_sentry;
uintptr_t stack;
uintptr_t stack_sentry_app;
uintptr_t stack_app;
/* BTDM data */
uintptr_t data_start_btdm;
uintptr_t data_end_btdm;
uintptr_t bss_start_btdm;
uintptr_t bss_end_btdm;
uintptr_t data_start_btdm_rom;
uintptr_t data_end_btdm_rom;
uintptr_t data_start_interface_btdm;
uintptr_t data_end_interface_btdm;
uintptr_t bss_start_interface_btdm;
uintptr_t bss_end_interface_btdm;
/* PHY data */
uintptr_t dram_start_phyrom;
uintptr_t dram_end_phyrom;
/* Wi-Fi data */
uintptr_t dram_start_coexist;
uintptr_t dram_end_coexist;
uintptr_t dram_start_net80211;
uintptr_t dram_end_net80211;
uintptr_t dram_start_pp;
uintptr_t dram_end_pp;
uintptr_t data_start_interface_coexist;
uintptr_t data_end_interface_coexist;
uintptr_t bss_start_interface_coexist;
uintptr_t bss_end_interface_coexist;
uintptr_t data_start_interface_net80211;
uintptr_t data_end_interface_net80211;
uintptr_t bss_start_interface_net80211;
uintptr_t bss_end_interface_net80211;
uintptr_t data_start_interface_pp;
uintptr_t data_end_interface_pp;
uintptr_t bss_start_interface_pp;
uintptr_t bss_end_interface_pp;
uintptr_t dram_start_usbdev_rom;
uintptr_t dram_end_usbdev_rom;
uintptr_t dram_start_uart_rom;
uintptr_t dram_end_uart_rom;
};
extern const struct esp32s3_rom_layout_s *ets_rom_layout_p;
#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_ROM_LAYOUT_H */

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arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h Normal file
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/****************************************************************************
* arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SOC_H
#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SOC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#include <stdbool.h>
#include "xtensa_attr.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define PRO_CPU_NUM (0)
#define APP_CPU_NUM (1)
#define PRO_CPUID (0xcdcd)
#define APP_CPUID (0xabab)
/* Largest span of contiguous memory (DRAM or IRAM) in the address space */
#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW)
#define DR_REG_UART_BASE 0x60000000
#define DR_REG_SPI1_BASE 0x60002000
#define DR_REG_SPI0_BASE 0x60003000
#define DR_REG_GPIO_BASE 0x60004000
#define DR_REG_GPIO_SD_BASE 0x60004f00
#define DR_REG_FE2_BASE 0x60005000
#define DR_REG_FE_BASE 0x60006000
#define DR_REG_EFUSE_BASE 0x60007000
#define DR_REG_RTCCNTL_BASE 0x60008000
#define DR_REG_RTCIO_BASE 0x60008400
#define DR_REG_SENS_BASE 0x60008800
#define DR_REG_RTC_I2C_BASE 0x60008C00
#define DR_REG_IO_MUX_BASE 0x60009000
#define DR_REG_HINF_BASE 0x6000B000
#define DR_REG_UHCI1_BASE 0x6000C000
#define DR_REG_I2S_BASE 0x6000F000
#define DR_REG_UART1_BASE 0x60010000
#define DR_REG_BT_BASE 0x60011000
#define DR_REG_I2C_EXT_BASE 0x60013000
#define DR_REG_UHCI0_BASE 0x60014000
#define DR_REG_SLCHOST_BASE 0x60015000
#define DR_REG_RMT_BASE 0x60016000
#define DR_REG_PCNT_BASE 0x60017000
#define DR_REG_SLC_BASE 0x60018000
#define DR_REG_LEDC_BASE 0x60019000
#define DR_REG_NRX_BASE 0x6001CC00
#define DR_REG_BB_BASE 0x6001D000
#define DR_REG_PWM0_BASE 0x6001E000
#define DR_REG_TIMERGROUP0_BASE 0x6001F000
#define DR_REG_TIMERGROUP1_BASE 0x60020000
#define DR_REG_RTC_SLOWMEM_BASE 0x60021000
#define DR_REG_SYSTIMER_BASE 0x60023000
#define DR_REG_SPI2_BASE 0x60024000
#define DR_REG_SPI3_BASE 0x60025000
#define DR_REG_SYSCON_BASE 0x60026000
#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */
#define DR_REG_I2C1_EXT_BASE 0x60027000
#define DR_REG_SDMMC_BASE 0x60028000
#define DR_REG_PERI_BACKUP_BASE 0x6002A000
#define DR_REG_TWAI_BASE 0x6002B000
#define DR_REG_PWM1_BASE 0x6002C000
#define DR_REG_I2S1_BASE 0x6002D000
#define DR_REG_UART2_BASE 0x6002E000
#define DR_REG_USB_DEVICE_BASE 0x60038000
#define DR_REG_USB_WRAP_BASE 0x60039000
#define DR_REG_AES_BASE 0x6003A000
#define DR_REG_SHA_BASE 0x6003B000
#define DR_REG_RSA_BASE 0x6003C000
#define DR_REG_HMAC_BASE 0x6003E000
#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003D000
#define DR_REG_GDMA_BASE 0x6003F000
#define DR_REG_APB_SARADC_BASE 0x60040000
#define DR_REG_LCD_CAM_BASE 0x60041000
#define DR_REG_SYSTEM_BASE 0x600C0000
#define DR_REG_SENSITIVE_BASE 0x600C1000
#define DR_REG_INTERRUPT_BASE 0x600C2000
/* Cache configuration */
#define DR_REG_EXTMEM_BASE 0x600C4000
#define DR_REG_MMU_TABLE 0x600C5000
#define DR_REG_ITAG_TABLE 0x600C6000
#define DR_REG_DTAG_TABLE 0x600C8000
#define DR_REG_EXT_MEM_ENC 0x600CC000
#define DR_REG_ASSIST_DEBUG_BASE 0x600CE000
#define DR_REG_WORLD_CNTL_BASE 0x600D0000
#define DR_REG_DPORT_END 0x600D3FFC
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ((i) > 1 ? 0xe000 : 0))
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ((i) > 1 ? 0xe000 : 0 ))
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000)
/* Registers Operation */
#define ETS_UNCACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
#define BIT(nr) (1UL << (nr))
/* Write value to register */
#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
/* Read value from register */
#define REG_READ(_r) (*(volatile uint32_t *)(_r))
/* Get bit or get bits from register */
#define REG_GET_BIT(_r, _b) (*(volatile uint32_t *)(_r) & (_b))
/* Set bit or set bits to register */
#define REG_SET_BIT(_r, _b) (*(volatile uint32_t *)(_r) |= (_b))
/* Clear bit or clear bits of register */
#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t *)(_r) &= ~(_b))
/* Set bits of register controlled by mask */
#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t *)(_r) = (*(volatile uint32_t *)(_r) & ~(_m)) | ((_b) & (_m)))
/* Get field from register,
* used when _f is not left shifted by _f##_S
*/
#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f##_V))
/* Set field to register,
* used when _f is not left shifted by _f##_S
*/
#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))))
/* Get field value from a variable,
* used when _f is not left shifted by _f##_S
*/
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
/* Get field value from a variable,
* used when _f is left shifted by _f##_S
*/
#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
/* Set field value to a variable,
* used when _f is not left shifted by _f##_S
*/
#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
/* Set field value to a variable,
* used when _f is left shifted by _f##_S
*/
#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
/* Generate a value from a field value,
* used when _f is not left shifted by _f##_S
*/
#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
/* Generate a value from a field value,
* used when _f is left shifted by _f##_S
*/
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
/* Read value from register */
#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)))
/* Write value to register */
#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val)
/* Clear bits of register controlled by mask */
#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))))
/* Set bits of register controlled by mask */
#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)))
/* Get bits of register controlled by mask */
#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask))
/* Get bits of register controlled by highest bit and lowest bit */
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
/* Set bits of register controlled by mask and shift */
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) ))
/* Get field of register */
#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask))
/* Extract the field from the register and shift it to avoid wrong reading */
#define REG_MASK(_reg, _field) ((_reg & (_field##_M)) >> (_field##_S))
/* Helper to place a value in a field */
#define VALUE_TO_FIELD(_value, _field) ((_value << (_field##_S)) & (_field##_M))
/* Peripheral Clock */
#define APB_CLK_FREQ_ROM (40*1000000)
#define CPU_CLK_FREQ_ROM (40*1000000)
#define UART_CLK_FREQ_ROM (40*1000000)
#define EFUSE_CLK_FREQ_ROM (20*1000000)
#define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ (80*1000000)
#define REF_CLK_FREQ (1000000)
#define RTC_CLK_FREQ (20*1000000)
#define XTAL_CLK_FREQ (40*1000000)
#define UART_CLK_FREQ APB_CLK_FREQ
#define WDT_CLK_FREQ APB_CLK_FREQ
#define TIMER_CLK_FREQ (80000000>>4)
#define SPI_CLK_DIV 4
#define TICKS_PER_US_ROM 40
#define GPIO_MATRIX_DELAY_NS 0
/* Overall memory map */
#define SOC_DROM_LOW 0x3C000000
#define SOC_DROM_HIGH 0x3D000000
#define SOC_IROM_LOW 0x42000000
#define SOC_IROM_HIGH 0x44000000
#define SOC_IRAM_LOW 0x40370000
#define SOC_IRAM_HIGH 0x403E0000
#define SOC_DRAM_LOW 0x3FC88000
#define SOC_DRAM_HIGH 0x3FD00000
#define SOC_RTC_IRAM_LOW 0x600FE000
#define SOC_RTC_IRAM_HIGH 0x60100000
#define SOC_RTC_DRAM_LOW 0x600FE000
#define SOC_RTC_DRAM_HIGH 0x60100000
#define SOC_RTC_DATA_LOW 0x50000000
#define SOC_RTC_DATA_HIGH 0x50002000
#define SOC_EXTRAM_DATA_LOW 0x3D000000
#define SOC_EXTRAM_DATA_HIGH 0x3E000000
#define SOC_IROM_MASK_LOW 0x40000000
#define SOC_IROM_MASK_HIGH 0x4001A100
#define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW)
/* First and last words of the D/IRAM region, for both the DRAM address
* as well as the IRAM alias.
*/
#define SOC_DIRAM_IRAM_LOW 0x40378000
#define SOC_DIRAM_IRAM_HIGH 0x403E0000
#define SOC_DIRAM_DRAM_LOW 0x3FC88000
#define SOC_DIRAM_DRAM_HIGH 0x3FCF0000
/* Region of memory accessible via DMA in internal memory.
* See esp_ptr_dma_capable().
*/
#define SOC_DMA_LOW 0x3FC88000
#define SOC_DMA_HIGH 0x3FD00000
/* Region of memory accessible via DMA in external memory.
* See esp_ptr_dma_ext_capable().
*/
#define SOC_DMA_EXT_LOW SOC_EXTRAM_DATA_LOW
#define SOC_DMA_EXT_HIGH SOC_EXTRAM_DATA_HIGH
/* Region of memory that is byte-accessible.
* See esp_ptr_byte_accessible().
*/
#define SOC_BYTE_ACCESSIBLE_LOW 0x3FC88000
#define SOC_BYTE_ACCESSIBLE_HIGH 0x3FD00000
/* Region of memory that is internal, as in on the same silicon die as the
* ESP32 CPUs (excluding RTC data region, that's checked separately.)
* See esp_ptr_internal().
*/
#define SOC_MEM_INTERNAL_LOW 0x3FC88000
#define SOC_MEM_INTERNAL_HIGH 0x403E2000
/* Start (highest address) of ROM boot stack, only relevant during
* early boot
*/
#define SOC_ROM_STACK_START 0x3fcebf10
/* Interrupt cpu using table, Please see the core-isa.h */
/****************************************************************************
* Intr num Level Type PRO CPU usage APP CPU usage
* 0 1 extern level WMAC Reserved
* 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA
* 2 1 extern level
* 3 1 extern level
* 4 1 extern level WBB
* 5 1 extern level BT/BLE Controller BT/BLE Controller
* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
* 7 1 software BT/BLE VHCI BT/BLE VHCI
* 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX)
* 9 1 extern level
* 10 1 extern edge
* 11 3 profiling
* 12 1 extern level
* 13 1 extern level
* 14 7 nmi Reserved Reserved
* 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3)
* 16 5 timer
* 17 1 extern level
* 18 1 extern level
* 19 2 extern level
* 20 2 extern level
* 21 2 extern level
* 22 3 extern edge
* 23 3 extern level
* 24 4 extern level TG1_WDT
* 25 4 extern level CACHEERR
* 26 5 extern level
* 27 3 extern level Reserved Reserved
* 28 4 extern edge DPORT ACCESS DPORT ACCESS
* 29 3 software Reserved Reserved
* 30 4 extern edge Reserved Reserved
* 31 5 extern level
****************************************************************************/
/* Core voltage needs to be increased in two cases:
* 1. running at 240 MHz
* 2. running with 80MHz Flash frequency
*/
#if defined(CONFIG_ESP32S3_FLASH_FREQ_80M) || defined(CONFIG_ESP32S3_FLASH_FREQ_120M)
#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V25
#else
#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10
#endif
#define DIG_DBIAS_240M RTC_CNTL_DBIAS_1V25
#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
/* CPU0 Interrupt number reserved, not touch this. */
#define ETS_WMAC_INUM 0
#define ETS_BT_HOST_INUM 1
#define ETS_WBB_INUM 4
#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
#define ETS_FRC1_INUM 22
#define ETS_T1_WDT_INUM 24
#define ETS_CACHEERR_INUM 25
#define ETS_DPORT_INUM 28
/* CPU0 Interrupt number used in ROM, should be cancelled in SDK */
#define ETS_SLC_INUM 1
#define ETS_UART0_INUM 5
#define ETS_UART1_INUM 5
#define ETS_SPI2_INUM 1
/* CPU0 Interrupt number used in ROM code only when module init function
* called, should pay attention here.
*/
#define ETS_FRC_TIMER2_INUM 10 /* use edge*/
#define ETS_GPIO_INUM 4
/* Other interrupt number should be managed by the user */
/* Invalid interrupt for number interrupt matrix */
#define ETS_INVALID_INUM 6
#define MHZ (1000000)
#define RTC_PLL_FREQ_320M 320
#define RTC_PLL_FREQ_480M 480
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s3_sp_dram
*
* Description:
* Check if the stack pointer is in DRAM.
*
****************************************************************************/
static inline bool IRAM_ATTR esp32s3_sp_dram(uint32_t sp)
{
return (sp >= SOC_DRAM_LOW + 0x10 && sp < SOC_DRAM_HIGH - 0x10);
}
/****************************************************************************
* Name: esp32s3_ptr_extram
*
* Description:
* Check if the buffer comes from the external RAM
*
****************************************************************************/
static inline bool IRAM_ATTR esp32s3_ptr_extram(const void *p)
{
return ((intptr_t)p >= SOC_EXTRAM_DATA_LOW &&
(intptr_t)p < SOC_EXTRAM_DATA_HIGH);
}
/****************************************************************************
* Name: esp32s3_ptr_exec
*
* Description:
* Check if the pointer is within an executable range.
*
****************************************************************************/
static inline bool IRAM_ATTR esp32s3_ptr_exec(const void *p)
{
intptr_t ip = (intptr_t)p;
return (ip >= SOC_IROM_LOW && ip < SOC_IROM_HIGH)
|| (ip >= SOC_IRAM_LOW && ip < SOC_IRAM_HIGH)
|| (ip >= SOC_IROM_MASK_LOW && ip < SOC_IROM_MASK_HIGH)
#if defined(SOC_CACHE_APP_LOW) && !defined(CONFIG_SMP)
|| (ip >= SOC_CACHE_APP_LOW && ip < SOC_CACHE_APP_HIGH)
#endif
|| (ip >= SOC_RTC_IRAM_LOW && ip < SOC_RTC_IRAM_HIGH);
}
#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SOC_H */

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/****************************************************************************
* arch/xtensa/src/esp32s3/hardware/esp32s3_systimer.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SYSTIMER_H
#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SYSTIMER_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "esp32s3_soc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* SYSTIMER_CONF_REG register
* Configure system timer clock
*/
#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
/* SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
* register file clk gating
*/
#define SYSTIMER_CLK_EN (BIT(31))
#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
#define SYSTIMER_CLK_EN_V 0x00000001
#define SYSTIMER_CLK_EN_S 31
/* SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
* timer unit0 work enable
*/
#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30))
#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001
#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30
/* SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
* timer unit1 work enable
*/
#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29))
#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001
#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29
/* SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
* If timer unit0 is stalled when core0 stalled
*/
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28))
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28
/* SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
* If timer unit0 is stalled when core1 stalled
*/
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27))
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27
/* SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
* If timer unit1 is stalled when core0 stalled
*/
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26))
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26
/* SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
* If timer unit1 is stalled when core1 stalled
*/
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25))
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25
/* SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
* target0 work enable
*/
#define SYSTIMER_TARGET0_WORK_EN (BIT(24))
#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001
#define SYSTIMER_TARGET0_WORK_EN_S 24
/* SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
* target1 work enable
*/
#define SYSTIMER_TARGET1_WORK_EN (BIT(23))
#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001
#define SYSTIMER_TARGET1_WORK_EN_S 23
/* SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
* target2 work enable
*/
#define SYSTIMER_TARGET2_WORK_EN (BIT(22))
#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001
#define SYSTIMER_TARGET2_WORK_EN_S 22
/* SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0;
* systimer clock force on
*/
#define SYSTIMER_SYSTIMER_CLK_FO (BIT(0))
#define SYSTIMER_SYSTIMER_CLK_FO_M (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S)
#define SYSTIMER_SYSTIMER_CLK_FO_V 0x00000001
#define SYSTIMER_SYSTIMER_CLK_FO_S 0
/* SYSTIMER_UNIT0_OP_REG register
* system timer unit0 value update register
*/
#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
/* SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
* update timer_unit0
*/
#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30))
#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001
#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30
/* SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
* timer value is sync and valid
*/
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29))
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29
/* SYSTIMER_UNIT1_OP_REG register
* system timer unit1 value update register
*/
#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
/* SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
* update timer unit1
*/
#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30))
#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001
#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30
/* SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
* timer value is sync and valid
*/
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29))
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29
/* SYSTIMER_UNIT0_LOAD_HI_REG register
* system timer unit0 value high load register
*/
#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
/* SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
* timer unit0 load high 20 bits
*/
#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000fffff
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000fffff
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0
/* SYSTIMER_UNIT0_LOAD_LO_REG register
* system timer unit0 value low load register
*/
#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
/* SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* timer unit0 load low 32 bits
*/
#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xffffffff
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xffffffff
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0
/* SYSTIMER_UNIT1_LOAD_HI_REG register
* system timer unit1 value high load register
*/
#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
/* SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
* timer unit1 load high 20 bits
*/
#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000fffff
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000fffff
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0
/* SYSTIMER_UNIT1_LOAD_LO_REG register
* system timer unit1 value low load register
*/
#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
/* SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* timer unit1 load low 32 bits
*/
#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xffffffff
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xffffffff
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0
/* SYSTIMER_TARGET0_HI_REG register
* system timer comp0 value high register
*/
#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
/* SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
* timer taget0 high 20 bits
*/
#define SYSTIMER_TIMER_TARGET0_HI 0x000fffff
#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
#define SYSTIMER_TIMER_TARGET0_HI_V 0x000fffff
#define SYSTIMER_TIMER_TARGET0_HI_S 0
/* SYSTIMER_TARGET0_LO_REG register
* system timer comp0 value low register
*/
#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
/* SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
* timer taget0 low 32 bits
*/
#define SYSTIMER_TIMER_TARGET0_LO 0xffffffff
#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
#define SYSTIMER_TIMER_TARGET0_LO_V 0xffffffff
#define SYSTIMER_TIMER_TARGET0_LO_S 0
/* SYSTIMER_TARGET1_HI_REG register
* system timer comp1 value high register
*/
#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
/* SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
* timer taget1 high 20 bits
*/
#define SYSTIMER_TIMER_TARGET1_HI 0x000fffff
#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
#define SYSTIMER_TIMER_TARGET1_HI_V 0x000fffff
#define SYSTIMER_TIMER_TARGET1_HI_S 0
/* SYSTIMER_TARGET1_LO_REG register
* system timer comp1 value low register
*/
#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
/* SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
* timer taget1 low 32 bits
*/
#define SYSTIMER_TIMER_TARGET1_LO 0xffffffff
#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
#define SYSTIMER_TIMER_TARGET1_LO_V 0xffffffff
#define SYSTIMER_TIMER_TARGET1_LO_S 0
/* SYSTIMER_TARGET2_HI_REG register
* system timer comp2 value high register
*/
#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
/* SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
* timer taget2 high 20 bits
*/
#define SYSTIMER_TIMER_TARGET2_HI 0x000fffff
#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
#define SYSTIMER_TIMER_TARGET2_HI_V 0x000fffff
#define SYSTIMER_TIMER_TARGET2_HI_S 0
/* SYSTIMER_TARGET2_LO_REG register
* system timer comp2 value low register
*/
#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
/* SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
* timer taget2 low 32 bits
*/
#define SYSTIMER_TIMER_TARGET2_LO 0xffffffff
#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
#define SYSTIMER_TIMER_TARGET2_LO_V 0xffffffff
#define SYSTIMER_TIMER_TARGET2_LO_S 0
/* SYSTIMER_TARGET0_CONF_REG register
* system timer comp0 target mode register
*/
#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
/* SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31))
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31
/* SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
* Set target0 to period mode
*/
#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30))
#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001
#define SYSTIMER_TARGET0_PERIOD_MODE_S 30
/* SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
* target0 period
*/
#define SYSTIMER_TARGET0_PERIOD 0x03ffffff
#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
#define SYSTIMER_TARGET0_PERIOD_V 0x03ffffff
#define SYSTIMER_TARGET0_PERIOD_S 0
/* SYSTIMER_TARGET1_CONF_REG register
* system timer comp1 target mode register
*/
#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
/* SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31))
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31
/* SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
* Set target1 to period mode
*/
#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30))
#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001
#define SYSTIMER_TARGET1_PERIOD_MODE_S 30
/* SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
* target1 period
*/
#define SYSTIMER_TARGET1_PERIOD 0x03ffffff
#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
#define SYSTIMER_TARGET1_PERIOD_V 0x03ffffff
#define SYSTIMER_TARGET1_PERIOD_S 0
/* SYSTIMER_TARGET2_CONF_REG register
* system timer comp2 target mode register
*/
#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
/* SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31))
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31
/* SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
* Set target2 to period mode
*/
#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30))
#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001
#define SYSTIMER_TARGET2_PERIOD_MODE_S 30
/* SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
* target2 period
*/
#define SYSTIMER_TARGET2_PERIOD 0x03ffffff
#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
#define SYSTIMER_TARGET2_PERIOD_V 0x03ffffff
#define SYSTIMER_TARGET2_PERIOD_S 0
/* SYSTIMER_UNIT0_VALUE_HI_REG register
* system timer unit0 value high register
*/
#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
/* SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
* timer read value high 20bits
*/
#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000fffff
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000fffff
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0
/* SYSTIMER_UNIT0_VALUE_LO_REG register
* system timer unit0 value low register
*/
#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
/* SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
* timer read value low 32bits
*/
#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xffffffff
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xffffffff
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0
/* SYSTIMER_UNIT1_VALUE_HI_REG register
* system timer unit1 value high register
*/
#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
/* SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
* timer read value high 20bits
*/
#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000fffff
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000fffff
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0
/* SYSTIMER_UNIT1_VALUE_LO_REG register
* system timer unit1 value low register
*/
#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
/* SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
* timer read value low 32bits
*/
#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xffffffff
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xffffffff
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0
/* SYSTIMER_COMP0_LOAD_REG register
* system timer comp0 conf sync register
*/
#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
/* SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
* timer comp0 sync enable signal
*/
#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0))
#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001
#define SYSTIMER_TIMER_COMP0_LOAD_S 0
/* SYSTIMER_COMP1_LOAD_REG register
* system timer comp1 conf sync register
*/
#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
/* SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
* timer comp1 sync enable signal
*/
#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0))
#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001
#define SYSTIMER_TIMER_COMP1_LOAD_S 0
/* SYSTIMER_COMP2_LOAD_REG register
* system timer comp2 conf sync register
*/
#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
/* SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
* timer comp2 sync enable signal
*/
#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0))
#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001
#define SYSTIMER_TIMER_COMP2_LOAD_S 0
/* SYSTIMER_UNIT0_LOAD_REG register
* system timer unit0 conf sync register
*/
#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
/* SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
* timer unit0 sync enable signal
*/
#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0))
#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001
#define SYSTIMER_TIMER_UNIT0_LOAD_S 0
/* SYSTIMER_UNIT1_LOAD_REG register
* system timer unit1 conf sync register
*/
#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
/* SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
* timer unit1 sync enable signal
*/
#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0))
#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001
#define SYSTIMER_TIMER_UNIT1_LOAD_S 0
/* SYSTIMER_INT_ENA_REG register
* systimer interrupt enable register
*/
#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
/* SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
* interupt2 enable
*/
#define SYSTIMER_TARGET2_INT_ENA (BIT(2))
#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001
#define SYSTIMER_TARGET2_INT_ENA_S 2
/* SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
* interupt1 enable
*/
#define SYSTIMER_TARGET1_INT_ENA (BIT(1))
#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001
#define SYSTIMER_TARGET1_INT_ENA_S 1
/* SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
* interupt0 enable
*/
#define SYSTIMER_TARGET0_INT_ENA (BIT(0))
#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001
#define SYSTIMER_TARGET0_INT_ENA_S 0
/* SYSTIMER_INT_RAW_REG register
* systimer interrupt raw register
*/
#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
/* SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
* interupt2 raw
*/
#define SYSTIMER_TARGET2_INT_RAW (BIT(2))
#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001
#define SYSTIMER_TARGET2_INT_RAW_S 2
/* SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* interupt1 raw
*/
#define SYSTIMER_TARGET1_INT_RAW (BIT(1))
#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001
#define SYSTIMER_TARGET1_INT_RAW_S 1
/* SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* interupt0 raw
*/
#define SYSTIMER_TARGET0_INT_RAW (BIT(0))
#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001
#define SYSTIMER_TARGET0_INT_RAW_S 0
/* SYSTIMER_INT_CLR_REG register
* systimer interrupt clear register
*/
#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
/* SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
* interupt2 clear
*/
#define SYSTIMER_TARGET2_INT_CLR (BIT(2))
#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001
#define SYSTIMER_TARGET2_INT_CLR_S 2
/* SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
* interupt1 clear
*/
#define SYSTIMER_TARGET1_INT_CLR (BIT(1))
#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001
#define SYSTIMER_TARGET1_INT_CLR_S 1
/* SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
* interupt0 clear
*/
#define SYSTIMER_TARGET0_INT_CLR (BIT(0))
#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001
#define SYSTIMER_TARGET0_INT_CLR_S 0
/* SYSTIMER_INT_ST_REG register
* systimer interrupt status register
*/
#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
/* SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
* interupt2 status
*/
#define SYSTIMER_TARGET2_INT_ST (BIT(2))
#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
#define SYSTIMER_TARGET2_INT_ST_V 0x00000001
#define SYSTIMER_TARGET2_INT_ST_S 2
/* SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
* interupt1 status
*/
#define SYSTIMER_TARGET1_INT_ST (BIT(1))
#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
#define SYSTIMER_TARGET1_INT_ST_V 0x00000001
#define SYSTIMER_TARGET1_INT_ST_S 1
/* SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
* interupt0 status
*/
#define SYSTIMER_TARGET0_INT_ST (BIT(0))
#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
#define SYSTIMER_TARGET0_INT_ST_V 0x00000001
#define SYSTIMER_TARGET0_INT_ST_S 0
/* SYSTIMER_REAL_TARGET0_LO_REG register
* system timer comp0 actual target value low register
*/
#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74)
/* SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0;
* actual target value value low 32bits
*/
#define SYSTIMER_TARGET0_LO_RO 0xffffffff
#define SYSTIMER_TARGET0_LO_RO_M (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S)
#define SYSTIMER_TARGET0_LO_RO_V 0xffffffff
#define SYSTIMER_TARGET0_LO_RO_S 0
/* SYSTIMER_REAL_TARGET0_HI_REG register
* system timer comp0 actual target value high register
*/
#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78)
/* SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0;
* actual target value value high 20bits
*/
#define SYSTIMER_TARGET0_HI_RO 0x000fffff
#define SYSTIMER_TARGET0_HI_RO_M (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S)
#define SYSTIMER_TARGET0_HI_RO_V 0x000fffff
#define SYSTIMER_TARGET0_HI_RO_S 0
/* SYSTIMER_REAL_TARGET1_LO_REG register
* system timer comp1 actual target value low register
*/
#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c)
/* SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0;
* actual target value value low 32bits
*/
#define SYSTIMER_TARGET1_LO_RO 0xffffffff
#define SYSTIMER_TARGET1_LO_RO_M (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S)
#define SYSTIMER_TARGET1_LO_RO_V 0xffffffff
#define SYSTIMER_TARGET1_LO_RO_S 0
/* SYSTIMER_REAL_TARGET1_HI_REG register
* system timer comp1 actual target value high register
*/
#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80)
/* SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0;
* actual target value value high 20bits
*/
#define SYSTIMER_TARGET1_HI_RO 0x000fffff
#define SYSTIMER_TARGET1_HI_RO_M (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S)
#define SYSTIMER_TARGET1_HI_RO_V 0x000fffff
#define SYSTIMER_TARGET1_HI_RO_S 0
/* SYSTIMER_REAL_TARGET2_LO_REG register
* system timer comp2 actual target value low register
*/
#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84)
/* SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0;
* actual target value value low 32bits
*/
#define SYSTIMER_TARGET2_LO_RO 0xffffffff
#define SYSTIMER_TARGET2_LO_RO_M (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S)
#define SYSTIMER_TARGET2_LO_RO_V 0xffffffff
#define SYSTIMER_TARGET2_LO_RO_S 0
/* SYSTIMER_REAL_TARGET2_HI_REG register
* system timer comp2 actual target value high register
*/
#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88)
/* SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0;
* actual target value value high 20bits
*/
#define SYSTIMER_TARGET2_HI_RO 0x000fffff
#define SYSTIMER_TARGET2_HI_RO_M (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S)
#define SYSTIMER_TARGET2_HI_RO_V 0x000fffff
#define SYSTIMER_TARGET2_HI_RO_S 0
/* SYSTIMER_DATE_REG register
* system timer version control register
*/
#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
/* SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 33628753;
* systimer register version
*/
#define SYSTIMER_DATE 0xffffffff
#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
#define SYSTIMER_DATE_V 0xffffffff
#define SYSTIMER_DATE_S 0
#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SYSTIMER_H */

1961
arch/xtensa/src/esp32s3/hardware/esp32s3_uart.h Normal file
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File diff suppressed because it is too large Load Diff

2
arch/xtensa/src/lx7/Toolchain.defs
View File

@ -38,7 +38,7 @@ ifeq ($(CONFIG_XTENSA_TOOLCHAIN_XCLANG), y)
endif
ifeq ($(CONFIG_XTENSA_TOOLCHAIN_ESP), y)
CROSSDEV = xtensa-esp32s2-elf-
CROSSDEV = xtensa-$(CONFIG_ARCH_CHIP)-elf-
endif
ARCHCPUFLAGS =

18
boards/Kconfig
View File

@ -279,6 +279,17 @@ config ARCH_BOARD_ESP32S2_SAOLA_1
---help---
This is the ESP32-S2-Saola-1 board
config ARCH_BOARD_ESP32S3_DEVKIT
bool "Espressif ESP32-S3 DevKit"
depends on ARCH_CHIP_ESP32S3WROOM1 || ARCH_CHIP_ESP32S3MINI1
select ARCH_HAVE_LEDS
---help---
The ESP32-S3 DevKit features the ESP32-S3 CPU with dual Xtensa LX7 cores.
It comes in two flavors, the ESP32-S3-DevKitM-1 and the ESP32-S3-DevKitC-1.
The ESP32-C3-DevKitM-1 version contains the ESP32-S3-MINI-1/1U module and the
ESP32-S3-DevKitC-1 version may be based either on ESP32-S3-WROOM-1/1U or
ESP32-S3-WROOM-2/2U.
config ARCH_BOARD_ET_STM32_STAMP
bool "Futurlec: ET-STM32 Stamp"
depends on ARCH_CHIP_STM32F103RE
@ -2401,6 +2412,7 @@ config ARCH_BOARD
default "esp32-wrover-kit" if ARCH_BOARD_ESP32_WROVERKIT
default "esp32c3-devkit" if ARCH_BOARD_ESP32C3_DEVKIT
default "esp32s2-saola-1" if ARCH_BOARD_ESP32S2_SAOLA_1
default "esp32s3-devkit" if ARCH_BOARD_ESP32S3_DEVKIT
default "et-stm32-stamp" if ARCH_BOARD_ET_STM32_STAMP
default "ez80f910200kitg" if ARCH_BOARD_EZ80F910200KITG
default "ez80f910200zco" if ARCH_BOARD_EZ80F910200ZCO
@ -3282,6 +3294,12 @@ endif
if ARCH_BOARD_ESP32S2_SAOLA_1
source "boards/xtensa/esp32s2/esp32s2-saola-1/Kconfig"
endif
if ARCH_CHIP_ESP32S3 && !ARCH_BOARD_CUSTOM
source "boards/xtensa/esp32s3/common/Kconfig"
endif
if ARCH_BOARD_ESP32S3_DEVKIT
source "boards/xtensa/esp32s3/esp32s3-devkit/Kconfig"
endif
if ARCH_BOARD_SIM
source "boards/sim/sim/sim/Kconfig"
endif

13
boards/xtensa/esp32s3/common/Kconfig Normal file
View File

@ -0,0 +1,13 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
config ESP32S3_MERGE_BINS
bool "Merge raw binary files into a single file"
default n
---help---
Merge the raw binary files into a single file for flashing to the
device.
This is only useful when the path to binary files (e.g. bootloader)
is provided via the ESPTOOL_BINDIR variable.

33
boards/xtensa/esp32s3/common/Makefile Normal file
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@ -0,0 +1,33 @@
#############################################################################
# boards/xtensa/esp32s3/common/Makefile
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
#############################################################################
include $(TOPDIR)/Make.defs
include board/Make.defs
include src/Make.defs
DEPPATH += --dep-path board
DEPPATH += --dep-path src
include $(TOPDIR)/boards/Board.mk
ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
BOARDDIR = $(ARCHSRCDIR)$(DELIM)board
CFLAGS += $(shell $(INCDIR) "$(CC)" $(BOARDDIR)$(DELIM)include)

23
boards/xtensa/esp32s3/common/src/Make.defs Normal file
View File

@ -0,0 +1,23 @@
#############################################################################
# boards/xtensa/esp32s3/common/src/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
#############################################################################
DEPPATH += --dep-path src
VPATH += :src
CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src)

8
boards/xtensa/esp32s3/esp32s3-devkit/Kconfig Normal file
View File

@ -0,0 +1,8 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_BOARD_ESP32S3_DEVKIT
endif # ARCH_BOARD_ESP32S3_DEVKIT

48
boards/xtensa/esp32s3/esp32s3-devkit/configs/nsh/defconfig Normal file
View File

@ -0,0 +1,48 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_ARCH_LEDS is not set
# CONFIG_NSH_ARGCAT is not set
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
# CONFIG_NSH_CMDPARMS is not set
CONFIG_ARCH="xtensa"
CONFIG_ARCH_BOARD="esp32s3-devkit"
CONFIG_ARCH_BOARD_ESP32S3_DEVKIT=y
CONFIG_ARCH_CHIP="esp32s3"
CONFIG_ARCH_CHIP_ESP32S3=y
CONFIG_ARCH_CHIP_ESP32S3WROOM1=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH_XTENSA=y
CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BUILTIN=y
CONFIG_DEBUG_FULLOPT=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_ESP32S3_UART0=y
CONFIG_FS_PROCFS=y
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_IDLETHREAD_STACKSIZE=3072
CONFIG_INIT_ENTRYPOINT="nsh_main"
CONFIG_INTELHEX_BINARY=y
CONFIG_MM_REGIONS=3
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_RAM_SIZE=114688
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_SDCLONE_DISABLE=y
CONFIG_START_DAY=6
CONFIG_START_MONTH=12
CONFIG_START_YEAR=2011
CONFIG_SYSTEM_NSH=y
CONFIG_UART0_SERIAL_CONSOLE=y

73
boards/xtensa/esp32s3/esp32s3-devkit/include/board.h Normal file
View File

@ -0,0 +1,73 @@
/****************************************************************************
* boards/xtensa/esp32s3/esp32s3-devkit/include/board.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __BOARDS_XTENSA_ESP32S3_ESP32S3_DEVKIT_INCLUDE_BOARD_H
#define __BOARDS_XTENSA_ESP32S3_ESP32S3_DEVKIT_INCLUDE_BOARD_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Clocking *****************************************************************/
/* The ESP32-S3 DevKit board is fitted with a 40MHz crystal */
#define BOARD_XTAL_FREQUENCY 40000000
/* Clock reconfiguration is currently disabled, so the CPU will be running
* at the XTAL frequency or at two times the XTAL frequency, depending upon
* how we load the code:
*
* - If we load the code into FLASH at address 0x1000 where it is started by
* the second level bootloader, then the frequency is the crystal
* frequency.
* - If we load the code into IRAM after the second level bootloader has run
* this frequency will be twice the crystal frequency.
*
* Don't ask me for an explanation.
*/
/* Note: The bootloader (esp-idf bootloader.bin) configures:
*
* - CPU frequency to 80MHz
*
* Reference:
* https://github.com/espressif/esp-idf/blob
* /ebf7e811b12e3c1e347340e5b9ec014e9c6319ba/components
* /bootloader_support/src/bootloader_clock_init.c#L26-L27
*/
#ifdef CONFIG_ESP32S3_RUN_IRAM
# define BOARD_CLOCK_FREQUENCY (2 * BOARD_XTAL_FREQUENCY)
#else
#ifdef CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ
# define BOARD_CLOCK_FREQUENCY (CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ * 1000000)
#else
# define BOARD_CLOCK_FREQUENCY 80000000
#endif
#endif
/* LED definitions **********************************************************/
/* Define how many LEDs this board has (needed by userleds) */
#define BOARD_NLEDS 1
#endif /* __BOARDS_XTENSA_ESP32S3_ESP32S3_DEVKIT_INCLUDE_BOARD_H */

1
boards/xtensa/esp32s3/esp32s3-devkit/scripts/.gitignore vendored Normal file
View File

@ -0,0 +1 @@
/esp32s3_out.ld

92
boards/xtensa/esp32s3/esp32s3-devkit/scripts/Make.defs Normal file
View File

@ -0,0 +1,92 @@
############################################################################
# boards/xtensa/esp32s3/esp32s3-devkit/scripts/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/tools/esp32s3/Config.mk
include $(TOPDIR)/arch/xtensa/src/lx7/Toolchain.defs
LDSCRIPT1 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s3_out.ld
LDSCRIPT2 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s3.ld
LDSCRIPT3 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s3_rom.ld
LDSCRIPT4 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s3_peripherals.ld
ifeq ($(CONFIG_CYGWIN_WINTOOL),y)
ARCHSCRIPT = -T "${shell cygpath -w $(LDSCRIPT1)}"
ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT2)}"
ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT3)}"
ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT4)}"
else
ARCHSCRIPT = -T$(LDSCRIPT1) -T$(LDSCRIPT2) -T$(LDSCRIPT3) -T$(LDSCRIPT4)
endif
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
ARCHOPTIMIZATION = -g
endif
ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce
endif
ARCHCFLAGS = -fno-builtin -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -mlongcalls
ARCHCXXFLAGS = $(ARCHCFLAGS) -fno-exceptions -fcheck-new -fno-rtti
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
ARCHPICFLAGS = -fpic
CFLAGS := $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
# Loadable module definitions
CMODULEFLAGS = $(CFLAGS) -mtext-section-literals
LDMODULEFLAGS = -r -e module_initialize
ifeq ($(CONFIG_CYGWIN_WINTOOL),y)
LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}"
else
LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld
endif
# ELF module definitions
CELFFLAGS = $(CFLAGS) -mtext-section-literals
CXXELFFLAGS = $(CXXFLAGS) -mtext-section-literals
LDELFFLAGS = -r -e main
ifeq ($(CONFIG_CYGWIN_WINTOOL),y)
LDELFFLAGS += -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)gnu-elf.ld}"
else
LDELFFLAGS += -T $(BOARD_DIR)$(DELIM)scripts$(DELIM)gnu-elf.ld
endif
ifeq ($(CONFIG_CYGWIN_WINTOOL),y)
LDFLAGS += -Map="${shell cygpath -w $(TOPDIR)/nuttx.map}" --cref
else
LDFLAGS += -Map=$(TOPDIR)/nuttx.map --cref
endif
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
LDFLAGS += -g
endif

269
boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3.ld Normal file
View File

@ -0,0 +1,269 @@
/****************************************************************************
* boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3_flash.ld
****************************************************************************/
/* Default entry point: */
ENTRY(__start);
_diram_i_start = 0x40378000;
SECTIONS
{
/* Send .iram0 code to iram */
.iram0.vectors :
{
_iram_start = ABSOLUTE(.);
/* Vectors go to IRAM. */
_init_start = ABSOLUTE(.);
/* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
. = 0x0;
KEEP (*(.window_vectors.text));
. = 0x180;
KEEP (*(.xtensa_level2_vector.text));
. = 0x1c0;
KEEP (*(.xtensa_level3_vector.text));
. = 0x200;
KEEP (*(.xtensa_level4_vector.text));
. = 0x240;
KEEP (*(.xtensa_level5_vector.text));
. = 0x280;
KEEP (*(.debug_exception_vector.text));
. = 0x2c0;
KEEP (*(.nmi_vector.text));
. = 0x300;
KEEP (*(.kernel_exception_vector.text));
. = 0x340;
KEEP (*(.user_exception_vector.text));
. = 0x3c0;
KEEP (*(.double_exception_vector.text));
. = 0x400;
*(.*_vector.literal)
. = ALIGN(16);
*(.entry.text)
*(.init.literal)
*(.init)
} > iram0_0_seg
.iram0.text :
{
/* Code marked as running out of IRAM */
*(.iram1 .iram1.*)
/* align + add 16B for CPU dummy speculative instr. fetch */
. = ALIGN(4) + 16;
_iram_text = ABSOLUTE(.);
} > iram0_0_seg
.dram0.dummy (NOLOAD) :
{
/* This section is required to skip .iram0.text area because iram0_0_seg
* and dram0_0_seg reflect the same address space on different buses.
*/
. = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
} > dram0_0_seg
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
/* .bss initialized on power-up */
. = ALIGN(8);
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(COMMON)
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.share.mem)
*(.gnu.linkonce.b.*)
. = ALIGN(8);
_ebss = ABSOLUTE(.);
} > dram0_0_seg
.noinit (NOLOAD) :
{
/* This section contains data that is not initialized during load,
* or during the application's initialization sequence.
*/
. = ALIGN(4);
*(.noinit .noinit.*)
. = ALIGN(4);
} > dram0_0_seg
.dram0.data :
{
/* .data initialized on power-up in ROMed configurations. */
_sdata = ABSOLUTE(.);
KEEP (*(.data))
KEEP (*(.data.*))
KEEP (*(.gnu.linkonce.d.*))
KEEP (*(.data1))
KEEP (*(.sdata))
KEEP (*(.sdata.*))
KEEP (*(.gnu.linkonce.s.*))
KEEP (*(.sdata2))
KEEP (*(.sdata2.*))
KEEP (*(.gnu.linkonce.s2.*))
KEEP (*(.jcr))
*(.dram1 .dram1.*)
_edata = ABSOLUTE(.);
. = ALIGN(4);
/* Heap starts at the end of .data */
_sheap = ABSOLUTE(.);
} > dram0_0_seg
.flash.text :
{
_stext = .;
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
/* CPU will try to prefetch up to 16 bytes of instructions.
* This means that any configuration (e.g. MMU, PMS) must allow
* safe access to up to 16 bytes after the last real instruction, add
* dummy bytes to ensure this
*/
. += 16;
_etext = .;
} > default_code_seg
.flash_rodata_dummy (NOLOAD) :
{
/* This dummy section represents the .flash.text section but in default_rodata_seg.
* Thus, it must have its alignment and (at least) its size.
*/
/* Start at the same alignment constraint than .flash.text */
. = ALIGN(ALIGNOF(.flash.text));
/* Create an empty gap as big as .flash.text section */
. = SIZEOF(.flash.text);
/* Prepare the alignment of the section above. Few bytes (0x20) must be
* added for the mapping header.
*/
. = ALIGN(0x10000) + 0x20;
_rodata_reserved_start = .;
} > default_rodata_seg
.flash.rodata : ALIGN(0x10)
{
_srodata = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table)
*(.gcc_except_table.*)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
*(.eh_frame)
. = ALIGN(4);
/* C++ constructor and destructor tables, properly ordered: */
_sinit = ABSOLUTE(.);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
_einit = ABSOLUTE(.);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
_erodata = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
_rodata_reserved_end = ABSOLUTE(.);
. = ALIGN(4);
} > default_rodata_seg
/* Marks the end of IRAM code segment */
.iram0.text_end (NOLOAD) :
{
/* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and
* 256B alignment for PMS split lines.
*/
. += 16;
. = ALIGN(256);
} > iram0_0_seg
.iram0.data :
{
. = ALIGN(4);
*(.iram.data)
*(.iram.data.*)
} > iram0_0_seg
.iram0.bss (NOLOAD) :
{
. = ALIGN(4);
*(.iram.bss)
*(.iram.bss.*)
. = ALIGN(4);
_iram_end = ABSOLUTE(.);
} > iram0_0_seg
}

113
boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3.template.ld Normal file
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@ -0,0 +1,113 @@
/****************************************************************************
* boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3.template.ld
* ESP32-S3 Linker Script Memory Layout
*
* This file describes the memory layout (memory blocks) as virtual
* memory addresses.
*
* esp32s3.common.ld contains output sections to link compiler output
* into these memory blocks.
*
* NOTE: That this is not the actual linker script but rather a "template"
* for the elf32_out.ld script. This template script is passed through
* the C preprocessor to include selected configuration options.
*
****************************************************************************/
#include <nuttx/config.h>
#define SRAM_IRAM_START 0x40370000
#define SRAM_DIRAM_I_START 0x40378000
#define SRAM_IRAM_END 0x403ba000
#define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START)
#define SRAM_DRAM_START 0x3fc88000
/* 2nd stage bootloader iram_loader_seg start address */
#define SRAM_DRAM_END (SRAM_IRAM_END - I_D_SRAM_OFFSET)
#define I_D_SRAM_SIZE (SRAM_DRAM_END - SRAM_DRAM_START)
#define ICACHE_SIZE 0x8000
#define SRAM_IRAM_ORG (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)
#define SRAM_IRAM_SIZE (I_D_SRAM_SIZE + ICACHE_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)
#define DCACHE_SIZE 0x10000
#define SRAM_DRAM_ORG (SRAM_DRAM_START)
#ifdef CONFIG_ESP32S3_FLASH_4M
# define FLASH_SIZE 0x400000
#elif defined (CONFIG_ESP32S3_FLASH_8M)
# define FLASH_SIZE 0x800000
#elif defined (CONFIG_ESP32S3_FLASH_16M)
# define FLASH_SIZE 0x1000000
#endif
MEMORY
{
/* Below values assume the flash cache is on, and have the blocks this
* uses subtracted from the length of the various regions. The 'data access
* port' dram/drom regions map to the same iram/irom regions but are
* connected to the data port of the CPU and eg allow bytewise access.
*/
/* IRAM for CPU */
iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = SRAM_IRAM_SIZE
/* Flash mapped instruction data. */
/* The 0x20 offset is a convenience for the app binary image generation.
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
* header. Setting this offset makes it simple to meet the flash cache MMU's
* constraint that (paddr % 64KB == vaddr % 64KB).
*/
irom0_0_seg (RX) : org = 0x42000020, len = FLASH_SIZE - 0x20
/* Shared data RAM, excluding memory reserved for bootloader and ROM
* bss/data/stack.
*/
dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = I_D_SRAM_SIZE
/* Flash mapped constant data */
/* The 0x20 offset is a convenience for the app binary image generation.
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
* header. Setting this offset makes it simple to meet the flash cache MMU's
* constraint that (paddr % 64KB == vaddr % 64KB).
*/
drom0_0_seg (R) : org = 0x3c000020, len = FLASH_SIZE - 0x20
/* RTC fast memory (executable). Persists over deep sleep. */
rtc_iram_seg(RWX) : org = 0x600fe000, len = 0x2000
/* RTC fast memory (same block as above), viewed from data bus */
rtc_data_seg(RW) : org = 0x600fe000, len = 0x2000
/* RTC slow memory (data accessible). Persists over deep sleep.
* Start of RTC slow memory is reserved for ULP co-processor code + data,
* if enabled.
*/
rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM,
len = 0x2000 - CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM
}
#ifdef CONFIG_ESP32S3_RUN_IRAM
REGION_ALIAS("default_rodata_seg", dram0_0_seg);
REGION_ALIAS("default_code_seg", iram0_0_seg);
#else
REGION_ALIAS("default_rodata_seg", drom0_0_seg);
REGION_ALIAS("default_code_seg", irom0_0_seg);
#endif /* CONFIG_ESP32S3_RUN_IRAM */

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/****************************************************************************
* boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3_peripherals.ld
****************************************************************************/
PROVIDE ( UART0 = 0x60000000 );
PROVIDE ( SPIMEM1 = 0x60002000 );
PROVIDE ( SPIMEM0 = 0x60003000 );
PROVIDE ( GPIO = 0x60004000 );
PROVIDE ( SIGMADELTA = 0x60004f00 );
PROVIDE ( RTCCNTL = 0x60008000 );
PROVIDE ( RTCIO = 0x60008400 );
PROVIDE ( SENS = 0x60008800 );
PROVIDE ( HINF = 0x6000B000 );
PROVIDE ( I2S0 = 0x6000F000 );
PROVIDE ( I2S1 = 0x6002D000 );
PROVIDE ( UART1 = 0x60010000 );
PROVIDE ( I2C0 = 0x60013000 );
PROVIDE ( UHCI0 = 0x60014000 );
PROVIDE ( UHCI1 = 0x60014000 );
PROVIDE ( HOST = 0x60015000 );
PROVIDE ( RMT = 0x60016000 );
PROVIDE ( RMTMEM = 0x60016800 );
PROVIDE ( PCNT = 0x60017000 );
PROVIDE ( SLC = 0x60018000 );
PROVIDE ( LEDC = 0x60019000 );
PROVIDE ( MCPWM0 = 0x6001E000 );
PROVIDE ( MCPWM1 = 0x6002C000 );
PROVIDE ( MCP = 0x600c3000 );
PROVIDE ( TIMERG0 = 0x6001F000 );
PROVIDE ( TIMERG1 = 0x60020000 );
PROVIDE ( SYSTIMER = 0x60023000 );
PROVIDE ( GPSPI2 = 0x60024000 );
PROVIDE ( GPSPI3 = 0x60025000 );
PROVIDE ( SYSCON = 0x60026000 );
PROVIDE ( I2C1 = 0x60027000 );
PROVIDE ( SDMMC = 0x60028000 );
PROVIDE ( TWAI = 0x6002B000 );
PROVIDE ( GPSPI4 = 0x60037000 );
PROVIDE ( GDMA = 0x6003F000 );
PROVIDE ( UART2 = 0x6002E000 );
PROVIDE ( DMA = 0x6003F000 );
PROVIDE ( APB_SARADC = 0x60040000 );
PROVIDE ( LCD_CAM = 0x60041000 );
PROVIDE ( USB_SERIAL_JTAG = 0x60038000 );
PROVIDE ( USB0 = 0x60080000 );
PROVIDE ( USBH = 0x60080000 );
PROVIDE ( USB_WRAP = 0x60039000 );

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############################################################################
# boards/xtensa/esp32s3/esp32s3-devkit/src/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/Make.defs
SCRIPTDIR = $(BOARD_DIR)$(DELIM)scripts
CONFIGFILE = $(TOPDIR)$(DELIM)include$(DELIM)nuttx$(DELIM)config.h
CSRCS = esp32s3_boot.c esp32s3_bringup.c
ifeq ($(CONFIG_BOARDCTL),y)
CSRCS += esp32s3_appinit.c
ifeq ($(CONFIG_BOARDCTL_RESET),y)
CSRCS += esp32s3_reset.c
endif
endif
SCRIPTIN = $(SCRIPTDIR)$(DELIM)esp32s3.template.ld
SCRIPTOUT = $(SCRIPTDIR)$(DELIM)esp32s3_out.ld
.PHONY = context distclean
$(SCRIPTOUT): $(SCRIPTIN) $(CONFIGFILE)
$(Q) $(CC) -isystem $(TOPDIR)/include -C -P -x c -E $(SCRIPTIN) -o $@
context:: $(SCRIPTOUT)
distclean::
$(call DELFILE, $(SCRIPTOUT))
DEPPATH += --dep-path board
VPATH += :board
CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board)

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/****************************************************************************
* boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3-devkit.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __BOARDS_XTENSA_ESP32S3_ESP32S3_DEVKIT_SRC_ESP32S3_DEVKIT_H
#define __BOARDS_XTENSA_ESP32S3_ESP32S3_DEVKIT_SRC_ESP32S3_DEVKIT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <stdint.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s3_bringup
*
* Description:
* Perform architecture-specific initialization
*
* CONFIG_BOARD_LATE_INITIALIZE=y :
* Called from board_late_initialize().
*
* CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_BOARDCTL=y :
* Called from the NSH library via board_app_initialize()
*
****************************************************************************/
int esp32s3_bringup(void);
#endif /* __ASSEMBLY__ */
#endif /* __BOARDS_XTENSA_ESP32S3_ESP32S3_DEVKIT_SRC_ESP32S3_DEVKIT_H */

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/****************************************************************************
* boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_appinit.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <nuttx/board.h>
#include "esp32s3-devkit.h"
#ifdef CONFIG_BOARDCTL
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_app_initialize
*
* Description:
* Perform application specific initialization. This function is never
* called directly from application code, but only indirectly via the
* (non-standard) boardctl() interface using the command BOARDIOC_INIT.
*
* Input Parameters:
* arg - The boardctl() argument is passed to the board_app_initialize()
* implementation without modification. The argument has no
* meaning to NuttX; the meaning of the argument is a contract
* between the board-specific initialization logic and the
* matching application logic. The value could be such things as a
* mode enumeration value, a set of DIP switch settings, a
* pointer to configuration data read from a file or serial FLASH,
* or whatever you would like to do with it. Every implementation
* should accept zero/NULL as a default configuration.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure to indicate the nature of the failure.
*
****************************************************************************/
int board_app_initialize(uintptr_t arg)
{
#ifdef CONFIG_BOARD_LATE_INITIALIZE
/* Board initialization already performed by board_late_initialize() */
return OK;
#else
/* Perform board-specific initialization */
return esp32s3_bringup();
#endif
}
#endif /* CONFIG_BOARDCTL */

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/****************************************************************************
* boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_boot.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/board.h>
#include <nuttx/mm/mm.h>
#include <arch/board/board.h>
#include "esp32s3-devkit.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s3_board_initialize
*
* Description:
* All ESP32-S3 boards must provide the following entry point.
* This entry point is called early in the initialization -- after all
* memory has been configured and mapped but before any devices have been
* initialized.
*
****************************************************************************/
void esp32s3_board_initialize(void)
{
}
/****************************************************************************
* Name: board_late_initialize
*
* Description:
* If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
* initialization call will be performed in the boot-up sequence to a
* function called board_late_initialize(). board_late_initialize() will
* be called immediately after up_initialize() is called and just before
* the initial application is started. This additional initialization
* phase may be used, for example, to initialize board-specific device
* drivers.
*
****************************************************************************/
#ifdef CONFIG_BOARD_LATE_INITIALIZE
void board_late_initialize(void)
{
/* Perform board-specific initialization */
esp32s3_bringup();
}
#endif

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/****************************************************************************
* boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdio.h>
#include <fcntl.h>
#include <unistd.h>
#include <syslog.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <sys/types.h>
#include <syslog.h>
#include <debug.h>
#include <stdio.h>
#include <errno.h>
#include <nuttx/fs/fs.h>
#include "esp32s3-devkit.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s3_bringup
*
* Description:
* Perform architecture-specific initialization
*
* CONFIG_BOARD_LATE_INITIALIZE=y :
* Called from board_late_initialize().
*
* CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y :
* Called from the NSH library
*
****************************************************************************/
int esp32s3_bringup(void)
{
int ret;
#ifdef CONFIG_FS_PROCFS
/* Mount the procfs file system */
ret = nx_mount(NULL, "/proc", "procfs", 0, NULL);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret);
}
#endif
#ifdef CONFIG_FS_TMPFS
/* Mount the tmpfs file system */
ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: Failed to mount tmpfs at %s: %d\n",
CONFIG_LIBC_TMPDIR, ret);
}
#endif
/* If we got here then perhaps not all initialization was successful, but
* at least enough succeeded to bring-up NSH with perhaps reduced
* capabilities.
*/
UNUSED(ret);
return OK;
}

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/****************************************************************************
* boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_reset.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#ifdef CONFIG_BOARDCTL_RESET
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_reset
*
* Description:
* Reset board. Support for this function is required by board-level
* logic if CONFIG_BOARDCTL_RESET is selected.
*
* Input Parameters:
* status - Status information provided with the reset event. This
* meaning of this status information is board-specific. If not
* used by a board, the value zero may be provided in calls to
* board_reset().
*
* Returned Value:
* If this function returns, then it was not possible to power-off the
* board due to some constraints. The return value in this case is a
* board-specific reason for the failure to shutdown.
*
****************************************************************************/
int board_reset(int status)
{
up_systemreset();
return 0;
}
#endif /* CONFIG_BOARDCTL_RESET */

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############################################################################
# tools/esp32s3/Config.mk
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
# These are the macros that will be used in the NuttX make system to compile
# and assemble source files and to insert the resulting object files into an
# archive. These replace the default definitions at tools/Config.mk
ifeq ($(CONFIG_ESP32S3_FLASH_4M),y)
FLASH_SIZE := 4MB
else ifeq ($(CONFIG_ESP32S3_FLASH_8M),y)
FLASH_SIZE := 8MB
else ifeq ($(CONFIG_ESP32S3_FLASH_16M),y)
FLASH_SIZE := 16MB
endif
ifeq ($(CONFIG_ESP32S3_FLASH_MODE_DIO),y)
FLASH_MODE := dio
else ifeq ($(CONFIG_ESP32S3_FLASH_MODE_DOUT),y)
FLASH_MODE := dout
else ifeq ($(CONFIG_ESP32S3_FLASH_MODE_QIO),y)
FLASH_MODE := qio
else ifeq ($(CONFIG_ESP32S3_FLASH_MODE_QOUT),y)
FLASH_MODE := qout
endif
ifeq ($(CONFIG_ESP32S3_FLASH_FREQ_120M),y)
FLASH_FREQ := 120m
else ifeq ($(CONFIG_ESP32S3_FLASH_FREQ_80M),y)
FLASH_FREQ := 80m
else ifeq ($(CONFIG_ESP32S3_FLASH_FREQ_40M),y)
FLASH_FREQ := 40m
else ifeq ($(CONFIG_ESP32S3_FLASH_FREQ_20M),y)
FLASH_FREQ := 20m
endif
ifeq ($(CONFIG_ESP32S3_FLASH_DETECT),y)
ESPTOOL_WRITEFLASH_OPTS := -fs detect -fm dio -ff $(FLASH_FREQ)
else
ESPTOOL_WRITEFLASH_OPTS := -fs $(FLASH_SIZE) -fm dio -ff $(FLASH_FREQ)
endif
ESPTOOL_FLASH_OPTS := -fs $(FLASH_SIZE) -fm $(FLASH_MODE) -ff $(FLASH_FREQ)
# Configure the variables according to build environment
ifdef ESPTOOL_BINDIR
ifeq ($(CONFIG_ESP32S3_APP_FORMAT_LEGACY),y)
BL_OFFSET := 0x0
PT_OFFSET := $(CONFIG_ESP32S3_PARTITION_TABLE_OFFSET)
BOOTLOADER := $(ESPTOOL_BINDIR)/bootloader-esp32s3.bin
PARTITION_TABLE := $(ESPTOOL_BINDIR)/partition-table-esp32s3.bin
FLASH_BL := $(BL_OFFSET) $(BOOTLOADER)
FLASH_PT := $(PT_OFFSET) $(PARTITION_TABLE)
ESPTOOL_BINS := $(FLASH_BL) $(FLASH_PT)
endif
endif
ifeq ($(CONFIG_ESP32S3_APP_FORMAT_LEGACY),y)
APP_OFFSET := 0x10000
APP_IMAGE := nuttx.bin
FLASH_APP := $(APP_OFFSET) $(APP_IMAGE)
endif
ESPTOOL_BINS += $(FLASH_APP)
# MERGEBIN -- Merge raw binary files into a single file
define MERGEBIN
$(Q) if [ -z $(ESPTOOL_BINDIR) ]; then \
echo "MERGEBIN error: Missing argument for binary files directory."; \
echo "USAGE: make ESPTOOL_BINDIR=<dir>"; \
exit 1; \
fi
$(Q) if [ -z $(FLASH_SIZE) ]; then \
echo "Missing Flash memory size configuration for the ESP32-S3 chip."; \
exit 1; \
fi
esptool.py -c esp32s3 merge_bin --output nuttx.merged.bin $(ESPTOOL_FLASH_OPTS) $(ESPTOOL_BINS)
$(Q) echo nuttx.merged.bin >> nuttx.manifest
$(Q) echo "Generated: nuttx.merged.bin"
endef
# MKIMAGE -- Convert an ELF file into a compatible binary file
define MKIMAGE
$(Q) echo "MKIMAGE: ESP32-S3 binary"
$(Q) if ! esptool.py version 1>/dev/null 2>&1; then \
echo ""; \
echo "esptool.py not found. Please run: \"pip install esptool\""; \
echo ""; \
echo "Run make again to create the nuttx.bin image."; \
exit 1; \
fi
$(Q) if [ -z $(FLASH_SIZE) ]; then \
echo "Missing Flash memory size configuration for the ESP32-S3 chip."; \
exit 1; \
fi
esptool.py -c esp32s3 elf2image $(ESPTOOL_FLASH_OPTS) -o nuttx.bin nuttx
$(Q) echo "Generated: nuttx.bin (ESP32-S3 compatible)"
endef
# POSTBUILD -- Perform post build operations
define POSTBUILD
$(call MKIMAGE)
$(if $(CONFIG_ESP32S3_MERGE_BINS),$(call MERGEBIN))
endef
# ESPTOOL_BAUD -- Serial port baud rate used when flashing/reading via esptool.py
ESPTOOL_BAUD ?= 921600
# FLASH -- Download a binary image via esptool.py
define FLASH
$(Q) if [ -z $(ESPTOOL_PORT) ]; then \
echo "FLASH error: Missing serial port device argument."; \
echo "USAGE: make flash ESPTOOL_PORT=<port> [ ESPTOOL_BAUD=<baud> ] [ ESPTOOL_BINDIR=<dir> ]"; \
exit 1; \
fi
$(eval ESPTOOL_OPTS := -c esp32s3 -p $(ESPTOOL_PORT) -b $(ESPTOOL_BAUD) $(if $(CONFIG_ESP32S3_ESPTOOLPY_NO_STUB),--no-stub))
esptool.py $(ESPTOOL_OPTS) write_flash $(ESPTOOL_WRITEFLASH_OPTS) $(ESPTOOL_BINS)
endef