TM3C123: Add chip characteristics and interrupt definition files
This commit is contained in:
Gregory Nutt
parent
cb10073586
commit
b10bc3238b
@ -55,6 +55,7 @@
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# undef TM4C /* Not TM4C family */
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# define TIVA_NTIMERS 4 /* Four general purpose timers */
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# define TIVA_NWIDETIMERS 0 /* No general purpose wide timers */
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# define TIVA_NWDT 1 /* One watchdog timer */
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# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef TIVA_ETHTS /* No timestamp register */
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# define TIVA_NSSI 2 /* Two SSI modules */
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@ -65,12 +66,14 @@
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# define TIVA_NQEI 0 /* No quadrature encoders */
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# define TIVA_NPORTS 8 /* 8 Ports (GPIOA-H) 5-38 GPIOs */
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# define TIVA_NCANCONTROLLER 0 /* No CAN controllers */
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# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
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#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# undef TM4C /* Not TM4C family */
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# define TIVA_NTIMERS 3 /* Three general purpose timers */
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# define TIVA_NWIDETIMERS 0 /* No general purpose wide timers */
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# define TIVA_NWDT 1 /* One watchdog timer */
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# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef TIVA_ETHTS /* No timestamp register */
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# define TIVA_NSSI 1 /* One SSI module */
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@ -81,12 +84,14 @@
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# define TIVA_NQEI 0 /* No quadrature encoders */
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# define TIVA_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
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# define TIVA_NCANCONTROLLER 0 /* No CAN controllers */
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# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
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#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# undef TM4C /* Not TM4C family */
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# define TIVA_NTIMERS 4 /* Four general purpose timers */
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# define TIVA_NWIDETIMERS 0 /* No general purpose wide timers */
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# define TIVA_NWDT 1 /* One watchdog timer */
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# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef TIVA_ETHTS /* No timestamp register */
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# define TIVA_NSSI 1 /* One SSI module */
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@ -97,12 +102,14 @@
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# define TIVA_NQEI 2 /* Two quadrature encoders */
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# define TIVA_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
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# define TIVA_NCANCONTROLLER 0 /* No CAN controllers */
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# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
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#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# undef TM4C /* Not TM4C family */
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# define TIVA_NTIMERS 4 /* Four general purpose timers */
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# define TIVA_NWIDETIMERS 0 /* No general purpose wide timers */
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# define TIVA_NWDT 1 /* One watchdog timer */
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# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef TIVA_ETHTS /* No timestamp register */
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# define TIVA_NSSI 2 /* Two SSI modules */
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@ -114,12 +121,14 @@
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# define TIVA_NQEI 2 /* Two quadrature encoders */
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# define TIVA_NPORTS 9 /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */
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# define TIVA_NCANCONTROLLER 0 /* No CAN controllers */
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# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
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#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# undef TM4C /* Not TM4C family */
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# define TIVA_NTIMERS 6 /* Four general purpose timers */
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# define TIVA_NWIDETIMERS 0 /* No general purpose wide timers */
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# define TIVA_NWDT 1 /* One watchdog timer */
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# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
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# define TIVA_NSSI 1 /* One SSI module */
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# define TIVA_NUARTS 3 /* Two UART modules */
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@ -129,12 +138,14 @@
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# define TIVA_NQEI 2 /* Two quadrature encoders */
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# define TIVA_NPORTS 7 /* 7 Ports (GPIOA-G), 5-42 GPIOs */
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# define TIVA_NCANCONTROLLER 1 /* One CAN controller */
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# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
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#elif defined(CONFIG_ARCH_CHIP_LM4F120)
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# undef LM3S /* Not LM3S family */
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# define LM4F 1 /* LM4F family */
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# undef TM4C /* Not TM4C family */
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# define TIVA_NTIMERS 6 /* Six general purpose timers */
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# define TIVA_NWIDETIMERS 6 /* Six general purpose wide timers */
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# define TIVA_NWDT 2 /* Two watchdog timer timers */
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# define TIVA_NETHCONTROLLERS 0 /* No Ethernet controller */
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# define TIVA_NSSI 4 /* Four SSI module */
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# define TIVA_NUARTS 8 /* Eight UART modules */
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@ -144,6 +155,25 @@
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# define TIVA_NQEI 0 /* No quadrature encoders */
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# define TIVA_NPORTS 6 /* 6 Ports (GPIOA-F), 0-43 GPIOs */
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# define TIVA_NCANCONTROLLER 1 /* One CAN controller */
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# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
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#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PGE) || defined(CONFIG_ARCH_CHIP_TM4C123GH6PZ) || \
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defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB)
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# undef LM3S /* Not LM3S family */
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# undef LM4F /* Not LM4F family */
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# define TM4C 1 /* TM4C family */
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# define TIVA_NTIMERS 6 /* Six general purpose timers */
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# define TIVA_NWIDETIMERS 6 /* Six general purpose wide timers */
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# define TIVA_NWDT 2 /* Two watchdog timers */
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# define TIVA_NETHCONTROLLERS 0 /* No Ethernet controller */
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# define TIVA_NSSI 4 /* Four SSI module */
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# define TIVA_NUARTS 8 /* Eight UART modules */
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# define TIVA_NI2C 6 /* Six I2C modules */
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# define TIVA_NADC 2 /* Two ADC modules */
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# define TIVA_NPWM 2 /* Two PWM generator modules */
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# define TIVA_NQEI 1 /* One quadrature encoders */
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# define TIVA_NPORTS 15 /* Fifteen Ports (GPIOA-Q) */
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# define TIVA_NCANCONTROLLER 2 /* Two CAN controllers */
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# define TIVA_NUSBOTGFS 1 /* One USB 2.0 OTG FS */
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#else
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# error "Capabilities not specified for this Stellaris chip"
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#endif
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@ -89,6 +89,8 @@
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# include <arch/tiva/lm3s_irq.h>
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#elif defined(CONFIG_ARCH_CHIP_LM4F)
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# include <arch/tiva/lm4f_irq.h>
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#elif defined(CONFIG_ARCH_CHIP_TM4C)
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# include <arch/tiva/tm3c_irq.h>
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#else
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# error "Unsupported Stellaris IRQ file"
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#endif
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@ -93,7 +93,7 @@
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# define TIVA_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
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# define TIVA_RESERVED_47 (47) /* Vector 47: Reserved */
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# define TIVA_RESERVED_48 (48) /* Vector 48: Reserved */
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# define TIVA_IRQ_UART2 (49) /* Vector 22: UART 2 */
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# define TIVA_IRQ_UART2 (49) /* Vector 49: UART 2 */
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# define TIVA_IRQ_SSI1 (50) /* Vector 50: SSI 1 */
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# define TIVA_IRQ_TIMER3A (51) /* Vector 51: 16/32-Bit Timer 3 A */
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244
arch/arm/include/tiva/tm3c_irq.h
Normal file
244
arch/arm/include/tiva/tm3c_irq.h
Normal file
@ -0,0 +1,244 @@
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/************************************************************************************
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* arch/arm/include/tiva/tm3c_irq.h
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_TIVA_TM3C_IRQ_H
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#define __ARCH_ARM_INCLUDE_TIVA_TM3C_IRQ_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
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* bits in the NVIC. This does, however, waste several words of memory in the IRQ
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* to handle mapping tables.
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*/
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/* External interrupts (vectors >= 16) */
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#define TIVA_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */
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#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB)
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# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
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# define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
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# define TIVA_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
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# define TIVA_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
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# define TIVA_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
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# define TIVA_IRQ_UART0 (21) /* Vector 21: UART 0 */
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# define TIVA_IRQ_UART1 (22) /* Vector 22: UART 1 */
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# define TIVA_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
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# define TIVA_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
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# define TIVA_IRQ_PWM0_FAULT (25) /* Vector 25: PWM0 Fault */
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# define TIVA_IRQ_PWM0_GEN0 (26) /* Vector 26: PWM0 Generator 0 */
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# define TIVA_IRQ_PWM0_GEN1 (27) /* Vector 27: PWM0 Generator 1 */
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# define TIVA_IRQ_PWM0_GEN2 (28) /* Vector 28: PWM0 Generator 2 */
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# define TIVA_IRQ_QEI0 (29) /* Vector 29: QEI0 */
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# define TIVA_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
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# define TIVA_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
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# define TIVA_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
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# define TIVA_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
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# define TIVA_IRQ_WDOG (34) /* Vector 34: Watchdog Timers 0 and 1 */
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# define TIVA_IRQ_TIMER0A (35) /* Vector 35: 16/32-Bit Timer 0 A */
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# define TIVA_IRQ_TIMER0B (36) /* Vector 36: 16/32-Bit Timer 0 B */
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# define TIVA_IRQ_TIMER1A (37) /* Vector 37: 16/32-Bit Timer 1 A */
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# define TIVA_IRQ_TIMER1B (38) /* Vector 38: 16/32-Bit Timer 1 B */
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# define TIVA_IRQ_TIMER2A (39) /* Vector 39: 16/32-Bit Timer 2 A */
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# define TIVA_IRQ_TIMER2B (40) /* Vector 40: 16/32-Bit Timer 2 B */
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# define TIVA_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
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# define TIVA_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
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# define TIVA_IRQ_COMPARE2 (43) /* Vector 43: Analog Comparator 2 */
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# define TIVA_IRQ_SYSCON (44) /* Vector 44: System Control */
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# define TIVA_IRQ_FLASHCON (45) /* Vector 45: FLASH and EEPROM Control */
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# define TIVA_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
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# define TIVA_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
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# define TIVA_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */
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# define TIVA_IRQ_UART2 (49) /* Vector 49: UART 2 */
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# define TIVA_IRQ_SSI1 (50) /* Vector 50: SSI 1 */
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# define TIVA_IRQ_TIMER3A (51) /* Vector 51: 16/32-Bit Timer 3 A */
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# define TIVA_IRQ_TIMER3B (52) /* Vector 52: 16/32-Bit Timer 3 B */
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# define TIVA_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
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# define TIVA_IRQ_QEI1 (54) /* Vector 54: QEI1 */
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# define TIVA_IRQ_CAN0 (55) /* Vector 55: CAN 0 */
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# define TIVA_IRQ_CAN1 (56) /* Vector 56: CAN 1 */
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# define TIVA_RESERVED_57 (57) /* Vector 57: Reserved */
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# define TIVA_RESERVED_58 (58) /* Vector 58: Reserved */
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# define TIVA_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
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# define TIVA_IRQ_USB (60) /* Vector 60: USB */
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# define TIVA_IRQ_PWM0_GEN3 (61) /* Vector 61: PWM0 Generator 3 */
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# define TIVA_IRQ_UDMASOFT (62) /* Vector 62: uDMA Software */
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# define TIVA_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */
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# define TIVA_IRQ_ADC1_0 (64) /* Vector 64: ADC1 Sequence 0 */
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# define TIVA_IRQ_ADC1_1 (65) /* Vector 65: ADC1 Sequence 1 */
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# define TIVA_IRQ_ADC1_2 (66) /* Vector 66: ADC1 Sequence 2 */
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# define TIVA_IRQ_ADC1_3 (67) /* Vector 67: ADC1 Sequence 3 */
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# define TIVA_RESERVED_68 (68) /* Vector 68: Reserved */
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# define TIVA_RESERVED_69 (69) /* Vector 69: Reserved */
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# define TIVA_IRQ_GPIOJ (70) /* Vector 70: GPIO Port J */
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# define TIVA_IRQ_GPIOK (71) /* Vector 71: GPIO Port K */
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# define TIVA_IRQ_GPIOL (72) /* Vector 72: GPIO Port L */
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# define TIVA_IRQ_SSI2 (73) /* Vector 73: SSI 2 */
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# define TIVA_IRQ_SSI3 (74) /* Vector 74: SSI 3 */
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# define TIVA_IRQ_UART3 (75) /* Vector 75: UART 3 */
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# define TIVA_IRQ_UART4 (76) /* Vector 76: UART 4 */
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# define TIVA_IRQ_UART5 (77) /* Vector 77: UART 5 */
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# define TIVA_IRQ_UART6 (78) /* Vector 78: UART 6 */
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# define TIVA_IRQ_UART7 (79) /* Vector 79: UART 7 */
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# define TIVA_RESERVED_80 (80) /* Vector 80: Reserved */
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# define TIVA_RESERVED_81 (81) /* Vector 81: Reserved */
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# define TIVA_RESERVED_82 (82) /* Vector 82: Reserved */
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# define TIVA_RESERVED_83 (83) /* Vector 83: Reserved */
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# define TIVA_IRQ_I2C2 (84) /* Vector 84: I2C 2 */
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# define TIVA_IRQ_I2C3 (85) /* Vector 85: I2C 3 */
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# define TIVA_IRQ_TIMER4A (86) /* Vector 86: 16/32-Bit Timer 4 A */
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# define TIVA_IRQ_TIMER4B (87) /* Vector 87: 16/32-Bit Timer 4 B */
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# define TIVA_RESERVED_88 (88) /* Vector 88: Reserved */
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# define TIVA_RESERVED_89 (89) /* Vector 89: Reserved */
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# define TIVA_RESERVED_90 (90) /* Vector 90: Reserved */
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# define TIVA_RESERVED_91 (91) /* Vector 91: Reserved */
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# define TIVA_RESERVED_92 (92) /* Vector 92: Reserved */
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# define TIVA_RESERVED_93 (93) /* Vector 93: Reserved */
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# define TIVA_RESERVED_94 (94) /* Vector 94: Reserved */
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# define TIVA_RESERVED_95 (95) /* Vector 95: Reserved */
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# define TIVA_RESERVED_96 (96) /* Vector 96: Reserved */
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# define TIVA_RESERVED_97 (97) /* Vector 97: Reserved */
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# define TIVA_RESERVED_98 (98) /* Vector 98: Reserved */
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# define TIVA_RESERVED_99 (99) /* Vector 99: Reserved */
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# define TIVA_RESERVED_100 (100) /* Vector 100: Reserved */
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# define TIVA_RESERVED_101 (101) /* Vector 101: Reserved */
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# define TIVA_RESERVED_102 (102) /* Vector 102: Reserved */
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# define TIVA_RESERVED_103 (103) /* Vector 103: Reserved */
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# define TIVA_RESERVED_104 (104) /* Vector 104: Reserved */
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# define TIVA_RESERVED_105 (105) /* Vector 105: Reserved */
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# define TIVA_RESERVED_106 (106) /* Vector 106: Reserved */
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# define TIVA_RESERVED_107 (107) /* Vector 107: Reserved */
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# define TIVA_IRQ_TIMER5A (108) /* Vector 108: 16/32-Bit Timer 5 A */
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# define TIVA_IRQ_TIMER5B (109) /* Vector 109: 16/32-Bit Timer 5 B */
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# define TIVA_IRQ_WTIMER0A (110) /* Vector 110: 32/64-Bit Timer 0 A */
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# define TIVA_IRQ_WTIMER0B (111) /* Vector 111: 32/64-Bit Timer 0 B */
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# define TIVA_IRQ_WTIMER1A (112) /* Vector 112: 32/64-Bit Timer 1 A */
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# define TIVA_IRQ_WTIMER1B (113) /* Vector 113: 32/64-Bit Timer 1 B */
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# define TIVA_IRQ_WTIMER2A (114) /* Vector 114: 32/64-Bit Timer 2 A */
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# define TIVA_IRQ_WTIMER2B (115) /* Vector 115: 32/64-Bit Timer 2 B */
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# define TIVA_IRQ_WTIMER3A (116) /* Vector 116: 32/64-Bit Timer 3 A */
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# define TIVA_IRQ_WTIMER3B (117) /* Vector 117: 32/64-Bit Timer 3 B */
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# define TIVA_IRQ_WTIMER4A (118) /* Vector 118: 32/64-Bit Timer 4 A */
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# define TIVA_IRQ_WTIMER4B (119) /* Vector 119: 32/64-Bit Timer 4 B */
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# define TIVA_IRQ_WTIMER5A (120) /* Vector 120: 32/64-Bit Timer 5 A */
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# define TIVA_IRQ_WTIMER5B (121) /* Vector 121: 32/64-Bit Timer 5 B */
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# define TIVA_IRQ_SYSTEM (122) /* Vector 122: System Exception (imprecise) */
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# define TIVA_RESERVED_123 (123) /* Vector 123: Reserved */
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# define TIVA_RESERVED_124 (124) /* Vector 124: Reserved */
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# define TIVA_IRQ_I2C4 (125) /* Vector 125: I2C4 */
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# define TIVA_IRQ_I2C5 (126) /* Vector 126: I2C5 */
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# define TIVA_IRQ_GPIOM (127) /* Vector 127: GPIO Port M */
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# define TIVA_IRQ_GPION (128) /* Vector 128: GPIO Port N */
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# define TIVA_RESERVED_129 (129) /* Vector 129: Reserved */
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# define TIVA_RESERVED_130 (130) /* Vector 130: Reserved */
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# define TIVA_RESERVED_131 (131) /* Vector 131: Reserved */
|
||||
# define TIVA_IRQ_GPIOP (132) /* Vector 132: GPIO Port P (Summary or P0) */
|
||||
# define TIVA_IRQ_GPIOP1 (133) /* Vector 133: GPIO Port P1 */
|
||||
# define TIVA_IRQ_GPIOP2 (134) /* Vector 134: GPIO Port P2 */
|
||||
# define TIVA_IRQ_GPIOP3 (135) /* Vector 135: GPIO Port P3 */
|
||||
# define TIVA_IRQ_GPIOP4 (136) /* Vector 136: GPIO Port P4 */
|
||||
# define TIVA_IRQ_GPIOP5 (137) /* Vector 137: GPIO Port P5 */
|
||||
# define TIVA_IRQ_GPIOP6 (138) /* Vector 138: GPIO Port P6 */
|
||||
# define TIVA_IRQ_GPIOP7 (139) /* Vector 139: GPIO Port P7 */
|
||||
|
||||
# define TIVA_IRQ_GPIOPQ (140) /* Vector 140: GPIO Port Q (Summary or Q0) */
|
||||
# define TIVA_IRQ_GPIOPQ1 (141) /* Vector 141: GPIO Port Q1 */
|
||||
# define TIVA_IRQ_GPIOPQ2 (142) /* Vector 142: GPIO Port Q2 */
|
||||
# define TIVA_IRQ_GPIOPQ3 (143) /* Vector 143: GPIO Port Q3 */
|
||||
# define TIVA_IRQ_GPIOPQ4 (144) /* Vector 144: GPIO Port Q4 */
|
||||
# define TIVA_IRQ_GPIOPQ5 (145) /* Vector 145: GPIO Port Q5 */
|
||||
# define TIVA_IRQ_GPIOPQ6 (146) /* Vector 146: GPIO Port Q6 */
|
||||
# define TIVA_IRQ_GPIOPQ7 (147) /* Vector 147: GPIO Port Q7 */
|
||||
# define TIVA_RESERVED_148 (148) /* Vector 148: Reserved */
|
||||
# define TIVA_RESERVED_149 (149) /* Vector 149: Reserved */
|
||||
|
||||
# define TIVA_IRQ_PWM1_GEN0 (150) /* Vector 150: PWM1 Generator 0 */
|
||||
# define TIVA_IRQ_PWM1_GEN1 (151) /* Vector 151: PWM1 Generator 1 */
|
||||
# define TIVA_IRQ_PWM1_GEN2 (152) /* Vector 152: PWM1 Generator 2 */
|
||||
# define TIVA_IRQ_PWM1_GEN3 (153) /* Vector 153: PWM1 Generator 3 */
|
||||
# define TIVA_IRQ_PWM1_FAULT (154) /* Vector 154: PWM1 Fault */
|
||||
|
||||
# define NR_VECTORS (155)
|
||||
# define NR_IRQS (123) /* (Really fewer because of reserved vectors) */
|
||||
|
||||
#else
|
||||
# error "IRQ Numbers not known for this Tiva chip"
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_TIVA_TM3C_IRQ_H */
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/tiva/chip/lm3s_vectors.S
|
||||
* arch/arm/src/tiva/chip/lm3s_vectors.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
@ -43,7 +43,7 @@
|
||||
|
||||
/* This file is included by tiva_vectors.S. It provides the macro VECTOR that
|
||||
* supplies ach Stellaris vector in terms of a (lower-case) ISR label and an
|
||||
* (upper-case) IRQ number as defined in arch/arm/include/lm/lm3s_irq.h.
|
||||
* (upper-case) IRQ number as defined in arch/arm/include/tiva/lm3s_irq.h.
|
||||
* tiva_vectors.S will define the VECTOR in different ways in order to generate
|
||||
* the interrupt vectors and handlers in their final form.
|
||||
*/
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/tiva/chip/lm4f_vectors.S
|
||||
* arch/arm/src/tiva/chip/lm4f_vectors.f
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
@ -43,7 +43,7 @@
|
||||
|
||||
/* This file is included by tiva_vectors.S. It provides the macro VECTOR that
|
||||
* supplies ach Stellaris vector in terms of a (lower-case) ISR label and an
|
||||
* (upper-case) IRQ number as defined in arch/arm/include/lm/lm4f_irq.h.
|
||||
* (upper-case) IRQ number as defined in arch/arm/include/tiva/lm4f_irq.h.
|
||||
* tiva_vectors.S will define the VECTOR in different ways in order to generate
|
||||
* the interrupt vectors and handlers in their final form.
|
||||
*/
|
||||
|
||||
@ -43,6 +43,8 @@
|
||||
# include "chip/lm3s_vectors.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM4F)
|
||||
# include "chip/lm4f_vectors.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_TM3C)
|
||||
# include "chip/tm3c_vectors.h"
|
||||
#else
|
||||
# error "Unsupported Tiva/Stellaris vector file"
|
||||
#endif
|
||||
|
||||
224
arch/arm/src/tiva/chip/tm3c_vectors.h
Normal file
224
arch/arm/src/tiva/chip/tm3c_vectors.h
Normal file
@ -0,0 +1,224 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/tiva/chip/tm2c_vectors.h
|
||||
*
|
||||
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Preprocessor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Vectors
|
||||
************************************************************************************/
|
||||
|
||||
/* This file is included by tiva_vectors.S. It provides the macro VECTOR that
|
||||
* supplies each Tiva vector in terms of a (lower-case) ISR label and an
|
||||
* (upper-case) IRQ number as defined in arch/arm/include/tiva/tm3c_irq.h.
|
||||
* tiva_vectors.S will define the VECTOR in different ways in order to generate
|
||||
* the interrupt vectors and handlers in their final form.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB)
|
||||
|
||||
/* If the common ARMv7-M vector handling is used, then all it needs is the following
|
||||
* definition that provides the number of supported vectors.
|
||||
*/
|
||||
|
||||
# ifdef CONFIG_ARMV7M_CMNVECTOR
|
||||
|
||||
/* Reserve 155 interrupt table entries for I/O interrupts. */
|
||||
|
||||
ARMV7M_PERIPHERAL_INTERRUPTS 155
|
||||
|
||||
# else
|
||||
|
||||
VECTOR(tiva_gpioa, TIVA_IRQ_GPIOA) /* Vector 16: GPIO Port A */
|
||||
VECTOR(tiva_gpiob, TIVA_IRQ_GPIOB) /* Vector 17: GPIO Port B */
|
||||
VECTOR(tiva_gpioc, TIVA_IRQ_GPIOC) /* Vector 18: GPIO Port C */
|
||||
VECTOR(tiva_gpiod, TIVA_IRQ_GPIOD) /* Vector 19: GPIO Port D */
|
||||
|
||||
VECTOR(tiva_gpioe, TIVA_IRQ_GPIOE) /* Vector 20: GPIO Port E */
|
||||
VECTOR(tiva_uart0, TIVA_IRQ_UART0) /* Vector 21: UART 0 */
|
||||
VECTOR(tiva_uart1, TIVA_IRQ_UART1) /* Vector 22: UART 1 */
|
||||
VECTOR(tiva_ssi0, TIVA_IRQ_SSI0) /* Vector 23: SSI 0 */
|
||||
VECTOR(tiva_i2c0, TIVA_IRQ_I2C0) /* Vector 24: I2C 0 */
|
||||
|
||||
VECTOR(tiva_pwm0_fault, TIVA_IRQ_PWM0_FAULT) /* Vector 25: PWM0 Fault */
|
||||
VECTOR(tiva_pwm0_fault, TIVA_IRQ_PWM0_FAULT) /* Vector 26: PWM0 Generator 0 */
|
||||
VECTOR(tiva_pwm0_gen1, TIVA_IRQ_PWM0_GEN1) /* Vector 27: PWM0 Generator 1 */
|
||||
VECTOR(tiva_pwm0_gen2, TIVA_IRQ_PWM0_GEN2) /* Vector 28: PWM0 Generator 2 */
|
||||
VECTOR(tiva_qei0, TIVA_IRQ_QEI0) /* Vector 29: QEI0 */
|
||||
|
||||
VECTOR(tiva_adc0, TIVA_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */
|
||||
VECTOR(tiva_adc1, TIVA_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */
|
||||
VECTOR(tiva_adc2, TIVA_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */
|
||||
VECTOR(tiva_adc3, TIVA_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */
|
||||
VECTOR(tiva_wdog, TIVA_IRQ_WDOG) /* Vector 34: Watchdog Timers 0 and 1 */
|
||||
VECTOR(tiva_timer0a, TIVA_IRQ_TIMER0A) /* Vector 35: 16/32-Bit Timer 0 A */
|
||||
VECTOR(tiva_timer0b, TIVA_IRQ_TIMER0B) /* Vector 36: 16/32-Bit Timer 0 B */
|
||||
VECTOR(tiva_timer1a, TIVA_IRQ_TIMER1A) /* Vector 37: 16/32-Bit Timer 1 A */
|
||||
VECTOR(tiva_timer1b, TIVA_IRQ_TIMER1B) /* Vector 38: 16/32-Bit Timer 1 B */
|
||||
VECTOR(tiva_timer2a, TIVA_IRQ_TIMER2A) /* Vector 39: 16/32-Bit Timer 2 A */
|
||||
|
||||
VECTOR(tiva_timer2b, TIVA_IRQ_TIMER2B) /* Vector 40: 16/32-Bit Timer 2 B */
|
||||
VECTOR(tiva_compare0, TIVA_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */
|
||||
VECTOR(tiva_compare1, TIVA_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */
|
||||
VECTOR(tiva_compare2, TIVA_IRQ_COMPARE2) /* Vector 43: Analog Comparator 2 */
|
||||
VECTOR(tiva_syscon, TIVA_IRQ_SYSCON) /* Vector 44: System Control */
|
||||
VECTOR(tiva_flashcon, TIVA_IRQ_FLASHCON) /* Vector 45: FLASH and EEPROM Control */
|
||||
VECTOR(tiva_gpiof, TIVA_IRQ_GPIOF) /* Vector 46: GPIO Port F */
|
||||
VECTOR(tiva_gpiog, TIVA_IRQ_GPIOG) /* Vector 47: GPIO Port G */
|
||||
VECTOR(tiva_gpioh, TIVA_IRQ_GPIOH) /* Vector 48: GPIO Port H */
|
||||
VECTOR(tiva_uart2, TIVA_IRQ_UART2) /* Vector 22: UART 2 */
|
||||
|
||||
VECTOR(tiva_ssi1, TIVA_IRQ_SSI1) /* Vector 50: SSI 1 */
|
||||
VECTOR(tiva_timer3a, TIVA_IRQ_TIMER3A) /* Vector 51: 16/32-Bit Timer 3 A */
|
||||
VECTOR(tiva_timer3b, TIVA_IRQ_TIMER3B) /* Vector 52: 16/32-Bit Timer 3 B */
|
||||
VECTOR(tiva_i2c1, TIVA_IRQ_I2C1) /* Vector 53: I2C 1 */
|
||||
VECTOR(tiva_qei1, TIVA_IRQ_QEI1) /* Vector 54: QEI1 */
|
||||
VECTOR(tiva_can0, TIVA_IRQ_CAN0) /* Vector 55: CAN 0 */
|
||||
VECTOR(tiva_can1, TIVA_IRQ_CAN1) /* Vector 56: CAN 1 */
|
||||
UNUSED(TIVA_RESERVED_57) /* Vector 57: Reserved */
|
||||
UNUSED(TIVA_RESERVED_58) /* Vector 58: Reserved */
|
||||
VECTOR(tiva_hibernate, TIVA_IRQ_HIBERNATE) /* Vector 59: Hibernation Module */
|
||||
|
||||
VECTOR(tiva_usb, TIVA_IRQ_USB) /* Vector 60: USB */
|
||||
VECTOR(tiva_pwm0_gen3, TIVA_IRQ_PWM0_GEN3) /* Vector 61: PWM0 Generator 3 */
|
||||
VECTOR(tiva_udmasoft, TIVA_IRQ_UDMASOFT) /* Vector 62: uDMA Software */
|
||||
VECTOR(tiva_udmaerro, TIVA_IRQ_UDMAERROR) /* Vector 63: uDMA Error */
|
||||
VECTOR(tiva_adc1_0, TIVA_IRQ_ADC1_0) /* Vector 64: ADC1 Sequence 0 */
|
||||
VECTOR(tiva_adc1_1, TIVA_IRQ_ADC1_1) /* Vector 65: ADC1 Sequence 1 */
|
||||
VECTOR(tiva_adc1_2, TIVA_IRQ_ADC1_2) /* Vector 66: ADC1 Sequence 2 */
|
||||
VECTOR(tiva_adc1_3, TIVA_IRQ_ADC1_3) /* Vector 67: ADC1 Sequence 3 */
|
||||
UNUSED(TIVA_RESERVED_68) /* Vector 68: Reserved */
|
||||
UNUSED(TIVA_RESERVED_69) /* Vector 69: Reserved */
|
||||
|
||||
VECTOR(tiva_gpioj, TIVA_IRQ_GPIOJ) /* Vector 70: GPIO Port J */
|
||||
VECTOR(tiva_gpiok, TIVA_IRQ_GPIOK) /* Vector 71: GPIO Port K */
|
||||
VECTOR(tiva_gpiol, TIVA_IRQ_GPIOL) /* Vector 72: GPIO Port L */
|
||||
VECTOR(tiva_ssi2, TIVA_IRQ_SSI2) /* Vector 73: SSI 2 */
|
||||
VECTOR(tiva_ssi3, TIVA_IRQ_SSI3) /* Vector 74: SSI 3 */
|
||||
VECTOR(tiva_uart3, TIVA_IRQ_UART3) /* Vector 75: UART 3 */
|
||||
VECTOR(tiva_uart4, TIVA_IRQ_UART4) /* Vector 76: UART 4 */
|
||||
VECTOR(tiva_uart5, TIVA_IRQ_UART5) /* Vector 77: UART 5 */
|
||||
VECTOR(tiva_uart6, TIVA_IRQ_UART6) /* Vector 78: UART 6 */
|
||||
VECTOR(tiva_uart7, TIVA_IRQ_UART7) /* Vector 79: UART 7 */
|
||||
|
||||
UNUSED(TIVA_RESERVED_80) /* Vector 80: Reserved */
|
||||
UNUSED(TIVA_RESERVED_81) /* Vector 81: Reserved */
|
||||
UNUSED(TIVA_RESERVED_82) /* Vector 82: Reserved */
|
||||
UNUSED(TIVA_RESERVED_83) /* Vector 83: Reserved */
|
||||
VECTOR(tiva_i2c2, TIVA_IRQ_I2C2) /* Vector 84: I2C 2 */
|
||||
VECTOR(tiva_i2c3, TIVA_IRQ_I2C3) /* Vector 85: I2C 3 */
|
||||
VECTOR(tiva_timer4a, TIVA_IRQ_TIMER4A) /* Vector 86: 16/32-Bit Timer 4 A */
|
||||
VECTOR(tiva_timer4b, TIVA_IRQ_TIMER4B) /* Vector 87: 16/32-Bit Timer 4 B */
|
||||
UNUSED(TIVA_RESERVED_88) /* Vector 88: Reserved */
|
||||
UNUSED(TIVA_RESERVED_89) /* Vector 89: Reserved */
|
||||
|
||||
UNUSED(TIVA_RESERVED_90) /* Vector 90: Reserved */
|
||||
UNUSED(TIVA_RESERVED_91) /* Vector 91: Reserved */
|
||||
UNUSED(TIVA_RESERVED_92) /* Vector 92: Reserved */
|
||||
UNUSED(TIVA_RESERVED_93) /* Vector 93: Reserved */
|
||||
UNUSED(TIVA_RESERVED_94) /* Vector 94: Reserved */
|
||||
UNUSED(TIVA_RESERVED_95) /* Vector 95: Reserved */
|
||||
UNUSED(TIVA_RESERVED_96) /* Vector 96: Reserved */
|
||||
UNUSED(TIVA_RESERVED_97) /* Vector 97: Reserved */
|
||||
UNUSED(TIVA_RESERVED_98) /* Vector 98: Reserved */
|
||||
UNUSED(TIVA_RESERVED_99) /* Vector 99: Reserved */
|
||||
|
||||
UNUSED(TIVA_RESERVED_100) /* Vector 100: Reserved */
|
||||
UNUSED(TIVA_RESERVED_101) /* Vector 101: Reserved */
|
||||
UNUSED(TIVA_RESERVED_102) /* Vector 102: Reserved */
|
||||
UNUSED(TIVA_RESERVED_103) /* Vector 103: Reserved */
|
||||
UNUSED(TIVA_RESERVED_104) /* Vector 104: Reserved */
|
||||
UNUSED(TIVA_RESERVED_105) /* Vector 105: Reserved */
|
||||
UNUSED(TIVA_RESERVED_106) /* Vector 106: Reserved */
|
||||
UNUSED(TIVA_RESERVED_107) /* Vector 107: Reserved */
|
||||
VECTOR(tiva_timer5a, TIVA_IRQ_TIMER5A) /* Vector 108: 16/32-Bit Timer 5 A */
|
||||
VECTOR(tiva_timer5b, TIVA_IRQ_TIMER5B) /* Vector 109: 16/32-Bit Timer 5 B */
|
||||
|
||||
VECTOR(tiva_wtimer0a, TIVA_IRQ_WTIMER0A) /* Vector 110: 32/64-Bit Timer 0 A */
|
||||
VECTOR(tiva_wtimer0b, TIVA_IRQ_WTIMER0B) /* Vector 111: 32/64-Bit Timer 0 B */
|
||||
VECTOR(tiva_wtimer1a, TIVA_IRQ_WTIMER1A) /* Vector 112: 32/64-Bit Timer 1 A */
|
||||
VECTOR(tiva_wtimer1b, TIVA_IRQ_WTIMER1B) /* Vector 113: 32/64-Bit Timer 1 B */
|
||||
VECTOR(tiva_wtimer2a, TIVA_IRQ_WTIMER2A) /* Vector 114: 32/64-Bit Timer 2 A */
|
||||
VECTOR(tiva_wtimer2b, TIVA_IRQ_WTIMER2B) /* Vector 115: 32/64-Bit Timer 2 B */
|
||||
VECTOR(tiva_wtimer3a, TIVA_IRQ_WTIMER3A) /* Vector 116: 32/64-Bit Timer 3 A */
|
||||
VECTOR(tiva_wtimer3b, TIVA_IRQ_WTIMER3B) /* Vector 117: 32/64-Bit Timer 3 B */
|
||||
VECTOR(tiva_wtimer4a, TIVA_IRQ_WTIMER4A) /* Vector 118: 32/64-Bit Timer 4 A */
|
||||
VECTOR(tiva_WTIMER4B, TIVA_IRQ_WTIMER4B) /* Vector 119: 32/64-Bit Timer 4 B */
|
||||
|
||||
VECTOR(tiva_wtimer5a, TIVA_IRQ_WTIMER5A) /* Vector 120: 32/64-Bit Timer 5 A */
|
||||
VECTOR(tiva_wtimer5b, TIVA_IRQ_WTIMER5B) /* Vector 121: 32/64-Bit Timer 5 B */
|
||||
VECTOR(tiva_system, TIVA_IRQ_SYSTEM) /* Vector 122: System Exception (imprecise) */
|
||||
UNUSED(TIVA_RESERVED_123) /* Vector 123: Reserved */
|
||||
UNUSED(TIVA_RESERVED_124) /* Vector 124: Reserved */
|
||||
VECTOR(tiva_i2c4, TIVA_IRQ_I2C4) /* Vector 125: I2C4 */
|
||||
VECTOR(tiva_i2c5, TIVA_IRQ_I2C5) /* Vector 126: I2C5 */
|
||||
VECTOR(tiva_gpiom, TIVA_IRQ_GPIOM) /* Vector 127: GPIO Port M */
|
||||
VECTOR(tiva_gpion, TIVA_IRQ_GPION) /* Vector 128: GPIO Port N */
|
||||
UNUSED(TIVA_RESERVED_129) /* Vector 129: Reserved */
|
||||
|
||||
UNUSED(TIVA_RESERVED_130) /* Vector 130: Reserved */
|
||||
UNUSED(TIVA_RESERVED_131) /* Vector 131: Reserved */
|
||||
VECTOR(tiva_gpiop, TIVA_IRQ_GPIOP) /* Vector 132: GPIO Port P (Summary or P0) */
|
||||
VECTOR(tiva_gpiop1, TIVA_IRQ_GPIOP1) /* Vector 133: GPIO Port P1 */
|
||||
VECTOR(tiva_gpiop2, TIVA_IRQ_GPIOP2) /* Vector 134: GPIO Port P2 */
|
||||
VECTOR(tiva_gpiop3, TIVA_IRQ_GPIOP3) /* Vector 135: GPIO Port P3 */
|
||||
VECTOR(tiva_gpiop4, TIVA_IRQ_GPIOP4) /* Vector 136: GPIO Port P4 */
|
||||
VECTOR(tiva_gpiop5, TIVA_IRQ_GPIOP5) /* Vector 137: GPIO Port P5 */
|
||||
VECTOR(tiva_gpiop6, TIVA_IRQ_GPIOP6) /* Vector 138: GPIO Port P6 */
|
||||
VECTOR(tiva_gpiop7, TIVA_IRQ_GPIOP7) /* Vector 139: GPIO Port P7 */
|
||||
|
||||
VECTOR(tiva_gpioq, TIVA_IRQ_GPIOQ) /* Vector 140: GPIO Port Q (Summary or Q0) */
|
||||
VECTOR(tiva_gpioq1, TIVA_IRQ_GPIOQ1) /* Vector 141: GPIO Port Q1 */
|
||||
VECTOR(tiva_gpioq2, TIVA_IRQ_GPIOQ2) /* Vector 142: GPIO Port Q2 */
|
||||
VECTOR(tiva_gpioq3, TIVA_IRQ_GPIOQ3) /* Vector 143: GPIO Port Q3 */
|
||||
VECTOR(tiva_gpioq4, TIVA_IRQ_GPIOQ4) /* Vector 144: GPIO Port Q4 */
|
||||
VECTOR(tiva_gpioq5, TIVA_IRQ_GPIOQ5) /* Vector 145: GPIO Port Q5 */
|
||||
VECTOR(tiva_gpioq6, TIVA_IRQ_GPIOQ6) /* Vector 146: GPIO Port Q6 */
|
||||
VECTOR(tiva_gpioq7, TIVA_IRQ_GPIOQ7) /* Vector 147: GPIO Port Q7 */
|
||||
UNUSED(TIVA_RESERVED_148) /* Vector 148: Reserved */
|
||||
UNUSED(TIVA_RESERVED_149) /* Vector 149: Reserved */
|
||||
|
||||
VECTOR(tiva_pwm1_gen0, TIVA_IRQ_PWM1_GEN0) /* Vector 150: PWM1 Generator 0 */
|
||||
VECTOR(tiva_pwm1_gen1, TIVA_IRQ_PWM1_GEN1) /* Vector 151: PWM1 Generator 1 */
|
||||
VECTOR(tiva_pwm1_gen2, TIVA_IRQ_PWM1_GEN2) /* Vector 152: PWM1 Generator 2 */
|
||||
VECTOR(tiva_pwm1_gen3, TIVA_IRQ_PWM1_GEN3) /* Vector 153: PWM1 Generator 3 */
|
||||
VECTOR(tiva_pwm1_fault, TIVA_IRQ_PWM1_FAULT) /* Vector 154: PWM1 Fault */
|
||||
|
||||
# endif /* CONFIG_ARMV7M_CMNVECTOR */
|
||||
|
||||
#else
|
||||
# error "Vectors not known for this Tiva chip"
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user