SAML21: Add DMA descriptor management logic
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@ -34,13 +34,15 @@
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****************************************************************************/
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****************************************************************************/
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/* The ATSAML21J18A has 256KB of FLASH beginning at address 0x0000:0000 and
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/* The ATSAML21J18A has 256KB of FLASH beginning at address 0x0000:0000 and
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* 32KB of SRAM beginning at address 0x2000:0000
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* 32KB of SRAM beginning at address 0x2000:0000. There is also 8KB low-
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* power SRAM at 0x30000000 that may be used by the DMAC.
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*/
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*/
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MEMORY
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MEMORY
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{
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{
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flash (rx) : ORIGIN = 0x00000000, LENGTH = 256K
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flash (rx) : ORIGIN = 0x00000000, LENGTH = 256K
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sram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
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sram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
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lpram (rw) : ORIGIN = 0x30000000, LENGTH = 8K
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}
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}
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OUTPUT_ARCH(arm)
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OUTPUT_ARCH(arm)
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@ -107,6 +109,10 @@ SECTIONS
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_ebss = ABSOLUTE(.);
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_ebss = ABSOLUTE(.);
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} > sram
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} > sram
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.lpram : {
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*(.lpram)
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} > lpram
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/* Stabs debugging sections. */
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stabstr 0 : { *(.stabstr) }
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