From b11a5ca8b2c31e8921cab407c747f5d9f31aba2b Mon Sep 17 00:00:00 2001 From: Dong Heng Date: Thu, 21 Jan 2021 20:13:10 +0800 Subject: [PATCH] risc-v/esp32c3: Add ESP32-C3 basic support Co-authored-by: Dong Heng Co-authored-by: Abdelatif Guettouche --- arch/risc-v/Kconfig | 12 + arch/risc-v/include/esp32c3/chip.h | 24 + arch/risc-v/include/esp32c3/irq.h | 293 ++++ arch/risc-v/include/rv32im/mcause.h | 63 + arch/risc-v/src/common/riscv_internal.h | 4 + arch/risc-v/src/esp32c3/Kconfig | 80 ++ arch/risc-v/src/esp32c3/Make.defs | 53 + arch/risc-v/src/esp32c3/chip.h | 31 + arch/risc-v/src/esp32c3/esp32c3.h | 50 + .../risc-v/src/esp32c3/esp32c3_allocateheap.c | 89 ++ arch/risc-v/src/esp32c3/esp32c3_attr.h | 53 + arch/risc-v/src/esp32c3/esp32c3_head.S | 77 ++ arch/risc-v/src/esp32c3/esp32c3_idle.c | 73 + arch/risc-v/src/esp32c3/esp32c3_interrupt.S | 170 +++ arch/risc-v/src/esp32c3/esp32c3_irq.c | 372 +++++ arch/risc-v/src/esp32c3/esp32c3_irq.h | 101 ++ arch/risc-v/src/esp32c3/esp32c3_memorymap.h | 43 + arch/risc-v/src/esp32c3/esp32c3_rom.h | 36 + arch/risc-v/src/esp32c3/esp32c3_start.c | 88 ++ arch/risc-v/src/esp32c3/esp32c3_timerisr.c | 128 ++ arch/risc-v/src/esp32c3/esp32c3_vectors.S | 79 ++ .../src/esp32c3/hardware/esp32c3_interrupt.h | 962 +++++++++++++ .../src/esp32c3/hardware/esp32c3_memorymap.h | 78 ++ .../risc-v/src/esp32c3/hardware/esp32c3_soc.h | 257 ++++ .../src/esp32c3/hardware/esp32c3_system.h | 1213 +++++++++++++++++ .../src/esp32c3/hardware/esp32c3_systimer.h | 587 ++++++++ arch/risc-v/src/rv32im/riscv_exception.c | 96 ++ tools/esp32c3/Config.mk | 77 ++ tools/esp32c3/Makefile | 63 + 29 files changed, 5252 insertions(+) create mode 100644 arch/risc-v/include/esp32c3/chip.h create mode 100644 arch/risc-v/include/esp32c3/irq.h create mode 100644 arch/risc-v/include/rv32im/mcause.h create mode 100644 arch/risc-v/src/esp32c3/Kconfig create mode 100644 arch/risc-v/src/esp32c3/Make.defs create mode 100644 arch/risc-v/src/esp32c3/chip.h create mode 100644 arch/risc-v/src/esp32c3/esp32c3.h create mode 100644 arch/risc-v/src/esp32c3/esp32c3_allocateheap.c create mode 100644 arch/risc-v/src/esp32c3/esp32c3_attr.h create mode 100644 arch/risc-v/src/esp32c3/esp32c3_head.S create mode 100644 arch/risc-v/src/esp32c3/esp32c3_idle.c create mode 100644 arch/risc-v/src/esp32c3/esp32c3_interrupt.S create mode 100644 arch/risc-v/src/esp32c3/esp32c3_irq.c create mode 100644 arch/risc-v/src/esp32c3/esp32c3_irq.h create mode 100644 arch/risc-v/src/esp32c3/esp32c3_memorymap.h create mode 100644 arch/risc-v/src/esp32c3/esp32c3_rom.h create mode 100644 arch/risc-v/src/esp32c3/esp32c3_start.c create mode 100644 arch/risc-v/src/esp32c3/esp32c3_timerisr.c create mode 100644 arch/risc-v/src/esp32c3/esp32c3_vectors.S create mode 100644 arch/risc-v/src/esp32c3/hardware/esp32c3_interrupt.h create mode 100644 arch/risc-v/src/esp32c3/hardware/esp32c3_memorymap.h create mode 100644 arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h create mode 100644 arch/risc-v/src/esp32c3/hardware/esp32c3_system.h create mode 100644 arch/risc-v/src/esp32c3/hardware/esp32c3_systimer.h create mode 100644 arch/risc-v/src/rv32im/riscv_exception.c create mode 100644 tools/esp32c3/Config.mk create mode 100644 tools/esp32c3/Makefile diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig index 3a3bdaaf75..86218ff88c 100644 --- a/arch/risc-v/Kconfig +++ b/arch/risc-v/Kconfig @@ -52,6 +52,14 @@ config ARCH_CHIP_BL602 ---help--- BouffaloLab BL602(rv32imfc) +config ARCH_CHIP_ESP32C3 + bool "Espressif ESP32-C3" + select ARCH_RV32IM + select RV32IM_HW_MULDIV + select ARCH_VECNOTIRQ + ---help--- + Espressif ESP32-C3 (RV32IMC). + config ARCH_CHIP_RISCV_CUSTOM bool "Custom RISC-V chip" select ARCH_CHIP_CUSTOM @@ -89,6 +97,7 @@ config ARCH_CHIP default "nr5m100" if ARCH_CHIP_NR5 default "gap8" if ARCH_CHIP_GAP8 default "bl602" if ARCH_CHIP_BL602 + default "esp32c3" if ARCH_CHIP_ESP32C3 config NR5_MPU bool "MPU support" @@ -124,4 +133,7 @@ endif if ARCH_CHIP_BL602 source arch/risc-v/src/bl602/Kconfig endif +if ARCH_CHIP_ESP32C3 +source arch/risc-v/src/esp32c3/Kconfig +endif endif diff --git a/arch/risc-v/include/esp32c3/chip.h b/arch/risc-v/include/esp32c3/chip.h new file mode 100644 index 0000000000..1710e6c8c3 --- /dev/null +++ b/arch/risc-v/include/esp32c3/chip.h @@ -0,0 +1,24 @@ +/**************************************************************************** + * arch/risc-v/include/esp32c3/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_ESP32C3_CHIP_H +#define __ARCH_RISCV_INCLUDE_ESP32C3_CHIP_H + +#endif /* __ARCH_RISCV_INCLUDE_ESP32C3_CHIP_H */ diff --git a/arch/risc-v/include/esp32c3/irq.h b/arch/risc-v/include/esp32c3/irq.h new file mode 100644 index 0000000000..2326fc9099 --- /dev/null +++ b/arch/risc-v/include/esp32c3/irq.h @@ -0,0 +1,293 @@ +/**************************************************************************** + * arch/risc-v/include/esp32c3/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_ESP32C3_IRQ_H +#define __ARCH_RISCV_INCLUDE_ESP32C3_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Interrupt Matrix + * + * The Interrupt Matrix embedded in the ESP32C3 independently allocates + * peripheral interrupt sources to the CPUs’ peripheral interrupts. + * This configuration is highly flexible in order to meet many different + * needs. + * + * Features + * - Accepts 62 peripheral interrupt sources as input. + * - Generate 31 peripheral interrupts to CPU as output. + * - Queries current interrupt status of peripheral interrupt sources. + */ + +#define ESP32C3_PERIPH_WIFI_MAC 0 +#define ESP32C3_PERIPH_WIFI_MAC_NMI 1 +#define ESP32C3_PERIPH_WIFI_PWR 2 +#define ESP32C3_PERIPH_WIFI_BB 3 +#define ESP32C3_PERIPH_BT_MAC 4 +#define ESP32C3_PERIPH_BT_BB 5 +#define ESP32C3_PERIPH_BT_BB_NMI 6 +#define ESP32C3_PERIPH_RWBT_IRQ 7 +#define ESP32C3_PERIPH_RWBLE_IRQ 8 +#define ESP32C3_PERIPH_RWBT_NMI 9 + +#define ESP32C3_PERIPH_RWBLE_NMI 10 +#define ESP32C3_PERIPH_I2C_MASTER 11 +#define ESP32C3_PERIPH_SLC0 12 +#define ESP32C3_PERIPH_SLC1 13 +#define ESP32C3_PERIPH_APB_CTRL 14 +#define ESP32C3_PERIPH_UHCI0 15 +#define ESP32C3_PERIPH_GPIO 16 +#define ESP32C3_PERIPH_GPIO_NMI 17 +#define ESP32C3_PERIPH_SPI1 18 +#define ESP32C3_PERIPH_SPI2 19 + +#define ESP32C3_PERIPH_I2S1 20 +#define ESP32C3_PERIPH_UART0 21 +#define ESP32C3_PERIPH_UART1 22 +#define ESP32C3_PERIPH_LEDC 23 +#define ESP32C3_PERIPH_EFUSE 24 +#define ESP32C3_PERIPH_TWAI 25 +#define ESP32C3_PERIPH_USB 26 +#define ESP32C3_PERIPH_RTC_CORE 27 +#define ESP32C3_PERIPH_RMT 28 +#define ESP32C3_PERIPH_I2C_EXT0 39 + +#define ESP32C3_PERIPH_TIMER1 30 +#define ESP32C3_PERIPH_TIMER2 31 +#define ESP32C3_PERIPH_TG0_T0 32 +#define ESP32C3_PERIPH_TG0_WDT 33 +#define ESP32C3_PERIPH_TG1_T0 34 +#define ESP32C3_PERIPH_TG1_WDT 35 +#define ESP32C3_PERIPH_CACHE_IA 36 +#define ESP32C3_PERIPH_SYSTIMER_T0 37 +#define ESP32C3_PERIPH_SYSTIMER_T1 38 +#define ESP32C3_PERIPH_SYSTIMER_T2 39 + +#define ESP32C3_PERIPH_SPIMEM_REJECT_CACHE 40 +#define ESP32C3_PERIPH_ICACHE_PRELOAD0 41 +#define ESP32C3_PERIPH_ICACHE_SYNC0 42 +#define ESP32C3_PERIPH_APB_ADC 43 +#define ESP32C3_PERIPH_DMA_CH0 44 +#define ESP32C3_PERIPH_DMA_CH0 45 +#define ESP32C3_PERIPH_DMA_CH0 46 +#define ESP32C3_PERIPH_RSA 47 +#define ESP32C3_PERIPH_AES 48 +#define ESP32C3_PERIPH_SHA 49 + +#define ESP32C3_PERIPH_FROM_CPU_INT0 50 +#define ESP32C3_PERIPH_FROM_CPU_INT1 51 +#define ESP32C3_PERIPH_FROM_CPU_INT2 52 +#define ESP32C3_PERIPH_FROM_CPU_INT3 53 +#define ESP32C3_PERIPH_ASSIST_DEBUG 54 +#define ESP32C3_PERIPH_DMA_APBPERI_PMS 55 +#define ESP32C3_PERIPH_CORE0_IRAM0_PMS 56 +#define ESP32C3_PERIPH_CORE0_DRAM0_PMS 57 +#define ESP32C3_PERIPH_CORE0_PIF_PMS 58 +#define ESP32C3_PERIPH_CORE0_PIF_PMS_SZIE 59 + +#define ESP32C3_PERIPH_BAK_PMS_VIOLATE 60 +#define ESP32C3_PERIPH_CACHE_CORE0_ACS 61 + +/* Total number of peripherals */ + +#define ESP32C3_NPERIPHERALS 62 + +/* CPU Interrupts. + * + * The ESP32 CPU interrupt controller accepts 31 asynchronous interrupts. + */ + +#define ESP32C3_CPUINT_MIN 1 +#define ESP32C3_CPUINT_MAX 31 + +/* IRQ numbers. */ + +/* ecall is dispatched like normal interrupts. It occupies an IRQ number. */ + +#define ESP32C3_IRQ_ECALL_M 0 +#define ESP32C3_IRQ_FIRSTPERIPH 1 /* First peripheral IRQ number */ + +/* Peripheral IRQs */ + +#define ESP32C3_IRQ_WIFI_MAC (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_WIFI_MAC) +#define ESP32C3_IRQ_WIFI_MAC_NMI (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_WIFI_MAC_NMI) +#define ESP32C3_IRQ_WIFI_PWR (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_WIFI_PWR) +#define ESP32C3_IRQ_WIFI_BB (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_WIFI_BB) +#define ESP32C3_IRQ_BT_MAC (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_BT_MAC) +#define ESP32C3_IRQ_BT_BB (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_BT_BB) +#define ESP32C3_IRQ_BT_BB_NMI (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_BT_BB_NMI) +#define ESP32C3_IRQ_RWBT_IRQ (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_RWBT_IRQ) +#define ESP32C3_IRQ_RWBLE_IRQ (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_RWBLE_IRQ) +#define ESP32C3_IRQ_RWBT_NMI (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_RWBT_NMI) +#define ESP32C3_IRQ_RWBLE_NMI (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_RWBLE_NMI) +#define ESP32C3_IRQ_I2C_MASTER (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_I2C_MASTER) +#define ESP32C3_IRQ_SLC0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SLC0) +#define ESP32C3_IRQ_SLC1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SLC1) +#define ESP32C3_IRQ_APB_CTRL (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_APB_CTRL) +#define ESP32C3_IRQ_UHCI0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_UHCI0) +#define ESP32C3_IRQ_GPIO (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_GPIO) +#define ESP32C3_IRQ_GPIO_NMI (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_GPIO_NMI) +#define ESP32C3_IRQ_SPI1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SPI1) +#define ESP32C3_IRQ_SPI2 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SPI2) +#define ESP32C3_IRQ_I2S1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_I2S1) +#define ESP32C3_IRQ_UART0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_UART0) +#define ESP32C3_IRQ_UART1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_UART1) +#define ESP32C3_IRQ_LEDC (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_LEDC) +#define ESP32C3_IRQ_EFUSE (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_EFUSE) +#define ESP32C3_IRQ_TWAI (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_TWAI) +#define ESP32C3_IRQ_USB (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_USB) +#define ESP32C3_IRQ_RTC_CORE (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_RTC_CORE) +#define ESP32C3_IRQ_RMT (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_RMT) +#define ESP32C3_IRQ_I2C_EXT0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_I2C_EXT0) +#define ESP32C3_IRQ_TIMER1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_TIMER1) +#define ESP32C3_IRQ_TIMER2 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_TIMER2) +#define ESP32C3_IRQ_TG0_T0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_TG0_T0) +#define ESP32C3_IRQ_TG0_WDT (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_TG0_WDT) +#define ESP32C3_IRQ_TG1_T0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_TG1_T0) +#define ESP32C3_IRQ_TG1_WDT (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_TG1_WDT) +#define ESP32C3_IRQ_CACHE_IA (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_CACHE_IA) +#define ESP32C3_IRQ_SYSTIMER_T0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SYSTIMER_T0) +#define ESP32C3_IRQ_SYSTIMER_T1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SYSTIMER_T1) +#define ESP32C3_IRQ_SYSTIMER_T2 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SYSTIMER_T2) +#define ESP32C3_IRQ_SPIMEM_REJECT_CACHE (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SPIMEM_REJECT_CACHE) +#define ESP32C3_IRQ_ICACHE_PRELOAD0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_ICACHE_PRELOAD0) +#define ESP32C3_IRQ_ICACHE_SYNC0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_ICACHE_SYNC0) +#define ESP32C3_IRQ_APB_ADC (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_APB_ADC) +#define ESP32C3_IRQ_DMA_CH0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_CH0) +#define ESP32C3_IRQ_DMA_CH0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_CH0) +#define ESP32C3_IRQ_DMA_CH0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_CH0) +#define ESP32C3_IRQ_RSA (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_RSA) +#define ESP32C3_IRQ_AES (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_AES) +#define ESP32C3_IRQ_SHA (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SHA) +#define ESP32C3_IRQ_FROM_CPU_INT0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_FROM_CPU_INT0) +#define ESP32C3_IRQ_FROM_CPU_INT1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_FROM_CPU_INT1) +#define ESP32C3_IRQ_FROM_CPU_INT2 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_FROM_CPU_INT2) +#define ESP32C3_IRQ_FROM_CPU_INT3 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_FROM_CPU_INT3) +#define ESP32C3_IRQ_ASSIST_DEBUG (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_ASSIST_DEBUG) +#define ESP32C3_IRQ_DMA_APBPERI_PMS (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_APBPERI_PMS) +#define ESP32C3_IRQ_CORE0_IRAM0_PMS (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_CORE0_IRAM0_PMS) +#define ESP32C3_IRQ_CORE0_DRAM0_PMS (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_CORE0_DRAM0_PMS) +#define ESP32C3_IRQ_CORE0_PIF_PMS (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_CORE0_PIF_PMS) +#define ESP32C3_IRQ_CORE0_PIF_PMS_SZIE (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_CORE0_PIF_PMS_SZIE) +#define ESP32C3_IRQ_BAK_PMS_VIOLATE (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_BAK_PMS_VIOLATE) +#define ESP32C3_IRQ_CACHE_CORE0_ACS (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_CACHE_CORE0_ACS) + +#define ESP32C3_NIRQ_PERIPH ESP32C3_NPERIPHERALS + +/* Total number of IRQs: Number of peripheral IRQs + 1 for ecall. */ + +#define NR_IRQS (ESP32C3_NIRQ_PERIPH + 1) + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Name: up_irq_restore + * + * Description: + * Restore the value of the mstatus register + * + ****************************************************************************/ + +static inline void up_irq_restore(irqstate_t flags) +{ + __asm__ __volatile__ + ( + "csrw mstatus, %0" : /* no output */ : "r" (flags) + ); +} + +/**************************************************************************** + * Name: up_irq_save + * + * Description: + * Disable interrupts and return the previous value of the mstatus register + * + ****************************************************************************/ + +static inline irqstate_t up_irq_save(void) +{ + irqstate_t flags; + + /* Read mstatus & clear machine interrupt enable (MIE) in mstatus */ + + __asm__ __volatile__ + ( + "csrrc %0, mstatus, %1" : "=r" (flags) : "r"(MSTATUS_MIE) + ); + + /* Return the previous mstatus value so that it can be restored with + * up_irq_restore(). + */ + + return flags; +} + +/**************************************************************************** + * Name: up_irq_enable + * + * Description: + * Return the current interrupt state and enable interrupts + * + ****************************************************************************/ + +static inline irqstate_t up_irq_enable(void) +{ + uint32_t flags; + + /* Read mstatus & set machine interrupt enable (MIE) in mstatus */ + + __asm__ __volatile__ + ( + "csrrs %0, mstatus, %1": "=r" (flags) : "r"(MSTATUS_MIE) + ); + + return flags; +} + +/**************************************************************************** + * Name: up_irq_disable + * + * Description: + * Disable interrupts + * + ****************************************************************************/ + +static inline void up_irq_disable(void) +{ + up_irq_save(); +} + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_RISCV_INCLUDE_ESP32C3_IRQ_H */ diff --git a/arch/risc-v/include/rv32im/mcause.h b/arch/risc-v/include/rv32im/mcause.h new file mode 100644 index 0000000000..34b9d71b25 --- /dev/null +++ b/arch/risc-v/include/rv32im/mcause.h @@ -0,0 +1,63 @@ +/**************************************************************************** + * arch/risc-v/include/rv32im/mcause.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_RV32IM_MCAUSE_H +#define __ARCH_RISCV_INCLUDE_RV32IM_MCAUSE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Interrupt(BIT31) or Exception(0) */ + +#define MCAUSE_INTERRUPT (1 << 31) +#define MCAUSE_INTERRUPT_MASK (~MCAUSE_INTERRUPT) + +/* Exception values *********************************************************/ + +#define MCAUSE_ADDE_MISALIGNED (0) /* Instruction address misaligned */ +#define MCAUSE_INST_ACCESS_FAULT (1) /* Instruction access fault */ +#define MCAUSE_ILLEGAL_INST (2) /* Illegal instruction */ +#define MCAUSE_BREAKPOINT (3) /* Breakpoint */ +#define MCAUSE_LOAD_MISALIGNED (4) /* Load address misaligned */ +#define MCAUSE_LOAD_ACCESS_FAULT (5) /* Load access fault */ +#define MCAUSE_STORE_MISALIGNED (6) /* Store/AMO address misaligned */ +#define MCAUSE_STORE_ACCESS_FAULT (7) /* Store/AMO access fault */ +#define MCAUSE_ECALL_U (8) /* Environment call from U-mode */ +#define MCAUSE_ECALL_S (9) /* Environment call from S-mode */ +#define MCAUSE_RESERVED (10) /* Reserved */ +#define MCAUSE_ECALL_M (11) /* Environment call from M-mode */ +#define MCAUSE_INST_PAGE_FAULT (12) /* Instruction page fault */ +#define MCAUSE_LOAD_PAGE_FAULT (13) /* Load page fault */ +#define MCAUSE_RESERVED (14) /* Reserved */ +#define MCAUSE_STORE_PAGE_FAULT (15) /* Store/AMO page fault */ + +/* Max RISC-V defined mcause exception values. */ + +#define MCAUSE_MAX_EXCEPTION (15) + +#endif /* __ARCH_RISCV_INCLUDE_RV32IM_MCAUSE_H */ + diff --git a/arch/risc-v/src/common/riscv_internal.h b/arch/risc-v/src/common/riscv_internal.h index cbfbd22997..1c700d359c 100644 --- a/arch/risc-v/src/common/riscv_internal.h +++ b/arch/risc-v/src/common/riscv_internal.h @@ -228,6 +228,10 @@ void up_earlyserialinit(void); void rpmsg_serialinit(void); #endif +/* Exception Handler ********************************************************/ + +void riscv_exception(uint32_t mcause, uint32_t *regs); + /* Debug ********************************************************************/ #ifdef CONFIG_STACK_COLORATION diff --git a/arch/risc-v/src/esp32c3/Kconfig b/arch/risc-v/src/esp32c3/Kconfig new file mode 100644 index 0000000000..c71809496c --- /dev/null +++ b/arch/risc-v/src/esp32c3/Kconfig @@ -0,0 +1,80 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_ESP32C3 + +comment "ESP32-C3 Configuration Options" + +choice + prompt "ESP32-C3 Chip Selection" + default ARCH_CHIP_ESP32C3WROOM02 + depends on ARCH_CHIP_ESP32C3 + +config ARCH_CHIP_ESP32C3X + bool "ESP32-C3" + select ESP32C3_ESP32C3XXX + ---help--- + ESP32 chip with a single RISC-V IMC core, no embedded Flash memory + +config ARCH_CHIP_ESP32C3FX4 + bool "ESP32-C3Fx4" + select ESP32C3_ESP32C3XXX + select ESP32C3_FLASH_4M + ---help--- + ESP32 chip with a single RISC-V IMC core, 4 MB of in-package Flash memory + +config ARCH_CHIP_ESP32C3MINI1 + bool "ESP32-C3-MINI-1" + select ESP32C3_ESP32C3XXX + select ESP32C3_FLASH_4M + ---help--- + Generic module with an embedded ESP32-C3Fx4 chip + +config ARCH_CHIP_ESP32C3WROOM02 + bool "ESP32-C3-WROOM-02" + select ESP32C3_ESP32C3XXX + select ESP32C3_FLASH_4M + ---help--- + Generic module with an embedded ESP32-C3 chip, 4 MB of Flash memory + +endchoice # ESP32-C3 Chip Selection + +comment "Selected ESP32-C3 chip without embedded Flash, an external Flash memory is required." + depends on ARCH_CHIP_ESP32C3X + +config ESP32C3_SINGLE_CPU + bool + default n + +config ESP32C3_DUAL_CPU + bool + default n + +config ESP32C3_FLASH_2M + bool + default n + +config ESP32C3_FLASH_4M + bool + default n + +config ESP32C3_FLASH_8M + bool + default n + +config ESP32C3_FLASH_16M + bool + default n + +config ESP32C3_ESP32C3XXX + bool + default n + select ESP32C3_SINGLE_CPU + +menu "ESP32-C3 Peripheral Support" + +endmenu + +endif # ARCH_CHIP_ESP32C3 diff --git a/arch/risc-v/src/esp32c3/Make.defs b/arch/risc-v/src/esp32c3/Make.defs new file mode 100644 index 0000000000..4079b26d83 --- /dev/null +++ b/arch/risc-v/src/esp32c3/Make.defs @@ -0,0 +1,53 @@ +############################################################################ +# arch/risc-v/src/esp32c3/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# Specify our HEAD assembly file. This will be linked as +# the first object file, so it will appear at address 0 + +HEAD_ASRC = esp32c3_head.S + +CHIP_ASRCS = esp32c3_vectors.S esp32c3_interrupt.S riscv_syscall.S + +ifeq ($(CONFIG_ARCH_SETJMP_H),y) +CMN_ASRCS += riscv_setjmp.S +endif + +# Specify C code within the common directory to be included + +CMN_CSRCS += riscv_initialize.c riscv_swint.c +CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c riscv_exception.c +CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c +CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c +CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c +CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c +CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c riscv_usestack.c + +ifeq ($(CONFIG_STACK_COLORATION),y) +CMN_CSRCS += riscv_checkstack.c +endif + +ifeq ($(CONFIG_ARCH_HAVE_VFORK),y) +CMN_CSRCS += riscv_vfork.c +endif + +# Specify our C code within this directory to be included + +CHIP_CSRCS = esp32c3_allocateheap.c esp32c3_start.c esp32c3_idle.c +CHIP_CSRCS += esp32c3_irq.c esp32c3_timerisr.c diff --git a/arch/risc-v/src/esp32c3/chip.h b/arch/risc-v/src/esp32c3/chip.h new file mode 100644 index 0000000000..67a6bcf303 --- /dev/null +++ b/arch/risc-v/src/esp32c3/chip.h @@ -0,0 +1,31 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_CHIP_H +#define __ARCH_RISCV_SRC_ESP32C3_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "esp32c3_memorymap.h" + +#endif /* __ARCH_RISCV_SRC_ESP32C3_CHIP_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3.h b/arch/risc-v/src/esp32c3/esp32c3.h new file mode 100644 index 0000000000..299aabae82 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3.h @@ -0,0 +1,50 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include +#include "riscv_internal.h" +#include "riscv_arch.h" +#include "esp32c3_rom.h" +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#define setbits(bs, a) modifyreg32(a, 0, bs) +#define resetbits(bs, a) modifyreg32(a, bs, 0) + +#endif + +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_allocateheap.c b/arch/risc-v/src/esp32c3/esp32c3_allocateheap.c new file mode 100644 index 0000000000..148157234b --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_allocateheap.c @@ -0,0 +1,89 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_allocateheap.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include "esp32c3.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * For the kernel build (CONFIG_BUILD_KERNEL=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the + * size of the unprotected, user-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated (and protected) by an analogous up_allocate_kheap(). + * + ****************************************************************************/ + +void up_allocate_heap(FAR void **heap_start, size_t *heap_size) +{ + /* These values come from the linker scripts (esp32c3.ld and + * esp32c3.template.ld.) Check boards/risc-v/esp32c3. + */ + + extern uint8_t *_sheap; + extern uint8_t *_eheap; + + board_autoled_on(LED_HEAPALLOCATE); + + *heap_start = (FAR void *)&_sheap; + *heap_size = (size_t)((uintptr_t)&_eheap - (uintptr_t)&_sheap); +} + +/**************************************************************************** + * Name: riscv_addregion + * + * Description: + * RAM may be added in non-contiguous chunks. This routine adds all chunks + * that may be used for heap. + * + ****************************************************************************/ + +#if CONFIG_MM_REGIONS > 1 +void riscv_addregion(void) +{ +} +#endif + diff --git a/arch/risc-v/src/esp32c3/esp32c3_attr.h b/arch/risc-v/src/esp32c3/esp32c3_attr.h new file mode 100644 index 0000000000..93122d60ff --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_attr.h @@ -0,0 +1,53 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_attr.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_ATTR_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_ATTR_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Forces code into IRAM instead of flash */ + +#define IRAM_ATTR __attribute__((section(".iram1"))) + +/* Forces data into DRAM instead of flash */ + +#define DRAM_ATTR __attribute__((section(".dram1"))) + +/* Forces code into RTC fast memory */ + +#define RTC_IRAM_ATTR __attribute__((section(".rtc.text"))) + +/* Forces data into RTC slow memory + * Any variable marked with this attribute will keep its value + * during a deep sleep / wake cycle. + */ + +#define RTC_DATA_ATTR __attribute__((section(".rtc.data"))) + +/* Forces read-only data into RTC slow memory + * Makes constant data available to RTC wake stubs. + */ + +#define RTC_RODATA_ATTR __attribute__((section(".rtc.rodata"))) + +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_ATTR_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_head.S b/arch/risc-v/src/esp32c3/esp32c3_head.S new file mode 100644 index 0000000000..0ed44ca81e --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_head.S @@ -0,0 +1,77 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_head.S + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "chip.h" + +/**************************************************************************** + * Public Symbols + ****************************************************************************/ + + .global __start + +/**************************************************************************** + * Section: .text + ****************************************************************************/ + + .section .text + +/**************************************************************************** + * Name: __start + ****************************************************************************/ + +__start: + .option push + .option norelax + + /* Set stack pointer to the idle thread stack */ + + lui sp, %hi(ESP32C3_IDLESTACK_TOP) + addi sp, sp, %lo(ESP32C3_IDLESTACK_TOP) + + /* Set gp pointer */ + + la gp, __global_pointer$ + + /* Disable all interrupts (i.e. timer, external) in mstatus */ + + csrw mstatus, zero + + .option pop + + /* Initialize the Machine Trap-Vector */ + + lui t0, %hi(_vector_table) + addi t0, t0, %lo(_vector_table) + csrw mtvec, t0 + + /* Jump to __esp32c3_start */ + + jal x1, __esp32c3_start + + /* We shouldn't return from __esp32c3_start */ + + ret diff --git a/arch/risc-v/src/esp32c3/esp32c3_idle.c b/arch/risc-v/src/esp32c3/esp32c3_idle.c new file mode 100644 index 0000000000..079bfd4a4e --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_idle.c @@ -0,0 +1,73 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_idle.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "esp32c3.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + /* This would be an appropriate place to put some MCU-specific logic to + * sleep in a reduced power mode until an interrupt occurs to save power + */ + + asm("WFI"); + +#endif +} diff --git a/arch/risc-v/src/esp32c3/esp32c3_interrupt.S b/arch/risc-v/src/esp32c3/esp32c3_interrupt.S new file mode 100644 index 0000000000..957f2de1a9 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_interrupt.S @@ -0,0 +1,170 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_interrupt.S + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "chip.h" + +/**************************************************************************** + * Public Symbols + ****************************************************************************/ + + .global _interrupt_handler + .global _exception_handler + .global g_intstackalloc + .global g_intstackbase + +/**************************************************************************** + * Section: .noinit + ****************************************************************************/ + + .section .noinit + +#if CONFIG_ARCH_INTERRUPTSTACK > 15 + .align 4 + .type g_intstackalloc, @object + .type g_intstackbase, @object +g_intstackalloc: + .skip CONFIG_ARCH_INTERRUPTSTACK +g_intstackbase: + .size g_intstackalloc, CONFIG_ARCH_INTERRUPTSTACK +#endif + +/**************************************************************************** + * Section: .iram1 + ****************************************************************************/ + + .section .iram1 + +/**************************************************************************** + * Name: _interrupt_handler + ****************************************************************************/ + + .type _interrupt_handler, @function + +_exception_handler: +_interrupt_handler: + addi sp, sp, -XCPTCONTEXT_SIZE + + sw x1, 1*4(sp) /* ra */ + sw x3, 3*4(sp) /* gp */ + sw x4, 4*4(sp) /* tp */ + sw x5, 5*4(sp) /* t0 */ + sw x6, 6*4(sp) /* t1 */ + sw x7, 7*4(sp) /* t2 */ + sw x8, 8*4(sp) /* s0 */ + sw x9, 9*4(sp) /* s1 */ + sw x10, 10*4(sp) /* a0 */ + sw x11, 11*4(sp) /* a1 */ + sw x12, 12*4(sp) /* a2 */ + sw x13, 13*4(sp) /* a3 */ + sw x14, 14*4(sp) /* a4 */ + sw x15, 15*4(sp) /* a5 */ + sw x16, 16*4(sp) /* a6 */ + sw x17, 17*4(sp) /* a7 */ + sw x18, 18*4(sp) /* s2 */ + sw x19, 19*4(sp) /* s3 */ + sw x20, 20*4(sp) /* s4 */ + sw x21, 21*4(sp) /* s5 */ + sw x22, 22*4(sp) /* s6 */ + sw x23, 23*4(sp) /* s7 */ + sw x24, 24*4(sp) /* s8 */ + sw x25, 25*4(sp) /* s9 */ + sw x26, 26*4(sp) /* s10 */ + sw x27, 27*4(sp) /* s11 */ + sw x28, 28*4(sp) /* t3 */ + sw x29, 29*4(sp) /* t4 */ + sw x30, 30*4(sp) /* t5 */ + sw x31, 31*4(sp) /* t6 */ + + addi s0, sp, XCPTCONTEXT_SIZE + sw s0, 2*4(sp) /* original SP */ + + csrr s0, mstatus + sw s0, 32*4(sp) /* mstatus */ + + csrr s0, mepc + sw s0, 0(sp) /* exception PC */ + + csrr a0, mcause /* exception cause */ + mv a1, sp /* context = sp */ + +#if CONFIG_ARCH_INTERRUPTSTACK > 15 + lui sp, %hi(g_intstackbase) + addi sp, sp, %lo(g_intstackbase) +#endif + + /* Call interrupt/exception handler in C */ + + jal x1, esp32c3_dispatch_irq + + /* If context switch is needed, return a new sp */ + + mv sp, a0 + + lw s0, 0(sp) /* restore mepc */ + csrw mepc, s0 + + lw s0, 32*4(sp) /* restore mstatus */ + csrw mstatus, s0 + + + lw x4, 4*4(sp) /* tp */ + lw x5, 5*4(sp) /* t0 */ + lw x6, 6*4(sp) /* t1 */ + lw x7, 7*4(sp) /* t2 */ + lw x8, 8*4(sp) /* s0 */ + lw x9, 9*4(sp) /* s1 */ + lw x10, 10*4(sp) /* a0 */ + lw x11, 11*4(sp) /* a1 */ + lw x12, 12*4(sp) /* a2 */ + lw x13, 13*4(sp) /* a3 */ + lw x14, 14*4(sp) /* a4 */ + lw x15, 15*4(sp) /* a5 */ + lw x16, 16*4(sp) /* a6 */ + lw x17, 17*4(sp) /* a7 */ + lw x18, 18*4(sp) /* s2 */ + lw x19, 19*4(sp) /* s3 */ + lw x20, 20*4(sp) /* s4 */ + lw x21, 21*4(sp) /* s5 */ + lw x22, 22*4(sp) /* s6 */ + lw x23, 23*4(sp) /* s7 */ + lw x24, 24*4(sp) /* s8 */ + lw x25, 25*4(sp) /* s9 */ + lw x26, 26*4(sp) /* s10 */ + lw x27, 27*4(sp) /* s11 */ + lw x28, 28*4(sp) /* t3 */ + lw x29, 29*4(sp) /* t4 */ + lw x30, 30*4(sp) /* t5 */ + lw x31, 31*4(sp) /* t6 */ + + lw x1, 1*4(sp) /* ra */ + + lw sp, 2*4(sp) /* restore original sp */ + + /* Return from Machine Interrupt */ + + mret + diff --git a/arch/risc-v/src/esp32c3/esp32c3_irq.c b/arch/risc-v/src/esp32c3/esp32c3_irq.c new file mode 100644 index 0000000000..2ebc5e1b82 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_irq.c @@ -0,0 +1,372 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_irq.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include "riscv_internal.h" +#include "hardware/esp32c3_interrupt.h" + +#include "esp32c3.h" +#include "esp32c3_attr.h" + +#include "esp32c3_irq.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ESP32C3_DEFAULT_INT_THRESHOLD 1 + +/* No peripheral assigned to this CPU interrupt */ + +#define CPUINT_UNASSIGNED 0xff + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uint32_t *g_current_regs; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +uint8_t g_cpuint_map[ESP32C3_CPUINT_MAX]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + int periphid; + + /* Indicate that no peripheral interrupts are assigned to CPU interrupts */ + + memset(g_cpuint_map, CPUINT_UNASSIGNED, ESP32C3_CPUINT_MAX); + + /* Clear all peripheral interrupts from "bootloader" */ + + for (periphid = 0; periphid < ESP32C3_NPERIPHERALS; periphid++) + { + putreg32(0, DR_REG_INTERRUPT_BASE + periphid * 4); + } + + /* Set CPU interrupt threshold level */ + + putreg32(ESP32C3_DEFAULT_INT_THRESHOLD, INTERRUPT_CPU_INT_THRESH_REG); + + /* Attach the ECALL interrupt. */ + + irq_attach(ESP32C3_IRQ_ECALL_M, up_swint, NULL); + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + + /* And finally, enable interrupts */ + + up_irq_enable(); +#endif +} + +/**************************************************************************** + * Name: up_get_newintctx + * + * Description: + * Return initial mstatus when a task is created. + * + ****************************************************************************/ + +uint32_t up_get_newintctx(void) +{ + /* Set machine previous privilege mode to machine mode. + * Also set machine previous interrupt enable + */ + + return (MSTATUS_MPPM | MSTATUS_MPIE); +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the CPU interrupt specified by 'cpuint' + * + ****************************************************************************/ + +void up_enable_irq(int cpuint) +{ + irqstate_t irqstate; + + DEBUGASSERT(cpuint >= ESP32C3_CPUINT_MIN && cpuint <= ESP32C3_CPUINT_MAX); + + irqstate = enter_critical_section(); + setbits(1 << cpuint, INTERRUPT_CPU_INT_ENABLE_REG); + leave_critical_section(irqstate); +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the CPU interrupt specified by 'cpuint' + * + ****************************************************************************/ + +void up_disable_irq(int cpuint) +{ + irqstate_t irqstate; + + DEBUGASSERT(cpuint >= ESP32C3_CPUINT_MIN && cpuint <= ESP32C3_CPUINT_MAX); + + irqstate = enter_critical_section(); + resetbits(1 << cpuint, INTERRUPT_CPU_INT_ENABLE_REG); + leave_critical_section(irqstate); +} + +/**************************************************************************** + * Name: esp32c3_request_irq + * + * Description: + * Request IRQ and resource with given parameters. + * + * Input Parameters: + * periphid - Peripheral ID + * prio - Interrupt priority + * flags - Interrupt flags + * + * Returned Value: + * Allocated CPU interrupt on success, a negated error on failure. + * + ****************************************************************************/ + +int esp32c3_request_irq(uint8_t periphid, uint8_t prio, uint32_t flags) +{ + int ret; + uint32_t regval; + int cpuint; + irqstate_t irqstate; + + DEBUGASSERT(periphid < ESP32C3_NPERIPHERALS); + DEBUGASSERT((prio >= ESP32C3_INT_PRIO_MIN) && + (prio <= ESP32C3_INT_PRIO_MAX)); + + irqstate = enter_critical_section(); + + /* Skip over enabled interrupts. NOTE: bit 0 is reserved. */ + + regval = getreg32(INTERRUPT_CPU_INT_ENABLE_REG); + for (cpuint = 1; cpuint <= ESP32C3_CPUINT_MAX; cpuint++) + { + if (!(regval & (1 << cpuint))) + { + break; + } + } + + irqinfo("INFO: cpuint=%d\n", cpuint); + + if (cpuint <= ESP32C3_CPUINT_MAX) + { + DEBUGASSERT(g_cpuint_map[cpuint] == CPUINT_UNASSIGNED); + + /* We have a free CPU interrupt. We can continue with mapping the + * peripheral. + */ + + /* Save the CPU interrupt ID. We will return this value. */ + + ret = cpuint; + + /* Update our CPU interrupt to Peripheral map. */ + + g_cpuint_map[cpuint] = periphid; + + /* Set the interrupt priority. */ + + putreg32(prio, INTERRUPT_CPU_INT_PRI_0_REG + cpuint * 4); + + /* Set the interrupt type (Edge or Level). */ + + if (flags & ESP32C3_INT_EDGE) + { + setbits(1 << cpuint, INTERRUPT_CPU_INT_TYPE_REG); + } + else + { + resetbits(1 << cpuint, INTERRUPT_CPU_INT_TYPE_REG); + } + + /* Map the CPU interrupt ID to the peripheral. */ + + putreg32(cpuint, DR_REG_INTERRUPT_BASE + periphid * 4); + + /* Disable the CPU interrupt. */ + + resetbits(1 << cpuint, INTERRUPT_CPU_INT_ENABLE_REG); + } + else + { + /* We couldn't find a free CPU interrupt. */ + + ret = -ENOMEM; + } + + leave_critical_section(irqstate); + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_free_cpuint + * + * Description: + * Free CPU interrupt. + * + * Input Parameters: + * periphid - Peripheral ID. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_free_cpuint(uint8_t periphid) +{ + irqstate_t irqstate; + uint32_t cpuint; + + DEBUGASSERT(periphid < ESP32C3_NPERIPHERALS); + + irqstate = enter_critical_section(); + + /* Get the CPU interrupt ID mapped to this peripheral. */ + + cpuint = getreg32(DR_REG_INTERRUPT_BASE + periphid * 4) & 0x1f; + irqinfo("INFO: irq[%d]=%08lx\n", periphid, cpuint); + + if (cpuint) + { + /* Undo the allocation process: + * 1. Unmap the peripheral from the CPU interrupt ID. + * 2. Reset the interrupt type. + * 3. Reset the interrupt priority. + * 4. Clear the CPU interrupt. + */ + + DEBUGASSERT(g_cpuint_map[cpuint] != CPUINT_UNASSIGNED); + + g_cpuint_map[cpuint] = CPUINT_UNASSIGNED; + putreg32(0, DR_REG_INTERRUPT_BASE + periphid * 4); + resetbits(1 << cpuint, INTERRUPT_CPU_INT_TYPE_REG); + putreg32(0, INTERRUPT_CPU_INT_PRI_0_REG + cpuint * 4); + resetbits(1 << cpuint, INTERRUPT_CPU_INT_ENABLE_REG); + } + + leave_critical_section(irqstate); +} + +/**************************************************************************** + * Name: esp32c3_dispatch_irq + * + * Description: + * Process interrupt and its callback function. + * + * Input Parameters: + * mcause - RISC-V "mcause" register. + * regs - Saved registers reference. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +IRAM_ATTR uint32_t *esp32c3_dispatch_irq(uint32_t mcause, uint32_t *regs) +{ + int cpuint; + int irq; + + DEBUGASSERT(g_current_regs == NULL); + g_current_regs = regs; + + irqinfo("INFO: mcause=%08lx\n", mcause); + + /* If the board supports LEDs, turn on an LED now to indicate that we are + * processing an interrupt. + */ + + board_autoled_on(LED_INIRQ); + + if (MCAUSE_INTERRUPT & mcause) + { + cpuint = mcause & MCAUSE_INTERRUPT_MASK; + + DEBUGASSERT(cpuint <= ESP32C3_CPUINT_MAX); + + irqinfo("INFO: cpuint=%d\n", cpuint); + + /* Clear edge interrupts. */ + + putreg32(1 << cpuint, INTERRUPT_CPU_INT_CLEAR_REG); + + irq = g_cpuint_map[cpuint] + ESP32C3_IRQ_FIRSTPERIPH; + irq_dispatch(irq, regs); + + /* Toggle the bit back to zero. */ + + resetbits(1 << cpuint, INTERRUPT_CPU_INT_CLEAR_REG); + } + else + { + if (mcause == MCAUSE_ECALL_M) + { + irq_dispatch(ESP32C3_IRQ_ECALL_M, regs); + } + else + { + riscv_exception(mcause, regs); + } + } + + regs = (uint32_t *)g_current_regs; + g_current_regs = NULL; + + board_autoled_off(LED_INIRQ); + + return regs; +} diff --git a/arch/risc-v/src/esp32c3/esp32c3_irq.h b/arch/risc-v/src/esp32c3/esp32c3_irq.h new file mode 100644 index 0000000000..457e5f66c9 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_irq.h @@ -0,0 +1,101 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_IRQ_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ESP32C3_INT_LEVEL (0 << 0) +#define ESP32C3_INT_EDGE (1 << 0) + +#define ESP32C3_INT_PRIO_MIN 1 +#define ESP32C3_INT_PRIO_MAX 7 + +#define ESP32C3_INT_PRIO_DEF 1 + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void); + +/**************************************************************************** + * Name: esp32c3_request_irq + * + * Description: + * Request IRQ and resource with given parameters. + * + * Input Parameters: + * periphid - Peripheral ID + * prio - Interrupt priority + * flags - Interrupt flags + * + * Returned Value: + * Allocated CPU interrupt on success, a negated error on failure. + * + ****************************************************************************/ + +int esp32c3_request_irq(uint8_t periphid, uint8_t prio, uint32_t flags); + +/**************************************************************************** + * Name: esp32c3_free_cpuint + * + * Description: + * Free IRQ and resource. + * + * Input Parameters: + * periphid - Peripheral ID. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_free_cpuint(uint8_t periphid); + +/**************************************************************************** + * Name: esp32c3_dispatch_irq + * + * Description: + * Process interrupt and its callback function. + * + * Input Parameters: + * mcause - RISC-V "mcause" register value + * regs - Saved register value array + * + * Returned Value: + * None. + * + ****************************************************************************/ + +uint32_t *esp32c3_dispatch_irq(uint32_t mcause, uint32_t *regs); + +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_CPUINT_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_memorymap.h b/arch/risc-v/src/esp32c3/esp32c3_memorymap.h new file mode 100644 index 0000000000..296345f5b8 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_memorymap.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef _ARCH_RISCV_SRC_ESP32C3_ESP32C3_MEMORYMAP_H +#define _ARCH_RISCV_SRC_ESP32C3_ESP32C3_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Idle thread stack starts from _ebss */ + +#ifndef __ASSEMBLY__ +#define ESP32C3_IDLESTACK_BASE (uint32_t)&g_idlestack +#else +#define ESP32C3_IDLESTACK_BASE g_idlestack +#endif + +#define ESP32C3_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3) +#define ESP32C3_IDLESTACK_TOP (ESP32C3_IDLESTACK_BASE + ESP32C3_IDLESTACK_SIZE) + +#endif /* _ARCH_RISCV_SRC_ESP32C3_ESP32C3_MEMORYMAP_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_rom.h b/arch/risc-v/src/esp32c3/esp32c3_rom.h new file mode 100644 index 0000000000..e898b9408e --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_rom.h @@ -0,0 +1,36 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_rom.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_ROM_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_ROM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Name: ets_printf + ****************************************************************************/ + +int ets_printf(const char *fmt, ...); + +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_ROM_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_start.c b/arch/risc-v/src/esp32c3/esp32c3_start.c new file mode 100644 index 0000000000..413f93389d --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_start.c @@ -0,0 +1,88 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_start.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "chip.h" +#include "esp32c3.h" +#include "esp32c3_irq.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +# define showprogress(c) ets_printf("%c", c) +#else +# define showprogress(c) +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Address of the IDLE thread */ + +uint8_t g_idlestack[ESP32C3_IDLESTACK_SIZE] + __attribute__((aligned(16), section(".noinit"))); +uint32_t g_idle_topstack = ESP32C3_IDLESTACK_TOP; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: __esp32c3_start + ****************************************************************************/ + +void __esp32c3_start(void) +{ + uint32_t *dest; + + showprogress('A'); + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = &_sbss; dest < &_ebss; dest++) + { + *dest = 0; + } + + showprogress('B'); + + /* Call nx_start() */ + + nx_start(); + + /* Shouldn't get here */ + + for (; ; ); +} diff --git a/arch/risc-v/src/esp32c3/esp32c3_timerisr.c b/arch/risc-v/src/esp32c3/esp32c3_timerisr.c new file mode 100644 index 0000000000..2feb1b4b49 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_timerisr.c @@ -0,0 +1,128 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_timerisr.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "esp32c3.h" +#include "esp32c3_irq.h" +#include "hardware/esp32c3_systimer.h" +#include "hardware/esp32c3_system.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ESP32C3_SYSTIMER_TICKS_PER_SEC (16 * 1000 * 1000) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: systimer_isr + ****************************************************************************/ + +static int systimer_isr(int irq, FAR void *context, FAR void *arg) +{ + setbits(SYS_TIMER_TARGET0_INT_CLR, SYS_TIMER_SYSTIMER_INT_CLR_REG); + + /* Process timer interrupt */ + + nxsched_process_timer(); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + uint32_t regval; + int cpuint; + + /* Enable timer clock */ + + setbits(SYSTEM_SYSTIMER_CLK_EN, SYSTEM_PERIP_CLK_EN0_REG); + resetbits(SYSTEM_SYSTIMER_RST, SYSTEM_PERIP_RST_EN0_REG); + + setbits(SYS_TIMER_CLK_EN, SYS_TIMER_SYSTIMER_CONF_REG); + + /* Configure alarm0 counter1 */ + + regval = SYS_TIMER_TARGET0_PERIOD_MODE | + (1 << SYS_TIMER_TARGET0_TIMER_UNIT_SEL_S) | + ((ESP32C3_SYSTIMER_TICKS_PER_SEC / CLOCKS_PER_SEC) << + SYS_TIMER_TARGET0_PERIOD_S); + putreg32(regval, SYS_TIMER_SYSTIMER_TARGET0_CONF_REG); + + putreg32(SYS_TIMER_TIMER_COMP0_LOAD, SYS_TIMER_SYSTIMER_COMP0_LOAD_REG); + + /* Stall timer when stall CPU, specially when using JTAG to debug */ + + setbits(SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN, SYS_TIMER_SYSTIMER_CONF_REG); + + /* Enable interrupt */ + + setbits(SYS_TIMER_TARGET0_INT_CLR, SYS_TIMER_SYSTIMER_INT_CLR_REG); + setbits(SYS_TIMER_TARGET0_INT_ENA, SYS_TIMER_SYSTIMER_INT_ENA_REG); + + regval = SYS_TIMER_TARGET0_WORK_EN; + setbits(regval, SYS_TIMER_SYSTIMER_CONF_REG); + + /* Start alarm0 counter1 */ + + regval = SYS_TIMER_TIMER_UNIT1_WORK_EN; + setbits(regval, SYS_TIMER_SYSTIMER_CONF_REG); + + cpuint = esp32c3_request_irq(ESP32C3_PERIPH_SYSTIMER_T0, + ESP32C3_INT_PRIO_DEF, + ESP32C3_INT_LEVEL); + + /* Attach the timer interrupt. */ + + irq_attach(ESP32C3_IRQ_SYSTIMER_T0, (xcpt_t)systimer_isr, NULL); + + /* Enable the allocated CPU interrupt. */ + + up_enable_irq(cpuint); +} diff --git a/arch/risc-v/src/esp32c3/esp32c3_vectors.S b/arch/risc-v/src/esp32c3/esp32c3_vectors.S new file mode 100644 index 0000000000..6256a9fab5 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_vectors.S @@ -0,0 +1,79 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_vectors.S + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "chip.h" + +/**************************************************************************** + * Public Symbols + ****************************************************************************/ + + .global _vector_table + +/**************************************************************************** + * Section: .exception_vectors.text + ****************************************************************************/ + + .section .exception_vectors.text + +/**************************************************************************** + * Name: _vector_table + ****************************************************************************/ + + .balign 0x100 + .type _vector_table, @function + +_vector_table: + .option push + .option norvc + + /* exception handler, entry 0 */ + + j _exception_handler + + /* 29 identical entries, all pointing to the interrupt handler */ + + .rept (29) + j _interrupt_handler + .endr + + /* Call panic handler for ESP32C3_CPU_INT_T1_WDT interrupt (soc-level panic)*/ + + j _panic_handler + + /* Call panic handler for ESP32C3_CPU_INT_CACHEERR interrupt (soc-level panic)*/ + + j _panic_handler + +/**************************************************************************** + * Name: _panic_handler + ****************************************************************************/ + + .type _panic_handler, @function + +_panic_handler: + j _panic_handler diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_interrupt.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_interrupt.h new file mode 100644 index 0000000000..74daa4c553 --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_interrupt.h @@ -0,0 +1,962 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/esp32c3_system.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_INTERRUPT_H +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_INTERRUPT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define INTERRUPT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x000) + +/* INTERRUPT_MAC_INTR_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_MAC_INTR_MAP 0x0000001f +#define INTERRUPT_MAC_INTR_MAP_M ((INTERRUPT_MAC_INTR_MAP_V) << (INTERRUPT_MAC_INTR_MAP_S)) +#define INTERRUPT_MAC_INTR_MAP_V 0x1f +#define INTERRUPT_MAC_INTR_MAP_S 0 + +#define INTERRUPT_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x004) + +/* INTERRUPT_MAC_NMI_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_MAC_NMI_MAP 0x0000001f +#define INTERRUPT_MAC_NMI_MAP_M ((INTERRUPT_MAC_NMI_MAP_V) << (INTERRUPT_MAC_NMI_MAP_S)) +#define INTERRUPT_MAC_NMI_MAP_V 0x1f +#define INTERRUPT_MAC_NMI_MAP_S 0 + +#define INTERRUPT_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x008) + +/* INTERRUPT_PWR_INTR_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_PWR_INTR_MAP 0x0000001f +#define INTERRUPT_PWR_INTR_MAP_M ((INTERRUPT_PWR_INTR_MAP_V) << (INTERRUPT_PWR_INTR_MAP_S)) +#define INTERRUPT_PWR_INTR_MAP_V 0x1f +#define INTERRUPT_PWR_INTR_MAP_S 0 + +#define INTERRUPT_BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x00c) + +/* INTERRUPT_BB_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_BB_INT_MAP 0x0000001f +#define INTERRUPT_BB_INT_MAP_M ((INTERRUPT_BB_INT_MAP_V) << (INTERRUPT_BB_INT_MAP_S)) +#define INTERRUPT_BB_INT_MAP_V 0x1f +#define INTERRUPT_BB_INT_MAP_S 0 + +#define INTERRUPT_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x010) + +/* INTERRUPT_BT_MAC_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_BT_MAC_INT_MAP 0x0000001f +#define INTERRUPT_BT_MAC_INT_MAP_M ((INTERRUPT_BT_MAC_INT_MAP_V) << (INTERRUPT_BT_MAC_INT_MAP_S)) +#define INTERRUPT_BT_MAC_INT_MAP_V 0x1f +#define INTERRUPT_BT_MAC_INT_MAP_S 0 + +#define INTERRUPT_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x014) + +/* INTERRUPT_BT_BB_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_BT_BB_INT_MAP 0x0000001f +#define INTERRUPT_BT_BB_INT_MAP_M ((INTERRUPT_BT_BB_INT_MAP_V) << (INTERRUPT_BT_BB_INT_MAP_S)) +#define INTERRUPT_BT_BB_INT_MAP_V 0x1f +#define INTERRUPT_BT_BB_INT_MAP_S 0 + +#define INTERRUPT_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x018) + +/* INTERRUPT_BT_BB_NMI_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_BT_BB_NMI_MAP 0x0000001f +#define INTERRUPT_BT_BB_NMI_MAP_M ((INTERRUPT_BT_BB_NMI_MAP_V) << (INTERRUPT_BT_BB_NMI_MAP_S)) +#define INTERRUPT_BT_BB_NMI_MAP_V 0x1f +#define INTERRUPT_BT_BB_NMI_MAP_S 0 + +#define INTERRUPT_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_BASE + 0x01c) + +/* INTERRUPT_RWBT_IRQ_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_RWBT_IRQ_MAP 0x0000001f +#define INTERRUPT_RWBT_IRQ_MAP_M ((INTERRUPT_RWBT_IRQ_MAP_V) << (INTERRUPT_RWBT_IRQ_MAP_S)) +#define INTERRUPT_RWBT_IRQ_MAP_V 0x1f +#define INTERRUPT_RWBT_IRQ_MAP_S 0 + +#define INTERRUPT_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_BASE + 0x020) + +/* INTERRUPT_RWBLE_IRQ_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_RWBLE_IRQ_MAP 0x0000001f +#define INTERRUPT_RWBLE_IRQ_MAP_M ((INTERRUPT_RWBLE_IRQ_MAP_V) << (INTERRUPT_RWBLE_IRQ_MAP_S)) +#define INTERRUPT_RWBLE_IRQ_MAP_V 0x1f +#define INTERRUPT_RWBLE_IRQ_MAP_S 0 + +#define INTERRUPT_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x024) + +/* INTERRUPT_RWBT_NMI_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_RWBT_NMI_MAP 0x0000001f +#define INTERRUPT_RWBT_NMI_MAP_M ((INTERRUPT_RWBT_NMI_MAP_V) << (INTERRUPT_RWBT_NMI_MAP_S)) +#define INTERRUPT_RWBT_NMI_MAP_V 0x1f +#define INTERRUPT_RWBT_NMI_MAP_S 0 + +#define INTERRUPT_RWBLE_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x028) + +/* INTERRUPT_RWBLE_NMI_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_RWBLE_NMI_MAP 0x0000001f +#define INTERRUPT_RWBLE_NMI_MAP_M ((INTERRUPT_RWBLE_NMI_MAP_V) << (INTERRUPT_RWBLE_NMI_MAP_S)) +#define INTERRUPT_RWBLE_NMI_MAP_V 0x1f +#define INTERRUPT_RWBLE_NMI_MAP_S 0 + +#define INTERRUPT_I2C_MST_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x02c) + +/* INTERRUPT_I2C_MST_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_I2C_MST_INT_MAP 0x0000001f +#define INTERRUPT_I2C_MST_INT_MAP_M ((INTERRUPT_I2C_MST_INT_MAP_V) << (INTERRUPT_I2C_MST_INT_MAP_S)) +#define INTERRUPT_I2C_MST_INT_MAP_V 0x1f +#define INTERRUPT_I2C_MST_INT_MAP_S 0 + +#define INTERRUPT_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x030) + +/* INTERRUPT_SLC0_INTR_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_SLC0_INTR_MAP 0x0000001f +#define INTERRUPT_SLC0_INTR_MAP_M ((INTERRUPT_SLC0_INTR_MAP_V) << (INTERRUPT_SLC0_INTR_MAP_S)) +#define INTERRUPT_SLC0_INTR_MAP_V 0x1f +#define INTERRUPT_SLC0_INTR_MAP_S 0 + +#define INTERRUPT_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x034) + +/* INTERRUPT_SLC1_INTR_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_SLC1_INTR_MAP 0x0000001f +#define INTERRUPT_SLC1_INTR_MAP_M ((INTERRUPT_SLC1_INTR_MAP_V) << (INTERRUPT_SLC1_INTR_MAP_S)) +#define INTERRUPT_SLC1_INTR_MAP_V 0x1f +#define INTERRUPT_SLC1_INTR_MAP_S 0 + +#define INTERRUPT_APB_CTRL_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x038) + +/* INTERRUPT_APB_CTRL_INTR_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_APB_CTRL_INTR_MAP 0x0000001f +#define INTERRUPT_APB_CTRL_INTR_MAP_M ((INTERRUPT_APB_CTRL_INTR_MAP_V) << (INTERRUPT_APB_CTRL_INTR_MAP_S)) +#define INTERRUPT_APB_CTRL_INTR_MAP_V 0x1f +#define INTERRUPT_APB_CTRL_INTR_MAP_S 0 + +#define INTERRUPT_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x03c) + +/* INTERRUPT_UHCI0_INTR_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_UHCI0_INTR_MAP 0x0000001f +#define INTERRUPT_UHCI0_INTR_MAP_M ((INTERRUPT_UHCI0_INTR_MAP_V) << (INTERRUPT_UHCI0_INTR_MAP_S)) +#define INTERRUPT_UHCI0_INTR_MAP_V 0x1f +#define INTERRUPT_UHCI0_INTR_MAP_S 0 + +#define INTERRUPT_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_BASE + 0x040) + +/* INTERRUPT_GPIO_INTERRUPT_PRO_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_GPIO_INTERRUPT_PRO_MAP 0x0000001f +#define INTERRUPT_GPIO_INTERRUPT_PRO_MAP_M ((INTERRUPT_GPIO_INTERRUPT_PRO_MAP_V) << (INTERRUPT_GPIO_INTERRUPT_PRO_MAP_S)) +#define INTERRUPT_GPIO_INTERRUPT_PRO_MAP_V 0x1f +#define INTERRUPT_GPIO_INTERRUPT_PRO_MAP_S 0 + +#define INTERRUPT_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x044) + +/* INTERRUPT_GPIO_INTERRUPT_PRO_NMI_MAP : R/W [4:0] 5'd0 ; */ + +#define INTERRUPT_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001f +#define INTERRUPT_GPIO_INTERRUPT_PRO_NMI_MAP_M ((INTERRUPT_GPIO_INTERRUPT_PRO_NMI_MAP_V) << (INTERRUPT_GPIO_INTERRUPT_PRO_NMI_MAP_S)) +#define INTERRUPT_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1f +#define INTERRUPT_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 + +#define INTERRUPT_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x048) + +/* INTERRUPT_SPI_INTR_1_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_SPI_INTR_1_MAP 0x0000001f +#define INTERRUPT_SPI_INTR_1_MAP_M ((INTERRUPT_SPI_INTR_1_MAP_V) << (INTERRUPT_SPI_INTR_1_MAP_S)) +#define INTERRUPT_SPI_INTR_1_MAP_V 0x1f +#define INTERRUPT_SPI_INTR_1_MAP_S 0 + +#define INTERRUPT_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x04c) + +/* INTERRUPT_SPI_INTR_2_MAP : R/W [4:0] : 5'd0 ; */ +#define INTERRUPT_SPI_INTR_2_MAP 0x0000001f +#define INTERRUPT_SPI_INTR_2_MAP_M ((INTERRUPT_SPI_INTR_2_MAP_V) << (INTERRUPT_SPI_INTR_2_MAP_S)) +#define INTERRUPT_SPI_INTR_2_MAP_V 0x1f +#define INTERRUPT_SPI_INTR_2_MAP_S 0 + +#define INTERRUPT_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x050) + +/* INTERRUPT_I2S1_INT_MAP : R/W [4:0] : 5'd0 ; */ +#define INTERRUPT_I2S1_INT_MAP 0x0000001f +#define INTERRUPT_I2S1_INT_MAP_M ((INTERRUPT_I2S1_INT_MAP_V) << (INTERRUPT_I2S1_INT_MAP_S)) +#define INTERRUPT_I2S1_INT_MAP_V 0x1f +#define INTERRUPT_I2S1_INT_MAP_S 0 + +#define INTERRUPT_UART_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x054) + +/* INTERRUPT_UART_INTR_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_UART_INTR_MAP 0x0000001f +#define INTERRUPT_UART_INTR_MAP_M ((INTERRUPT_UART_INTR_MAP_V) << (INTERRUPT_UART_INTR_MAP_S)) +#define INTERRUPT_UART_INTR_MAP_V 0x1f +#define INTERRUPT_UART_INTR_MAP_S 0 + +#define INTERRUPT_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x058) + +/* INTERRUPT_UART1_INTR_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_UART1_INTR_MAP 0x0000001f +#define INTERRUPT_UART1_INTR_MAP_M ((INTERRUPT_UART1_INTR_MAP_V) << (INTERRUPT_UART1_INTR_MAP_S)) +#define INTERRUPT_UART1_INTR_MAP_V 0x1f +#define INTERRUPT_UART1_INTR_MAP_S 0 + +#define INTERRUPT_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x05c) + +/* INTERRUPT_LEDC_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_LEDC_INT_MAP 0x0000001f +#define INTERRUPT_LEDC_INT_MAP_M ((INTERRUPT_LEDC_INT_MAP_V) << (INTERRUPT_LEDC_INT_MAP_S)) +#define INTERRUPT_LEDC_INT_MAP_V 0x1f +#define INTERRUPT_LEDC_INT_MAP_S 0 + +#define INTERRUPT_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x060) + +/* INTERRUPT_EFUSE_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_EFUSE_INT_MAP 0x0000001f +#define INTERRUPT_EFUSE_INT_MAP_M ((INTERRUPT_EFUSE_INT_MAP_V) << (INTERRUPT_EFUSE_INT_MAP_S)) +#define INTERRUPT_EFUSE_INT_MAP_V 0x1f +#define INTERRUPT_EFUSE_INT_MAP_S 0 + +#define INTERRUPT_CAN_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x064) + +/* INTERRUPT_CAN_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_CAN_INT_MAP 0x0000001f +#define INTERRUPT_CAN_INT_MAP_M ((INTERRUPT_CAN_INT_MAP_V) << (INTERRUPT_CAN_INT_MAP_S)) +#define INTERRUPT_CAN_INT_MAP_V 0x1f +#define INTERRUPT_CAN_INT_MAP_S 0 + +#define INTERRUPT_USB_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x068) + +/* INTERRUPT_USB_INTR_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_USB_INTR_MAP 0x0000001f +#define INTERRUPT_USB_INTR_MAP_M ((INTERRUPT_USB_INTR_MAP_V) << (INTERRUPT_USB_INTR_MAP_S)) +#define INTERRUPT_USB_INTR_MAP_V 0x1f +#define INTERRUPT_USB_INTR_MAP_S 0 + +#define INTERRUPT_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x06c) + +/* INTERRUPT_RTC_CORE_INTR_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_RTC_CORE_INTR_MAP 0x0000001f +#define INTERRUPT_RTC_CORE_INTR_MAP_M ((INTERRUPT_RTC_CORE_INTR_MAP_V) << (INTERRUPT_RTC_CORE_INTR_MAP_S)) +#define INTERRUPT_RTC_CORE_INTR_MAP_V 0x1f +#define INTERRUPT_RTC_CORE_INTR_MAP_S 0 + +#define INTERRUPT_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x070) + +/* INTERRUPT_RMT_INTR_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_RMT_INTR_MAP 0x0000001f +#define INTERRUPT_RMT_INTR_MAP_M ((INTERRUPT_RMT_INTR_MAP_V) << (INTERRUPT_RMT_INTR_MAP_S)) +#define INTERRUPT_RMT_INTR_MAP_V 0x1f +#define INTERRUPT_RMT_INTR_MAP_S 0 + +#define INTERRUPT_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x074) + +/* INTERRUPT_I2C_EXT0_INTR_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_I2C_EXT0_INTR_MAP 0x0000001f +#define INTERRUPT_I2C_EXT0_INTR_MAP_M ((INTERRUPT_I2C_EXT0_INTR_MAP_V) << (INTERRUPT_I2C_EXT0_INTR_MAP_S)) +#define INTERRUPT_I2C_EXT0_INTR_MAP_V 0x1f +#define INTERRUPT_I2C_EXT0_INTR_MAP_S 0 + +#define INTERRUPT_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x078) + +/* INTERRUPT_TIMER_INT1_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_TIMER_INT1_MAP 0x0000001f +#define INTERRUPT_TIMER_INT1_MAP_M ((INTERRUPT_TIMER_INT1_MAP_V) << (INTERRUPT_TIMER_INT1_MAP_S)) +#define INTERRUPT_TIMER_INT1_MAP_V 0x1f +#define INTERRUPT_TIMER_INT1_MAP_S 0 + +#define INTERRUPT_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x07c) + +/* INTERRUPT_TIMER_INT2_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_TIMER_INT2_MAP 0x0000001f +#define INTERRUPT_TIMER_INT2_MAP_M ((INTERRUPT_TIMER_INT2_MAP_V) << (INTERRUPT_TIMER_INT2_MAP_S)) +#define INTERRUPT_TIMER_INT2_MAP_V 0x1f +#define INTERRUPT_TIMER_INT2_MAP_S 0 + +#define INTERRUPT_TG_T0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x080) + +/* INTERRUPT_TG_T0_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_TG_T0_INT_MAP 0x0000001f +#define INTERRUPT_TG_T0_INT_MAP_M ((INTERRUPT_TG_T0_INT_MAP_V) << (INTERRUPT_TG_T0_INT_MAP_S)) +#define INTERRUPT_TG_T0_INT_MAP_V 0x1f +#define INTERRUPT_TG_T0_INT_MAP_S 0 + +#define INTERRUPT_TG_WDT_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x084) + +/* INTERRUPT_TG_WDT_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_TG_WDT_INT_MAP 0x0000001f +#define INTERRUPT_TG_WDT_INT_MAP_M ((INTERRUPT_TG_WDT_INT_MAP_V) << (INTERRUPT_TG_WDT_INT_MAP_S)) +#define INTERRUPT_TG_WDT_INT_MAP_V 0x1f +#define INTERRUPT_TG_WDT_INT_MAP_S 0 + +#define INTERRUPT_TG1_T0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x088) + +/* INTERRUPT_TG1_T0_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_TG1_T0_INT_MAP 0x0000001f +#define INTERRUPT_TG1_T0_INT_MAP_M ((INTERRUPT_TG1_T0_INT_MAP_V) << (INTERRUPT_TG1_T0_INT_MAP_S)) +#define INTERRUPT_TG1_T0_INT_MAP_V 0x1f +#define INTERRUPT_TG1_T0_INT_MAP_S 0 + +#define INTERRUPT_TG1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x08c) + +/* INTERRUPT_TG1_WDT_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_TG1_WDT_INT_MAP 0x0000001f +#define INTERRUPT_TG1_WDT_INT_MAP_M ((INTERRUPT_TG1_WDT_INT_MAP_V) << (INTERRUPT_TG1_WDT_INT_MAP_S)) +#define INTERRUPT_TG1_WDT_INT_MAP_V 0x1f +#define INTERRUPT_TG1_WDT_INT_MAP_S 0 + +#define INTERRUPT_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x090) + +/* INTERRUPT_CACHE_IA_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_CACHE_IA_INT_MAP 0x0000001f +#define INTERRUPT_CACHE_IA_INT_MAP_M ((INTERRUPT_CACHE_IA_INT_MAP_V) << (INTERRUPT_CACHE_IA_INT_MAP_S)) +#define INTERRUPT_CACHE_IA_INT_MAP_V 0x1f +#define INTERRUPT_CACHE_IA_INT_MAP_S 0 + +#define INTERRUPT_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x094) + +/* INTERRUPT_SYSTIMER_TARGET0_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_SYSTIMER_TARGET0_INT_MAP 0x0000001f +#define INTERRUPT_SYSTIMER_TARGET0_INT_MAP_M ((INTERRUPT_SYSTIMER_TARGET0_INT_MAP_V) << (INTERRUPT_SYSTIMER_TARGET0_INT_MAP_S)) +#define INTERRUPT_SYSTIMER_TARGET0_INT_MAP_V 0x1f +#define INTERRUPT_SYSTIMER_TARGET0_INT_MAP_S 0 + +#define INTERRUPT_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x098) + +/* INTERRUPT_SYSTIMER_TARGET1_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_SYSTIMER_TARGET1_INT_MAP 0x0000001f +#define INTERRUPT_SYSTIMER_TARGET1_INT_MAP_M ((INTERRUPT_SYSTIMER_TARGET1_INT_MAP_V) << (INTERRUPT_SYSTIMER_TARGET1_INT_MAP_S)) +#define INTERRUPT_SYSTIMER_TARGET1_INT_MAP_V 0x1f +#define INTERRUPT_SYSTIMER_TARGET1_INT_MAP_S 0 + +#define INTERRUPT_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x09c) + +/* INTERRUPT_SYSTIMER_TARGET2_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_SYSTIMER_TARGET2_INT_MAP 0x0000001f +#define INTERRUPT_SYSTIMER_TARGET2_INT_MAP_M ((INTERRUPT_SYSTIMER_TARGET2_INT_MAP_V) << (INTERRUPT_SYSTIMER_TARGET2_INT_MAP_S)) +#define INTERRUPT_SYSTIMER_TARGET2_INT_MAP_V 0x1f +#define INTERRUPT_SYSTIMER_TARGET2_INT_MAP_S 0 + +#define INTERRUPT_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0a0) + +/* INTERRUPT_SPI_MEM_REJECT_INTR_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_SPI_MEM_REJECT_INTR_MAP 0x0000001f +#define INTERRUPT_SPI_MEM_REJECT_INTR_MAP_M ((INTERRUPT_SPI_MEM_REJECT_INTR_MAP_V) << (INTERRUPT_SPI_MEM_REJECT_INTR_MAP_S)) +#define INTERRUPT_SPI_MEM_REJECT_INTR_MAP_V 0x1f +#define INTERRUPT_SPI_MEM_REJECT_INTR_MAP_S 0 + +#define INTERRUPT_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0a4) + +/* INTERRUPT_ICACHE_PRELOAD_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_ICACHE_PRELOAD_INT_MAP 0x0000001f +#define INTERRUPT_ICACHE_PRELOAD_INT_MAP_M ((INTERRUPT_ICACHE_PRELOAD_INT_MAP_V) << (INTERRUPT_ICACHE_PRELOAD_INT_MAP_S)) +#define INTERRUPT_ICACHE_PRELOAD_INT_MAP_V 0x1f +#define INTERRUPT_ICACHE_PRELOAD_INT_MAP_S 0 + +#define INTERRUPT_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0a8) + +/* INTERRUPT_ICACHE_SYNC_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_ICACHE_SYNC_INT_MAP 0x0000001f +#define INTERRUPT_ICACHE_SYNC_INT_MAP_M ((INTERRUPT_ICACHE_SYNC_INT_MAP_V) << (INTERRUPT_ICACHE_SYNC_INT_MAP_S)) +#define INTERRUPT_ICACHE_SYNC_INT_MAP_V 0x1f +#define INTERRUPT_ICACHE_SYNC_INT_MAP_S 0 + +#define INTERRUPT_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0ac) + +/* INTERRUPT_APB_ADC_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_APB_ADC_INT_MAP 0x0000001f +#define INTERRUPT_APB_ADC_INT_MAP_M ((INTERRUPT_APB_ADC_INT_MAP_V) << (INTERRUPT_APB_ADC_INT_MAP_S)) +#define INTERRUPT_APB_ADC_INT_MAP_V 0x1f +#define INTERRUPT_APB_ADC_INT_MAP_S 0 + +#define INTERRUPT_DMA_CH0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0b0) + +/* INTERRUPT_DMA_CH0_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_DMA_CH0_INT_MAP 0x0000001f +#define INTERRUPT_DMA_CH0_INT_MAP_M ((INTERRUPT_DMA_CH0_INT_MAP_V) << (INTERRUPT_DMA_CH0_INT_MAP_S)) +#define INTERRUPT_DMA_CH0_INT_MAP_V 0x1f +#define INTERRUPT_DMA_CH0_INT_MAP_S 0 + +#define INTERRUPT_DMA_CH1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0b4) + +/* INTERRUPT_DMA_CH1_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_DMA_CH1_INT_MAP 0x0000001f +#define INTERRUPT_DMA_CH1_INT_MAP_M ((INTERRUPT_DMA_CH1_INT_MAP_V) << (INTERRUPT_DMA_CH1_INT_MAP_S)) +#define INTERRUPT_DMA_CH1_INT_MAP_V 0x1f +#define INTERRUPT_DMA_CH1_INT_MAP_S 0 + +#define INTERRUPT_DMA_CH2_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0b8) + +/* INTERRUPT_DMA_CH2_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_DMA_CH2_INT_MAP 0x0000001f +#define INTERRUPT_DMA_CH2_INT_MAP_M ((INTERRUPT_DMA_CH2_INT_MAP_V) << (INTERRUPT_DMA_CH2_INT_MAP_S)) +#define INTERRUPT_DMA_CH2_INT_MAP_V 0x1f +#define INTERRUPT_DMA_CH2_INT_MAP_S 0 + +#define INTERRUPT_RSA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0bc) + +/* INTERRUPT_RSA_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_RSA_INT_MAP 0x0000001f +#define INTERRUPT_RSA_INT_MAP_M ((INTERRUPT_RSA_INT_MAP_V) << (INTERRUPT_RSA_INT_MAP_S)) +#define INTERRUPT_RSA_INT_MAP_V 0x1f +#define INTERRUPT_RSA_INT_MAP_S 0 + +#define INTERRUPT_AES_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0c0) + +/* INTERRUPT_AES_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_AES_INT_MAP 0x0000001f +#define INTERRUPT_AES_INT_MAP_M ((INTERRUPT_AES_INT_MAP_V) << (INTERRUPT_AES_INT_MAP_S)) +#define INTERRUPT_AES_INT_MAP_V 0x1f +#define INTERRUPT_AES_INT_MAP_S 0 + +#define INTERRUPT_SHA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0c4) + +/* INTERRUPT_SHA_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_SHA_INT_MAP 0x0000001f +#define INTERRUPT_SHA_INT_MAP_M ((INTERRUPT_SHA_INT_MAP_V) << (INTERRUPT_SHA_INT_MAP_S)) +#define INTERRUPT_SHA_INT_MAP_V 0x1f +#define INTERRUPT_SHA_INT_MAP_S 0 + +#define INTERRUPT_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0c8) + +/* INTERRUPT_CPU_INTR_FROM_CPU_0_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_CPU_INTR_FROM_CPU_0_MAP 0x0000001f +#define INTERRUPT_CPU_INTR_FROM_CPU_0_MAP_M ((INTERRUPT_CPU_INTR_FROM_CPU_0_MAP_V) << (INTERRUPT_CPU_INTR_FROM_CPU_0_MAP_S)) +#define INTERRUPT_CPU_INTR_FROM_CPU_0_MAP_V 0x1f +#define INTERRUPT_CPU_INTR_FROM_CPU_0_MAP_S 0 + +#define INTERRUPT_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0cc) + +/* INTERRUPT_CPU_INTR_FROM_CPU_1_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_CPU_INTR_FROM_CPU_1_MAP 0x0000001f +#define INTERRUPT_CPU_INTR_FROM_CPU_1_MAP_M ((INTERRUPT_CPU_INTR_FROM_CPU_1_MAP_V) << (INTERRUPT_CPU_INTR_FROM_CPU_1_MAP_S)) +#define INTERRUPT_CPU_INTR_FROM_CPU_1_MAP_V 0x1f +#define INTERRUPT_CPU_INTR_FROM_CPU_1_MAP_S 0 + +#define INTERRUPT_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0d0) + +/* INTERRUPT_CPU_INTR_FROM_CPU_2_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_CPU_INTR_FROM_CPU_2_MAP 0x0000001f +#define INTERRUPT_CPU_INTR_FROM_CPU_2_MAP_M ((INTERRUPT_CPU_INTR_FROM_CPU_2_MAP_V) << (INTERRUPT_CPU_INTR_FROM_CPU_2_MAP_S)) +#define INTERRUPT_CPU_INTR_FROM_CPU_2_MAP_V 0x1f +#define INTERRUPT_CPU_INTR_FROM_CPU_2_MAP_S 0 + +#define INTERRUPT_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0d4) + +/* INTERRUPT_CPU_INTR_FROM_CPU_3_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_CPU_INTR_FROM_CPU_3_MAP 0x0000001f +#define INTERRUPT_CPU_INTR_FROM_CPU_3_MAP_M ((INTERRUPT_CPU_INTR_FROM_CPU_3_MAP_V) << (INTERRUPT_CPU_INTR_FROM_CPU_3_MAP_S)) +#define INTERRUPT_CPU_INTR_FROM_CPU_3_MAP_V 0x1f +#define INTERRUPT_CPU_INTR_FROM_CPU_3_MAP_S 0 + +#define INTERRUPT_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0d8) + +/* INTERRUPT_ASSIST_DEBUG_INTR_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_ASSIST_DEBUG_INTR_MAP 0x0000001f +#define INTERRUPT_ASSIST_DEBUG_INTR_MAP_M ((INTERRUPT_ASSIST_DEBUG_INTR_MAP_V) << (INTERRUPT_ASSIST_DEBUG_INTR_MAP_S)) +#define INTERRUPT_ASSIST_DEBUG_INTR_MAP_V 0x1f +#define INTERRUPT_ASSIST_DEBUG_INTR_MAP_S 0 + +#define INTERRUPT_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0dc) + +/* INTERRUPT_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001f +#define INTERRUPT_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1f +#define INTERRUPT_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0e0) + +/* INTERRUPT_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001f +#define INTERRUPT_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1f +#define INTERRUPT_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0e4) + +/* INTERRUPT_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001f +#define INTERRUPT_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1f +#define INTERRUPT_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0e8) + +/* INTERRUPT_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001f +#define INTERRUPT_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1f +#define INTERRUPT_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0ec) + +/* INTERRUPT_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : + * R/W [4:0] : 5'd0 + */ + +#define INTERRUPT_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001f +#define INTERRUPT_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V) << (INTERRUPT_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S)) +#define INTERRUPT_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1f +#define INTERRUPT_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0 + +#define INTERRUPT_BACKUP_PMS_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0f0) + +/* INTERRUPT_BACKUP_PMS_VIOLATE_INTR_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_BACKUP_PMS_VIOLATE_INTR_MAP 0x0000001f +#define INTERRUPT_BACKUP_PMS_VIOLATE_INTR_MAP_M ((INTERRUPT_BACKUP_PMS_VIOLATE_INTR_MAP_V) << (INTERRUPT_BACKUP_PMS_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_BACKUP_PMS_VIOLATE_INTR_MAP_V 0x1f +#define INTERRUPT_BACKUP_PMS_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0f4) + +/* INTERRUPT_CACHE_CORE0_ACS_INT_MAP : R/W [4:0] : 5'd0 ; */ + +#define INTERRUPT_CACHE_CORE0_ACS_INT_MAP 0x0000001f +#define INTERRUPT_CACHE_CORE0_ACS_INT_MAP_M ((INTERRUPT_CACHE_CORE0_ACS_INT_MAP_V) << (INTERRUPT_CACHE_CORE0_ACS_INT_MAP_S)) +#define INTERRUPT_CACHE_CORE0_ACS_INT_MAP_V 0x1f +#define INTERRUPT_CACHE_CORE0_ACS_INT_MAP_S 0 + +#define INTERRUPT_INTR_STATUS_0_REG (DR_REG_INTERRUPT_BASE + 0x0f8) + +/* INTERRUPT_INTR_STATUS_0 : RO [31:0] : 32'h0 ; */ + +#define INTERRUPT_INTR_STATUS_0 0xffffffff +#define INTERRUPT_INTR_STATUS_0_M ((INTERRUPT_INTR_STATUS_0_V) << (INTERRUPT_INTR_STATUS_0_S)) +#define INTERRUPT_INTR_STATUS_0_V 0xffffffff +#define INTERRUPT_INTR_STATUS_0_S 0 + +#define INTERRUPT_INTR_STATUS_1_REG (DR_REG_INTERRUPT_BASE + 0x0fc) + +/* INTERRUPT_INTR_STATUS_1 : RO [31:0] : 32'h0 ; */ + +#define INTERRUPT_INTR_STATUS_1 0xffffffff +#define INTERRUPT_INTR_STATUS_1_M ((INTERRUPT_INTR_STATUS_1_V) << (INTERRUPT_INTR_STATUS_1_S)) +#define INTERRUPT_INTR_STATUS_1_V 0xffffffff +#define INTERRUPT_INTR_STATUS_1_S 0 + +#define INTERRUPT_CLOCK_GATE_REG (DR_REG_INTERRUPT_BASE + 0x100) + +/* INTERRUPT_CLK_EN : R/W [0] : 1'b1 ; */ + +#define INTERRUPT_CLK_EN (BIT(0)) +#define INTERRUPT_CLK_EN_M (BIT(0)) +#define INTERRUPT_CLK_EN_V 0x1 +#define INTERRUPT_CLK_EN_S 0 + +#define INTERRUPT_CPU_INT_ENABLE_REG (DR_REG_INTERRUPT_BASE + 0x104) + +/* INTERRUPT_CPU_INT_ENABLE : R/W [31:0] : 32'b0 ; */ + +#define INTERRUPT_CPU_INT_ENABLE 0xffffffff +#define INTERRUPT_CPU_INT_ENABLE_M ((INTERRUPT_CPU_INT_ENABLE_V) << (INTERRUPT_CPU_INT_ENABLE_S)) +#define INTERRUPT_CPU_INT_ENABLE_V 0xffffffff +#define INTERRUPT_CPU_INT_ENABLE_S 0 + +#define INTERRUPT_CPU_INT_TYPE_REG (DR_REG_INTERRUPT_BASE + 0x108) + +/* INTERRUPT_CPU_INT_TYPE : R/W [31:0] : 32'b0 ; */ + +#define INTERRUPT_CPU_INT_TYPE 0xffffffff +#define INTERRUPT_CPU_INT_TYPE_M ((INTERRUPT_CPU_INT_TYPE_V) << (INTERRUPT_CPU_INT_TYPE_S)) +#define INTERRUPT_CPU_INT_TYPE_V 0xffffffff +#define INTERRUPT_CPU_INT_TYPE_S 0 + +#define INTERRUPT_CPU_INT_CLEAR_REG (DR_REG_INTERRUPT_BASE + 0x10c) + +/* INTERRUPT_CPU_INT_CLEAR : R/W [31:0] : 32'b0 ; */ + +#define INTERRUPT_CPU_INT_CLEAR 0xffffffff +#define INTERRUPT_CPU_INT_CLEAR_M ((INTERRUPT_CPU_INT_CLEAR_V) << (INTERRUPT_CPU_INT_CLEAR_S)) +#define INTERRUPT_CPU_INT_CLEAR_V 0xffffffff +#define INTERRUPT_CPU_INT_CLEAR_S 0 + +#define INTERRUPT_CPU_INT_EIP_STATUS_REG (DR_REG_INTERRUPT_BASE + 0x110) + +/* INTERRUPT_CPU_INT_EIP_STATUS : RO [31:0] : 32'b0 ; */ + +#define INTERRUPT_CPU_INT_EIP_STATUS 0xffffffff +#define INTERRUPT_CPU_INT_EIP_STATUS_M ((INTERRUPT_CPU_INT_EIP_STATUS_V) << (INTERRUPT_CPU_INT_EIP_STATUS_S)) +#define INTERRUPT_CPU_INT_EIP_STATUS_V 0xffffffff +#define INTERRUPT_CPU_INT_EIP_STATUS_S 0 + +#define INTERRUPT_CPU_INT_PRI_0_REG (DR_REG_INTERRUPT_BASE + 0x114) + +/* INTERRUPT_CPU_PRI_0_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_0_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_0_MAP_M ((INTERRUPT_CPU_PRI_0_MAP_V) << (INTERRUPT_CPU_PRI_0_MAP_S)) +#define INTERRUPT_CPU_PRI_0_MAP_V 0xf +#define INTERRUPT_CPU_PRI_0_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_1_REG (DR_REG_INTERRUPT_BASE + 0x118) + +/* INTERRUPT_CPU_PRI_1_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_1_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_1_MAP_M ((INTERRUPT_CPU_PRI_1_MAP_V) << (INTERRUPT_CPU_PRI_1_MAP_S)) +#define INTERRUPT_CPU_PRI_1_MAP_V 0xf +#define INTERRUPT_CPU_PRI_1_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_2_REG (DR_REG_INTERRUPT_BASE + 0x11c) + +/* INTERRUPT_CPU_PRI_2_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_2_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_2_MAP_M ((INTERRUPT_CPU_PRI_2_MAP_V) << (INTERRUPT_CPU_PRI_2_MAP_S)) +#define INTERRUPT_CPU_PRI_2_MAP_V 0xf +#define INTERRUPT_CPU_PRI_2_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_3_REG (DR_REG_INTERRUPT_BASE + 0x120) + +/* INTERRUPT_CPU_PRI_3_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_3_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_3_MAP_M ((INTERRUPT_CPU_PRI_3_MAP_V) << (INTERRUPT_CPU_PRI_3_MAP_S)) +#define INTERRUPT_CPU_PRI_3_MAP_V 0xf +#define INTERRUPT_CPU_PRI_3_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_4_REG (DR_REG_INTERRUPT_BASE + 0x124) + +/* INTERRUPT_CPU_PRI_4_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_4_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_4_MAP_M ((INTERRUPT_CPU_PRI_4_MAP_V) << (INTERRUPT_CPU_PRI_4_MAP_S)) +#define INTERRUPT_CPU_PRI_4_MAP_V 0xf +#define INTERRUPT_CPU_PRI_4_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_5_REG (DR_REG_INTERRUPT_BASE + 0x128) + +/* INTERRUPT_CPU_PRI_5_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_5_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_5_MAP_M ((INTERRUPT_CPU_PRI_5_MAP_V) << (INTERRUPT_CPU_PRI_5_MAP_S)) +#define INTERRUPT_CPU_PRI_5_MAP_V 0xf +#define INTERRUPT_CPU_PRI_5_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_6_REG (DR_REG_INTERRUPT_BASE + 0x12c) + +/* INTERRUPT_CPU_PRI_6_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_6_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_6_MAP_M ((INTERRUPT_CPU_PRI_6_MAP_V) << (INTERRUPT_CPU_PRI_6_MAP_S)) +#define INTERRUPT_CPU_PRI_6_MAP_V 0xf +#define INTERRUPT_CPU_PRI_6_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_7_REG (DR_REG_INTERRUPT_BASE + 0x130) + +/* INTERRUPT_CPU_PRI_7_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_7_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_7_MAP_M ((INTERRUPT_CPU_PRI_7_MAP_V) << (INTERRUPT_CPU_PRI_7_MAP_S)) +#define INTERRUPT_CPU_PRI_7_MAP_V 0xf +#define INTERRUPT_CPU_PRI_7_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_8_REG (DR_REG_INTERRUPT_BASE + 0x134) + +/* INTERRUPT_CPU_PRI_8_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_8_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_8_MAP_M ((INTERRUPT_CPU_PRI_8_MAP_V) << (INTERRUPT_CPU_PRI_8_MAP_S)) +#define INTERRUPT_CPU_PRI_8_MAP_V 0xf +#define INTERRUPT_CPU_PRI_8_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_9_REG (DR_REG_INTERRUPT_BASE + 0x138) + +/* INTERRUPT_CPU_PRI_9_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_9_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_9_MAP_M ((INTERRUPT_CPU_PRI_9_MAP_V) << (INTERRUPT_CPU_PRI_9_MAP_S)) +#define INTERRUPT_CPU_PRI_9_MAP_V 0xf +#define INTERRUPT_CPU_PRI_9_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_10_REG (DR_REG_INTERRUPT_BASE + 0x13c) + +/* INTERRUPT_CPU_PRI_10_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_10_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_10_MAP_M ((INTERRUPT_CPU_PRI_10_MAP_V) << (INTERRUPT_CPU_PRI_10_MAP_S)) +#define INTERRUPT_CPU_PRI_10_MAP_V 0xf +#define INTERRUPT_CPU_PRI_10_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_11_REG (DR_REG_INTERRUPT_BASE + 0x140) + +/* INTERRUPT_CPU_PRI_11_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_11_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_11_MAP_M ((INTERRUPT_CPU_PRI_11_MAP_V) << (INTERRUPT_CPU_PRI_11_MAP_S)) +#define INTERRUPT_CPU_PRI_11_MAP_V 0xf +#define INTERRUPT_CPU_PRI_11_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_12_REG (DR_REG_INTERRUPT_BASE + 0x144) + +/* INTERRUPT_CPU_PRI_12_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_12_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_12_MAP_M ((INTERRUPT_CPU_PRI_12_MAP_V) << (INTERRUPT_CPU_PRI_12_MAP_S)) +#define INTERRUPT_CPU_PRI_12_MAP_V 0xf +#define INTERRUPT_CPU_PRI_12_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_13_REG (DR_REG_INTERRUPT_BASE + 0x148) + +/* INTERRUPT_CPU_PRI_13_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_13_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_13_MAP_M ((INTERRUPT_CPU_PRI_13_MAP_V) << (INTERRUPT_CPU_PRI_13_MAP_S)) +#define INTERRUPT_CPU_PRI_13_MAP_V 0xf +#define INTERRUPT_CPU_PRI_13_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_14_REG (DR_REG_INTERRUPT_BASE + 0x14c) + +/* INTERRUPT_CPU_PRI_14_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_14_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_14_MAP_M ((INTERRUPT_CPU_PRI_14_MAP_V) << (INTERRUPT_CPU_PRI_14_MAP_S)) +#define INTERRUPT_CPU_PRI_14_MAP_V 0xf +#define INTERRUPT_CPU_PRI_14_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_15_REG (DR_REG_INTERRUPT_BASE + 0x150) + +/* INTERRUPT_CPU_PRI_15_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_15_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_15_MAP_M ((INTERRUPT_CPU_PRI_15_MAP_V) << (INTERRUPT_CPU_PRI_15_MAP_S)) +#define INTERRUPT_CPU_PRI_15_MAP_V 0xf +#define INTERRUPT_CPU_PRI_15_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_16_REG (DR_REG_INTERRUPT_BASE + 0x154) + +/* INTERRUPT_CPU_PRI_16_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_16_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_16_MAP_M ((INTERRUPT_CPU_PRI_16_MAP_V) << (INTERRUPT_CPU_PRI_16_MAP_S)) +#define INTERRUPT_CPU_PRI_16_MAP_V 0xf +#define INTERRUPT_CPU_PRI_16_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_17_REG (DR_REG_INTERRUPT_BASE + 0x158) + +/* INTERRUPT_CPU_PRI_17_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_17_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_17_MAP_M ((INTERRUPT_CPU_PRI_17_MAP_V) << (INTERRUPT_CPU_PRI_17_MAP_S)) +#define INTERRUPT_CPU_PRI_17_MAP_V 0xf +#define INTERRUPT_CPU_PRI_17_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_18_REG (DR_REG_INTERRUPT_BASE + 0x15c) + +/* INTERRUPT_CPU_PRI_18_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_18_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_18_MAP_M ((INTERRUPT_CPU_PRI_18_MAP_V) << (INTERRUPT_CPU_PRI_18_MAP_S)) +#define INTERRUPT_CPU_PRI_18_MAP_V 0xf +#define INTERRUPT_CPU_PRI_18_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_19_REG (DR_REG_INTERRUPT_BASE + 0x160) + +/* INTERRUPT_CPU_PRI_19_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_19_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_19_MAP_M ((INTERRUPT_CPU_PRI_19_MAP_V) << (INTERRUPT_CPU_PRI_19_MAP_S)) +#define INTERRUPT_CPU_PRI_19_MAP_V 0xf +#define INTERRUPT_CPU_PRI_19_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_20_REG (DR_REG_INTERRUPT_BASE + 0x164) + +/* INTERRUPT_CPU_PRI_20_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_20_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_20_MAP_M ((INTERRUPT_CPU_PRI_20_MAP_V) << (INTERRUPT_CPU_PRI_20_MAP_S)) +#define INTERRUPT_CPU_PRI_20_MAP_V 0xf +#define INTERRUPT_CPU_PRI_20_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_21_REG (DR_REG_INTERRUPT_BASE + 0x168) + +/* INTERRUPT_CPU_PRI_21_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_21_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_21_MAP_M ((INTERRUPT_CPU_PRI_21_MAP_V) << (INTERRUPT_CPU_PRI_21_MAP_S)) +#define INTERRUPT_CPU_PRI_21_MAP_V 0xf +#define INTERRUPT_CPU_PRI_21_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_22_REG (DR_REG_INTERRUPT_BASE + 0x16c) + +/* INTERRUPT_CPU_PRI_22_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_22_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_22_MAP_M ((INTERRUPT_CPU_PRI_22_MAP_V) << (INTERRUPT_CPU_PRI_22_MAP_S)) +#define INTERRUPT_CPU_PRI_22_MAP_V 0xf +#define INTERRUPT_CPU_PRI_22_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_23_REG (DR_REG_INTERRUPT_BASE + 0x170) + +/* INTERRUPT_CPU_PRI_23_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_23_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_23_MAP_M ((INTERRUPT_CPU_PRI_23_MAP_V) << (INTERRUPT_CPU_PRI_23_MAP_S)) +#define INTERRUPT_CPU_PRI_23_MAP_V 0xf +#define INTERRUPT_CPU_PRI_23_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_24_REG (DR_REG_INTERRUPT_BASE + 0x174) + +/* INTERRUPT_CPU_PRI_24_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_24_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_24_MAP_M ((INTERRUPT_CPU_PRI_24_MAP_V) << (INTERRUPT_CPU_PRI_24_MAP_S)) +#define INTERRUPT_CPU_PRI_24_MAP_V 0xf +#define INTERRUPT_CPU_PRI_24_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_25_REG (DR_REG_INTERRUPT_BASE + 0x178) + +/* INTERRUPT_CPU_PRI_25_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_25_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_25_MAP_M ((INTERRUPT_CPU_PRI_25_MAP_V) << (INTERRUPT_CPU_PRI_25_MAP_S)) +#define INTERRUPT_CPU_PRI_25_MAP_V 0xf +#define INTERRUPT_CPU_PRI_25_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_26_REG (DR_REG_INTERRUPT_BASE + 0x17c) + +/* INTERRUPT_CPU_PRI_26_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_26_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_26_MAP_M ((INTERRUPT_CPU_PRI_26_MAP_V) << (INTERRUPT_CPU_PRI_26_MAP_S)) +#define INTERRUPT_CPU_PRI_26_MAP_V 0xf +#define INTERRUPT_CPU_PRI_26_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_27_REG (DR_REG_INTERRUPT_BASE + 0x180) + +/* INTERRUPT_CPU_PRI_27_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_27_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_27_MAP_M ((INTERRUPT_CPU_PRI_27_MAP_V) << (INTERRUPT_CPU_PRI_27_MAP_S)) +#define INTERRUPT_CPU_PRI_27_MAP_V 0xf +#define INTERRUPT_CPU_PRI_27_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_28_REG (DR_REG_INTERRUPT_BASE + 0x184) + +/* INTERRUPT_CPU_PRI_28_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_28_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_28_MAP_M ((INTERRUPT_CPU_PRI_28_MAP_V) << (INTERRUPT_CPU_PRI_28_MAP_S)) +#define INTERRUPT_CPU_PRI_28_MAP_V 0xf +#define INTERRUPT_CPU_PRI_28_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_29_REG (DR_REG_INTERRUPT_BASE + 0x188) + +/* INTERRUPT_CPU_PRI_29_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_29_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_29_MAP_M ((INTERRUPT_CPU_PRI_29_MAP_V) << (INTERRUPT_CPU_PRI_29_MAP_S)) +#define INTERRUPT_CPU_PRI_29_MAP_V 0xf +#define INTERRUPT_CPU_PRI_29_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_30_REG (DR_REG_INTERRUPT_BASE + 0x18c) + +/* INTERRUPT_CPU_PRI_30_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_30_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_30_MAP_M ((INTERRUPT_CPU_PRI_30_MAP_V) << (INTERRUPT_CPU_PRI_30_MAP_S)) +#define INTERRUPT_CPU_PRI_30_MAP_V 0xf +#define INTERRUPT_CPU_PRI_30_MAP_S 0 + +#define INTERRUPT_CPU_INT_PRI_31_REG (DR_REG_INTERRUPT_BASE + 0x190) + +/* INTERRUPT_CPU_PRI_31_MAP : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_PRI_31_MAP 0x0000000f +#define INTERRUPT_CPU_PRI_31_MAP_M ((INTERRUPT_CPU_PRI_31_MAP_V) << (INTERRUPT_CPU_PRI_31_MAP_S)) +#define INTERRUPT_CPU_PRI_31_MAP_V 0xf +#define INTERRUPT_CPU_PRI_31_MAP_S 0 +#define INTC_INT_PRIO_REG(n) (INTERRUPT_CPU_INT_PRI_0_REG + (n)*4) + +#define INTERRUPT_CPU_INT_THRESH_REG (DR_REG_INTERRUPT_BASE + 0x194) + +/* INTERRUPT_CPU_INT_THRESH : R/W [3:0] : 4'b0 ; */ + +#define INTERRUPT_CPU_INT_THRESH 0x0000000f +#define INTERRUPT_CPU_INT_THRESH_M ((INTERRUPT_CPU_INT_THRESH_V) << (INTERRUPT_CPU_INT_THRESH_S)) +#define INTERRUPT_CPU_INT_THRESH_V 0xf +#define INTERRUPT_CPU_INT_THRESH_S 0 + +#define INTERRUPT_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_BASE + 0x7fc) + +/* INTERRUPT_INTERRUPT_DATE : R/W [27:0] : 28'h2007210 ; */ + +#define INTERRUPT_INTERRUPT_DATE 0x0fffffff +#define INTERRUPT_INTERRUPT_DATE_M ((INTERRUPT_INTERRUPT_DATE_V) << (INTERRUPT_INTERRUPT_DATE_S)) +#define INTERRUPT_INTERRUPT_DATE_V 0xfffffff +#define INTERRUPT_INTERRUPT_DATE_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_INTERRUPT_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_memorymap.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_memorymap.h new file mode 100644 index 0000000000..51a80589ae --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_memorymap.h @@ -0,0 +1,78 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/esp32c3_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_MEMORYMAP_H +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ESP32C3_SYSTEM_BASE 0x600c0000 +#define ESP32C3_SENSITIVE_BASE 0x600c1000 +#define ESP32C3_INTERRUPT_BASE 0x600c2000 +#define ESP32C3_DMA_COPY_BASE 0x600c3000 +#define ESP32C3_EXTMEM_BASE 0x600c4000 +#define ESP32C3_MMU_TABLE 0x600c5000 +#define ESP32C3_AES_BASE 0x6003a000 +#define ESP32C3_SHA_BASE 0x6003b000 +#define ESP32C3_RSA_BASE 0x6003c000 +#define ESP32C3_HMAC_BASE 0x6003e000 +#define ESP32C3_DIGITAL_SIGNATURE_BASE 0x6003d000 +#define ESP32C3_GDMA_BASE 0x6003f000 +#define ESP32C3_ASSIST_DEBUG_BASE 0x600ce000 +#define ESP32C3_DEDICATED_GPIO_BASE 0x600cf000 +#define ESP32C3_WORLD_CNTL_BASE 0x600d0000 +#define ESP32C3_DPORT_END 0x600d3ffc +#define ESP32C3_UART_BASE 0x60000000 +#define ESP32C3_SPI1_BASE 0x60002000 +#define ESP32C3_SPI0_BASE 0x60003000 +#define ESP32C3_GPIO_BASE 0x60004000 +#define ESP32C3_FE2_BASE 0x60005000 +#define ESP32C3_FE_BASE 0x60006000 +#define ESP32C3_RTCCNTL_BASE 0x60008000 +#define ESP32C3_IO_MUX_BASE 0x60009000 +#define ESP32C3_RTC_I2C_BASE 0x6000e000 +#define ESP32C3_UART1_BASE 0x60010000 +#define ESP32C3_I2C_EXT_BASE 0x60013000 +#define ESP32C3_UHCI0_BASE 0x60014000 +#define ESP32C3_RMT_BASE 0x60016000 +#define ESP32C3_LEDC_BASE 0x60019000 +#define ESP32C3_EFUSE_BASE 0x60008800 +#define ESP32C3_NRX_BASE 0x6001cc00 +#define ESP32C3_BB_BASE 0x6001d000 +#define ESP32C3_TIMERGROUP0_BASE 0x6001f000 +#define ESP32C3_TIMERGROUP1_BASE 0x60020000 +#define ESP32C3_SYS_TIMER_BASE 0x60023000 +#define ESP32C3_SPI2_BASE 0x60024000 +#define ESP32C3_SYSCON_BASE 0x60026000 +#define ESP32C3_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON */ +#define ESP32C3_TWAI_BASE 0x6002b000 +#define ESP32C3_I2S0_BASE 0x6002d000 +#define ESP32C3_APB_SARADC_BASE 0x60040000 +#define ESP32C3_AES_XTS_BASE 0x600cc000 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_MEMORYMAP_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h new file mode 100644 index 0000000000..8fe1f834bc --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h @@ -0,0 +1,257 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SOC_H +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SOC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define DR_REG_SYSTEM_BASE 0x600c0000 +#define DR_REG_SENSITIVE_BASE 0x600c1000 +#define DR_REG_INTERRUPT_BASE 0x600c2000 +#define DR_REG_DMA_COPY_BASE 0x600c3000 +#define DR_REG_EXTMEM_BASE 0x600c4000 +#define DR_REG_MMU_TABLE 0x600c5000 +#define DR_REG_AES_BASE 0x6003a000 +#define DR_REG_SHA_BASE 0x6003b000 +#define DR_REG_RSA_BASE 0x6003c000 +#define DR_REG_HMAC_BASE 0x6003e000 +#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 +#define DR_REG_GDMA_BASE 0x6003f000 +#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000 +#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000 +#define DR_REG_WORLD_CNTL_BASE 0x600d0000 +#define DR_REG_DPORT_END 0x600d3FFC +#define DR_REG_UART_BASE 0x60000000 +#define DR_REG_SPI1_BASE 0x60002000 +#define DR_REG_SPI0_BASE 0x60003000 +#define DR_REG_GPIO_BASE 0x60004000 +#define DR_REG_FE2_BASE 0x60005000 +#define DR_REG_FE_BASE 0x60006000 +#define DR_REG_RTCCNTL_BASE 0x60008000 +#define DR_REG_IO_MUX_BASE 0x60009000 +#define DR_REG_RTC_I2C_BASE 0x6000e000 +#define DR_REG_UART1_BASE 0x60010000 +#define DR_REG_I2C_EXT_BASE 0x60013000 +#define DR_REG_UHCI0_BASE 0x60014000 +#define DR_REG_RMT_BASE 0x60016000 +#define DR_REG_LEDC_BASE 0x60019000 +#define DR_REG_EFUSE_BASE 0x60008800 +#define DR_REG_NRX_BASE 0x6001CC00 +#define DR_REG_BB_BASE 0x6001D000 +#define DR_REG_TIMERGROUP0_BASE 0x6001F000 +#define DR_REG_TIMERGROUP1_BASE 0x60020000 +#define DR_REG_SYS_TIMER_BASE 0x60023000 +#define DR_REG_SPI2_BASE 0x60024000 +#define DR_REG_SYSCON_BASE 0x60026000 +#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON */ +#define DR_REG_TWAI_BASE 0x6002B000 +#define DR_REG_I2S0_BASE 0x6002D000 +#define DR_REG_APB_SARADC_BASE 0x60040000 +#define DR_REG_AES_XTS_BASE 0x600CC000 + +#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) +#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + \ + ( (i) > 1 ? 0xe000 : 0 ) ) +#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + \ + ( (i) > 1 ? 0xe000 : 0 ) ) +#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) +#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000) +#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) +#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) +#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000) + +/* Periheral Clock */ + +#define APB_CLK_FREQ_ROM (40 * 1000000) +#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM +#define UART_CLK_FREQ_ROM (40 * 1000000) +#define EFUSE_CLK_FREQ_ROM (20 * 1000000) +#define CPU_CLK_FREQ APB_CLK_FREQ +#define APB_CLK_FREQ (80 * 1000000) +#define REF_CLK_FREQ (1000000) +#define RTC_CLK_FREQ (20 * 1000000) +#define XTAL_CLK_FREQ (40 * 1000000) +#define UART_CLK_FREQ APB_CLK_FREQ +#define WDT_CLK_FREQ APB_CLK_FREQ +#define TIMER_CLK_FREQ (80000000 >> 4) /* 80MHz divided by 16 */ +#define SPI_CLK_DIV 4 +#define TICKS_PER_US_ROM 40 /* CPU is 80MHz */ +#define GPIO_MATRIX_DELAY_NS 0 + +/* Overall memory map */ + +#define SOC_DROM_LOW 0x3c000000 +#define SOC_DROM_HIGH 0x3c800000 +#define SOC_IROM_LOW 0x42000000 +#define SOC_IROM_HIGH 0x42800000 +#define SOC_IROM_MASK_LOW 0x40000000 +#define SOC_IROM_MASK_HIGH 0x40060000 +#define SOC_DROM_MASK_LOW 0x3ff00000 +#define SOC_DROM_MASK_HIGH 0x3ff20000 +#define SOC_IRAM_LOW 0x4037c000 +#define SOC_IRAM_HIGH 0x403e0000 +#define SOC_DRAM_LOW 0x3fc80000 +#define SOC_DRAM_HIGH 0x3fce0000 +#define SOC_RTC_IRAM_LOW 0x50000000 /* ESP32-C3 only has RTC fast memory */ +#define SOC_RTC_IRAM_HIGH 0x50002000 +#define SOC_RTC_DRAM_LOW 0x50000000 +#define SOC_RTC_DRAM_HIGH 0x50002000 +#define SOC_RTC_DATA_LOW 0x50000000 +#define SOC_RTC_DATA_HIGH 0x50002000 + +/* First and last words of the D/IRAM region, for both the DRAM address as + * well as the IRAM alias. + */ + +#define SOC_DIRAM_IRAM_LOW 0x40380000 +#define SOC_DIRAM_IRAM_HIGH 0x403e0000 +#define SOC_DIRAM_DRAM_LOW 0x3fc80000 +#define SOC_DIRAM_DRAM_HIGH 0x3fce0000 + +/* Region of memory accessible via DMA. See esp_ptr_dma_capable(). */ + +#define SOC_DMA_LOW 0x3fc88000 +#define SOC_DMA_HIGH 0x3fd00000 + +/* Region of RAM that is byte-accessible. See esp_ptr_byte_accessible(). */ + +#define SOC_BYTE_ACCESSIBLE_LOW 0x3fc88000 +#define SOC_BYTE_ACCESSIBLE_HIGH 0x3fd00000 + +/* Region of memory that is internal, as in on the same silicon die as the + * ESP32 CPU (excluding RTC data region, that's checked separately.) + * See esp_ptr_internal(). + */ + +#define SOC_MEM_INTERNAL_LOW 0x3fc80000 +#define SOC_MEM_INTERNAL_HIGH 0x3fce0000 +#define SOC_MEM_INTERNAL_LOW1 0x40370000 +#define SOC_MEM_INTERNAL_HIGH1 0x403e0000 +#define SOC_MEM_INTERNAL_LOW2 0x600fe000 +#define SOC_MEM_INTERNAL_HIGH2 0x60100000 + +/* Largest span of contiguous memory (DRAM or IRAM) in the address space */ + +#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) + +/* Region of address space that holds peripherals */ + +#define SOC_PERIPHERAL_LOW 0x60000000 +#define SOC_PERIPHERAL_HIGH 0x60100000 + +/* Debug region, not used by software */ + +#define SOC_DEBUG_LOW 0x20000000 +#define SOC_DEBUG_HIGH 0x28000000 + +/* Start (highest address) of ROM boot stack, only relevant during + * early boot + */ + +#define SOC_ROM_STACK_START 0x3fcebf10 + +/* Interrupt cpu using table */ + +/**************************************************************************** + *Intr num Level Type PRO CPU usage + * 0 1 extern level WMAC + * 1 1 extern level BT/BLE Host VHCI + * 2 1 extern level + * 3 1 extern level + * 4 1 extern level WBB + * 5 1 extern level BT/BLE Controller + * 6 1 timer RTOS Tick + * 7 1 software BT/BLE VHCI + * 8 1 extern level BT/BLE BB(RX/TX) + * 9 1 extern level + * 10 1 extern edge + * 11 3 profiling + * 12 1 extern level + * 13 1 extern level + * 14 7 nmi Reserved + * 15 3 timer RTOS Tick(L3) + * 16 5 timer + * 17 1 extern level + * 18 1 extern level + * 19 2 extern level + * 20 2 extern level + * 21 2 extern level + * 22 3 extern edge + * 23 3 extern level + * 24 4 extern level TG1_WDT + * 25 4 extern level CACHEERR + * 26 5 extern level + * 27 3 extern level Reserved + * 28 4 extern edge DPORT ACCESS + * 29 3 software Reserved + * 30 4 extern edge Reserved + * 31 5 extern level + ****************************************************************************/ + +/* CPU Interrupt number reserved, do not touch this. */ + +#define ETS_WMAC_INUM 1 +/* #define ETS_BT_HOST_INUM 1 */ +#define ETS_WBB_INUM 4 +#define ETS_SYSTICK_INUM 9 +#define ETS_TG0_T1_INUM 10 /* use edge interrupt */ +#define ETS_CPU_INTR0_INUM 12 /* used as freertos soft intr */ +#define ETS_FRC1_INUM 22 +#define ETS_T1_WDT_INUM 24 +#define ETS_CACHEERR_INUM 25 +#define ETS_DPORT_INUM 28 + +/* CPU Max valid interrupt number */ + +#define ETS_MAX_INUM 31 + +/* CPU Interrupt number used in ROM, should be cancelled in SDK */ + +#define ETS_SLC_INUM 1 +#define ETS_UART0_INUM 5 +#define ETS_UART1_INUM 5 +#define ETS_SPI2_INUM 1 + +/* CPU Interrupt number used in ROM code only when module init function + * called, should pay attention here. + */ + +#define ETS_GPIO_INUM 4 + +/* Other interrupt number should be managed by the user */ + +/* Invalid interrupt for number interrupt matrix */ + +#define ETS_INVALID_INUM 0 + +/* Interrupt medium level, used for INT WDT for example */ + +#define SOC_INTERRUPT_LEVEL_MEDIUM 4 + +#define BIT(nr) (1UL << (nr)) + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SOC_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_system.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_system.h new file mode 100644 index 0000000000..bac37bc24f --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_system.h @@ -0,0 +1,1213 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/esp32c3_system.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SYSTEM_H +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SYSTEM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x000) + +/* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W [7] : 1'b0 ; */ + +#define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7)) +#define SYSTEM_CLK_EN_DEDICATED_GPIO_M (BIT(7)) +#define SYSTEM_CLK_EN_DEDICATED_GPIO_V 0x1 +#define SYSTEM_CLK_EN_DEDICATED_GPIO_S 7 + +/* SYSTEM_CLK_EN_ASSIST_DEBUG : R/W [6] : 1'b0 ; */ + +#define SYSTEM_CLK_EN_ASSIST_DEBUG (BIT(6)) +#define SYSTEM_CLK_EN_ASSIST_DEBUG_M (BIT(6)) +#define SYSTEM_CLK_EN_ASSIST_DEBUG_V 0x1 +#define SYSTEM_CLK_EN_ASSIST_DEBUG_S 6 + +#define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x004) + +/* SYSTEM_RST_EN_DEDICATED_GPIO : R/W [7] : 1'b1 ; */ + +#define SYSTEM_RST_EN_DEDICATED_GPIO (BIT(7)) +#define SYSTEM_RST_EN_DEDICATED_GPIO_M (BIT(7)) +#define SYSTEM_RST_EN_DEDICATED_GPIO_V 0x1 +#define SYSTEM_RST_EN_DEDICATED_GPIO_S 7 + +/* SYSTEM_RST_EN_ASSIST_DEBUG : R/W [6] : 1'b1 ; */ + +#define SYSTEM_RST_EN_ASSIST_DEBUG (BIT(6)) +#define SYSTEM_RST_EN_ASSIST_DEBUG_M (BIT(6)) +#define SYSTEM_RST_EN_ASSIST_DEBUG_V 0x1 +#define SYSTEM_RST_EN_ASSIST_DEBUG_S 6 + +#define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x008) + +/* SYSTEM_CPU_WAITI_DELAY_NUM : R/W [7:4] : 4'h0 ; */ + +#define SYSTEM_CPU_WAITI_DELAY_NUM 0x0000000f +#define SYSTEM_CPU_WAITI_DELAY_NUM_M (SYSTEM_CPU_WAITI_DELAY_NUM_V << SYSTEM_CPU_WAITI_DELAY_NUM_S +#define SYSTEM_CPU_WAITI_DELAY_NUM_V 0xf +#define SYSTEM_CPU_WAITI_DELAY_NUM_S 4 + +/* SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W [3] : 1'b1 ; */ + +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON (BIT(3)) +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (BIT(3)) +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V 0x1 +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S 3 + +/* SYSTEM_PLL_FREQ_SEL : R/W [2] : 1'b1 ; */ + +#define SYSTEM_PLL_FREQ_SEL (BIT(2)) +#define SYSTEM_PLL_FREQ_SEL_M (BIT(2)) +#define SYSTEM_PLL_FREQ_SEL_V 0x1 +#define SYSTEM_PLL_FREQ_SEL_S 2 + +/* SYSTEM_CPUPERIOD_SEL : R/W [1:0] : 2'b0 ; */ + +#define SYSTEM_CPUPERIOD_SEL 0x00000003 +#define SYSTEM_CPUPERIOD_SEL_M (SYSTEM_CPUPERIOD_SEL_V << SYSTEM_CPUPERIOD_SEL_S) +#define SYSTEM_CPUPERIOD_SEL_V 0x3 +#define SYSTEM_CPUPERIOD_SEL_S 0 + +#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x00c) + +/* SYSTEM_LSLP_MEM_PD_MASK : R/W [0] : 1'b1 ; */ + +#define SYSTEM_LSLP_MEM_PD_MASK (BIT(0)) +#define SYSTEM_LSLP_MEM_PD_MASK_M (BIT(0)) +#define SYSTEM_LSLP_MEM_PD_MASK_V 0x1 +#define SYSTEM_LSLP_MEM_PD_MASK_S 0 + +#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x010) + +/* SYSTEM_SPI4_CLK_EN : R/W [31] : 1'h1 ; */ + +#define SYSTEM_SPI4_CLK_EN (BIT(31)) +#define SYSTEM_SPI4_CLK_EN_M (BIT(31)) +#define SYSTEM_SPI4_CLK_EN_V 0x1 +#define SYSTEM_SPI4_CLK_EN_S 31 + +/* SYSTEM_ADC2_ARB_CLK_EN : R/W [30] : 1'b1 ; */ + +#define SYSTEM_ADC2_ARB_CLK_EN (BIT(30)) +#define SYSTEM_ADC2_ARB_CLK_EN_M (BIT(30)) +#define SYSTEM_ADC2_ARB_CLK_EN_V 0x1 +#define SYSTEM_ADC2_ARB_CLK_EN_S 30 + +/* SYSTEM_SYSTIMER_CLK_EN : R/W [29] : 1'b1 ; */ + +#define SYSTEM_SYSTIMER_CLK_EN (BIT(29)) +#define SYSTEM_SYSTIMER_CLK_EN_M (BIT(29)) +#define SYSTEM_SYSTIMER_CLK_EN_V 0x1 +#define SYSTEM_SYSTIMER_CLK_EN_S 29 + +/* SYSTEM_APB_SARADC_CLK_EN : R/W [28] : 1'b1 ; */ + +#define SYSTEM_APB_SARADC_CLK_EN (BIT(28)) +#define SYSTEM_APB_SARADC_CLK_EN_M (BIT(28)) +#define SYSTEM_APB_SARADC_CLK_EN_V 0x1 +#define SYSTEM_APB_SARADC_CLK_EN_S 28 + +/* SYSTEM_SPI3_DMA_CLK_EN : R/W [27] : 1'b1 ; */ + +#define SYSTEM_SPI3_DMA_CLK_EN (BIT(27)) +#define SYSTEM_SPI3_DMA_CLK_EN_M (BIT(27)) +#define SYSTEM_SPI3_DMA_CLK_EN_V 0x1 +#define SYSTEM_SPI3_DMA_CLK_EN_S 27 + +/* SYSTEM_PWM3_CLK_EN : R/W [26] : 1'b0 ; */ + +#define SYSTEM_PWM3_CLK_EN (BIT(26)) +#define SYSTEM_PWM3_CLK_EN_M (BIT(26)) +#define SYSTEM_PWM3_CLK_EN_V 0x1 +#define SYSTEM_PWM3_CLK_EN_S 26 + +/* SYSTEM_PWM2_CLK_EN : R/W [25] : 1'b0 ; */ + +#define SYSTEM_PWM2_CLK_EN (BIT(25)) +#define SYSTEM_PWM2_CLK_EN_M (BIT(25)) +#define SYSTEM_PWM2_CLK_EN_V 0x1 +#define SYSTEM_PWM2_CLK_EN_S 25 + +/* SYSTEM_UART_MEM_CLK_EN : R/W [24] : 1'b1 ; */ + +#define SYSTEM_UART_MEM_CLK_EN (BIT(24)) +#define SYSTEM_UART_MEM_CLK_EN_M (BIT(24)) +#define SYSTEM_UART_MEM_CLK_EN_V 0x1 +#define SYSTEM_UART_MEM_CLK_EN_S 24 + +/* SYSTEM_USB_DEVICE_CLK_EN : R/W [23] : 1'b1 ; */ + +#define SYSTEM_USB_DEVICE_CLK_EN (BIT(23)) +#define SYSTEM_USB_DEVICE_CLK_EN_M (BIT(23)) +#define SYSTEM_USB_DEVICE_CLK_EN_V 0x1 +#define SYSTEM_USB_DEVICE_CLK_EN_S 23 + +/* SYSTEM_SPI2_DMA_CLK_EN : R/W [22] : 1'b1 ; */ + +#define SYSTEM_SPI2_DMA_CLK_EN (BIT(22)) +#define SYSTEM_SPI2_DMA_CLK_EN_M (BIT(22)) +#define SYSTEM_SPI2_DMA_CLK_EN_V 0x1 +#define SYSTEM_SPI2_DMA_CLK_EN_S 22 + +/* SYSTEM_I2S1_CLK_EN : R/W [21] : 1'b0 ; */ + +#define SYSTEM_I2S1_CLK_EN (BIT(21)) +#define SYSTEM_I2S1_CLK_EN_M (BIT(21)) +#define SYSTEM_I2S1_CLK_EN_V 0x1 +#define SYSTEM_I2S1_CLK_EN_S 21 + +/* SYSTEM_PWM1_CLK_EN : R/W [20] : 1'b0 ; */ + +#define SYSTEM_PWM1_CLK_EN (BIT(20)) +#define SYSTEM_PWM1_CLK_EN_M (BIT(20)) +#define SYSTEM_PWM1_CLK_EN_V 0x1 +#define SYSTEM_PWM1_CLK_EN_S 20 + +/* SYSTEM_TWAI_CLK_EN : R/W [19] : 1'b0 ; */ + +#define SYSTEM_TWAI_CLK_EN (BIT(19)) +#define SYSTEM_TWAI_CLK_EN_M (BIT(19)) +#define SYSTEM_TWAI_CLK_EN_V 0x1 +#define SYSTEM_TWAI_CLK_EN_S 19 + +/* SYSTEM_I2C_EXT1_CLK_EN : R/W [18] : 1'b0 ; */ + +#define SYSTEM_I2C_EXT1_CLK_EN (BIT(18)) +#define SYSTEM_I2C_EXT1_CLK_EN_M (BIT(18)) +#define SYSTEM_I2C_EXT1_CLK_EN_V 0x1 +#define SYSTEM_I2C_EXT1_CLK_EN_S 18 + +/* SYSTEM_PWM0_CLK_EN : R/W [17] : 1'b0 ; */ + +#define SYSTEM_PWM0_CLK_EN (BIT(17)) +#define SYSTEM_PWM0_CLK_EN_M (BIT(17)) +#define SYSTEM_PWM0_CLK_EN_V 0x1 +#define SYSTEM_PWM0_CLK_EN_S 17 + +/* SYSTEM_SPI3_CLK_EN : R/W [16] : 1'b1 ; */ + +#define SYSTEM_SPI3_CLK_EN (BIT(16)) +#define SYSTEM_SPI3_CLK_EN_M (BIT(16)) +#define SYSTEM_SPI3_CLK_EN_V 0x1 +#define SYSTEM_SPI3_CLK_EN_S 16 + +/* SYSTEM_TIMERGROUP1_CLK_EN : R/W [15] : 1'b1 ; */ + +#define SYSTEM_TIMERGROUP1_CLK_EN (BIT(15)) +#define SYSTEM_TIMERGROUP1_CLK_EN_M (BIT(15)) +#define SYSTEM_TIMERGROUP1_CLK_EN_V 0x1 +#define SYSTEM_TIMERGROUP1_CLK_EN_S 15 + +/* SYSTEM_EFUSE_CLK_EN : R/W [14] : 1'b1 ; */ + +#define SYSTEM_EFUSE_CLK_EN (BIT(14)) +#define SYSTEM_EFUSE_CLK_EN_M (BIT(14)) +#define SYSTEM_EFUSE_CLK_EN_V 0x1 +#define SYSTEM_EFUSE_CLK_EN_S 14 + +/* SYSTEM_TIMERGROUP_CLK_EN : R/W [13] : 1'b1 ; */ + +#define SYSTEM_TIMERGROUP_CLK_EN (BIT(13)) +#define SYSTEM_TIMERGROUP_CLK_EN_M (BIT(13)) +#define SYSTEM_TIMERGROUP_CLK_EN_V 0x1 +#define SYSTEM_TIMERGROUP_CLK_EN_S 13 + +/* SYSTEM_UHCI1_CLK_EN : R/W [12] : 1'b0 ; */ + +#define SYSTEM_UHCI1_CLK_EN (BIT(12)) +#define SYSTEM_UHCI1_CLK_EN_M (BIT(12)) +#define SYSTEM_UHCI1_CLK_EN_V 0x1 +#define SYSTEM_UHCI1_CLK_EN_S 12 + +/* SYSTEM_LEDC_CLK_EN : R/W [11] : 1'b0 ; */ + +#define SYSTEM_LEDC_CLK_EN (BIT(11)) +#define SYSTEM_LEDC_CLK_EN_M (BIT(11)) +#define SYSTEM_LEDC_CLK_EN_V 0x1 +#define SYSTEM_LEDC_CLK_EN_S 11 + +/* SYSTEM_PCNT_CLK_EN : R/W [10] : 1'b0 ; */ + +#define SYSTEM_PCNT_CLK_EN (BIT(10)) +#define SYSTEM_PCNT_CLK_EN_M (BIT(10)) +#define SYSTEM_PCNT_CLK_EN_V 0x1 +#define SYSTEM_PCNT_CLK_EN_S 10 + +/* SYSTEM_RMT_CLK_EN : R/W [9] : 1'b0 ; */ + +#define SYSTEM_RMT_CLK_EN (BIT(9)) +#define SYSTEM_RMT_CLK_EN_M (BIT(9)) +#define SYSTEM_RMT_CLK_EN_V 0x1 +#define SYSTEM_RMT_CLK_EN_S 9 + +/* SYSTEM_UHCI0_CLK_EN : R/W [8] : 1'b0 ; */ + +#define SYSTEM_UHCI0_CLK_EN (BIT(8)) +#define SYSTEM_UHCI0_CLK_EN_M (BIT(8)) +#define SYSTEM_UHCI0_CLK_EN_V 0x1 +#define SYSTEM_UHCI0_CLK_EN_S 8 + +/* SYSTEM_I2C_EXT0_CLK_EN : R/W [7] : 1'b0 ; */ + +#define SYSTEM_I2C_EXT0_CLK_EN (BIT(7)) +#define SYSTEM_I2C_EXT0_CLK_EN_M (BIT(7)) +#define SYSTEM_I2C_EXT0_CLK_EN_V 0x1 +#define SYSTEM_I2C_EXT0_CLK_EN_S 7 + +/* SYSTEM_SPI2_CLK_EN : R/W [6] : 1'b1 ; */ + +#define SYSTEM_SPI2_CLK_EN (BIT(6)) +#define SYSTEM_SPI2_CLK_EN_M (BIT(6)) +#define SYSTEM_SPI2_CLK_EN_V 0x1 +#define SYSTEM_SPI2_CLK_EN_S 6 + +/* SYSTEM_UART1_CLK_EN : R/W [5] : 1'b1 ; */ + +#define SYSTEM_UART1_CLK_EN (BIT(5)) +#define SYSTEM_UART1_CLK_EN_M (BIT(5)) +#define SYSTEM_UART1_CLK_EN_V 0x1 +#define SYSTEM_UART1_CLK_EN_S 5 + +/* SYSTEM_I2S0_CLK_EN : R/W [4] : 1'b0 ; */ + +#define SYSTEM_I2S0_CLK_EN (BIT(4)) +#define SYSTEM_I2S0_CLK_EN_M (BIT(4)) +#define SYSTEM_I2S0_CLK_EN_V 0x1 +#define SYSTEM_I2S0_CLK_EN_S 4 + +/* SYSTEM_WDG_CLK_EN : R/W [3] : 1'b1 ; */ + +#define SYSTEM_WDG_CLK_EN (BIT(3)) +#define SYSTEM_WDG_CLK_EN_M (BIT(3)) +#define SYSTEM_WDG_CLK_EN_V 0x1 +#define SYSTEM_WDG_CLK_EN_S 3 + +/* SYSTEM_UART_CLK_EN : R/W [2] : 1'b1 ; */ + +#define SYSTEM_UART_CLK_EN (BIT(2)) +#define SYSTEM_UART_CLK_EN_M (BIT(2)) +#define SYSTEM_UART_CLK_EN_V 0x1 +#define SYSTEM_UART_CLK_EN_S 2 + +/* SYSTEM_SPI01_CLK_EN : R/W [1] : 1'b1 ; */ + +#define SYSTEM_SPI01_CLK_EN (BIT(1)) +#define SYSTEM_SPI01_CLK_EN_M (BIT(1)) +#define SYSTEM_SPI01_CLK_EN_V 0x1 +#define SYSTEM_SPI01_CLK_EN_S 1 + +/* SYSTEM_TIMERS_CLK_EN : R/W [0] : 1'b1 ; */ + +#define SYSTEM_TIMERS_CLK_EN (BIT(0)) +#define SYSTEM_TIMERS_CLK_EN_M (BIT(0)) +#define SYSTEM_TIMERS_CLK_EN_V 0x1 +#define SYSTEM_TIMERS_CLK_EN_S 0 + +#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x014) + +/* SYSTEM_TSENS_CLK_EN : R/W [10] : 1'b0 ; */ + +#define SYSTEM_TSENS_CLK_EN (BIT(10)) +#define SYSTEM_TSENS_CLK_EN_M (BIT(10)) +#define SYSTEM_TSENS_CLK_EN_V 0x1 +#define SYSTEM_TSENS_CLK_EN_S 10 + +/* SYSTEM_UART2_CLK_EN : R/W [9] : 1'b1 ; */ + +#define SYSTEM_UART2_CLK_EN (BIT(9)) +#define SYSTEM_UART2_CLK_EN_M (BIT(9)) +#define SYSTEM_UART2_CLK_EN_V 0x1 +#define SYSTEM_UART2_CLK_EN_S 9 + +/* SYSTEM_LCD_CAM_CLK_EN : R/W [8] : 1'b0 ; */ + +#define SYSTEM_LCD_CAM_CLK_EN (BIT(8)) +#define SYSTEM_LCD_CAM_CLK_EN_M (BIT(8)) +#define SYSTEM_LCD_CAM_CLK_EN_V 0x1 +#define SYSTEM_LCD_CAM_CLK_EN_S 8 + +/* SYSTEM_SDIO_HOST_CLK_EN : R/W [7] : 1'b0 ; */ + +#define SYSTEM_SDIO_HOST_CLK_EN (BIT(7)) +#define SYSTEM_SDIO_HOST_CLK_EN_M (BIT(7)) +#define SYSTEM_SDIO_HOST_CLK_EN_V 0x1 +#define SYSTEM_SDIO_HOST_CLK_EN_S 7 + +/* SYSTEM_DMA_CLK_EN : R/W [6] : 1'b0 ; */ + +#define SYSTEM_DMA_CLK_EN (BIT(6)) +#define SYSTEM_DMA_CLK_EN_M (BIT(6)) +#define SYSTEM_DMA_CLK_EN_V 0x1 +#define SYSTEM_DMA_CLK_EN_S 6 + +/* SYSTEM_CRYPTO_HMAC_CLK_EN : R/W [5] : 1'b0 ; */ + +#define SYSTEM_CRYPTO_HMAC_CLK_EN (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_CLK_EN_M (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_HMAC_CLK_EN_S 5 + +/* SYSTEM_CRYPTO_DS_CLK_EN : R/W [4] : 1'b0 ; */ + +#define SYSTEM_CRYPTO_DS_CLK_EN (BIT(4)) +#define SYSTEM_CRYPTO_DS_CLK_EN_M (BIT(4)) +#define SYSTEM_CRYPTO_DS_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_DS_CLK_EN_S 4 + +/* SYSTEM_CRYPTO_RSA_CLK_EN : R/W [3] : 1'b0 ; */ + +#define SYSTEM_CRYPTO_RSA_CLK_EN (BIT(3)) +#define SYSTEM_CRYPTO_RSA_CLK_EN_M (BIT(3)) +#define SYSTEM_CRYPTO_RSA_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_RSA_CLK_EN_S 3 + +/* SYSTEM_CRYPTO_SHA_CLK_EN : R/W [2] : 1'b0 ; */ + +#define SYSTEM_CRYPTO_SHA_CLK_EN (BIT(2)) +#define SYSTEM_CRYPTO_SHA_CLK_EN_M (BIT(2)) +#define SYSTEM_CRYPTO_SHA_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_SHA_CLK_EN_S 2 + +/* SYSTEM_CRYPTO_AES_CLK_EN : R/W [1] : 1'b0 ; */ + +#define SYSTEM_CRYPTO_AES_CLK_EN (BIT(1)) +#define SYSTEM_CRYPTO_AES_CLK_EN_M (BIT(1)) +#define SYSTEM_CRYPTO_AES_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_AES_CLK_EN_S 1 + +#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x018) + +/* SYSTEM_SPI4_RST : R/W [31] : 1'h0 ; */ + +#define SYSTEM_SPI4_RST (BIT(31)) +#define SYSTEM_SPI4_RST_M (BIT(31)) +#define SYSTEM_SPI4_RST_V 0x1 +#define SYSTEM_SPI4_RST_S 31 + +/* SYSTEM_ADC2_ARB_RST : R/W [30] : 1'b0 ; */ + +#define SYSTEM_ADC2_ARB_RST (BIT(30)) +#define SYSTEM_ADC2_ARB_RST_M (BIT(30)) +#define SYSTEM_ADC2_ARB_RST_V 0x1 +#define SYSTEM_ADC2_ARB_RST_S 30 + +/* SYSTEM_SYSTIMER_RST : R/W [29] : 1'b0 ; */ + +#define SYSTEM_SYSTIMER_RST (BIT(29)) +#define SYSTEM_SYSTIMER_RST_M (BIT(29)) +#define SYSTEM_SYSTIMER_RST_V 0x1 +#define SYSTEM_SYSTIMER_RST_S 29 + +/* SYSTEM_APB_SARADC_RST : R/W [28] : 1'b0 ; */ + +#define SYSTEM_APB_SARADC_RST (BIT(28)) +#define SYSTEM_APB_SARADC_RST_M (BIT(28)) +#define SYSTEM_APB_SARADC_RST_V 0x1 +#define SYSTEM_APB_SARADC_RST_S 28 + +/* SYSTEM_SPI3_DMA_RST : R/W [27] : 1'b0 ; */ + +#define SYSTEM_SPI3_DMA_RST (BIT(27)) +#define SYSTEM_SPI3_DMA_RST_M (BIT(27)) +#define SYSTEM_SPI3_DMA_RST_V 0x1 +#define SYSTEM_SPI3_DMA_RST_S 27 + +/* SYSTEM_PWM3_RST : R/W [26] : 1'b0 ; */ + +#define SYSTEM_PWM3_RST (BIT(26)) +#define SYSTEM_PWM3_RST_M (BIT(26)) +#define SYSTEM_PWM3_RST_V 0x1 +#define SYSTEM_PWM3_RST_S 26 + +/* SYSTEM_PWM2_RST : R/W [25] : 1'b0 ; */ + +#define SYSTEM_PWM2_RST (BIT(25)) +#define SYSTEM_PWM2_RST_M (BIT(25)) +#define SYSTEM_PWM2_RST_V 0x1 +#define SYSTEM_PWM2_RST_S 25 + +/* SYSTEM_UART_MEM_RST : R/W [24] : 1'b0 ; */ + +#define SYSTEM_UART_MEM_RST (BIT(24)) +#define SYSTEM_UART_MEM_RST_M (BIT(24)) +#define SYSTEM_UART_MEM_RST_V 0x1 +#define SYSTEM_UART_MEM_RST_S 24 + +/* SYSTEM_USB_DEVICE_RST : R/W [23] : 1'b0 ; */ + +#define SYSTEM_USB_DEVICE_RST (BIT(23)) +#define SYSTEM_USB_DEVICE_RST_M (BIT(23)) +#define SYSTEM_USB_DEVICE_RST_V 0x1 +#define SYSTEM_USB_DEVICE_RST_S 23 + +/* SYSTEM_SPI2_DMA_RST : R/W [22] : 1'b0 ; */ + +#define SYSTEM_SPI2_DMA_RST (BIT(22)) +#define SYSTEM_SPI2_DMA_RST_M (BIT(22)) +#define SYSTEM_SPI2_DMA_RST_V 0x1 +#define SYSTEM_SPI2_DMA_RST_S 22 + +/* SYSTEM_I2S1_RST : R/W [21] : 1'b0 ; */ + +#define SYSTEM_I2S1_RST (BIT(21)) +#define SYSTEM_I2S1_RST_M (BIT(21)) +#define SYSTEM_I2S1_RST_V 0x1 +#define SYSTEM_I2S1_RST_S 21 + +/* SYSTEM_PWM1_RST : R/W [20] : 1'b0 ; */ + +#define SYSTEM_PWM1_RST (BIT(20)) +#define SYSTEM_PWM1_RST_M (BIT(20)) +#define SYSTEM_PWM1_RST_V 0x1 +#define SYSTEM_PWM1_RST_S 20 + +/* SYSTEM_TWAI_RST : R/W [19] : 1'b0 ; */ + +#define SYSTEM_TWAI_RST (BIT(19)) +#define SYSTEM_TWAI_RST_M (BIT(19)) +#define SYSTEM_TWAI_RST_V 0x1 +#define SYSTEM_TWAI_RST_S 19 + +/* SYSTEM_I2C_EXT1_RST : R/W [18] : 1'b0 ; */ + +#define SYSTEM_I2C_EXT1_RST (BIT(18)) +#define SYSTEM_I2C_EXT1_RST_M (BIT(18)) +#define SYSTEM_I2C_EXT1_RST_V 0x1 +#define SYSTEM_I2C_EXT1_RST_S 18 + +/* SYSTEM_PWM0_RST : R/W [17] : 1'b0 ; */ + +#define SYSTEM_PWM0_RST (BIT(17)) +#define SYSTEM_PWM0_RST_M (BIT(17)) +#define SYSTEM_PWM0_RST_V 0x1 +#define SYSTEM_PWM0_RST_S 17 + +/* SYSTEM_SPI3_RST : R/W [16] : 1'b0 ; */ + +#define SYSTEM_SPI3_RST (BIT(16)) +#define SYSTEM_SPI3_RST_M (BIT(16)) +#define SYSTEM_SPI3_RST_V 0x1 +#define SYSTEM_SPI3_RST_S 16 + +/* SYSTEM_TIMERGROUP1_RST : R/W [15] : 1'b0 ; */ + +#define SYSTEM_TIMERGROUP1_RST (BIT(15)) +#define SYSTEM_TIMERGROUP1_RST_M (BIT(15)) +#define SYSTEM_TIMERGROUP1_RST_V 0x1 +#define SYSTEM_TIMERGROUP1_RST_S 15 + +/* SYSTEM_EFUSE_RST : R/W [14] : 1'b0 ; */ + +#define SYSTEM_EFUSE_RST (BIT(14)) +#define SYSTEM_EFUSE_RST_M (BIT(14)) +#define SYSTEM_EFUSE_RST_V 0x1 +#define SYSTEM_EFUSE_RST_S 14 + +/* SYSTEM_TIMERGROUP_RST : R/W [13] : 1'b0 ; */ + +#define SYSTEM_TIMERGROUP_RST (BIT(13)) +#define SYSTEM_TIMERGROUP_RST_M (BIT(13)) +#define SYSTEM_TIMERGROUP_RST_V 0x1 +#define SYSTEM_TIMERGROUP_RST_S 13 + +/* SYSTEM_UHCI1_RST : R/W [12] : 1'b0 ; */ + +#define SYSTEM_UHCI1_RST (BIT(12)) +#define SYSTEM_UHCI1_RST_M (BIT(12)) +#define SYSTEM_UHCI1_RST_V 0x1 +#define SYSTEM_UHCI1_RST_S 12 + +/* SYSTEM_LEDC_RST : R/W [11] : 1'b0 ; */ + +#define SYSTEM_LEDC_RST (BIT(11)) +#define SYSTEM_LEDC_RST_M (BIT(11)) +#define SYSTEM_LEDC_RST_V 0x1 +#define SYSTEM_LEDC_RST_S 11 + +/* SYSTEM_PCNT_RST : R/W [10] : 1'b0 ; */ + +#define SYSTEM_PCNT_RST (BIT(10)) +#define SYSTEM_PCNT_RST_M (BIT(10)) +#define SYSTEM_PCNT_RST_V 0x1 +#define SYSTEM_PCNT_RST_S 10 + +/* SYSTEM_RMT_RST : R/W [9] : 1'b0 ; */ + +#define SYSTEM_RMT_RST (BIT(9)) +#define SYSTEM_RMT_RST_M (BIT(9)) +#define SYSTEM_RMT_RST_V 0x1 +#define SYSTEM_RMT_RST_S 9 + +/* SYSTEM_UHCI0_RST : R/W [8] : 1'b0 ; */ + +#define SYSTEM_UHCI0_RST (BIT(8)) +#define SYSTEM_UHCI0_RST_M (BIT(8)) +#define SYSTEM_UHCI0_RST_V 0x1 +#define SYSTEM_UHCI0_RST_S 8 + +/* SYSTEM_I2C_EXT0_RST : R/W [7] : 1'b0 ; */ + +#define SYSTEM_I2C_EXT0_RST (BIT(7)) +#define SYSTEM_I2C_EXT0_RST_M (BIT(7)) +#define SYSTEM_I2C_EXT0_RST_V 0x1 +#define SYSTEM_I2C_EXT0_RST_S 7 + +/* SYSTEM_SPI2_RST : R/W [6] : 1'b0 ; */ + +#define SYSTEM_SPI2_RST (BIT(6)) +#define SYSTEM_SPI2_RST_M (BIT(6)) +#define SYSTEM_SPI2_RST_V 0x1 +#define SYSTEM_SPI2_RST_S 6 + +/* SYSTEM_UART1_RST : R/W [5] : 1'b0 ; */ + +#define SYSTEM_UART1_RST (BIT(5)) +#define SYSTEM_UART1_RST_M (BIT(5)) +#define SYSTEM_UART1_RST_V 0x1 +#define SYSTEM_UART1_RST_S 5 + +/* SYSTEM_I2S0_RST : R/W [4] : 1'b0 ; */ + +#define SYSTEM_I2S0_RST (BIT(4)) +#define SYSTEM_I2S0_RST_M (BIT(4)) +#define SYSTEM_I2S0_RST_V 0x1 +#define SYSTEM_I2S0_RST_S 4 + +/* SYSTEM_WDG_RST : R/W [3] : 1'b0 ; */ + +#define SYSTEM_WDG_RST (BIT(3)) +#define SYSTEM_WDG_RST_M (BIT(3)) +#define SYSTEM_WDG_RST_V 0x1 +#define SYSTEM_WDG_RST_S 3 + +/* SYSTEM_UART_RST : R/W [2] : 1'b0 ; */ + +#define SYSTEM_UART_RST (BIT(2)) +#define SYSTEM_UART_RST_M (BIT(2)) +#define SYSTEM_UART_RST_V 0x1 +#define SYSTEM_UART_RST_S 2 + +/* SYSTEM_SPI01_RST : R/W [1] : 1'b0 ; */ + +#define SYSTEM_SPI01_RST (BIT(1)) +#define SYSTEM_SPI01_RST_M (BIT(1)) +#define SYSTEM_SPI01_RST_V 0x1 +#define SYSTEM_SPI01_RST_S 1 + +/* SYSTEM_TIMERS_RST : R/W [0] : 1'b0 ; */ + +#define SYSTEM_TIMERS_RST (BIT(0)) +#define SYSTEM_TIMERS_RST_M (BIT(0)) +#define SYSTEM_TIMERS_RST_V 0x1 +#define SYSTEM_TIMERS_RST_S 0 + +#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x01c) + +/* SYSTEM_TSENS_RST : R/W [10] : 1'b0 ; */ + +#define SYSTEM_TSENS_RST (BIT(10)) +#define SYSTEM_TSENS_RST_M (BIT(10)) +#define SYSTEM_TSENS_RST_V 0x1 +#define SYSTEM_TSENS_RST_S 10 + +/* SYSTEM_UART2_RST : R/W [9] : 1'b0 ; */ + +#define SYSTEM_UART2_RST (BIT(9)) +#define SYSTEM_UART2_RST_M (BIT(9)) +#define SYSTEM_UART2_RST_V 0x1 +#define SYSTEM_UART2_RST_S 9 + +/* SYSTEM_LCD_CAM_RST : R/W [8] : 1'b1 ; */ + +#define SYSTEM_LCD_CAM_RST (BIT(8)) +#define SYSTEM_LCD_CAM_RST_M (BIT(8)) +#define SYSTEM_LCD_CAM_RST_V 0x1 +#define SYSTEM_LCD_CAM_RST_S 8 + +/* SYSTEM_SDIO_HOST_RST : R/W [7] : 1'b1 ; */ + +#define SYSTEM_SDIO_HOST_RST (BIT(7)) +#define SYSTEM_SDIO_HOST_RST_M (BIT(7)) +#define SYSTEM_SDIO_HOST_RST_V 0x1 +#define SYSTEM_SDIO_HOST_RST_S 7 + +/* SYSTEM_DMA_RST : R/W [6] : 1'b1 ; */ + +#define SYSTEM_DMA_RST (BIT(6)) +#define SYSTEM_DMA_RST_M (BIT(6)) +#define SYSTEM_DMA_RST_V 0x1 +#define SYSTEM_DMA_RST_S 6 + +/* SYSTEM_CRYPTO_HMAC_RST : R/W [5] : 1'b1 ; */ + +#define SYSTEM_CRYPTO_HMAC_RST (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_RST_M (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_RST_V 0x1 +#define SYSTEM_CRYPTO_HMAC_RST_S 5 + +/* SYSTEM_CRYPTO_DS_RST : R/W [4] : 1'b1 ; */ + +#define SYSTEM_CRYPTO_DS_RST (BIT(4)) +#define SYSTEM_CRYPTO_DS_RST_M (BIT(4)) +#define SYSTEM_CRYPTO_DS_RST_V 0x1 +#define SYSTEM_CRYPTO_DS_RST_S 4 + +/* SYSTEM_CRYPTO_RSA_RST : R/W [3] : 1'b1 ; */ + +#define SYSTEM_CRYPTO_RSA_RST (BIT(3)) +#define SYSTEM_CRYPTO_RSA_RST_M (BIT(3)) +#define SYSTEM_CRYPTO_RSA_RST_V 0x1 +#define SYSTEM_CRYPTO_RSA_RST_S 3 + +/* SYSTEM_CRYPTO_SHA_RST : R/W [2] : 1'b1 ; */ + +#define SYSTEM_CRYPTO_SHA_RST (BIT(2)) +#define SYSTEM_CRYPTO_SHA_RST_M (BIT(2)) +#define SYSTEM_CRYPTO_SHA_RST_V 0x1 +#define SYSTEM_CRYPTO_SHA_RST_S 2 + +/* SYSTEM_CRYPTO_AES_RST : R/W [1] : 1'b1 ; */ + +#define SYSTEM_CRYPTO_AES_RST (BIT(1)) +#define SYSTEM_CRYPTO_AES_RST_M (BIT(1)) +#define SYSTEM_CRYPTO_AES_RST_V 0x1 +#define SYSTEM_CRYPTO_AES_RST_S 1 + +#define SYSTEM_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x020) + +/* SYSTEM_BT_LPCK_DIV_NUM : R/W [11:0] : 12'd255 ; */ + +#define SYSTEM_BT_LPCK_DIV_NUM 0x00000fff +#define SYSTEM_BT_LPCK_DIV_NUM_M (SYSTEM_BT_LPCK_DIV_NUM_V << SYSTEM_BT_LPCK_DIV_NUM_S) +#define SYSTEM_BT_LPCK_DIV_NUM_V 0xfff +#define SYSTEM_BT_LPCK_DIV_NUM_S 0 + +#define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x024) + +/* SYSTEM_LPCLK_RTC_EN : R/W [28] : 1'b0 ; */ + +#define SYSTEM_LPCLK_RTC_EN (BIT(28)) +#define SYSTEM_LPCLK_RTC_EN_M (BIT(28)) +#define SYSTEM_LPCLK_RTC_EN_V 0x1 +#define SYSTEM_LPCLK_RTC_EN_S 28 + +/* SYSTEM_LPCLK_SEL_XTAL32K : R/W [27] : 1'b0 ; */ + +#define SYSTEM_LPCLK_SEL_XTAL32K (BIT(27)) +#define SYSTEM_LPCLK_SEL_XTAL32K_M (BIT(27)) +#define SYSTEM_LPCLK_SEL_XTAL32K_V 0x1 +#define SYSTEM_LPCLK_SEL_XTAL32K_S 27 + +/* SYSTEM_LPCLK_SEL_XTAL : R/W [26] : 1'b0 ; */ + +#define SYSTEM_LPCLK_SEL_XTAL (BIT(26)) +#define SYSTEM_LPCLK_SEL_XTAL_M (BIT(26)) +#define SYSTEM_LPCLK_SEL_XTAL_V 0x1 +#define SYSTEM_LPCLK_SEL_XTAL_S 26 + +/* SYSTEM_LPCLK_SEL_8M : R/W [25] : 1'b1 ; */ + +#define SYSTEM_LPCLK_SEL_8M (BIT(25)) +#define SYSTEM_LPCLK_SEL_8M_M (BIT(25)) +#define SYSTEM_LPCLK_SEL_8M_V 0x1 +#define SYSTEM_LPCLK_SEL_8M_S 25 + +/* SYSTEM_LPCLK_SEL_RTC_SLOW : R/W [24] : 1'b0 ; */ + +#define SYSTEM_LPCLK_SEL_RTC_SLOW (BIT(24)) +#define SYSTEM_LPCLK_SEL_RTC_SLOW_M (BIT(24)) +#define SYSTEM_LPCLK_SEL_RTC_SLOW_V 0x1 +#define SYSTEM_LPCLK_SEL_RTC_SLOW_S 24 + +/* SYSTEM_BT_LPCK_DIV_A : R/W [23:12] : 12'd1 ; */ + +#define SYSTEM_BT_LPCK_DIV_A 0x00000fff +#define SYSTEM_BT_LPCK_DIV_A_M (SYSTEM_BT_LPCK_DIV_A_V << SYSTEM_BT_LPCK_DIV_A_S) +#define SYSTEM_BT_LPCK_DIV_A_V 0xfff +#define SYSTEM_BT_LPCK_DIV_A_S 12 + +/* SYSTEM_BT_LPCK_DIV_B : R/W [11:0] : 12'd1 ; */ + +#define SYSTEM_BT_LPCK_DIV_B 0x00000fff +#define SYSTEM_BT_LPCK_DIV_B_M (SYSTEM_BT_LPCK_DIV_B_V << SYSTEM_BT_LPCK_DIV_B_S) +#define SYSTEM_BT_LPCK_DIV_B_V 0xfff +#define SYSTEM_BT_LPCK_DIV_B_S 0 + +#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x028) + +/* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W [0] : 1'b0 ; */ + +#define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_0_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_0_S 0 + +#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x02c) + +/* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W [0] : 1'b0 ; */ + +#define SYSTEM_CPU_INTR_FROM_CPU_1 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_1_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_1_S 0 + +#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x030) + +/* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W [0] : 1'b0 ; */ + +#define SYSTEM_CPU_INTR_FROM_CPU_2 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_2_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_2_S 0 + +#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x034) + +/* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W [0] : 1'b0 ; */ + +#define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_3_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_3_S 0 + +#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x038) + +/* SYSTEM_RSA_MEM_FORCE_PD : R/W [2] : 1'b0 ; */ + +#define SYSTEM_RSA_MEM_FORCE_PD (BIT(2)) +#define SYSTEM_RSA_MEM_FORCE_PD_M (BIT(2)) +#define SYSTEM_RSA_MEM_FORCE_PD_V 0x1 +#define SYSTEM_RSA_MEM_FORCE_PD_S 2 + +/* SYSTEM_RSA_MEM_FORCE_PU : R/W [1] : 1'b0 ; */ + +#define SYSTEM_RSA_MEM_FORCE_PU (BIT(1)) +#define SYSTEM_RSA_MEM_FORCE_PU_M (BIT(1)) +#define SYSTEM_RSA_MEM_FORCE_PU_V 0x1 +#define SYSTEM_RSA_MEM_FORCE_PU_S 1 + +/* SYSTEM_RSA_MEM_PD : R/W [0] : 1'b1 ; */ + +#define SYSTEM_RSA_MEM_PD (BIT(0)) +#define SYSTEM_RSA_MEM_PD_M (BIT(0)) +#define SYSTEM_RSA_MEM_PD_V 0x1 +#define SYSTEM_RSA_MEM_PD_S 0 + +#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x03c) + +/* SYSTEM_EDMA_RESET : R/W [1] : 1'b0 ; */ + +#define SYSTEM_EDMA_RESET (BIT(1)) +#define SYSTEM_EDMA_RESET_M (BIT(1)) +#define SYSTEM_EDMA_RESET_V 0x1 +#define SYSTEM_EDMA_RESET_S 1 + +/* SYSTEM_EDMA_CLK_ON : R/W [0] : 1'b1 ; */ + +#define SYSTEM_EDMA_CLK_ON (BIT(0)) +#define SYSTEM_EDMA_CLK_ON_M (BIT(0)) +#define SYSTEM_EDMA_CLK_ON_V 0x1 +#define SYSTEM_EDMA_CLK_ON_S 0 + +#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x040) + +/* SYSTEM_DCACHE_RESET : R/W [3] : 1'b0 ; */ + +#define SYSTEM_DCACHE_RESET (BIT(3)) +#define SYSTEM_DCACHE_RESET_M (BIT(3)) +#define SYSTEM_DCACHE_RESET_V 0x1 +#define SYSTEM_DCACHE_RESET_S 3 + +/* SYSTEM_DCACHE_CLK_ON : R/W [2] : 1'b1 ; */ + +#define SYSTEM_DCACHE_CLK_ON (BIT(2)) +#define SYSTEM_DCACHE_CLK_ON_M (BIT(2)) +#define SYSTEM_DCACHE_CLK_ON_V 0x1 +#define SYSTEM_DCACHE_CLK_ON_S 2 + +/* SYSTEM_ICACHE_RESET : R/W [1] : 1'b0 ; */ + +#define SYSTEM_ICACHE_RESET (BIT(1)) +#define SYSTEM_ICACHE_RESET_M (BIT(1)) +#define SYSTEM_ICACHE_RESET_V 0x1 +#define SYSTEM_ICACHE_RESET_S 1 + +/* SYSTEM_ICACHE_CLK_ON : R/W [0] : 1'b1 ; */ + +#define SYSTEM_ICACHE_CLK_ON (BIT(0)) +#define SYSTEM_ICACHE_CLK_ON_M (BIT(0)) +#define SYSTEM_ICACHE_CLK_ON_V 0x1 +#define SYSTEM_ICACHE_CLK_ON_S 0 + +#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x044) + +/* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W [3] : 1'b0 ; */ + +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(3)) +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 + +/* SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W [2] : 1'b0 ; */ + +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (BIT(2)) +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x1 +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 + +/* SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W [1] : 1'b0 ; */ + +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (BIT(1)) +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x1 +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 + +/* SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W [0] : 1'b0 ; */ + +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (BIT(0)) +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x1 +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0 + +#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x048) + +/* SYSTEM_RTC_MEM_CRC_FINISH : RO [31] : 1'b0 ; */ + +#define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31)) +#define SYSTEM_RTC_MEM_CRC_FINISH_M (BIT(31)) +#define SYSTEM_RTC_MEM_CRC_FINISH_V 0x1 +#define SYSTEM_RTC_MEM_CRC_FINISH_S 31 + +/* SYSTEM_RTC_MEM_CRC_LEN : R/W [30:20] : 11'h7ff ; */ + +#define SYSTEM_RTC_MEM_CRC_LEN 0x000007ff +#define SYSTEM_RTC_MEM_CRC_LEN_M (SYSTEM_RTC_MEM_CRC_LEN_V << SYSTEM_RTC_MEM_CRC_LEN_S) +#define SYSTEM_RTC_MEM_CRC_LEN_V 0x7ff +#define SYSTEM_RTC_MEM_CRC_LEN_S 20 + +/* SYSTEM_RTC_MEM_CRC_ADDR : R/W [19:9] : 11'h0 ; */ + +#define SYSTEM_RTC_MEM_CRC_ADDR 0x000007ff +#define SYSTEM_RTC_MEM_CRC_ADDR_M (SYSTEM_RTC_MEM_CRC_ADDR_V << SYSTEM_RTC_MEM_CRC_ADDR_S) +#define SYSTEM_RTC_MEM_CRC_ADDR_V 0x7ff +#define SYSTEM_RTC_MEM_CRC_ADDR_S 9 + +/* SYSTEM_RTC_MEM_CRC_START : R/W [8] : 1'b0 ; */ + +#define SYSTEM_RTC_MEM_CRC_START (BIT(8)) +#define SYSTEM_RTC_MEM_CRC_START_M (BIT(8)) +#define SYSTEM_RTC_MEM_CRC_START_V 0x1 +#define SYSTEM_RTC_MEM_CRC_START_S 8 + +#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x04c) + +/* SYSTEM_RTC_MEM_CRC_RES : RO [31:0] : 32'b0 ; */ + +#define SYSTEM_RTC_MEM_CRC_RES 0xffffffff +#define SYSTEM_RTC_MEM_CRC_RES_M (SYSTEM_RTC_MEM_CRC_RES_V << SYSTEM_RTC_MEM_CRC_RES_S) +#define SYSTEM_RTC_MEM_CRC_RES_V 0xffffffff +#define SYSTEM_RTC_MEM_CRC_RES_S 0 + +#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x050) + +/* SYSTEM_REDUNDANT_ECO_RESULT : RO [1] : 1'b0 ; */ + +#define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1)) +#define SYSTEM_REDUNDANT_ECO_RESULT_M (BIT(1)) +#define SYSTEM_REDUNDANT_ECO_RESULT_V 0x1 +#define SYSTEM_REDUNDANT_ECO_RESULT_S 1 + +/* SYSTEM_REDUNDANT_ECO_DRIVE : R/W [0] : 1'b0 ; */ + +#define SYSTEM_REDUNDANT_ECO_DRIVE (BIT(0)) +#define SYSTEM_REDUNDANT_ECO_DRIVE_M (BIT(0)) +#define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x1 +#define SYSTEM_REDUNDANT_ECO_DRIVE_S 0 + +#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x054) + +/* SYSTEM_CLK_EN : R/W [0] : 1'b1 ; */ + +#define SYSTEM_CLK_EN (BIT(0)) +#define SYSTEM_CLK_EN_M (BIT(0)) +#define SYSTEM_CLK_EN_V 0x1 +#define SYSTEM_CLK_EN_S 0 + +#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x058) + +/* SYSTEM_CLK_DIV_EN : RO [19] : 1'd0 ; */ + +#define SYSTEM_CLK_DIV_EN (BIT(19)) +#define SYSTEM_CLK_DIV_EN_M (BIT(19)) +#define SYSTEM_CLK_DIV_EN_V 0x1 +#define SYSTEM_CLK_DIV_EN_S 19 + +/* SYSTEM_CLK_XTAL_FREQ : RO [18:12] : 7'd0 ; */ + +#define SYSTEM_CLK_XTAL_FREQ 0x0000007f +#define SYSTEM_CLK_XTAL_FREQ_M (SYSTEM_CLK_XTAL_FREQ_V << SYSTEM_CLK_XTAL_FREQ_S) +#define SYSTEM_CLK_XTAL_FREQ_V 0x7f +#define SYSTEM_CLK_XTAL_FREQ_S 12 + +/* SYSTEM_SOC_CLK_SEL : R/W [11:10] : 2'd0 ; */ + +#define SYSTEM_SOC_CLK_SEL 0x00000003 +#define SYSTEM_SOC_CLK_SEL_M (SYSTEM_SOC_CLK_SEL_V << SYSTEM_SOC_CLK_SEL_S) +#define SYSTEM_SOC_CLK_SEL_V 0x3 +#define SYSTEM_SOC_CLK_SEL_S 10 + +/* SYSTEM_PRE_DIV_CNT : R/W [9:0] : 10'h1 ; */ + +#define SYSTEM_PRE_DIV_CNT 0x000003ff +#define SYSTEM_PRE_DIV_CNT_M (SYSTEM_PRE_DIV_CNT_V << SYSTEM_PRE_DIV_CNT_S) +#define SYSTEM_PRE_DIV_CNT_V 0x3ff +#define SYSTEM_PRE_DIV_CNT_S 0 + +#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x05c) + +/* SYSTEM_MEM_VT_SEL : R/W [23:22] : 2'd0 ; */ + +#define SYSTEM_MEM_VT_SEL 0x00000003 +#define SYSTEM_MEM_VT_SEL_M (SYSTEM_MEM_VT_SEL_V << SYSTEM_MEM_VT_SEL_S) +#define SYSTEM_MEM_VT_SEL_V 0x3 +#define SYSTEM_MEM_VT_SEL_S 22 + +/* SYSTEM_MEM_TIMING_ERR_CNT : RO [21:6] : 16'h0 ; */ + +#define SYSTEM_MEM_TIMING_ERR_CNT 0x0000ffff +#define SYSTEM_MEM_TIMING_ERR_CNT_M (SYSTEM_MEM_TIMING_ERR_CNT_V << SYSTEM_MEM_TIMING_ERR_CNT_S) +#define SYSTEM_MEM_TIMING_ERR_CNT_V 0xffff +#define SYSTEM_MEM_TIMING_ERR_CNT_S 6 + +/* SYSTEM_MEM_PVT_MONITOR_EN : R/W [5] : 1'b0 ; */ + +#define SYSTEM_MEM_PVT_MONITOR_EN (BIT(5)) +#define SYSTEM_MEM_PVT_MONITOR_EN_M (BIT(5)) +#define SYSTEM_MEM_PVT_MONITOR_EN_V 0x1 +#define SYSTEM_MEM_PVT_MONITOR_EN_S 5 + +/* SYSTEM_MEM_ERR_CNT_CLR : WO [4] : 1'b0 ; */ + +#define SYSTEM_MEM_ERR_CNT_CLR (BIT(4)) +#define SYSTEM_MEM_ERR_CNT_CLR_M (BIT(4)) +#define SYSTEM_MEM_ERR_CNT_CLR_V 0x1 +#define SYSTEM_MEM_ERR_CNT_CLR_S 4 + +/* SYSTEM_MEM_PATH_LEN : R/W [3:0] : 4'h3 ; */ + +#define SYSTEM_MEM_PATH_LEN 0x0000000f +#define SYSTEM_MEM_PATH_LEN_M (SYSTEM_MEM_PATH_LEN_V << SYSTEM_MEM_PATH_LEN_S) +#define SYSTEM_MEM_PATH_LEN_V 0xf +#define SYSTEM_MEM_PATH_LEN_S 0 + +#define SYSTEM_COMB_PVT_LVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x060) + +/* SYSTEM_COMB_PVT_MONITOR_EN_LVT : R/W [6] : 1'b0 ; */ + +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_M (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_V 0x1 +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_S 6 + +/* SYSTEM_COMB_ERR_CNT_CLR_LVT : WO [5] : 1'b0 ; */ + +#define SYSTEM_COMB_ERR_CNT_CLR_LVT (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_LVT_M (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_LVT_V 0x1 +#define SYSTEM_COMB_ERR_CNT_CLR_LVT_S 5 + +/* SYSTEM_COMB_PATH_LEN_LVT : R/W [4:0] : 5'h3 ; */ + +#define SYSTEM_COMB_PATH_LEN_LVT 0x0000001f +#define SYSTEM_COMB_PATH_LEN_LVT_M (SYSTEM_COMB_PATH_LEN_LVT_V << SYSTEM_COMB_PATH_LEN_LVT_S) +#define SYSTEM_COMB_PATH_LEN_LVT_V 0x1f +#define SYSTEM_COMB_PATH_LEN_LVT_S 0 + +#define SYSTEM_COMB_PVT_NVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x064) + +/* SYSTEM_COMB_PVT_MONITOR_EN_NVT : R/W [6] : 1'b0 ; */ + +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_M (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_V 0x1 +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_S 6 + +/* SYSTEM_COMB_ERR_CNT_CLR_NVT : WO [5] : 1'b0 ; */ + +#define SYSTEM_COMB_ERR_CNT_CLR_NVT (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_NVT_M (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_NVT_V 0x1 +#define SYSTEM_COMB_ERR_CNT_CLR_NVT_S 5 + +/* SYSTEM_COMB_PATH_LEN_NVT : R/W [4:0] : 5'h3 ; */ + +#define SYSTEM_COMB_PATH_LEN_NVT 0x0000001f +#define SYSTEM_COMB_PATH_LEN_NVT_M (SYSTEM_COMB_PATH_LEN_NVT_V << SYSTEM_COMB_PATH_LEN_NVT_S) +#define SYSTEM_COMB_PATH_LEN_NVT_V 0x1f +#define SYSTEM_COMB_PATH_LEN_NVT_S 0 + +#define SYSTEM_COMB_PVT_HVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x068) + +/* SYSTEM_COMB_PVT_MONITOR_EN_HVT : R/W [6] : 1'b0 ; */ + +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_M (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_V 0x1 +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_S 6 + +/* SYSTEM_COMB_ERR_CNT_CLR_HVT : WO [5] : 1'b0 ; */ + +#define SYSTEM_COMB_ERR_CNT_CLR_HVT (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_HVT_M (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_HVT_V 0x1 +#define SYSTEM_COMB_ERR_CNT_CLR_HVT_S 5 + +/* SYSTEM_COMB_PATH_LEN_HVT : R/W [4:0] : 5'h3 ; */ + +#define SYSTEM_COMB_PATH_LEN_HVT 0x0000001f +#define SYSTEM_COMB_PATH_LEN_HVT_M (SYSTEM_COMB_PATH_LEN_HVT_V << SYSTEM_COMB_PATH_LEN_HVT_S) +#define SYSTEM_COMB_PATH_LEN_HVT_V 0x1f +#define SYSTEM_COMB_PATH_LEN_HVT_S 0 + +#define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x06c) + +/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 : RO [15:0] : 16'h0 ; */ + +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 0x0000ffff +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_M (SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V << SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V 0xffff +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S 0 + +#define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x070) + +/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 : RO [15:0] : 16'h0 ; */ + +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 0x0000ffff +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_M (SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V << SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V 0xffff +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S 0 + +#define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x074) + +/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 : RO [15:0] : 16'h0 ; */ + +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 0x0000ffff +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_M (SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V << SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V 0xffff +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S 0 + +#define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x078) + +/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 : RO [15:0] : 16'h0 ; */ + +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 0x0000ffff +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_M (SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V << SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V 0xffff +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S 0 + +#define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x07c) + +/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 : RO [15:0] : 16'h0 ; */ + +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 0x0000ffff +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_M (SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V << SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V 0xffff +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S 0 + +#define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x080) + +/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 : RO [15:0] : 16'h0 ; */ + +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 0x0000ffff +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_M (SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V << SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V 0xffff +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S 0 + +#define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x084) + +/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 : RO [15:0] : 16'h0 ; */ + +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 0x0000ffff +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_M (SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V << SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V 0xffff +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S 0 + +#define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x088) + +/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 : RO [15:0] : 16'h0 ; */ + +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 0x0000ffff +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_M (SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V << SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V 0xffff +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S 0 + +#define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x08c) + +/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 : RO [15:0] : 16'h0 ; */ + +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 0x0000ffff +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_M (SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V << SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V 0xffff +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S 0 + +#define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x090) + +/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 : RO [15:0] : 16'h0 ; */ + +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 0x0000ffff +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_M (SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V << SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V 0xffff +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S 0 + +#define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x094) + +/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 : RO [15:0] : 16'h0 ; */ + +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 0x0000ffff +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_M (SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V << SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V 0xffff +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S 0 + +#define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x098) + +/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 : RO [15:0] : 16'h0 ; */ + +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 0x0000ffff +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_M (SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V << SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V 0xffff +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S 0 + +#define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0xffc) + +/* SYSTEM_DATE : R/W [27:0] : 28'h2007150 ; */ + +#define SYSTEM_DATE 0x0fffffff +#define SYSTEM_DATE_M (SYSTEM_DATE_V << SYSTEM_DATE_S) +#define SYSTEM_DATE_V 0xfffffff +#define SYSTEM_DATE_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SYSTEM_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_systimer.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_systimer.h new file mode 100644 index 0000000000..7d32e04fb1 --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_systimer.h @@ -0,0 +1,587 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/esp32c3_systimer.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SYSTIMER_H +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SYSTIMER_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SYS_TIMER_SYSTIMER_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0000) +/* SYS_TIMER_CLK_EN : R/W [31] : 1'b0 ; */ + +/* Description: register file clk gating */ + +#define SYS_TIMER_CLK_EN (BIT(31)) +#define SYS_TIMER_CLK_EN_M (BIT(31)) +#define SYS_TIMER_CLK_EN_V 0x1 +#define SYS_TIMER_CLK_EN_S 31 + +/* SYS_TIMER_TIMER_UNIT0_WORK_EN : R/W [30] : 1'b1 ; */ + +/* Description: timer unit0 work enable */ + +#define SYS_TIMER_TIMER_UNIT0_WORK_EN (BIT(30)) +#define SYS_TIMER_TIMER_UNIT0_WORK_EN_M (BIT(30)) +#define SYS_TIMER_TIMER_UNIT0_WORK_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_WORK_EN_S 30 + +/* SYS_TIMER_TIMER_UNIT1_WORK_EN : R/W [29] : 1'b0 ; */ + +/* Description: timer unit1 work enable */ + +#define SYS_TIMER_TIMER_UNIT1_WORK_EN (BIT(29)) +#define SYS_TIMER_TIMER_UNIT1_WORK_EN_M (BIT(29)) +#define SYS_TIMER_TIMER_UNIT1_WORK_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_WORK_EN_S 29 + +/* SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W [28] : 1'b0 ; */ + +/* Description: If timer unit0 is stalled when core0 stalled */ + +#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) +#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_M (BIT(28)) +#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 + +/* SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W [27] : 1'b0 ; */ + +/* Description: If timer unit0 is stalled when core1 stalled */ + +#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) +#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_M (BIT(27)) +#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 + +/* SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W [26] : 1'b1 ; */ + +/* Description: If timer unit1 is stalled when core0 stalled */ + +#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) +#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_M (BIT(26)) +#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 + +/* SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W [25] : 1'b1 ; */ + +/* Description: If timer unit1 is stalled when core1 stalled */ + +#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) +#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_M (BIT(25)) +#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 + +/* SYS_TIMER_TARGET0_WORK_EN : R/W [24] : 1'b0 ; */ + +/* Description: target0 work enable */ + +#define SYS_TIMER_TARGET0_WORK_EN (BIT(24)) +#define SYS_TIMER_TARGET0_WORK_EN_M (BIT(24)) +#define SYS_TIMER_TARGET0_WORK_EN_V 0x1 +#define SYS_TIMER_TARGET0_WORK_EN_S 24 + +/* SYS_TIMER_TARGET1_WORK_EN : R/W [23] : 1'b0 ; */ + +/* Description: target1 work enable */ + +#define SYS_TIMER_TARGET1_WORK_EN (BIT(23)) +#define SYS_TIMER_TARGET1_WORK_EN_M (BIT(23)) +#define SYS_TIMER_TARGET1_WORK_EN_V 0x1 +#define SYS_TIMER_TARGET1_WORK_EN_S 23 + +/* SYS_TIMER_TARGET2_WORK_EN : R/W [22] : 1'b0 ; */ + +/* Description: target2 work enable */ + +#define SYS_TIMER_TARGET2_WORK_EN (BIT(22)) +#define SYS_TIMER_TARGET2_WORK_EN_M (BIT(22)) +#define SYS_TIMER_TARGET2_WORK_EN_V 0x1 +#define SYS_TIMER_TARGET2_WORK_EN_S 22 + +/* SYS_TIMER_SYSTIMER_CLK_FO : R/W [0] : 1'b0 ; */ + +/* Description: systimer clock force on */ + +#define SYS_TIMER_SYSTIMER_CLK_FO (BIT(0)) +#define SYS_TIMER_SYSTIMER_CLK_FO_M (BIT(0)) +#define SYS_TIMER_SYSTIMER_CLK_FO_V 0x1 +#define SYS_TIMER_SYSTIMER_CLK_FO_S 0 + +#define SYS_TIMER_SYSTIMER_UNIT0_OP_REG (DR_REG_SYS_TIMER_BASE + 0x0004) + +/* SYS_TIMER_TIMER_UNIT0_UPDATE : WT [30] : 1'b0 ; */ + +/* Description: update timer_unit0 */ + +#define SYS_TIMER_TIMER_UNIT0_UPDATE (BIT(30)) +#define SYS_TIMER_TIMER_UNIT0_UPDATE_M (BIT(30)) +#define SYS_TIMER_TIMER_UNIT0_UPDATE_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_UPDATE_S 30 + +/* SYS_TIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC [29] : 1'b0 ; */ + +#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) +#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_M (BIT(29)) +#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_S 29 + +#define SYS_TIMER_SYSTIMER_UNIT1_OP_REG (DR_REG_SYS_TIMER_BASE + 0x0008) + +/* SYS_TIMER_TIMER_UNIT1_UPDATE : WT [30] : 1'b0 ; */ + +/* Description: update timer unit1 */ + +#define SYS_TIMER_TIMER_UNIT1_UPDATE (BIT(30)) +#define SYS_TIMER_TIMER_UNIT1_UPDATE_M (BIT(30)) +#define SYS_TIMER_TIMER_UNIT1_UPDATE_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_UPDATE_S 30 + +/* SYS_TIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC [29] : 1'b0 ; */ + +/* Description: timer value is sync and valid */ + +#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) +#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_M (BIT(29)) +#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_S 29 + +#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0x000c) + +/* SYS_TIMER_TIMER_UNIT0_LOAD_HI : R/W [19:0] : 20'd0 ; */ + +/* Description: timer unit0 load high 32 bit */ + +#define SYS_TIMER_TIMER_UNIT0_LOAD_HI 0x000fffff +#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT0_LOAD_HI_V)<<(SYS_TIMER_TIMER_UNIT0_LOAD_HI_S)) +#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_V 0xfffff +#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_S 0 + +#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0010) + +/* SYS_TIMER_TIMER_UNIT0_LOAD_LO : R/W [31:0] : 32'd0 ; */ + +/* Description: timer unit0 load low 32 bit */ + +#define SYS_TIMER_TIMER_UNIT0_LOAD_LO 0xffffffff +#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT0_LOAD_LO_V)<<(SYS_TIMER_TIMER_UNIT0_LOAD_LO_S)) +#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_V 0xffffffff +#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_S 0 + +#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0014) + +/* SYS_TIMER_TIMER_UNIT1_LOAD_HI : R/W [19:0] : 20'd0 ; */ + +/* Description: timer unit1 load high 32 bit */ + +#define SYS_TIMER_TIMER_UNIT1_LOAD_HI 0x000fffff +#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT1_LOAD_HI_V)<<(SYS_TIMER_TIMER_UNIT1_LOAD_HI_S)) +#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_V 0xfffff +#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_S 0 + +#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0018) + +/* SYS_TIMER_TIMER_UNIT1_LOAD_LO : R/W [31:0] : 32'd0 ; */ + +/* Description: timer unit1 load low 32 bit */ + +#define SYS_TIMER_TIMER_UNIT1_LOAD_LO 0xffffffff +#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT1_LOAD_LO_V)<<(SYS_TIMER_TIMER_UNIT1_LOAD_LO_S)) +#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_V 0xffffffff +#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_S 0 + +#define SYS_TIMER_SYSTIMER_TARGET0_HI_REG (DR_REG_SYS_TIMER_BASE + 0x001c) + +/* SYS_TIMER_TIMER_TARGET0_HI : R/W [19:0] : 20'd0 ; */ + +/* Description: timer taget0 high 32 bit */ + +#define SYS_TIMER_TIMER_TARGET0_HI 0x000fffff +#define SYS_TIMER_TIMER_TARGET0_HI_M ((SYS_TIMER_TIMER_TARGET0_HI_V)<<(SYS_TIMER_TIMER_TARGET0_HI_S)) +#define SYS_TIMER_TIMER_TARGET0_HI_V 0xfffff +#define SYS_TIMER_TIMER_TARGET0_HI_S 0 + +#define SYS_TIMER_SYSTIMER_TARGET0_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0020) + +/* SYS_TIMER_TIMER_TARGET0_LO : R/W [31:0] : 32'd0 ; */ + +/* Description: timer taget0 low 32 bit */ + +#define SYS_TIMER_TIMER_TARGET0_LO 0xffffffff +#define SYS_TIMER_TIMER_TARGET0_LO_M ((SYS_TIMER_TIMER_TARGET0_LO_V)<<(SYS_TIMER_TIMER_TARGET0_LO_S)) +#define SYS_TIMER_TIMER_TARGET0_LO_V 0xffffffff +#define SYS_TIMER_TIMER_TARGET0_LO_S 0 + +#define SYS_TIMER_SYSTIMER_TARGET1_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0024) + +/* SYS_TIMER_TIMER_TARGET1_HI : R/W [19:0] : 20'd0 ; */ + +/* Description: timer taget1 high 32 bit */ + +#define SYS_TIMER_TIMER_TARGET1_HI 0x000fffff +#define SYS_TIMER_TIMER_TARGET1_HI_M ((SYS_TIMER_TIMER_TARGET1_HI_V)<<(SYS_TIMER_TIMER_TARGET1_HI_S)) +#define SYS_TIMER_TIMER_TARGET1_HI_V 0xfffff +#define SYS_TIMER_TIMER_TARGET1_HI_S 0 + +#define SYS_TIMER_SYSTIMER_TARGET1_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0028) + +/* SYS_TIMER_TIMER_TARGET1_LO : R/W [31:0] : 32'd0 ; */ + +/* Description: timer taget1 low 32 bit */ + +#define SYS_TIMER_TIMER_TARGET1_LO 0xffffffff +#define SYS_TIMER_TIMER_TARGET1_LO_M ((SYS_TIMER_TIMER_TARGET1_LO_V)<<(SYS_TIMER_TIMER_TARGET1_LO_S)) +#define SYS_TIMER_TIMER_TARGET1_LO_V 0xffffffff +#define SYS_TIMER_TIMER_TARGET1_LO_S 0 + +#define SYS_TIMER_SYSTIMER_TARGET2_HI_REG (DR_REG_SYS_TIMER_BASE + 0x002c) + +/* SYS_TIMER_TIMER_TARGET2_HI : R/W [19:0] : 20'd0 ; */ + +/* Description: timer taget2 high 32 bit */ + +#define SYS_TIMER_TIMER_TARGET2_HI 0x000fffff +#define SYS_TIMER_TIMER_TARGET2_HI_M ((SYS_TIMER_TIMER_TARGET2_HI_V)<<(SYS_TIMER_TIMER_TARGET2_HI_S)) +#define SYS_TIMER_TIMER_TARGET2_HI_V 0xfffff +#define SYS_TIMER_TIMER_TARGET2_HI_S 0 + +#define SYS_TIMER_SYSTIMER_TARGET2_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0030) + +/* SYS_TIMER_TIMER_TARGET2_LO : R/W [31:0] : 32'd0 ; */ + +/* Description: timer taget2 low 32 bit */ + +#define SYS_TIMER_TIMER_TARGET2_LO 0xffffffff +#define SYS_TIMER_TIMER_TARGET2_LO_M ((SYS_TIMER_TIMER_TARGET2_LO_V)<<(SYS_TIMER_TIMER_TARGET2_LO_S)) +#define SYS_TIMER_TIMER_TARGET2_LO_V 0xffffffff +#define SYS_TIMER_TIMER_TARGET2_LO_S 0 + +#define SYS_TIMER_SYSTIMER_TARGET0_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0034) + +/* SYS_TIMER_TARGET0_TIMER_UNIT_SEL : R/W [31] : 1'b0 ; */ + +/* Description: select which unit to compare */ + +#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) +#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_M (BIT(31)) +#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_V 0x1 +#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_S 31 + +/* SYS_TIMER_TARGET0_PERIOD_MODE : R/W [30] : 1'b0 ; */ + +/* Description: Set target0 to period mode */ + +#define SYS_TIMER_TARGET0_PERIOD_MODE (BIT(30)) +#define SYS_TIMER_TARGET0_PERIOD_MODE_M (BIT(30)) +#define SYS_TIMER_TARGET0_PERIOD_MODE_V 0x1 +#define SYS_TIMER_TARGET0_PERIOD_MODE_S 30 + +/* SYS_TIMER_TARGET0_PERIOD : R/W [25:0] : 26'h0 ; */ + +/* Description: target0 period */ + +#define SYS_TIMER_TARGET0_PERIOD 0x03ffffff +#define SYS_TIMER_TARGET0_PERIOD_M ((SYS_TIMER_TARGET0_PERIOD_V)<<(SYS_TIMER_TARGET0_PERIOD_S)) +#define SYS_TIMER_TARGET0_PERIOD_V 0x3ffffff +#define SYS_TIMER_TARGET0_PERIOD_S 0 + +#define SYS_TIMER_SYSTIMER_TARGET1_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0038) + +/* SYS_TIMER_TARGET1_TIMER_UNIT_SEL : R/W [31] : 1'b0 ; */ + +/* Description: select which unit to compare */ + +#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) +#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_M (BIT(31)) +#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_V 0x1 +#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_S 31 + +/* SYS_TIMER_TARGET1_PERIOD_MODE : R/W [30] : 1'b0 ; */ + +/* Description: Set target1 to period mode */ + +#define SYS_TIMER_TARGET1_PERIOD_MODE (BIT(30)) +#define SYS_TIMER_TARGET1_PERIOD_MODE_M (BIT(30)) +#define SYS_TIMER_TARGET1_PERIOD_MODE_V 0x1 +#define SYS_TIMER_TARGET1_PERIOD_MODE_S 30 + +/* SYS_TIMER_TARGET1_PERIOD : R/W [25:0] : 26'h0 ; */ + +/* Description: target1 period */ + +#define SYS_TIMER_TARGET1_PERIOD 0x03ffffff +#define SYS_TIMER_TARGET1_PERIOD_M ((SYS_TIMER_TARGET1_PERIOD_V)<<(SYS_TIMER_TARGET1_PERIOD_S)) +#define SYS_TIMER_TARGET1_PERIOD_V 0x3ffffff +#define SYS_TIMER_TARGET1_PERIOD_S 0 + +#define SYS_TIMER_SYSTIMER_TARGET2_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x003c) + +/* SYS_TIMER_TARGET2_TIMER_UNIT_SEL : R/W [31] : 1'b0 ; */ + +/* Description: select which unit to compare */ + +#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) +#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_M (BIT(31)) +#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_V 0x1 +#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_S 31 + +/* SYS_TIMER_TARGET2_PERIOD_MODE : R/W [30] : 1'b0 ; */ + +/* Description: Set target2 to period mode */ + +#define SYS_TIMER_TARGET2_PERIOD_MODE (BIT(30)) +#define SYS_TIMER_TARGET2_PERIOD_MODE_M (BIT(30)) +#define SYS_TIMER_TARGET2_PERIOD_MODE_V 0x1 +#define SYS_TIMER_TARGET2_PERIOD_MODE_S 30 + +/* SYS_TIMER_TARGET2_PERIOD : R/W [25:0] : 26'h0 ; */ + +/* Description: target2 period */ + +#define SYS_TIMER_TARGET2_PERIOD 0x03ffffff +#define SYS_TIMER_TARGET2_PERIOD_M ((SYS_TIMER_TARGET2_PERIOD_V)<<(SYS_TIMER_TARGET2_PERIOD_S)) +#define SYS_TIMER_TARGET2_PERIOD_V 0x3ffffff +#define SYS_TIMER_TARGET2_PERIOD_S 0 + +#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0040) + +/* SYS_TIMER_TIMER_UNIT0_VALUE_HI : RO [19:0] : 20'd0 ; */ + +/* Description: timer read value high 32bit */ + +#define SYS_TIMER_TIMER_UNIT0_VALUE_HI 0x000fffff +#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT0_VALUE_HI_V)<<(SYS_TIMER_TIMER_UNIT0_VALUE_HI_S)) +#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_V 0xfffff +#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_S 0 + +#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0044) + +/* SYS_TIMER_TIMER_UNIT0_VALUE_LO : RO [31:0] : 32'd0 ; */ + +/* Description: timer read value low 32bit */ + +#define SYS_TIMER_TIMER_UNIT0_VALUE_LO 0xffffffff +#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT0_VALUE_LO_V)<<(SYS_TIMER_TIMER_UNIT0_VALUE_LO_S)) +#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_V 0xffffffff +#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_S 0 + +#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0048) + +/* SYS_TIMER_TIMER_UNIT1_VALUE_HI : RO [19:0] : 20'd0 ; */ + +/* Description: timer read value high 32bit */ + +#define SYS_TIMER_TIMER_UNIT1_VALUE_HI 0x000fffff +#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT1_VALUE_HI_V)<<(SYS_TIMER_TIMER_UNIT1_VALUE_HI_S)) +#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_V 0xfffff +#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_S 0 + +#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x004c) + +/* SYS_TIMER_TIMER_UNIT1_VALUE_LO : RO [31:0] : 32'd0 ; */ + +/* Description: timer read value low 32bit */ + +#define SYS_TIMER_TIMER_UNIT1_VALUE_LO 0xffffffff +#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT1_VALUE_LO_V)<<(SYS_TIMER_TIMER_UNIT1_VALUE_LO_S)) +#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_V 0xffffffff +#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_S 0 + +#define SYS_TIMER_SYSTIMER_COMP0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0050) + +/* SYS_TIMER_TIMER_COMP0_LOAD : WT [0] : 1'b0 ; */ + +/* Description: timer comp0 load value */ + +#define SYS_TIMER_TIMER_COMP0_LOAD (BIT(0)) +#define SYS_TIMER_TIMER_COMP0_LOAD_M (BIT(0)) +#define SYS_TIMER_TIMER_COMP0_LOAD_V 0x1 +#define SYS_TIMER_TIMER_COMP0_LOAD_S 0 + +#define SYS_TIMER_SYSTIMER_COMP1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0054) + +/* SYS_TIMER_TIMER_COMP1_LOAD : WT [0] : 1'b0 ; */ + +/* Description: timer comp1 load value */ + +#define SYS_TIMER_TIMER_COMP1_LOAD (BIT(0)) +#define SYS_TIMER_TIMER_COMP1_LOAD_M (BIT(0)) +#define SYS_TIMER_TIMER_COMP1_LOAD_V 0x1 +#define SYS_TIMER_TIMER_COMP1_LOAD_S 0 + +#define SYS_TIMER_SYSTIMER_COMP2_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0058) + +/* SYS_TIMER_TIMER_COMP2_LOAD : WT [0] : 1'b0 ; */ + +/* Description: timer comp2 load value */ + +#define SYS_TIMER_TIMER_COMP2_LOAD (BIT(0)) +#define SYS_TIMER_TIMER_COMP2_LOAD_M (BIT(0)) +#define SYS_TIMER_TIMER_COMP2_LOAD_V 0x1 +#define SYS_TIMER_TIMER_COMP2_LOAD_S 0 + +#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x005c) + +/* SYS_TIMER_TIMER_UNIT0_LOAD : WT [0] : 1'b0 ; */ + +/* Description: timer unit0 load value */ + +#define SYS_TIMER_TIMER_UNIT0_LOAD (BIT(0)) +#define SYS_TIMER_TIMER_UNIT0_LOAD_M (BIT(0)) +#define SYS_TIMER_TIMER_UNIT0_LOAD_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_LOAD_S 0 + +#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0060) + +/* SYS_TIMER_TIMER_UNIT1_LOAD : WT [0] : 1'b0 ; */ + +/* Description: timer unit1 load value */ + +#define SYS_TIMER_TIMER_UNIT1_LOAD (BIT(0)) +#define SYS_TIMER_TIMER_UNIT1_LOAD_M (BIT(0)) +#define SYS_TIMER_TIMER_UNIT1_LOAD_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_LOAD_S 0 + +#define SYS_TIMER_SYSTIMER_INT_ENA_REG (DR_REG_SYS_TIMER_BASE + 0x0064) + +/* SYS_TIMER_TARGET2_INT_ENA : R/W [2] : 1'b0 ; */ + +/* Description: interupt2 enable */ + +#define SYS_TIMER_TARGET2_INT_ENA (BIT(2)) +#define SYS_TIMER_TARGET2_INT_ENA_M (BIT(2)) +#define SYS_TIMER_TARGET2_INT_ENA_V 0x1 +#define SYS_TIMER_TARGET2_INT_ENA_S 2 + +/* SYS_TIMER_TARGET1_INT_ENA : R/W [1] : 1'b0 ; */ + +/* Description: interupt1 enable */ + +#define SYS_TIMER_TARGET1_INT_ENA (BIT(1)) +#define SYS_TIMER_TARGET1_INT_ENA_M (BIT(1)) +#define SYS_TIMER_TARGET1_INT_ENA_V 0x1 +#define SYS_TIMER_TARGET1_INT_ENA_S 1 + +/* SYS_TIMER_TARGET0_INT_ENA : R/W [0] : 1'b0 ; */ + +/* Description: interupt0 enable */ + +#define SYS_TIMER_TARGET0_INT_ENA (BIT(0)) +#define SYS_TIMER_TARGET0_INT_ENA_M (BIT(0)) +#define SYS_TIMER_TARGET0_INT_ENA_V 0x1 +#define SYS_TIMER_TARGET0_INT_ENA_S 0 + +#define SYS_TIMER_SYSTIMER_INT_RAW_REG (DR_REG_SYS_TIMER_BASE + 0x0068) + +/* SYS_TIMER_TARGET2_INT_RAW : R/WTC/SS [2] : 1'b0 ; */ + +/* Description: interupt2 raw */ + +#define SYS_TIMER_TARGET2_INT_RAW (BIT(2)) +#define SYS_TIMER_TARGET2_INT_RAW_M (BIT(2)) +#define SYS_TIMER_TARGET2_INT_RAW_V 0x1 +#define SYS_TIMER_TARGET2_INT_RAW_S 2 + +/* SYS_TIMER_TARGET1_INT_RAW : R/WTC/SS [1] : 1'b0 ; */ + +/* Description: interupt1 raw */ + +#define SYS_TIMER_TARGET1_INT_RAW (BIT(1)) +#define SYS_TIMER_TARGET1_INT_RAW_M (BIT(1)) +#define SYS_TIMER_TARGET1_INT_RAW_V 0x1 +#define SYS_TIMER_TARGET1_INT_RAW_S 1 + +/* SYS_TIMER_TARGET0_INT_RAW : R/WTC/SS [0] : 1'b0 ; */ + +/* Description: interupt0 raw */ + +#define SYS_TIMER_TARGET0_INT_RAW (BIT(0)) +#define SYS_TIMER_TARGET0_INT_RAW_M (BIT(0)) +#define SYS_TIMER_TARGET0_INT_RAW_V 0x1 +#define SYS_TIMER_TARGET0_INT_RAW_S 0 + +#define SYS_TIMER_SYSTIMER_INT_CLR_REG (DR_REG_SYS_TIMER_BASE + 0x006c) + +/* SYS_TIMER_TARGET2_INT_CLR : WT [2] : 1'b0 ; */ + +/* Description: interupt2 clear */ + +#define SYS_TIMER_TARGET2_INT_CLR (BIT(2)) +#define SYS_TIMER_TARGET2_INT_CLR_M (BIT(2)) +#define SYS_TIMER_TARGET2_INT_CLR_V 0x1 +#define SYS_TIMER_TARGET2_INT_CLR_S 2 + +/* SYS_TIMER_TARGET1_INT_CLR : WT [1] : 1'b0 ; */ + +/* Description: interupt1 clear */ + +#define SYS_TIMER_TARGET1_INT_CLR (BIT(1)) +#define SYS_TIMER_TARGET1_INT_CLR_M (BIT(1)) +#define SYS_TIMER_TARGET1_INT_CLR_V 0x1 +#define SYS_TIMER_TARGET1_INT_CLR_S 1 + +/* SYS_TIMER_TARGET0_INT_CLR : WT [0] : 1'b0 ; */ + +/* Description: interupt0 clear */ + +#define SYS_TIMER_TARGET0_INT_CLR (BIT(0)) +#define SYS_TIMER_TARGET0_INT_CLR_M (BIT(0)) +#define SYS_TIMER_TARGET0_INT_CLR_V 0x1 +#define SYS_TIMER_TARGET0_INT_CLR_S 0 + +#define SYS_TIMER_SYSTIMER_INT_ST_REG (DR_REG_SYS_TIMER_BASE + 0x0070) + +/* SYS_TIMER_TARGET2_INT_ST : RO [2] : 1'b0 ; */ + +#define SYS_TIMER_TARGET2_INT_ST (BIT(2)) +#define SYS_TIMER_TARGET2_INT_ST_M (BIT(2)) +#define SYS_TIMER_TARGET2_INT_ST_V 0x1 +#define SYS_TIMER_TARGET2_INT_ST_S 2 + +/* SYS_TIMER_TARGET1_INT_ST : RO [1] : 1'b0 ; */ + +#define SYS_TIMER_TARGET1_INT_ST (BIT(1)) +#define SYS_TIMER_TARGET1_INT_ST_M (BIT(1)) +#define SYS_TIMER_TARGET1_INT_ST_V 0x1 +#define SYS_TIMER_TARGET1_INT_ST_S 1 + +/* SYS_TIMER_TARGET0_INT_ST : RO [0] : 1'b0 ; */ + +#define SYS_TIMER_TARGET0_INT_ST (BIT(0)) +#define SYS_TIMER_TARGET0_INT_ST_M (BIT(0)) +#define SYS_TIMER_TARGET0_INT_ST_V 0x1 +#define SYS_TIMER_TARGET0_INT_ST_S 0 + +#define SYS_TIMER_SYSTIMER_DATE_REG (DR_REG_SYS_TIMER_BASE + 0x00fc) + +/* SYS_TIMER_DATE : R/W [31:0] : 28'h2006171 ; */ + +#define SYS_TIMER_DATE 0xffffffff +#define SYS_TIMER_DATE_M ((SYS_TIMER_DATE_V)<<(SYS_TIMER_DATE_S)) +#define SYS_TIMER_DATE_V 0xffffffff +#define SYS_TIMER_DATE_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SYSTIMER_H */ diff --git a/arch/risc-v/src/rv32im/riscv_exception.c b/arch/risc-v/src/rv32im/riscv_exception.c new file mode 100644 index 0000000000..8b908d1fb4 --- /dev/null +++ b/arch/risc-v/src/rv32im/riscv_exception.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * arch/risc-v/src/rv32im/riscv_exception.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "riscv_arch.h" +#include "riscv_internal.h" + +#ifdef CONFIG_DEBUG_INFO +static const char *g_reasons_str[MCAUSE_MAX_EXCEPTION + 1] = +{ + "Instruction address misaligned", + "Instruction access fault", + "Illegal instruction", + "Breakpoint", + "Load address misaligned", + "Load access fault", + "Store/AMO address misaligned", + "Store/AMO access fault", + "Environment call from U-mode", + "Environment call from S-mode", + "Reserved", + "Environment call from M-mode", + "Instruction page fault", + "Load page fault", + "Reserved", + "Store/AMO page fault" +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: riscv_exception + * + * Description: + * This is the exception handler. + * + ****************************************************************************/ + +void riscv_exception(uint32_t mcause, uint32_t *regs) +{ + uint32_t cause = mcause & MCAUSE_INTERRUPT_MASK; + +#ifdef CONFIG_DEBUG_INFO + if (mcause > MCAUSE_MAX_EXCEPTION) + { + _alert("EXCEPTION: Unknown. MCAUSE: %08" PRIx32 "\n", cause); + } + else + { + _alert("EXCEPTION: %s. MCAUSE: %08" PRIx32 "\n", + g_reasons_str[cause], cause); + } +#endif + + _alert("PANIC!!! Exception = %08" PRIx32 "\n", cause); + up_irq_save(); + g_current_regs = regs; + PANIC(); +} + diff --git a/tools/esp32c3/Config.mk b/tools/esp32c3/Config.mk new file mode 100644 index 0000000000..c8ebc374b1 --- /dev/null +++ b/tools/esp32c3/Config.mk @@ -0,0 +1,77 @@ +############################################################################ +# tools/esp32c3/Config.mk +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# These are the macros that will be used in the NuttX make system to compile +# and assemble source files and to insert the resulting object files into an +# archive. These replace the default definitions at tools/Config.mk + +ifdef ESPTOOL_BINDIR + BL_OFFSET=0x0 + PT_OFFSET=0x8000 + BOOTLOADER=$(ESPTOOL_BINDIR)/bootloader.bin + PARTITION_TABLE=$(ESPTOOL_BINDIR)/partition-table.bin + FLASH_BL=$(BL_OFFSET) $(BOOTLOADER) + FLASH_PT=$(PT_OFFSET) $(PARTITION_TABLE) +endif + +ifeq ($(CONFIG_ESP32C3_FLASH_2M),y) + FLASH_SIZE="2MB" +else ifeq ($(CONFIG_ESP32C3_FLASH_4M),y) + FLASH_SIZE="4MB" +else ifeq ($(CONFIG_ESP32C3_FLASH_8M),y) + FLASH_SIZE="8MB" +else ifeq ($(CONFIG_ESP32C3_FLASH_16M),y) + FLASH_SIZE="16MB" +endif + +# POSTBUILD -- Perform post build operations + +define POSTBUILD + $(Q) echo "MKIMAGE: ESP32-C3 binary" + $(Q) if ! esptool.py version 1>/dev/null 2>&1; then \ + echo ""; \ + echo "esptool.py not found. Please run: \"pip install esptool\""; \ + echo "Or run: \"make -C $(TOPDIR)/tools/esp32c3\" to install all IDF tools."; \ + echo ""; \ + echo "Run make again to create the nuttx.bin image."; \ + exit 1; \ + fi + $(Q) if [ -z $(FLASH_SIZE) ]; then \ + echo "Missing Flash memory size configuration for the ESP32-C3 chip."; \ + exit 1; \ + fi + esptool.py --chip esp32c3 elf2image --flash_mode dio --flash_size $(FLASH_SIZE) -o nuttx.bin nuttx + $(Q) echo "Generated: nuttx.bin (ESP32-C3 compatible)" +endef + +# ESPTOOL_BAUD -- Serial port baud rate used when flashing/reading via esptool.py + +ESPTOOL_BAUD ?= 921600 + +# DOWNLOAD -- Download binary image via esptool.py + +define DOWNLOAD + $(Q) if [ -z $(ESPTOOL_PORT) ]; then \ + echo "DOWNLOAD error: Missing serial port device argument."; \ + echo "USAGE: make download ESPTOOL_PORT= [ ESPTOOL_BAUD= ]"; \ + exit 1; \ + fi + esptool.py --chip esp32c3 --port $(ESPTOOL_PORT) --baud $(ESPTOOL_BAUD) write_flash $(FLASH_BL) $(FLASH_PT) 0x10000 $(1).bin +endef diff --git a/tools/esp32c3/Makefile b/tools/esp32c3/Makefile new file mode 100644 index 0000000000..ceea12bd0d --- /dev/null +++ b/tools/esp32c3/Makefile @@ -0,0 +1,63 @@ +############################################################################ +# tools/esp32c3/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +ESP_PATH = ${HOME}/esp + +IDF_PATH = ${ESP_PATH}/esp-idf + +BOOTLOADER_BIN = ${IDF_PATH}/hello_world/build/bootloader/bootloader.bin +PARTITION_TABLE_BIN = ${IDF_PATH}/hello_world/build/partition_table/partition-table.bin + +all: ${IDF_PATH} ${BOOTLOADER_BIN} ${PARTITION_TABLE_BIN} +default: all +.PHONY: clean esp-idf-hello-world + +# Add CFLAGS=-g on the make command line to build debug versions + +CFLAGS = -O2 -Wall + +${IDF_PATH}: + @mkdir -p ${ESP_PATH} + @echo "WARNING:this directory can be automatically removed" > ${ESP_PATH}/README + @cd ${ESP_PATH} && \ + ls esp-idf 1>/dev/null 2>&1 || git clone -b v4.3-beta1 --recursive https://github.com/espressif/esp-idf.git && \ + cd ${IDF_PATH} && \ + ./install.sh + +${IDF_PATH}/hello_world: + @cp -r ${IDF_PATH}/examples/get-started/hello_world ${IDF_PATH}/hello_world + +${IDF_PATH}/hello_world/build: SHELL:=/usr/bin/env bash +${IDF_PATH}/hello_world/build: ${IDF_PATH}/hello_world + @cd ${IDF_PATH} && \ + . export.sh && \ + cd hello_world && \ + idf.py set-target esp32c3 && \ + idf.py menuconfig && \ + echo "CONFIG_ESPTOOLPY_FLASHMODE_DOUT=y" >> sdkconfig && \ + idf.py build + +${BOOTLOADER_BIN}: ${IDF_PATH}/hello_world/build + +${PARTITION_TABLE_BIN}: ${IDF_PATH}/hello_world/build + +clean: + @rm -rf ${HOME}/.espressif + @grep "WARNING:this directory can be automatically removed" ${ESP_PATH}/README 1>/dev/null 2>&1 && rm -rf ${ESP_PATH}; echo