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Fix compiler errors

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@694 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2008-02-16 14:48:35 +00:00
parent 6ab50706bb
commit b125ca88c2
5 changed files with 57 additions and 55 deletions
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4
arch/z80/include/z8/irq.h
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@ -204,7 +204,7 @@
* WARNING: These have only been verified for the Z8F640X family! * WARNING: These have only been verified for the Z8F640X family!
*/ */
#if defined(_Z8ENCORE_F640X) || defined(_Z8ENCORE_640_FAMILY) #ifdef ENCORE_VECTORS
# define Z8_IRQ0_MIN Z8_TIMER2_IRQ # define Z8_IRQ0_MIN Z8_TIMER2_IRQ
# define Z8_IRQ0_BIT(irq) (Z8_ADC_IRQ - (irq)) # define Z8_IRQ0_BIT(irq) (Z8_ADC_IRQ - (irq))
@ -215,7 +215,7 @@
# define Z8_IRQ1_MAX Z8_P0AD_IRQ # define Z8_IRQ1_MAX Z8_P0AD_IRQ
# define Z8_IRQ2_MIN Z8_TIMER3_IRQ # define Z8_IRQ2_MIN Z8_TIMER3_IRQ
# define Z8_IRQ3_BIT(irq) (Z8_C0_IRQ - (irq)) # define Z8_IRQ2_BIT(irq) (Z8_C0_IRQ - (irq))
# define Z8_IRQ2_MAX Z8_C0_IRQ # define Z8_IRQ2_MAX Z8_C0_IRQ
#else #else

3
arch/z80/src/z8/Make.defs
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@ -44,5 +44,6 @@ CMN_CSRCS = up_initialize.c up_allocateheap.c up_createstack.c \
CHIP_SSRCS = z8_vector.S z8_saveusercontext.S z8_restorecontext.S CHIP_SSRCS = z8_vector.S z8_saveusercontext.S z8_restorecontext.S
CHIP_CSRCS = z8_initialstate.c z8_irq.c z8_saveirqcontext.c \ CHIP_CSRCS = z8_initialstate.c z8_irq.c z8_saveirqcontext.c \
z8_schedulesigaction.c z8_sigdeliver.c z8_registerdump.c z8_schedulesigaction.c z8_sigdeliver.c z8_timerisr.c \
z8_registerdump.c

44
arch/z80/src/z8/chip.h
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@ -50,7 +50,7 @@
#ifdef __ASSEMBLY__ #ifdef __ASSEMBLY__
# define _HX(h) %##h # define _HX(h) %##h
#else #else
# define _HX(w) 0x##h # define _HX(h) 0x##h
#endif #endif
/* Memory Map /* Memory Map
@ -78,24 +78,24 @@
/* Timer control register */ /* Timer control register */
#define Z8_TIMERCTL1_TEN _HX(80) /* Bit 7: Timer enabled */ #define Z8_TIMERCTL_TEN _HX(80) /* Bit 7: Timer enabled */
#define Z8_TIMERCTL1_TPOL _HX(40) /* Bit 6: Timer input/output polarity */ #define Z8_TIMERCTL_TPOL _HX(40) /* Bit 6: Timer input/output polarity */
#define Z8_TIMERSCTL_DIV1 _HX(00) /* Bits 3-5: Pre-scale divisor */ #define Z8_TIMERCTL_DIV1 _HX(00) /* Bits 3-5: Pre-scale divisor */
#define Z8_TIMERSCTL_DIV2 _HX(08) #define Z8_TIMERCTL_DIV2 _HX(08)
#define Z8_TIMERSCTL_DIV4 _HX(10) #define Z8_TIMERCTL_DIV4 _HX(10)
#define Z8_TIMERSCTL_DIV8 _HX(18) #define Z8_TIMERCTL_DIV8 _HX(18)
#define Z8_TIMERSCTL_DIV16 _HX(20) #define Z8_TIMERCTL_DIV16 _HX(20)
#define Z8_TIMERSCTL_DIV32 _HX(28) #define Z8_TIMERCTL_DIV32 _HX(28)
#define Z8_TIMERSCTL_DIV64 _HX(30) #define Z8_TIMERCTL_DIV64 _HX(30)
#define Z8_TIMERSCTL_DIV128 _HX(38) #define Z8_TIMERCTL_DIV128 _HX(38)
#define Z8_TIMERSCTL_ONESHOT _HX(00) /* Bits 0-2: Timer mode */ #define Z8_TIMERCTL_ONESHOT _HX(00) /* Bits 0-2: Timer mode */
#define Z8_TIMERSCTL_CONT _HX(01) #define Z8_TIMERCTL_CONT _HX(01)
#define Z8_TIMERSCTL_COUNTER _HX(02) #define Z8_TIMERCTL_COUNTER _HX(02)
#define Z8_TIMERSCTL_PWM _HX(03) #define Z8_TIMERCTL_PWM _HX(03)
#define Z8_TIMERSCTL_CAPTURE _HX(04) #define Z8_TIMERCTL_CAPTURE _HX(04)
#define Z8_TIMERSCTL_COMPARE _HX(05) #define Z8_TIMERCTL_COMPARE _HX(05)
#define Z8_TIMERSCTL_GATED _HX(06) #define Z8_TIMERCTL_GATED _HX(06)
#define Z8_TIMERSCTL_CAPCMP _HX(07) #define Z8_TIMERCTL_CAPCMP _HX(07)
/* Register access macros *********************************************************** /* Register access macros ***********************************************************
* *
@ -106,11 +106,11 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
# define getreg8(a) (a) # define getreg8(a) (a)
# define putreg8(v,a) ((a) = (v)) # define putreg8(v,a) (a) = (v)
# define getreg16(a) (a) # define getreg16(a) (a)
# define putreg16(v,a) ((a) = (v)) # define putreg16(v,a) (a) = (v)
# define getreg32(a) (a) # define getreg32(a) (a)
# define putreg32(v,a) ((a) = (v)) # define putreg32(v,a) (a) = (v)
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
/************************************************************************************ /************************************************************************************

39
arch/z80/src/z8/z8_irq.c
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@ -40,12 +40,11 @@
#include <nuttx/config.h> #include <nuttx/config.h>
#include <sys/types.h> #include <sys/types.h>
#include <ez8.h>
#include <nuttx/arch.h> #include <nuttx/arch.h>
#include <nuttx/irq.h> #include <nuttx/irq.h>
#include <ez8.h>
#include "chip/switch.h" #include "chip/switch.h"
#include "up_internal.h" #include "up_internal.h"
@ -81,13 +80,13 @@ void up_irqinitialize(void)
{ {
/* Clear and disable all interrupts. Set all to priority 0. */ /* Clear and disable all interrupts. Set all to priority 0. */
putreg8(0xff, Z8_IRQ0); putreg8(0xff, IRQ0);
putreg8(0xff, Z8_IRQ1); putreg8(0xff, IRQ1);
putreg8(0xff, Z8_IRQ2); putreg8(0xff, IRQ2);
putreg16(0x0000, Z8_IRQ0_EN); putreg16(0x0000, IRQ0EN);
putreg16(0x0000, Z8_IRQ1_EN); putreg16(0x0000, IRQ1EN);
putreg16(0x0000, Z8_IRQ2_EN); putreg16(0x0000, IRQ2EN);
/* And finally, enable interrupts */ /* And finally, enable interrupts */
@ -164,15 +163,15 @@ void up_disable_irq(int irq)
if (irq < Z8_IRQ0_MAX) if (irq < Z8_IRQ0_MAX)
{ {
putreg8((getreg8(Z8_IRQ0_ENH) & ~Z8_IRQ0_BIT(irq)), Z8_IRQ0_ENH); putreg8((getreg8(IRQ0ENH) & ~Z8_IRQ0_BIT(irq)), IRQ0ENH);
} }
else if (irq < Z8_IRQ1_MAX) else if (irq < Z8_IRQ1_MAX)
{ {
putreg8((getreg8(Z8_IRQ1_ENH) & ~Z8_IRQ1_BIT(irq)), Z8_IRQ1_ENH); putreg8((getreg8(IRQ1ENH) & ~Z8_IRQ1_BIT(irq)), IRQ1ENH);
} }
else if (irq < NR_IRQS) else if (irq < NR_IRQS)
{ {
putreg8((getreg8(Z8_IRQ2_ENH) & ~Z8_IRQ2_BIT(irq)), Z8_IRQ2_ENH); putreg8((getreg8(IRQ2ENH) & ~Z8_IRQ2_BIT(irq)), IRQ2ENH);
} }
} }
} }
@ -199,15 +198,15 @@ void up_enable_irq(int irq)
if (irq < Z8_IRQ0_MAX) if (irq < Z8_IRQ0_MAX)
{ {
putreg8((getreg8(Z8_IRQ0_ENH) | Z8_IRQ0_BIT(irq)), Z8_IRQ0_ENH); putreg8((getreg8(IRQ0ENH) | Z8_IRQ0_BIT(irq)), IRQ0ENH);
} }
else if (irq < Z8_IRQ1_MAX) else if (irq < Z8_IRQ1_MAX)
{ {
putreg8((getreg8(Z8_IRQ1_ENH) | Z8_IRQ1_BIT(irq)), Z8_IRQ1_ENH); putreg8((getreg8(IRQ1ENH) | Z8_IRQ1_BIT(irq)), IRQ1ENH);
} }
else if (irq < NR_IRQS) else if (irq < NR_IRQS)
{ {
putreg8((getreg8(Z8_IRQ2_ENH) | Z8_IRQ2_BIT(irq)), Z8_IRQ2_ENH); putreg8((getreg8(IRQ2ENH) | Z8_IRQ2_BIT(irq)), IRQ2ENH);
} }
} }
} }
@ -233,18 +232,18 @@ void up_maskack_irq(int irq)
if (irq < Z8_IRQ0_MAX) if (irq < Z8_IRQ0_MAX)
{ {
putreg8((getreg8(Z8_IRQ0_ENH) & ~Z8_IRQ0_BIT(irq)), Z8_IRQ0_ENH); putreg8((getreg8(IRQ0ENH) & ~Z8_IRQ0_BIT(irq)), IRQ0ENH);
putreg8(Z8_IRQ0_BIT(irq), Z8_IRQ0); putreg8(Z8_IRQ0_BIT(irq), IRQ0);
} }
else if (irq < Z8_IRQ1_MAX) else if (irq < Z8_IRQ1_MAX)
{ {
putreg8((getreg8(Z8_IRQ1_ENH) & ~Z8_IRQ1_BIT(irq)), Z8_IRQ1_ENH); putreg8((getreg8(IRQ1ENH) & ~Z8_IRQ1_BIT(irq)), IRQ1ENH);
putreg8(Z8_IRQ1_BIT(irq), Z8_IRQ2); putreg8(Z8_IRQ1_BIT(irq), IRQ2);
} }
else if (irq < NR_IRQS) else if (irq < NR_IRQS)
{ {
putreg8((getreg8(Z8_IRQ2_ENH) & ~Z8_IRQ2_BIT(irq)), Z8_IRQ2_ENH); putreg8((getreg8(IRQ2ENH) & ~Z8_IRQ2_BIT(irq)), IRQ2ENH);
putreg8(Z8_IRQ2_BIT(irq), Z8_IRQ2); putreg8(Z8_IRQ2_BIT(irq), IRQ2);
} }
} }
} }

22
arch/z80/src/z8/z8_timerisr.c
View File

@ -41,9 +41,9 @@
#include <sys/types.h> #include <sys/types.h>
#include <debug.h> #include <debug.h>
#include <ez8.h>
#include <nuttx/arch.h> #include <nuttx/arch.h>
#include <ez8.h>
#include "chip/chip.h" #include "chip/chip.h"
#include "clock_internal.h" #include "clock_internal.h"
@ -53,11 +53,6 @@
* Definitions * Definitions
***************************************************************************/ ***************************************************************************/
/* System clock frequency value from ZDS target settings */
extern ROM uint32 __user_frequency;
#define _DEFCLK ((uint32)&__user_frequency)
/*************************************************************************** /***************************************************************************
* Private Types * Private Types
***************************************************************************/ ***************************************************************************/
@ -70,6 +65,10 @@ extern ROM uint32 __user_frequency;
* Public Functions * Public Functions
***************************************************************************/ ***************************************************************************/
/* This function is normally prototyped int the ZiLOG header file sio.h */
extern uint32 get_freq(void);
/*************************************************************************** /***************************************************************************
* Function: up_timerisr * Function: up_timerisr
* *
@ -98,6 +97,8 @@ int up_timerisr(int irq, uint32 *regs)
void up_timerinit(void) void up_timerinit(void)
{ {
uint32 reload;
up_disable_irq(Z8_IRQ_SYSTIMER); up_disable_irq(Z8_IRQ_SYSTIMER);
/* Write to the timer control register to disable the timer, configure /* Write to the timer control register to disable the timer, configure
@ -105,13 +106,13 @@ void up_timerinit(void)
* divide by 4. * divide by 4.
*/ */
putreg8( Z8_TIMERSCTL_DIV4 | Z8_TIMERSCTL_CONT, Z8_TIMER0_CTL); putreg8((Z8_TIMERCTL_DIV4|Z8_TIMERCTL_CONT), T0CTL);
/* Write to the timer high and low byte registers to set a starting /* Write to the timer high and low byte registers to set a starting
* count value (this effects only the first pass in continuous mode) * count value (this effects only the first pass in continuous mode)
*/ */
putreg16(0x0001, Z8_TIMER0_HL); putreg16(0x0001, T0);
/* Write to the timer reload register to set the reload value. /* Write to the timer reload register to set the reload value.
* *
@ -127,13 +128,14 @@ void up_timerinit(void)
* reload_value = system_clock_frequency / 400 * reload_value = system_clock_frequency / 400
*/ */
putreg16(((uint32)_DEFCLK / 400), Z8_TIMER0_R); reload = get_freq() / 400;
putreg16((uint16)reload, T0R);
/* Write to the timer control register to enable the timer and to /* Write to the timer control register to enable the timer and to
* initiate counting * initiate counting
*/ */
putreg8((getreg8(Z8_TIMER0_CTL) | Z8_TIMERCTL_TEN), Z8_TIMER0_CTL); putreg8((getreg8(T0CTL)|Z8_TIMERCTL_TEN), T0CTL);
/* Set the timer priority */ /* Set the timer priority */