diff --git a/arch/arm/include/stm32/chip.h b/arch/arm/include/stm32/chip.h index c4b308996a..f4633631bc 100644 --- a/arch/arm/include/stm32/chip.h +++ b/arch/arm/include/stm32/chip.h @@ -1756,6 +1756,56 @@ # define STM32_NRNG 0 /* No Random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ +#elif defined(CONFIG_ARCH_CHIP_STM32F412CE) /* 144 pin LQFP package, 1MB FLASH, 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 4 /* 16-bit general timers 9, 12, 13, and 14 without DMA */ +# define STM32_NBTIM 0 /* 2 basic timers TIM6 and TIM7 */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 5 /* SPI1-5 */ +# define STM32_NI2S 3 /* I2S1-3 */ +# define STM32_NUSART 6 /* USART1, 2, 3 and 6 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* 2 CAN */ +# define STM32_NSDIO 1 /* One SDIO interface */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 81 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F412ZG) /* 144 pin LQFP package, 1MB FLASH, 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers TIM6 and TIM7 */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 5 /* SPI1-5 */ +# define STM32_NI2S 3 /* I2S1-3 */ +# define STM32_NUSART 6 /* USART1, 2, 3 and 6 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* 2 CAN */ +# define STM32_NSDIO 1 /* One SDIO interface */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 113 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + #elif defined(CONFIG_ARCH_CHIP_STM32F405RG) /* LQFP 64 10x10x1.4 1024Kb FLASH 192Kb SRAM */ # define STM32_NFSMC 0 /* No FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ diff --git a/arch/arm/include/stm32/stm32f40xxx_irq.h b/arch/arm/include/stm32/stm32f40xxx_irq.h index c864f65b91..3fb77643d9 100644 --- a/arch/arm/include/stm32/stm32f40xxx_irq.h +++ b/arch/arm/include/stm32/stm32f40xxx_irq.h @@ -332,7 +332,7 @@ #elif defined(CONFIG_STM32_STM32F429) # define STM32_IRQ_NEXTINT (91) # define NR_IRQS (STM32_IRQ_FIRST+91) -#elif defined(CONFIG_STM32_STM32F446) +#elif defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412) # define STM32_IRQ_NEXTINT (97) # define NR_IRQS (STM32_IRQ_FIRST+97) #elif defined(CONFIG_STM32_STM32F469) @@ -357,10 +357,6 @@ extern "C" #define EXTERN extern #endif -/**************************************************************************************************** - * Public Functions - ****************************************************************************************************/ - #undef EXTERN #ifdef __cplusplus } diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 2ea5e3770a..9095fc2106 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -1006,6 +1006,16 @@ config ARCH_CHIP_STM32F411VE select STM32_STM32F4XXX select STM32_STM32F411 +config ARCH_CHIP_STM32F412CE + bool "STM32F412CE" + select STM32_STM32F4XXX + select STM32_STM32F412 + +config ARCH_CHIP_STM32F412ZG + bool "STM32F412ZG" + select STM32_STM32F4XXX + select STM32_STM32F412 + config ARCH_CHIP_STM32F405RG bool "STM32F405RG" select STM32_STM32F4XXX @@ -1608,6 +1618,28 @@ config STM32_STM32F411 select STM32_HAVE_I2C3 select STM32_HAVE_OTGFS +config STM32_STM32F412 + bool + default n + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_USART2 + select STM32_HAVE_USART6 + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_CAN1 + select STM32_HAVE_ADC1 + select STM32_HAVE_OTGFS + select STM32_HAVE_I2SPLL + config STM32_STM32F405 bool default n diff --git a/arch/arm/src/stm32/hardware/stm32_i2c_v1.h b/arch/arm/src/stm32/hardware/stm32_i2c_v1.h index 6d757fc158..2de8c17d38 100644 --- a/arch/arm/src/stm32/hardware/stm32_i2c_v1.h +++ b/arch/arm/src/stm32/hardware/stm32_i2c_v1.h @@ -54,7 +54,7 @@ #define STM32_I2C_CCR_OFFSET 0x001c /* Clock control register (16-bit) */ #define STM32_I2C_TRISE_OFFSET 0x0020 /* TRISE Register (16-bit) */ #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F446) + defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412) # define STM32_I2C_FLTR_OFFSET 0x0024 /* FLTR Register (16-bit) */ #endif diff --git a/arch/arm/src/stm32/hardware/stm32_pwr.h b/arch/arm/src/stm32/hardware/stm32_pwr.h index 8e309f1df5..1e81437700 100644 --- a/arch/arm/src/stm32/hardware/stm32_pwr.h +++ b/arch/arm/src/stm32/hardware/stm32_pwr.h @@ -93,7 +93,8 @@ #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) # define PWR_CR_FPDS (1 << 9) /* Bit 9: Flash power down in Stop mode */ # if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) + defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) || \ + defined(CONFIG_STM32_STM32F412) # define PWR_CR_ADCDC1 (1 << 13) /* Bit 13: see AN4073 for details */ # define PWR_CR_VOS_MASK (3 << 14) /* Bits 14-15: Regulator voltage scaling output selection */ # define PWR_CR_VOS_SCALE_1 (3 << 14) /* Fmax = 168MHz */ @@ -127,7 +128,7 @@ # define PWR_CR_ODSWEN (1 << 17) /* Over Drive switch enabled */ #endif -#if defined(CONFIG_STM32_STM32F446) +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412) # define PWR_CR_FMSSR (1 << 20) /* Flash Memory Stop while System Run */ # define PWR_CR_FISSR (1 << 21) /* Flash Interface Stop while System Run*/ #endif @@ -154,7 +155,11 @@ defined(CONFIG_STM32_STM32F37XX) # define PWR_CSR_EWUP1 (1 << 8) /* Bit 8: Enable WKUP1 pin */ # define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */ -# define PWR_CSR_EWUP3 (1 << 10) /* Bit 8: Enable WKUP3 pin */ +# define PWR_CSR_EWUP3 (1 << 10) /* Bit 10: Enable WKUP3 pin */ +#elif defined(CONFIG_STM32_STM32F412) +# define PWR_CSR_EWUP3 (1 << 6) /* Bit 6: Enable WKUP3 pin */ +# define PWR_CSR_EWUP2 (1 << 7) /* Bit 7: Enable WKUP2 pin */ +# define PWR_CSR_EWUP1 (1 << 8) /* Bit 8: Enable WKUP1 pin */ #else # define PWR_CSR_EWUP (1 << 8) /* Bit 8: Enable WKUP pin */ #endif diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h b/arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h index b0b3feb1ec..b5d44ecc11 100644 --- a/arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h +++ b/arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h @@ -69,11 +69,12 @@ #define STM32_RCC_SSCGR_OFFSET 0x0080 /* Spread spectrum clock generation register */ #define STM32_RCC_PLLI2SCFGR_OFFSET 0x0084 /* PLLI2S configuration register */ #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) + defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) || \ + defined(CONFIG_STM32_STM32F412) # define STM32_RCC_PLLSAICFGR_OFFSET 0x0088 /* PLLSAI configuration register */ -# define STM32_RCC_DCKCFGR_OFFSET 0x008c /* Dedicated clocks configuration register */ +# define STM32_RCC_DCKCFGR_OFFSET 0x008c /* Dedicated clocks configuration register */ #endif -#if defined(CONFIG_STM32_STM32F446) +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412) # define STM32_RCC_CKGATENR_OFFSET 0x0090 /* Clock gating for the specified IPs */ # define STM32_RCC_DCKCFGR2_OFFSET 0x0094 /* Dedicated clocks configuration register */ #endif @@ -108,7 +109,7 @@ #define STM32_RCC_PLLSAICFGR (STM32_RCC_BASE+STM32_RCC_PLLSAICFGR_OFFSET) #define STM32_RCC_DCKCFGR (STM32_RCC_BASE+STM32_RCC_DCKCFGR_OFFSET) #endif -#if defined(CONFIG_STM32_STM32F446) +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412) # define STM32_RCC_CKGATENR (STM32_RCC_BASE+STM32_RCC_CKGATENR_OFFSET) # define STM32_RCC_DCKCFGR2 (STM32_RCC_BASE+STM32_RCC_DCKCFGR2_OFFSET) #endif @@ -140,16 +141,20 @@ * input clock divider */ #define RCC_PLLCFG_PLLM_MASK (0x3f << RCC_PLLCFG_PLLM_SHIFT) # define RCC_PLLCFG_PLLM(n) ((n) << RCC_PLLCFG_PLLM_SHIFT) /* n = 2..63 */ + #define RCC_PLLCFG_PLLN_SHIFT (6) /* Bits 6-14: Main PLL (PLL) VCO multiplier */ #define RCC_PLLCFG_PLLN_MASK (0x1ff << RCC_PLLCFG_PLLN_SHIFT) # define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 2..432 */ + #define RCC_PLLCFG_PLLP_SHIFT (16) /* Bits 16-17: Main PLL (PLL) main system clock divider */ #define RCC_PLLCFG_PLLP_MASK (3 << RCC_PLLCFG_PLLP_SHIFT) # define RCC_PLLCFG_PLLP(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLP_SHIFT) /* n=2,4,6,8 */ + # define RCC_PLLCFG_PLLP_2 (0 << RCC_PLLCFG_PLLP_SHIFT) /* 00: PLLP = 2 */ # define RCC_PLLCFG_PLLP_4 (1 << RCC_PLLCFG_PLLP_SHIFT) /* 01: PLLP = 4 */ # define RCC_PLLCFG_PLLP_6 (2 << RCC_PLLCFG_PLLP_SHIFT) /* 10: PLLP = 6 */ # define RCC_PLLCFG_PLLP_8 (3 << RCC_PLLCFG_PLLP_SHIFT) /* 11: PLLP = 8 */ + #define RCC_PLLCFG_PLLSRC (1 << 22) /* Bit 22: Main PLL(PLL) and audio PLL (PLLI2S) * entry clock source */ # define RCC_PLLCFG_PLLSRC_HSI (0) @@ -160,7 +165,7 @@ # define RCC_PLLCFG_PLLQ(n) ((n) << RCC_PLLCFG_PLLQ_SHIFT) /* n=2..15 */ #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F446) ||\ - defined(CONFIG_STM32_STM32F469) + defined(CONFIG_STM32_STM32F469) || defined(CONFIG_STM32_STM32F412) # define RCC_PLLCFG_PLLR_SHIFT (28) /* Bits 28-30: Main PLLR (PLLR) divider * (I2Ss, SAIs, SYSTEM and SPDIF-Rx clocks) */ # define RCC_PLLCFG_PLLR_MASK (7 << RCC_PLLCFG_PLLR_SHIFT) @@ -176,45 +181,52 @@ # define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) /* 00: HSI selected as system clock */ # define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT) /* 01: HSE selected as system clock */ # define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT) /* 10: PLL selected as system clock */ -#define RCC_CFGR_SWS_SHIFT (2) /* Bits 2-3: System Clock Switch Status */ + +#define RCC_CFGR_SWS_SHIFT (2) /* Bits 2-3: System Clock Switch Status */ #define RCC_CFGR_SWS_MASK (3 << RCC_CFGR_SWS_SHIFT) # define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 00: HSI oscillator used as system clock */ # define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT) /* 01: HSE oscillator used as system clock */ # define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT) /* 10: PLL used as system clock */ -#define RCC_CFGR_HPRE_SHIFT (4) /* Bits 4-7: AHB prescaler */ + +#define RCC_CFGR_HPRE_SHIFT (4) /* Bits 4-7: AHB prescaler */ #define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT) -# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */ -# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ -# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ +# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */ +# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ +# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ # define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */ # define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */ # define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */ # define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */ # define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */ # define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */ -#define RCC_CFGR_PPRE1_SHIFT (10) /* Bits 10-12: APB Low speed prescaler (APB1) */ + +#define RCC_CFGR_PPRE1_SHIFT (10) /* Bits 10-12: APB Low speed prescaler (APB1) */ #define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT) # define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */ # define RCC_CFGR_PPRE1_HCLKd2 (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */ # define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */ # define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */ # define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */ -#define RCC_CFGR_PPRE2_SHIFT (13) /* Bits 13-15: APB High speed prescaler (APB2) */ + +#define RCC_CFGR_PPRE2_SHIFT (13) /* Bits 13-15: APB High speed prescaler (APB2) */ #define RCC_CFGR_PPRE2_MASK (7 << RCC_CFGR_PPRE2_SHIFT) # define RCC_CFGR_PPRE2_HCLK (0 << RCC_CFGR_PPRE2_SHIFT) /* 0xx: HCLK not divided */ # define RCC_CFGR_PPRE2_HCLKd2 (4 << RCC_CFGR_PPRE2_SHIFT) /* 100: HCLK divided by 2 */ # define RCC_CFGR_PPRE2_HCLKd4 (5 << RCC_CFGR_PPRE2_SHIFT) /* 101: HCLK divided by 4 */ # define RCC_CFGR_PPRE2_HCLKd8 (6 << RCC_CFGR_PPRE2_SHIFT) /* 110: HCLK divided by 8 */ # define RCC_CFGR_PPRE2_HCLKd16 (7 << RCC_CFGR_PPRE2_SHIFT) /* 111: HCLK divided by 16 */ + #define RCC_CFGR_RTCPRE_SHIFT (16) /* Bits 16-20: APB High speed prescaler (APB2) */ #define RCC_CFGR_RTCPRE_MASK (31 << RCC_CFGR_RTCPRE_SHIFT) # define RCC_CFGR_RTCPRE(n) ((n) << RCC_CFGR_RTCPRE_SHIFT) /* HSE/n, n=1..31 */ + #define RCC_CFGR_MCO1_SHIFT (21) /* Bits 21-22: Microcontroller Clock Output */ #define RCC_CFGR_MCO1_MASK (3 << RCC_CFGR_MCO1_SHIFT) # define RCC_CFGR_MCO1_HSI (0 << RCC_CFGR_MCO1_SHIFT) /* 00: HSI clock selected */ # define RCC_CFGR_MCO1_LSE (1 << RCC_CFGR_MCO1_SHIFT) /* 01: LSE oscillator selected */ # define RCC_CFGR_MCO1_HSE (2 << RCC_CFGR_MCO1_SHIFT) /* 10: HSE oscillator clock selected */ # define RCC_CFGR_MCO1_PLL (3 << RCC_CFGR_MCO1_SHIFT) /* 11: PLL clock selected */ + #define RCC_CFGR_I2SSRC (1 << 23) /* Bit 23: I2S clock selection */ #define RCC_CFGR_MCO1PRE_SHIFT (24) /* Bits 24-26: MCO1 prescaler */ #define RCC_CFGR_MCO1PRE_MASK (7 << RCC_CFGR_MCO1PRE_SHIFT) @@ -223,6 +235,7 @@ # define RCC_CFGR_MCO1PRE_DIV3 (5 << RCC_CFGR_MCO1PRE_SHIFT) /* 101: division by 3 */ # define RCC_CFGR_MCO1PRE_DIV4 (6 << RCC_CFGR_MCO1PRE_SHIFT) /* 110: division by 4 */ # define RCC_CFGR_MCO1PRE_DIV5 (7 << RCC_CFGR_MCO1PRE_SHIFT) /* 111: division by 5 */ + #define RCC_CFGR_MCO2PRE_SHIFT (27) /* Bits 27-29: MCO2 prescaler */ #define RCC_CFGR_MCO2PRE_MASK (7 << RCC_CFGR_MCO2PRE_SHIFT) # define RCC_CFGR_MCO2PRE_NONE (0 << RCC_CFGR_MCO2PRE_SHIFT) /* 0xx: no division */ @@ -230,6 +243,7 @@ # define RCC_CFGR_MCO2PRE_DIV3 (5 << RCC_CFGR_MCO2PRE_SHIFT) /* 101: division by 3 */ # define RCC_CFGR_MCO2PRE_DIV4 (6 << RCC_CFGR_MCO2PRE_SHIFT) /* 110: division by 4 */ # define RCC_CFGR_MCO2PRE_DIV5 (7 << RCC_CFGR_MCO2PRE_SHIFT) /* 111: division by 5 */ + #define RCC_CFGR_MCO2_SHIFT (30) /* Bits 30-31: Microcontroller clock output 2 */ #define RCC_CFGR_MCO2_MASK (3 << RCC_CFGR_MCO2_SHIFT) # define RCC_CFGR_MCO2_SYSCLK (0 << RCC_CFGR_MCO2_SHIFT) /* 00: System clock (SYSCLK) selected */ @@ -306,13 +320,15 @@ # define RCC_AHB2RSTR_CRYPRST (1 << 4) /* Bit 4: Cryptographic module reset */ # define RCC_AHB2RSTR_HASHRST (1 << 5) /* Bit 5: Hash module reset */ # define RCC_AHB2RSTR_RNGRST (1 << 6) /* Bit 6: Random number generator module reset */ +#elif defined(CONFIG_STM32_STM32F412) + # define RCC_AHB2RSTR_RNGRST (1 << 6) /* Bit 6: Random number generator module reset */ #endif #define RCC_AHB2RSTR_OTGFSRST (1 << 7) /* Bit 7: USB OTG FS module reset */ /* AHB3 peripheral reset register */ #define RCC_AHB3RSTR_FSMCRST (1 << 0) /* Bit 0: Flexible static memory controller module reset */ -#if defined(CONFIG_STM32_STM32F446) +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412) # define RCC_AHB3RSTR_QSPIRST (1 << 1) /* Bit 1: QUADSPI memory controller module reset */ #endif @@ -358,7 +374,7 @@ #define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI1 reset */ #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) || \ - defined(CONFIG_STM32_STM32F411) + defined(CONFIG_STM32_STM32F411) || defined(CONFIG_STM32_STM32F412) # define RCC_APB2RSTR_SPI4RST (1 << 13) /* Bit 13: SPI4 reset */ #endif #define RCC_APB2RSTR_SYSCFGRST (1 << 14) /* Bit 14: System configuration controller reset */ @@ -366,7 +382,8 @@ #define RCC_APB2RSTR_TIM10RST (1 << 17) /* Bit 17: TIM10 reset */ #define RCC_APB2RSTR_TIM11RST (1 << 18) /* Bit 18: TIM11 reset */ #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F469) || defined(CONFIG_STM32_STM32F411) + defined(CONFIG_STM32_STM32F469) || defined(CONFIG_STM32_STM32F411) || \ + defined(CONFIG_STM32_STM32F412) # define RCC_APB2RSTR_SPI5RST (1 << 20) /* Bit 20: SPI 5 reset */ #endif #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ @@ -380,6 +397,9 @@ #if defined(CONFIG_STM32_STM32F446) # define RCC_APB2RSTR_SAI2RST (1 << 23) /* Bit 23: SAI 2 reset */ #endif +#if defined (CONFIG_STM32_STM32F412) +# define RCC_APB2RSTR_DFSDM1RST (1 << 24) /* Bit 24: DFSDM1 reset */ +#endif #if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F469) # define RCC_APB2RSTR_LTDCRST (1 << 26) /* Bit 26: LTDC reset */ #endif @@ -450,7 +470,7 @@ #define RCC_AHB3ENR_FSMCEN (1 << 0) /* Bit 0: Flexible static memory controller module clock enable */ #define RCC_AHB3ENR_FMCEN (1 << 0) /* Bit 0: Flexible memory controller module clock enable */ -#if defined(CONFIG_STM32_STM32F446) +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412) # define RCC_AHB3ENR_QSPIEN (1 << 1) /* Bit 1: QUADSPI memory controller module clock enable */ #endif @@ -465,6 +485,7 @@ #define RCC_APB1ENR_TIM12EN (1 << 6) /* Bit 6: TIM12 clock enable */ #define RCC_APB1ENR_TIM13EN (1 << 7) /* Bit 7: TIM13 clock enable */ #define RCC_APB1ENR_TIM14EN (1 << 8) /* Bit 8: TIM14 clock enable */ +#define RCC_APB1ENR_RTCAPBEN (1 << 10) /* Bit 10: RTCAPB clock enable */ #define RCC_APB1ENR_WWDGEN (1 << 11) /* Bit 11: Window watchdog clock enable */ #define RCC_APB1ENR_SPI2EN (1 << 14) /* Bit 14: SPI2 clock enable */ #define RCC_APB1ENR_SPI3EN (1 << 15) /* Bit 15: SPI3 clock enable */ @@ -478,7 +499,7 @@ #define RCC_APB1ENR_I2C1EN (1 << 21) /* Bit 21: I2C1 clock enable */ #define RCC_APB1ENR_I2C2EN (1 << 22) /* Bit 22: I2C2 clock enable */ #define RCC_APB1ENR_I2C3EN (1 << 23) /* Bit 23: I2C3 clock enable */ -#if defined(CONFIG_STM32_STM32F446) +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412) # define RCC_APB1ENR_FMPI2C1EN (1 << 24) /* Bit 24: FMPI2C1 clock enable */ #endif #define RCC_APB1ENR_CAN1EN (1 << 25) /* Bit 25: CAN 1 clock enable */ @@ -507,7 +528,7 @@ #define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI1 clock enable */ #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) || \ - defined(CONFIG_STM32_STM32F411) + defined(CONFIG_STM32_STM32F411) || defined(CONFIG_STM32_STM32F412) # define RCC_APB2ENR_SPI4EN (1 << 13) /* Bit 13: SPI4 clock enable */ #endif #define RCC_APB2ENR_SYSCFGEN (1 << 14) /* Bit 14: System configuration controller clock enable */ @@ -515,7 +536,8 @@ #define RCC_APB2ENR_TIM10EN (1 << 17) /* Bit 17: TIM10 clock enable */ #define RCC_APB2ENR_TIM11EN (1 << 18) /* Bit 18: TIM11 clock enable */ #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F469) || defined(CONFIG_STM32_STM32F411) + defined(CONFIG_STM32_STM32F469) || defined(CONFIG_STM32_STM32F411) || \ + defined(CONFIG_STM32_STM32F412) # define RCC_APB2ENR_SPI5EN (1 << 20) /* Bit 20: SPI5 clock enable */ #endif #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ @@ -529,6 +551,9 @@ #if defined(CONFIG_STM32_STM32F446) # define RCC_APB2ENR_SAI2EN (1 << 23) /* Bit 23: SAI2 clock enable */ #endif +#if defined(CONFIG_STM32_STM32F412) +# define RCC_APB2ENR_DFSDM1EN (1 << 24) /* Bit 24: DFSDM1 clock enable */ +#endif #if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F469) # define RCC_APB2ENR_LTDCEN (1 << 26) /* Bit 26: LTDC clock enable */ #endif @@ -576,10 +601,10 @@ defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \ defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ defined(CONFIG_STM32_STM32F469) -# define RCC_AHB1LPENR_DMA2DLPEN (1 << 23) /* Bit 23: DMA2D clock enable during Sleep mode */ -# define RCC_AHB1LPENR_ETHMACLPEN (1 << 25) /* Bit 25: Ethernet MAC clock enable during Sleep mode */ -# define RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26) /* Bit 26: Ethernet Transmission clock enable during Sleep mode */ -# define RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27) /* Bit 27: Ethernet Reception clock enable during Sleep mode */ +# define RCC_AHB1LPENR_DMA2DLPEN (1 << 23) /* Bit 23: DMA2D clock enable during Sleep mode */ +# define RCC_AHB1LPENR_ETHMACLPEN (1 << 25) /* Bit 25: Ethernet MAC clock enable during Sleep mode */ +# define RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26) /* Bit 26: Ethernet Transmission clock enable during Sleep mode */ +# define RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27) /* Bit 27: Ethernet Reception clock enable during Sleep mode */ # define RCC_AHB1LPENR_ETHMACPTPLPEN (1 << 28) /* Bit 28: Ethernet PTP clock enable during Sleep mode */ #endif #define RCC_AHB1LPENR_OTGHSLPEN (1 << 29) /* Bit 29: USB OTG HS clock enable during Sleep mode */ @@ -595,6 +620,8 @@ # define RCC_AHB2LPENR_CRYPLPEN (1 << 4) /* Bit 4: Cryptographic modules clock enable during Sleep mode */ # define RCC_AHB2LPENR_HASHLPEN (1 << 5) /* Bit 5: Hash modules clock enable during Sleep mode */ # define RCC_AHB2LPENR_RNGLPEN (1 << 6) /* Bit 6: Random number generator clock enable during Sleep mode */ +#elif defined(CONFIG_STM32_STM32F412) +# define RCC_AHB2LPENR_RNGLPEN (1 << 6) /* Bit 6: Random number generator clock enable during Sleep mode */ #endif #define RCC_AHB2LPENR_OTGFLPSEN (1 << 7) /* Bit 7: USB OTG FS clock enable during Sleep mode */ @@ -602,7 +629,7 @@ #define RCC_AHB3LPENR_FSMCLPEN (1 << 0) /* Bit 0: Flexible static memory controller module clock * enable during Sleep mode */ -#if defined(CONFIG_STM32_STM32F446) +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412) # define RCC_AHB3LPENR_QSPILPEN (1 << 1) /* Bit 1: QUADSPI memory controller module clock enable * during Sleep mode */ #endif @@ -618,6 +645,7 @@ #define RCC_APB1LPENR_TIM12LPEN (1 << 6) /* Bit 6: TIM12 clock enable during Sleep mode */ #define RCC_APB1LPENR_TIM13LPEN (1 << 7) /* Bit 7: TIM13 clock enable during Sleep mode */ #define RCC_APB1LPENR_TIM14LPEN (1 << 8) /* Bit 8: TIM14 clock enable during Sleep mode */ +#define RCC_APB1LPENR_RTCAPBEN (1 << 10) /* Bit 10: RTC APB clock enable during Sleep mode */ #define RCC_APB1LPENR_WWDGLPEN (1 << 11) /* Bit 11: Window watchdog clock enable during Sleep mode */ #define RCC_APB1LPENR_SPI2LPEN (1 << 14) /* Bit 14: SPI2 clock enable during Sleep mode */ #define RCC_APB1LPENR_SPI3LPEN (1 << 15) /* Bit 15: SPI3 clock enable during Sleep mode */ @@ -631,7 +659,7 @@ #define RCC_APB1LPENR_I2C1LPEN (1 << 21) /* Bit 21: I2C1 clock enable during Sleep mode */ #define RCC_APB1LPENR_I2C2LPEN (1 << 22) /* Bit 22: I2C2 clock enable during Sleep mode */ #define RCC_APB1LPENR_I2C3LPEN (1 << 23) /* Bit 23: I2C3 clock enable during Sleep mode */ -#if defined(CONFIG_STM32_STM32F446) +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412) # define RCC_APB1LPENR_FMPI2C1LPEN (1 << 24) /* Bit 24: FMPI2C1 clock enable during Sleep mode */ #endif #define RCC_APB1LPENR_CAN1LPEN (1 << 25) /* Bit 25: CAN 1 clock enable during Sleep mode */ @@ -660,7 +688,7 @@ #define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* Bit 12: SPI1 clock enable during Sleep mode */ #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) || \ - defined(CONFIG_STM32_STM32F411) + defined(CONFIG_STM32_STM32F411) || defined(CONFIG_STM32_STM32F412) # define RCC_APB2LPENR_SPI4LPEN (1 << 13) /* Bit 13: SPI4 clock enable during Sleep mode */ #endif #define RCC_APB2LPENR_SYSCFGLPEN (1 << 14) /* Bit 14: System configuration controller clock enable during Sleep mode */ @@ -668,7 +696,8 @@ #define RCC_APB2LPENR_TIM10LPEN (1 << 17) /* Bit 17: TIM10 clock enable during Sleep mode */ #define RCC_APB2LPENR_TIM11LPEN (1 << 18) /* Bit 18: TIM11 clock enable during Sleep mode */ #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F469) || defined(CONFIG_STM32_STM32F411) + defined(CONFIG_STM32_STM32F469) || defined(CONFIG_STM32_STM32F411) || \ + defined(CONFIG_STM32_STM32F412) # define RCC_APB2LPENR_SPI5LPEN (1 << 20) /* Bit 20: SPI5 clock enable during Sleep mode */ #endif #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ @@ -682,6 +711,9 @@ #if defined(CONFIG_STM32_STM32F446) # define RCC_APB2LPENR_SAI2LPEN (1 << 23) /* Bit 23: SAI2 clock enable during Sleep mode */ #endif +#if defined(CONFIG_STM32_STM32F412) +# define RCC_APB2LPENR_DFSDM1LPEN (1 << 24) /* Bit 24: DFSDM1 clock enable during Sleep mode */ +#endif #if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F469) # define RCC_APB2LPENR_LTDCLPEN (1 << 26) /* Bit 26: LTDC clock enable during Sleep mode */ #endif @@ -694,7 +726,8 @@ #define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */ #define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */ #define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */ -#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) || \ + defined(CONFIG_STM32_STM32F412) # define RCC_BDCR_LSEMOD_SHIFT (3) /* Bit 3: External Low Speed oscillator mode */ # define RCC_BDCR_LSEMOD_MASK (1 << RCC_BDCR_LSEMOD_SHIFT) # define RCC_BDCR_LSEMOD_LOWPWR (0 << RCC_BDCR_LSEMOD_SHIFT) /* LSE oscillator "low power" mode selection */ @@ -706,8 +739,10 @@ # define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */ # define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */ # define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */ -#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ -#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */ + +#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ + +#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */ /* Control/status register */ @@ -735,7 +770,7 @@ /* PLLI2S configuration register */ -#if defined(CONFIG_STM32_STM32F446) +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412) # define RCC_PLLI2SCFGR_PLLI2SM_SHIFT (0) /* Bits 0-5: Division factor M for audio PLL * (PLLI2S) input clock */ # define RCC_PLLI2SCFGR_PLLI2SM_MASK (0x3f << RCC_PLLI2SCFGR_PLLI2SM_SHIFT) @@ -750,8 +785,13 @@ /* Set PLLI2S P to 2,4,6,8 */ # define RCC_PLLI2SCFGR_PLLI2SP(n) (((((n)-2)/2) << RCC_PLLI2SCFGR_PLLI2SP_SHIFT) & RCC_PLLI2SCFGR_PLLI2SP_MASK) #endif +#if defined(CONFIG_STM32_STM32F412) +#define RCC_PLLI2SCFGR_PLLI2SSRC_SHIFT (22) +# define RCC_PLLI2SCFGR_PLLI2SSRC(n) ((n) << RCC_PLLI2SCFGR_PLLI2SSRC_SHIFT) /* Bit 22: PLLI2S entry clock source */ +#endif #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) + defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) || \ + defined(CONFIG_STM32_STM32F412) # define RCC_PLLI2SCFGR_PLLI2SQ_SHIFT (24) /* Bits 24-27: PLLI2S division factor for SAI1 clock */ # define RCC_PLLI2SCFGR_PLLI2SQ_MASK (0xf << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT) # define RCC_PLLI2SCFGR_PLLI2SQ(n) ((n) << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT) @@ -793,7 +833,8 @@ /* Dedicated clocks configuration register */ #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) + defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) || \ + defined(CONFIG_STM32_STM32F412) # define RCC_DCKCFGR_PLLI2SDIVQ_SHIFT (0) /* Bits 0-4: PLLI2S division 1..32 factor for I2S clock */ # define RCC_DCKCFGR_PLLI2SDIVQ_MASK (0x1f << RCC_DCKCFGR_PLLI2SDIVQ_SHIFT) # define RCC_DCKCFGR_PLLI2SDIVQ(n) (((n)-1) << RCC_DCKCFGR_PLLI2SDIVQ_SHIFT) @@ -834,14 +875,18 @@ # define RCC_DCKCFGR_SAI2SRC_HSX (3 << RCC_DCKCFGR_SAI2SRC_SHIFT) # endif # define RCC_DCKCFGR_TIMPRE (1 << 24) /* Bit 24: Timer clock prescaler selection */ -# if defined(CONFIG_STM32_STM32F446) +# if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412) # define RCC_DCKCFGR_I2S1SRC_SHIFT (25) /* Bits 25-26: I2S APB1 clock source selection */ # define RCC_DCKCFGR_I2S1SRC_MASK (0x3 << RCC_DCKCFGR_I2S1SRC_SHIFT) # define RCC_DCKCFGR_I2S1SRC_PLLI2S (0 << RCC_DCKCFGR_I2S1SRC_SHIFT) # define RCC_DCKCFGR_I2S1SRC_I2S_CKIN (1 << RCC_DCKCFGR_I2S1SRC_SHIFT) # define RCC_DCKCFGR_I2S1SRC_PLL (2 << RCC_DCKCFGR_I2S1SRC_SHIFT) # define RCC_DCKCFGR_I2S1SRC_HSX (3 << RCC_DCKCFGR_I2S1SRC_SHIFT) -# define RCC_DCKCFGR_I2S2SRC_SHIFT (28) /* Bits 28-29: I2S APB2 clock source selection */ +# if defined(CONFIG_STM32_STM32F412) +# define RCC_DCKCFGR_I2S2SRC_SHIFT (27) /* Bits 27-28: I2S APB2 clock source selection */ +# else +# define RCC_DCKCFGR_I2S2SRC_SHIFT (28) /* Bits 28-29: I2S APB2 clock source selection */ +# endif # define RCC_DCKCFGR_I2S2SRC_MASK (0x3 << RCC_DCKCFGR_I2S2SRC_SHIFT) # define RCC_DCKCFGR_I2S2SRC_PLLI2S (0 << RCC_DCKCFGR_I2S2SRC_SHIFT) # define RCC_DCKCFGR_I2S2SRC_I2S_CKIN (1 << RCC_DCKCFGR_I2S2SRC_SHIFT) @@ -853,10 +898,12 @@ # define RCC_DCKCFGR_48MSEL_MASK (1 << RCC_DCKCFGR_48MSEL_SHIFT) # define RCC_DCKCFGR_48MSEL_PLL (0 << RCC_DCKCFGR_48MSEL_SHIFT) /* 48 MHz clock from PLL is selected */ # define RCC_DCKCFGR_48MSEL_PLLSAI (1 << RCC_DCKCFGR_48MSEL_SHIFT) /* 48 MHz clock from PLLSAI is selected */ + # define RCC_DCKCFGR_SDMMCSEL_SHIFT (28) /* Bit 28: SDMMC clock source selection */ # define RCC_DCKCFGR_SDMMCSEL_MASK (1 << RCC_DCKCFGR_SDMMCSEL_SHIFT) # define RCC_DCKCFGR_SDMMCSEL_48MHZ (0 << RCC_DCKCFGR_SDMMCSEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */ # define RCC_DCKCFGR_SDMMCSEL_SYSCLK (1 << RCC_DCKCFGR_SDMMCSEL_SHIFT) /* System clock is selected as SDMMC clock */ + # define RCC_DCKCFGR_DSISEL_SHIFT (29) /* Bit 29: DSI clock selection */ # define RCC_DCKCFGR_DSISEL_MASK (1 << RCC_DCKCFGR_DSISEL_SHIFT) # define RCC_DCKCFGR_DSISEL_DSIPHY (0 << RCC_DCKCFGR_DSISEL_SHIFT) /* DSI-PHY clock is selected as DSI clock */ @@ -866,7 +913,7 @@ /* RCC clocks gated enable register */ -#if defined(CONFIG_STM32_STM32F446) +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412) # define RCC_CKGATENR_AHB2APB1_CKEN (1 << 0) /* Bit 0: AHB to APB1 Bridge clock enable */ # define RCC_CKGATENR_AHB2APB2_CKEN (1 << 1) /* Bit 1: AHB to APB2 Bridge clock enable */ # define RCC_CKGATENR_CM4DBG_CKEN (1 << 2) /* Bit 2: Cortex M4 ETM clock enable */ @@ -878,25 +925,29 @@ /* Dedicated clocks configuration register 2 */ -#if defined(CONFIG_STM32_STM32F446) -# define RCC_DCKCFGR2_FMPI2C1SEL_SHIFT (22) /* Bits 22-23: I2C4 clock source selection */ +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412) +# define RCC_DCKCFGR2_FMPI2C1SEL_SHIFT (22) /* Bits 22-23: I2C4 clock source selection */ # define RCC_DCKCFGR2_FMPI2C1SEL_MASK (3 << RCC_DCKCFGR2_FMPI2C1SEL_SHIFT) # define RCC_DCKCFGR2_FMPI2C1SEL_APB (0 << RCC_DCKCFGR2_FMPI2C1SEL_SHIFT) /* APB1 clock (PCLK1) is selected as I2C 4 clock */ # define RCC_DCKCFGR2_FMPI2C1SEL_SYSCLK (1 << RCC_DCKCFGR2_FMPI2C1SEL_SHIFT) /* System clock is selected as I2C 4 clock */ # define RCC_DCKCFGR2_FMPI2C1SEL_HSI (2 << RCC_DCKCFGR2_FMPI2C1SEL_SHIFT) /* HSI clock is selected as I2C 4 clock */ -# define RCC_DCKCFGR2_CECSEL_SHIFT (26) /* Bit 26: HDMI-CEC clock source selection */ + +# define RCC_DCKCFGR2_CECSEL_SHIFT (26) /* Bit 26: HDMI-CEC clock source selection */ # define RCC_DCKCFGR2_CECSEL_MASK (1 << RCC_DCKCFGR2_CECSEL_SHIFT) -# define RCC_DCKCFGR2_CECSEL_LSE (0 << RCC_DCKCFGR2_CECSEL_SHIFT) /* LSE clock is selected as HDMI-CEC clock */ -# define RCC_DCKCFGR2_CECSEL_HSI (1 << RCC_DCKCFGR2_CECSEL_SHIFT) /* HSI clock is selected as HDMI-CEC clock */ -# define RCC_DCKCFGR2_CK48MSEL_SHIFT (27) /* Bit 27: 48 MHz clock source selection */ +# define RCC_DCKCFGR2_CECSEL_LSE (0 << RCC_DCKCFGR2_CECSEL_SHIFT) /* LSE clock is selected as HDMI-CEC clock */ +# define RCC_DCKCFGR2_CECSEL_HSI (1 << RCC_DCKCFGR2_CECSEL_SHIFT) /* HSI clock is selected as HDMI-CEC clock */ + +# define RCC_DCKCFGR2_CK48MSEL_SHIFT (27) /* Bit 27: 48 MHz clock source selection */ # define RCC_DCKCFGR2_CK48MSEL_MASK (1 << RCC_DCKCFGR2_CK48MSEL_SHIFT) -# define RCC_DCKCFGR2_CK48MSEL_PLL (0 << RCC_DCKCFGR2_CK48MSEL_SHIFT) /* 48 MHz clock from PLL is selected */ -# define RCC_DCKCFGR2_CK48MSEL_PLLSAI (1 << RCC_DCKCFGR2_CK48MSEL_SHIFT) /* 48 MHz clock from PLLSAI is selected */ -# define RCC_DCKCFGR2_SDIOSEL_SHIFT (28) /* Bit 28: SDIO clock source selection */ +# define RCC_DCKCFGR2_CK48MSEL_PLL (0 << RCC_DCKCFGR2_CK48MSEL_SHIFT) /* 48 MHz clock from PLL is selected */ +# define RCC_DCKCFGR2_CK48MSEL_PLLSAI (1 << RCC_DCKCFGR2_CK48MSEL_SHIFT) /* 48 MHz clock from PLLSAI is selected */ + +# define RCC_DCKCFGR2_SDIOSEL_SHIFT (28) /* Bit 28: SDIO clock source selection */ # define RCC_DCKCFGR2_SDIOSEL_MASK (1 << RCC_DCKCFGR2_SDIOSEL_SHIFT) -# define RCC_DCKCFGR2_SDIOSEL_48MHZ (0 << RCC_DCKCFGR2_SDIOSEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */ -# define RCC_DCKCFGR2_SDIOSEL_SYSCLK (1 << RCC_DCKCFGR2_SDIOSEL_SHIFT) /* System clock is selected as SDMMC clock */ -# define RCC_DCKCFGR2_SPDIFRXSEL_SHIFT (29) /* Bit 29: SPDIF-Rx clock selection */ +# define RCC_DCKCFGR2_SDIOSEL_48MHZ (0 << RCC_DCKCFGR2_SDIOSEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */ +# define RCC_DCKCFGR2_SDIOSEL_SYSCLK (1 << RCC_DCKCFGR2_SDIOSEL_SHIFT) /* System clock is selected as SDMMC clock */ + +# define RCC_DCKCFGR2_SPDIFRXSEL_SHIFT (29) /* Bit 29: SPDIF-Rx clock selection */ # define RCC_DCKCFGR2_SPDIFRXSEL_MASK (1 << RCC_DCKCFGR2_SPDIFRXSEL_SHIFT) # define RCC_DCKCFGR2_SPDIFRXSEL_PLL (0 << RCC_DCKCFGR2_SPDIFRXSEL_SHIFT) /* PLL clock is selected as SPDIF-Rx clock */ # define RCC_DCKCFGR2_SPDIFRXSEL_PLLI2S (1 << RCC_DCKCFGR2_SPDIFRXSEL_SHIFT) /* PLLI2S clock is selected as SPDIF-Rx clock */ diff --git a/arch/arm/src/stm32/stm32_allocateheap.c b/arch/arm/src/stm32/stm32_allocateheap.c index 1998e07b2f..0f5da3e9a9 100644 --- a/arch/arm/src/stm32/stm32_allocateheap.c +++ b/arch/arm/src/stm32/stm32_allocateheap.c @@ -359,10 +359,11 @@ #elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -/* The STM32 F2 and the STM32 F401/F411 have no CCM SRAM */ +/* The STM32 F2 and the STM32 F401/F411/F412 have no CCM SRAM */ # if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F401) || \ - defined(CONFIG_STM32_STM32F411) || defined(CONFIG_STM32_STM32F410) + defined(CONFIG_STM32_STM32F411) || defined(CONFIG_STM32_STM32F410) || \ + defined(CONFIG_STM32_STM32F412) # undef CONFIG_STM32_CCMEXCLUDE # define CONFIG_STM32_CCMEXCLUDE 1 # endif diff --git a/arch/arm/src/stm32/stm32f40xxx_rcc.c b/arch/arm/src/stm32/stm32f40xxx_rcc.c index 957951a172..d78158ce00 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f40xxx_rcc.c @@ -204,7 +204,8 @@ static inline void rcc_enableahb1(void) #ifdef CONFIG_STM32_ETHMAC /* Ethernet MAC clocking */ - regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | RCC_AHB1ENR_ETHMACRXEN); + regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN + | RCC_AHB1ENR_ETHMACRXEN); #ifdef CONFIG_STM32_ETH_PTP /* Precision Time Protocol (PTP) */ @@ -688,7 +689,8 @@ static void stm32_stdclockconfig(void) regval = getreg32(STM32_PWR_CR); #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) + defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) || \ + defined(CONFIG_STM32_STM32F412) regval &= ~PWR_CR_VOS_MASK; regval |= PWR_CR_VOS_SCALE_1; #else @@ -773,7 +775,9 @@ static void stm32_stdclockconfig(void) } #endif - /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */ + /* Enable FLASH prefetch, instruction cache, data cache, + * and 5 wait states. + */ regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN #ifdef CONFIG_STM32_FLASH_PREFETCH @@ -791,7 +795,8 @@ static void stm32_stdclockconfig(void) /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) + != RCC_CFGR_SWS_PLL) { } @@ -909,6 +914,18 @@ static void stm32_stdclockconfig(void) regval |= (STM32_RCC_PLLI2SCFGR_PLLI2SN | STM32_RCC_PLLI2SCFGR_PLLI2SQ | STM32_RCC_PLLI2SCFGR_PLLI2SR); + +# elif defined(CONFIG_STM32_STM32F412) + + regval &= ~(RCC_PLLI2SCFGR_PLLI2SM_MASK + | RCC_PLLI2SCFGR_PLLI2SN_MASK + | RCC_PLLI2SCFGR_PLLI2SQ_MASK + | RCC_PLLI2SCFGR_PLLI2SR_MASK); + regval |= (STM32_RCC_PLLI2SCFGR_PLLI2SM + | STM32_RCC_PLLI2SCFGR_PLLI2SN + | STM32_RCC_PLLI2SCFGR_PLLI2SQ + | STM32_RCC_PLLI2SCFGR_PLLI2SR + | STM32_RCC_PLLI2SCFGR_PLLI2SSRC); # endif putreg32(regval, STM32_RCC_PLLI2SCFGR); @@ -917,6 +934,8 @@ static void stm32_stdclockconfig(void) regval = getreg32(STM32_RCC_DCKCFGR2); +# if defined(CONFIG_STM32_STM32F446) + regval &= ~(RCC_DCKCFGR2_FMPI2C1SEL_MASK | RCC_DCKCFGR2_CECSEL_MASK | RCC_DCKCFGR2_CK48MSEL_MASK @@ -928,6 +947,16 @@ static void stm32_stdclockconfig(void) | STM32_RCC_DCKCFGR2_SDIOSEL | STM32_RCC_DCKCFGR2_SPDIFRXSEL); +# elif defined(CONFIG_STM32_STM32F412) + + regval &= ~(RCC_DCKCFGR2_FMPI2C1SEL_MASK + | RCC_DCKCFGR2_CK48MSEL_MASK + | RCC_DCKCFGR2_SDIOSEL_MASK); + regval |= (STM32_RCC_DCKCFGR2_FMPI2C1SEL + | STM32_RCC_DCKCFGR2_CK48MSEL + | STM32_RCC_DCKCFGR2_SDIOSEL); +# endif + putreg32(regval, STM32_RCC_DCKCFGR2); # endif @@ -979,7 +1008,6 @@ static inline void rcc_itm_syslog(void) modifyreg32(STM32_DBGMCU_CR, DBGMCU_CR_TRACEMODE_MASK, DBGMCU_CR_ASYNCH | DBGMCU_CR_TRACEIOEN); - } #else # define rcc_itm_syslog() diff --git a/boards/Kconfig b/boards/Kconfig index 69d80745ee..6692f5061e 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -1135,6 +1135,14 @@ config ARCH_BOARD_NUCLEO_F411RE This is a minimal configuration that supports low-level test of the Nucleo F411RE in the NuttX source tree. +config ARCH_BOARD_NUCLEO_F412ZG + bool "STM32F412 Nucleo F412ZG" + depends on ARCH_CHIP_STM32F412ZG + select ARCH_HAVE_LEDS + ---help--- + This is a minimal configuration that supports low-level test of the + Nucleo F412ZG in the NuttX source tree. + config ARCH_BOARD_NUCLEO_F446RE bool "STM32F446 Nucleo F446RE" depends on ARCH_CHIP_STM32F446R @@ -2185,6 +2193,7 @@ config ARCH_BOARD default "nucleo-f429zi" if ARCH_BOARD_NUCLEO_F429ZI default "nucleo-f446re" if ARCH_BOARD_NUCLEO_F446RE default "nucleo-f410rb" if ARCH_BOARD_NUCLEO_F410RB + default "nucleo-f412zg" if ARCH_BOARD_NUCLEO_F412ZG default "nucleo-g070rb" if ARCH_BOARD_NUCLEO_G070RB default "nucleo-g071rb" if ARCH_BOARD_NUCLEO_G071RB default "nucleo-h743zi" if ARCH_BOARD_NUCLEO_H743ZI @@ -2686,6 +2695,9 @@ endif if ARCH_BOARD_NUCLEO_F410RB source "boards/arm/stm32/nucleo-f410rb/Kconfig" endif +if ARCH_BOARD_NUCLEO_F412ZG +source "boards/arm/stm32/nucleo-f412zg/Kconfig" +endif if ARCH_BOARD_NUCLEO_F44RE source "boards/arm/stm32/nucleo-f446re/Kconfig" endif diff --git a/boards/arm/stm32/nucleo-f412zg/Kconfig b/boards/arm/stm32/nucleo-f412zg/Kconfig new file mode 100644 index 0000000000..47332c24f5 --- /dev/null +++ b/boards/arm/stm32/nucleo-f412zg/Kconfig @@ -0,0 +1,10 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_NUCLEO_F412ZG + + + +endif diff --git a/boards/arm/stm32/nucleo-f412zg/README.txt b/boards/arm/stm32/nucleo-f412zg/README.txt new file mode 100644 index 0000000000..98b0d81c0c --- /dev/null +++ b/boards/arm/stm32/nucleo-f412zg/README.txt @@ -0,0 +1,255 @@ +README +====== + +This README discusses issues unique to NuttX configurations for the ST +NucleoF410RB board from ST Micro. See + + http://www.st.com/en/evaluation-tools/nucleo-f412zg.html + +NucleoF412ZG: + + Microprocessor: 32-bit ARM Cortex M4 at 100MHz STM32F412ZG + Memory: 1 MB Flash and 256 KB SRAM + ADC: 1x12-bit, 2.4 MSPS A/D converter: up to 16 channels + DMA: 2x8-stream DMA controllers with FIFOs and burst support + Timers: Up to 17 timers: up to 12 16-bit, 2 32-bit timers, two + watchdog timers, and a SysTick timer + GPIO: Up to 114 I/O ports with interrupt capability + I2C: Up to 4 I2C interfaces + USARTs: Up to 4 USARTs + SPIs: Up to 5 SPIs (5 I2S) + SDIO interface (SD/MMC/eMMC) + Advanced connectivity: USB 2.0 full-speed device/host/OTG controller with PHY + 2x CAN (2.0B Active) + True random number generator + CRC calculation unit + 96-bit unique ID + RTC + +JAKE: TODO + +See: +https://www.st.com/content/ccc/resource/technical/document/user_manual/group0/26/49/90/2e/33/0d/4a/da/DM00244518/files/DM00244518.pdf/jcr:content/translations/en.DM00244518.pdf + + Peripherals: 3 led, 2 push button + Debug: Serial wire debug and JTAG interfaces + Expansion I/F Ardino and Morpho Headers + + + +Contents +======== + + - Nucleo-64 Boards + - Button + - LED + - USARTs and Serial Consoles + - Configurations + +Nucleo-64 Boards +================ + +The Nucleo-F410RB board is member of the Nucleo-64 board family. The +Nucleo-64 is a standard board for use with several STM32 parts in the +LQFP64 package. Variants include + + Order code Targeted STM32 + ------------- -------------- + NUCLEO-F030R8 STM32F030R8T6 + NUCLEO-F070RB STM32F070RBT6 + NUCLEO-F072RB STM32F072RBT6 + NUCLEO-F091RC STM32F091RCT6 + NUCLEO-F103RB STM32F103RBT6 + NUCLEO-F302R8 STM32F302R8T6 + NUCLEO-F303RE STM32F303RET6 + NUCLEO-F334R8 STM32F334R8T6 + NUCLEO-F401RE STM32F401RET6 + NUCLEO-F410RB STM32F410RBT6 + NUCLEO-F411RE STM32F411RET6 + NUCLEO-F446RE STM32F446RET6 + NUCLEO-L053R8 STM32L053R8T6 + NUCLEO-L073RZ STM32L073RZT6 + NUCLEO-L152RE STM32L152RET6 + NUCLEO-L452RE STM32L452RET6 + NUCLEO-L476RG STM32L476RGT6 + +Hardware +======== + + Buttons + ------- + B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32 + microcontroller. + + LEDs + ---- + The Nucleo F410RB provide a single user LED, LD2. LD2 + is the green LED connected to Arduino signal D13 corresponding to MCU I/O + PA5 (pin 21) or PB13 (pin 34) depending on the STM32target. + + - When the I/O is HIGH value, the LED is on. + - When the I/O is LOW, the LED is off. + + These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + defined. In that case, the usage by the board port is defined in + include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related + events as follows when the red LED (PE24) is available: + + SYMBOL Meaning LD2 + ------------------- ----------------------- ----------- + LED_STARTED NuttX has been started OFF + LED_HEAPALLOCATE Heap has been allocated OFF + LED_IRQSENABLED Interrupts enabled OFF + LED_STACKCREATED Idle stack created ON + LED_INIRQ In an interrupt No change + LED_SIGNAL In a signal handler No change + LED_ASSERTION An assertion failed No change + LED_PANIC The system has crashed Blinking + LED_IDLE MCU is is sleep mode Not used + + Thus if LD2, NuttX has successfully booted and is, apparently, running + normally. If LD2 is flashing at approximately 2Hz, then a fatal error + has been detected and the system has halted. + +Serial Consoles +=============== + + USART1 + ------ + Pins and Connectors: + + RXD: PA11 CN10 pin 14 + PB7 CN7 pin 21 + TXD: PA10 CN9 pin 3, CN10 pin 33 + PB6 CN5 pin 3, CN10 pin 17 + + NOTE: You may need to edit the include/board.h to select different USART1 + pin selections. + + TTL to RS-232 converter connection: + + Nucleo CN10 STM32F410RB + ----------- ------------ + Pin 21 PA9 USART1_RX *Warning you make need to reverse RX/TX on + Pin 33 PA10 USART1_TX some RS-232 converters + Pin 20 GND + Pin 8 U5V + + To configure USART1 as the console: + + CONFIG_STM32_USART1=y + CONFIG_USART1_SERIALDRIVER=y + CONFIG_USART1_SERIAL_CONSOLE=y + CONFIG_USART1_RXBUFSIZE=256 + CONFIG_USART1_TXBUFSIZE=256 + CONFIG_USART1_BAUD=115200 + CONFIG_USART1_BITS=8 + CONFIG_USART1_PARITY=0 + CONFIG_USART1_2STOP=0 + + USART2 + ----- + Pins and Connectors: + + RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 + PD6 + TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 + PD5 + + UART2 is the default in all of these configurations. + + TTL to RS-232 converter connection: + + Nucleo CN9 STM32F410RB + ----------- ------------ + Pin 1 PA3 USART2_RX *Warning you make need to reverse RX/TX on + Pin 2 PA2 USART2_TX some RS-232 converters + + Solder Bridges. This configuration requires: + + - SB62 and SB63 Closed: PA2 and PA3 on STM32 MCU are connected to D1 and D0 + (pin 7 and pin 8) on Arduino connector CN9 and ST Morpho connector CN10 + as USART signals. Thus SB13 and SB14 should be OFF. + + - SB13 and SB14 Open: PA2 and PA3 on STM32F103C8T6 (ST-LINK MCU) are + disconnected to PA3 and PA2 on STM32 MCU. + + To configure USART2 as the console: + + CONFIG_STM32_USART2=y + CONFIG_USART2_SERIALDRIVER=y + CONFIG_USART2_SERIAL_CONSOLE=y + CONFIG_USART2_RXBUFSIZE=256 + CONFIG_USART2_TXBUFSIZE=256 + CONFIG_USART2_BAUD=115200 + CONFIG_USART2_BITS=8 + CONFIG_USART2_PARITY=0 + CONFIG_USART2_2STOP=0 + + USART6 + ------ + Pins and Connectors: + + RXD: PC7 CN5 pin2, CN10 pin 19 + PA12 CN10, pin 12 + TXD: PC6 CN10, pin 4 + PA11 CN10, pin 14 + + To configure USART6 as the console: + + CONFIG_STM32_USART6=y + CONFIG_USART6_SERIALDRIVER=y + CONFIG_USART6_SERIAL_CONSOLE=y + CONFIG_USART6_RXBUFSIZE=256 + CONFIG_USART6_TXBUFSIZE=256 + CONFIG_USART6_BAUD=115200 + CONFIG_USART6_BITS=8 + CONFIG_USART6_PARITY=0 + CONFIG_USART6_2STOP=0 + + Virtual COM Port + ---------------- + Yet another option is to use UART2 and the USB virtual COM port. This + option may be more convenient for long term development, but is painful + to use during board bring-up. + + Solder Bridges. This configuration requires: + + - SB62 and SB63 Open: PA2 and PA3 on STM32 MCU are disconnected to D1 + and D0 (pin 7 and pin 8) on Arduino connector CN9 and ST Morpho + connector CN10. + + - SB13 and SB14 Closed: PA2 and PA3 on STM32F103C8T6 (ST-LINK MCU) are + connected to PA3 and PA2 on STM32 MCU to have USART communication + between them. Thus SB61, SB62 and SB63 should be OFF. + + Configuring USART2 is the same as given above. + + Question: What BAUD should be configure to interface with the Virtual + COM port? 115200 8N1? + + Default + ------- + As shipped, SB62 and SB63 are open and SB13 and SB14 closed, so the + virtual COM port is enabled. + +Configurations +============== + + nsh: + --------- + Configures the NuttShell (nsh) located at apps/examples/nsh for the + Nucleo-F410RB board. The Configuration enables the serial interfaces + on UART2. Support for builtin applications is enabled, but in the base + configuration no builtin applications are selected (see NOTES below). + + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository. + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. diff --git a/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig new file mode 100644 index 0000000000..faaa043036 --- /dev/null +++ b/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_SYSCFG is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f412zg" +CONFIG_ARCH_BOARD_NUCLEO_F412ZG=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F412ZG=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_SIZET_LONG=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_USEBASEPRI=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CAN=y +CONFIG_CLOCK_MONOTONIC=y +CONFIG_DEBUG_HARDFAULT_ALERT=y +CONFIG_HAVE_CXX=y +CONFIG_I2C=y +CONFIG_INTELHEX_BINARY=y +CONFIG_MAX_TASKS=64 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_CHILDSTATUS=2 +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=8 +CONFIG_RAM_SIZE=262144 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_CHILD_STATUS=y +CONFIG_SCHED_EXIT_KILL_CHILDREN=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SPI=y +CONFIG_START_DAY=30 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FLASH_PREFETCH=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_TIMER=y +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USEC_PER_TICK=1000 +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/stm32/nucleo-f412zg/include/board.h b/boards/arm/stm32/nucleo-f412zg/include/board.h new file mode 100644 index 0000000000..eeda595073 --- /dev/null +++ b/boards/arm/stm32/nucleo-f412zg/include/board.h @@ -0,0 +1,238 @@ +/**************************************************************************** + * boards/arm/stm32/stm32f411e-disco/include/board.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Konstantin Berezenko + * + * based on boards/nucleo-f4x1re/include/board.h + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F412ZG_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F412ZG_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - 8 MHz Crystal + * LSE - not installed + */ + +#define STM32_BOARD_USEHSE 1 +#define STM32_BOARD_XTAL 8000000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 + +/* Main PLL Configuration */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8) +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) + +#define STM32_RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM(16) +#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) +#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) +#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2) +#define STM32_RCC_PLLI2SCFGR_PLLI2SSRC RCC_PLLI2SCFGR_PLLI2SSRC(0) /* HSE or HSI depending on PLLSRC of PLLCFGR*/ + +#define STM32_RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_PLL +#define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB +#define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ + +#define STM32_SYSCLK_FREQUENCY 96000000ul + +/* AHB clock (HCLK) is SYSCLK (96MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY +#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ + +/* APB1 clock (PCLK1) is HCLK/2 (48MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (96MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY) + +/* Timers driven from APB2 will be PCLK2 since no prescale division */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) + +/* Alternate function pin selections ****************************************/ + +/* USART2: + * RXD: PD6 CN9 pin 4 + * TXD: PD5 CN9 pin 6 + */ + +# define GPIO_USART2_RX GPIO_USART2_RX_2 +# define GPIO_USART2_TX GPIO_USART2_TX_2 + +/* USART6: + * RXD: PG9 CN10 pin 16 + * TXD: PG14 CN10 pin 14 + */ + +#define GPIO_USART6_RX GPIO_USART6_RX_2 +#define GPIO_USART6_TX GPIO_USART6_TX_2 + +/* I2C1: + * SCL: PB8 CN7 pin2 + * SDA: PB9 CN7 pin4 + */ + +#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 +#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 + +#define GPIO_I2C1_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C1_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) + +/* SPI1: + * MISO: PA6 CN7 pin 12 + * MOSI: PA7 CN7 pin 14 + * SCK: PA5 CN7 pin 10 + */ + +#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 +#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 +#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 + +/* CAN1: + * RX: PD0 CN9 pin 25 + * TX: PD1 CN9 pin 27 + */ + +#define GPIO_CAN1_RX GPIO_CAN1_RX_3 +#define GPIO_CAN1_TX GPIO_CAN1_TX_3 + +/* LEDs + * + * The NUCLEO-F412ZG board has 3 user leds. + * LD1: PB0 GREEN + * LD2: PB7 BLUE + * LD3: PB14 RED + */ + +#define BOARD_NLEDS 3 + +#define GPIO_LD1 \ +(GPIO_PORTB | GPIO_PIN0 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | \ +GPIO_SPEED_50MHz) + +#define GPIO_LD2 \ +(GPIO_PORTB | GPIO_PIN7 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | \ +GPIO_SPEED_50MHz) + +#define GPIO_LD3 \ +(GPIO_PORTB | GPIO_PIN14 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | \ +GPIO_SPEED_50MHz) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related + * events as follows when the red LED (PE24) is available: + * + * SYMBOL Meaning + * ------------------- ----------------------- + * LED_STARTED NuttX has been started + * LED_HEAPALLOCATE Heap has been allocated + * LED_IRQSENABLED Interrupts enabled + * LED_STACKCREATED Idle stack created + * LED_INIRQ In an interrupt + * LED_SIGNAL In a signal handler + * LED_ASSERTION An assertion failed + * LED_PANIC The system has crashed + * LED_IDLE MCU is is sleep mode + * + * Thus if LD2, NuttX has successfully booted and is, apparently, running + * normally. If LD2 is flashing at approximately 2Hz, then a fatal error + * has been detected and the system has halted. + */ + +#define LED_STARTED 1 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 3 +#define LED_INIRQ 0 +#define LED_SIGNAL 0 +#define LED_ASSERTION 1 +#define LED_PANIC 1 + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F412ZG_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f412zg/scripts/Make.defs b/boards/arm/stm32/nucleo-f412zg/scripts/Make.defs new file mode 100644 index 0000000000..7f51c47bf9 --- /dev/null +++ b/boards/arm/stm32/nucleo-f412zg/scripts/Make.defs @@ -0,0 +1,112 @@ +############################################################################ +# boards/arm/stm32/nucleo-f412/scripts/Make.defs +# +# Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = f412zg.ld + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +STRIP = $(CROSSDEV)strip --strip-unneeded +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = diff --git a/boards/arm/stm32/nucleo-f412zg/scripts/f412zg.ld b/boards/arm/stm32/nucleo-f412zg/scripts/f412zg.ld new file mode 100644 index 0000000000..507a7a5ee4 --- /dev/null +++ b/boards/arm/stm32/nucleo-f412zg/scripts/f412zg.ld @@ -0,0 +1,120 @@ +/**************************************************************************** + * boards/arm/stm32/nucleo-f412zg/scripts/f412zg.ld + * + * Copyright (C) 2020 Gregory Nutt. All rights reserved. + * Author: Jacob Dahl + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The STM32F412ZG has 1MB of FLASH beginning at address 0x0800:0000 and + * 256KB of SRAM beginning at address 0x2000:0000. When booting from FLASH, + * FLASH memory is aliased to address 0x0000:0000 where the code expects to + * begin execution by jumping to the entry point in the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1M + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 256K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32/nucleo-f412zg/src/Makefile b/boards/arm/stm32/nucleo-f412zg/src/Makefile new file mode 100644 index 0000000000..10c0e70d9d --- /dev/null +++ b/boards/arm/stm32/nucleo-f412zg/src/Makefile @@ -0,0 +1,53 @@ +############################################################################ +# boards/arm/stm32/stm32f411e-disco/src/Makefile +# +# Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +endif + +ifeq ($(CONFIG_NSH_LIBRARY),y) +CSRCS += stm32_appinit.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32/nucleo-f412zg/src/nucleo-f412zg.h b/boards/arm/stm32/nucleo-f412zg/src/nucleo-f412zg.h new file mode 100644 index 0000000000..3dcfafd56b --- /dev/null +++ b/boards/arm/stm32/nucleo-f412zg/src/nucleo-f412zg.h @@ -0,0 +1,183 @@ +/**************************************************************************** + * boards/arm/stm32/stm32f411e-disco/src/stm32f411e-disco.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Frank Bennett + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F412ZG_SRC_NUCLEO_F412ZG_H +#define __BOARDS_ARM_STM32_NUCLEO_F412ZG_SRC_NUCLEO_F412ZG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* LED. User LD2: the green LED is a user LED connected to Arduino signal + * D13 corresponding to MCU I/O PA5 (pin 21) or PB13 (pin 34) depending on + * the STM32 target. + * + * - When the I/O is HIGH value, the LED is on. + * - When the I/O is LOW, the LED is off. + */ + +/* Buttons + * + * B1 USER: the user button is connected to the I/O PA0 of the STM32 + * microcontroller. + */ + +#define MIN_IRQBUTTON BUTTON_USER +#define MAX_IRQBUTTON BUTTON_USER +#define NUM_IRQBUTTONS 1 + +#define GPIO_BTN_USER \ + (GPIO_INPUT |GPIO_FLOAT |GPIO_EXTI | GPIO_PORTA | GPIO_PIN0) + +/* SPI1 off */ + +#define GPIO_SPI1_MOSI_OFF (GPIO_INPUT | GPIO_PULLDOWN | \ + GPIO_PORTA | GPIO_PIN7) +#define GPIO_SPI1_MISO_OFF (GPIO_INPUT | GPIO_PULLDOWN | \ + GPIO_PORTA | GPIO_PIN6) +#define GPIO_SPI1_SCK_OFF (GPIO_INPUT | GPIO_PULLDOWN | \ + GPIO_PORTA | GPIO_PIN5) + +/* USB OTG FS + * + * PA9 OTG_FS_VBUS VBUS sensing (also connected to the green LED) + * PC0 OTG_FS_PowerSwitchOn + * PD5 OTG_FS_Overcurrent + */ + +#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|\ + GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9) +#define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|\ + GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN0) + +#ifdef CONFIG_USBHOST +# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_EXTI|GPIO_FLOAT|\ + GPIO_SPEED_100MHz|GPIO_PUSHPULL|\ + GPIO_PORTD|GPIO_PIN5) + +#else +# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|\ + GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN5) +#endif + +/* procfs File System */ + +#ifdef CONFIG_FS_PROCFS +# ifdef CONFIG_NSH_PROC_MOUNTPOINT +# define STM32_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT +# else +# define STM32_PROCFS_MOUNTPOINT "/proc" +# endif +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Global driver instances */ + +#ifdef CONFIG_STM32_SPI1 +extern struct spi_dev_s *g_spi1; +#endif +#ifdef CONFIG_STM32_SPI2 +extern struct spi_dev_s *g_spi2; +#endif + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins. + * + ****************************************************************************/ + +void stm32_spidev_initialize(void); + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_boardinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F4Discovery board. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_OTGFS +void stm32_usbinitialize(void); +#endif + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. This function will start a thread that will monitor for + * device connection/disconnection events. + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) +int stm32_usbhost_initialize(void); +#endif + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void); + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F412ZG_SRC_NUCLEO_F412ZG_H */ diff --git a/boards/arm/stm32/nucleo-f412zg/src/stm32_appinit.c b/boards/arm/stm32/nucleo-f412zg/src/stm32_appinit.c new file mode 100644 index 0000000000..fadc2cbae6 --- /dev/null +++ b/boards/arm/stm32/nucleo-f412zg/src/stm32_appinit.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * boards/arm/stm32/stm32f411e-disco/src/stm32_appinit.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include "nucleo-f412zg.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifndef CONFIG_BOARD_LATE_INITIALIZE + /* Perform board-specific initialization */ + + return stm32_bringup(); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32/nucleo-f412zg/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f412zg/src/stm32_autoleds.c new file mode 100644 index 0000000000..4ee685fa9e --- /dev/null +++ b/boards/arm/stm32/nucleo-f412zg/src/stm32_autoleds.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32/nucleo-f446re/src/stm32_autoleds.c + * + * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" +#include "stm32.h" +#include "nucleo-f412zg.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + stm32_configgpio(GPIO_LD1); + stm32_configgpio(GPIO_LD2); + stm32_configgpio(GPIO_LD3); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + case 1: + stm32_gpiowrite(GPIO_LD1, true); + break; + case 2: + stm32_gpiowrite(GPIO_LD1, true); + stm32_gpiowrite(GPIO_LD2, true); + break; + case 3: + stm32_gpiowrite(GPIO_LD1, true); + stm32_gpiowrite(GPIO_LD2, true); + stm32_gpiowrite(GPIO_LD3, true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case 1: + stm32_gpiowrite(GPIO_LD1, false); + break; + case 2: + stm32_gpiowrite(GPIO_LD1, false); + stm32_gpiowrite(GPIO_LD2, false); + break; + case 3: + stm32_gpiowrite(GPIO_LD1, false); + stm32_gpiowrite(GPIO_LD2, false); + stm32_gpiowrite(GPIO_LD3, false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f412zg/src/stm32_boot.c b/boards/arm/stm32/nucleo-f412zg/src/stm32_boot.c new file mode 100644 index 0000000000..29dc7815f6 --- /dev/null +++ b/boards/arm/stm32/nucleo-f412zg/src/stm32_boot.c @@ -0,0 +1,114 @@ +/**************************************************************************** + * boards/arm/stm32/stm32f411e-disco/src/stm32_boot.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Librae + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include + +#include "up_arch.h" +#include "nucleo-f412zg.h" +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the + * weak function stm32_spidev_initialize() has been brought into the link. + */ + + stm32_spidev_initialize(); +#endif + +#ifdef CONFIG_STM32_OTGFS + /* Initialize USB if the OTG FS controller is in the configuration. + * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. + */ + + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32/nucleo-f412zg/src/stm32_bringup.c b/boards/arm/stm32/nucleo-f412zg/src/stm32_bringup.c new file mode 100644 index 0000000000..439d4c5e2d --- /dev/null +++ b/boards/arm/stm32/nucleo-f412zg/src/stm32_bringup.c @@ -0,0 +1,99 @@ +/**************************************************************************** + * boards/arm/stm32/stm32f411e-disco/src/stm32_bringup.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-f412zg.h" + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to initialize USB host: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to mount procfs at %s: %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c b/boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c new file mode 100644 index 0000000000..ce8418f540 --- /dev/null +++ b/boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c @@ -0,0 +1,357 @@ +/**************************************************************************** + * boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Copyright (C) 2017 Brian Webb. All rights reserved. + * Author: Brian Webb + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "up_arch.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "nucleo-f412zg.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if !defined(CONFIG_USBDEV) && !defined(CONFIG_USBHOST) +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +#endif + +#ifndef CONFIG_STM32F411DISCO_USBHOST_PRIO +# define CONFIG_STM32F411DISCO_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_STM32F411DISCO_USBHOST_STACKSIZE +# define CONFIG_STM32F411DISCO_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in inialization to setup + * USB-related GPIO pins for the STM32F411 Discovery board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required. + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs. + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. This function will start a thread that will monitor + * for device connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int pid; +#if defined(CONFIG_USBHOST_HUB) || defined(CONFIG_USBHOST_MSC) || \ + defined(CONFIG_USBHOST_HIDKBD) || defined(CONFIG_USBHOST_HIDMOUSE) || \ + defined(CONFIG_USBHOST_XBOXCONTROLLER) + int ret; +#endif + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_XBOXCONTROLLER + /* Initialize the HID mouse class */ + + ret = usbhost_xboxcontroller_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the XBox Controller class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + pid = kthread_create("usbhost", CONFIG_STM32F411DISCO_USBHOST_PRIO, + CONFIG_STM32F411DISCO_USBHOST_STACKSIZE, + (main_t)usbhost_waiter, (FAR char * const *)NULL); + return pid < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface. + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a charge + * pump or, if 5 V are available on the application board, a basic power + * switch, must be added externally to drive the 5 V VBUS line. The + * external charge pump can be driven by any GPIO output. When the + * application decides to power on VBUS using the chosen GPIO, it must + * also set the port power bit in the host port control and status + * register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, and + * the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent condition + * is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */