ARMv7-A: Map all of .text, .bss, .data., stacks before enabling the MMU and caching. This is simpler and avoids fears I have about caching
This commit is contained in:
Gregory Nutt
parent
f2195a16b2
commit
b148465beb
@ -5248,4 +5248,8 @@
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enabled by CONFIG_PAGING out of arm_head.S. That was just
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too much conditional compilation to be supportable
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(2013-8-1).
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* arch/arm/src/sama5/arm_head.S: Setup page table mappings for
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all of .text, .bss, .data, stacks and heap before enabling
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the MMU and caching. This is safer because it avoids the
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caching issues (and much less redundant) (2013-8-1)
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@ -144,7 +144,6 @@
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* Read/eXecute address region. This is based on NUTTX_TEXT_SIZE.
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*/
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#define RX_NSECTIONS ((NUTTX_TEXT_SIZE+0x000fffff) >> 20)
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#define WR_NSECTIONS ((NUTTX_RAM_SIZE+0x000fffff) >> 20)
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/****************************************************************************
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@ -207,9 +206,9 @@ __start:
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/* Clear the 16K level 1 page table */
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ldr r4, .LCppgtable /* r4=phys. page table */
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ldr r5, .LCppgtable /* r5=phys. page table */
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#ifndef CONFIG_ARCH_ROMPGTABLE
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mov r0, r4
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mov r0, r5
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mov r1, #0
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add r2, r0, #PGTABLE_SIZE
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.Lpgtableclear:
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@ -220,6 +219,19 @@ __start:
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teq r0, r2
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bne .Lpgtableclear
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/* Load information needed to map the .text region. After the ldmia, we
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* will have:
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*
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* R1 = Aligned, physical address of the start of the .text region
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* R2 = Aligned, virtual address of the start of the .text region
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* R3 = MMU flags associated with the .txt region
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* R4 = The number of 1MB sections in the mapping
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* R5 = The physical address of the L1 page table (from above)
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*/
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adr r0, .LCtextinfo /* Address of text info */
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ldmia r0, {r1, r2, r3, r4} /* Load the text description */
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/* Create identity mapping for first MB of the .text section to support
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* this startup logic executing out of the physical address space. This
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* identity mapping will be removed by .Lvstart (see below). Of course,
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@ -228,54 +240,73 @@ __start:
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*/
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#ifndef CONFIG_IDENTITY_TEXTMAP
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ldr r0, .LCptextbase /* r0=phys. base address of .text section */
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ldr r1, .LCtextflags /* R1=.text section MMU flags */
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orr r3, r1, r0 /* r3=flags + base */
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str r3, [r4, r0, lsr #18] /* identity mapping */
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orr r0, r1, r3 /* OR MMU flags into physical address */
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str r0, [r5, r1, lsr #18] /* Identity mapping */
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#endif
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/* Create a virtual single section mapping for the first MB of the .text
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* address space. Now, we have the first 1MB mapping to both physical and
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* virtual addresses. The rest of the .text mapping will be completed in
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* .Lvstart once we have moved the physical mapping out of the way.
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/* Map the entire .text regtion. We do this before enabling caches so
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* we know that the data will be in place in the data cache. We map the
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* entire text region because we don't know which parts are needed for
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* start-up.
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*
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* Here we expect to have:
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* r4 = Address of the base of the L1 table
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* The page table base address is in R5. Each 32-bit page table entry
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* maps 1 MB of address space and is indexed by the lower 20 bits of
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* the virtual address in R2
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*/
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#ifdef CONFIG_IDENTITY_TEXTMAP
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ldr r0, .LCptextbase /* r0=phys. base address of .text section */
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ldr r1, .LCtextflags /* R1=.text section MMU flags */
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orr r3, r1, r0 /* r3=flags + base */
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#endif
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add r2, r5, r2, lsr #18 /* R2=Offset page table address */
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ldr r0, .LCvtextbase /* r0=virtual base address of .text section */
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str r3, [r4, r0, lsr #18] /* Save the L1 entry using vaddress as an index */
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/* NOTE: No .data/.bss access should be attempted. This temporary mapping
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* can only be assumed to cover the initial .text region.
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/* No loop until each page table entry has been written for the .text
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* regtion.
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*/
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.Lpgtextloop:
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orr r0, r1, r3 /* R0: OR MMU flags into physical address */
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subs r4, r4, #1 /* R4: Decrement the section count */
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str r0, [r2], #4 /* Save page table entry, increment page table address */
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add r1, r1, #(1024*1024) /* R1: Increment the physical address */
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bne .Lpgtextloop /* Loop while R4 is non-zero */
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#ifdef CONFIG_BOOT_RUNFROMFLASH
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/* If we are executing from FLASH, then we will need an additional mapping
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* for the page table itself (otherwise, we will crash when we try to modify
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* the page table after turning the MMU on.
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/* If we are executing from FLASH, then we will need additional mappings for
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* the primay RAM region that holds the .data, .bss, stack, and heap memory.
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*
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* Here we expect to have:
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* r4 = Address of the base of the L1 table
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* Here we expect to have:
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* r5 = Address of the base of the L1 table
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*
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* REVISIT: We might need this second mapping under certain conditions
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* when executing from RAM too. When the RAM region is larger than 1MB
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* and the page table is in the high end of RAM, then the single mapping
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* above will not be sufficient.
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* REVISIT: We might need this second mapping under certain conditions
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* when executing from RAM too. When the RAM region is larger than 1MB
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* and the page table is in the high end of RAM, then the single mapping
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* above will not be sufficient.
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*
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* REVISIT: If the page table is not located in the primary RAM regions,
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* then we will also need an additional map the page table if the page
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* table resides in internal SRAM.
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*
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* Load information needed to map the .text region. After the ldmia, we
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* will have:
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*
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* R1 = Aligned, physical address of the start of the .text region
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* R2 = Aligned, virtual address of the start of the .text region
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* R3 = MMU flags associated with the .txt region
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* R4 = The number of 1MB sections in the mapping
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* R5 = The physical address of the L1 page table (from above)
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*/
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ldr r0, .LCprambase /* r0=phys. base address of the primary RAM region */
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ldr r1, .LCramflags /* R1=MMU flags use with the primary RAM region */
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orr r3, r1, r0 /* r3=flags + base */
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adr r0, .LCraminfo /* Address of primary RAM info */
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ldmia r0, {r1, r2, r3, r4} /* Load the primary RAM description */
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add r2, r5, r2, lsr #18 /* R2=Offset page table addres */
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ldr r0, .LCvrambase /* r0=virtual base address of .text section */
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str r3, [r4, r0, lsr #18] /* Save the L1 entry using vaddress as an index */
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/* Loop until each page table entry has been written for the primary RAM
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* region.
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*/
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.Lpgramloop:
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orr r0, r1, r3 /* R0: OR MMU flags into physical address */
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subs r4, r4, #1 /* R4: Decrement the section count */
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str r0, [r2], #4 /* Save page table entry, increment page table address */
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add r1, r1, #(1024*1024) /* R1: Increment the physical address */
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bne .Lpgramloop /* Loop while R4 is non-zero */
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#endif /* CONFIG_BOOT_RUNFROMFLASH */
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#endif /* CONFIG_ARCH_ROMPGTABLE */
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@ -283,7 +314,7 @@ __start:
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/* The following logic will set up the ARMv7-A for normal operation.
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*
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* Here we expect to have:
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* r4 = Address of the base of the L1 table
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* r5 = Address of the base of the L1 table
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*/
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/* Invalidate caches and TLBs.
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@ -314,11 +345,11 @@ __start:
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*
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* Here we expect to have:
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* r0 = Zero
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* r4 = Address of the base of the L1 table
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* r5 = Address of the base of the L1 table
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*/
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mcr CP15_TTBR0(r4)
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mcr CP15_TTBR1(r4)
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mcr CP15_TTBR0(r5)
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mcr CP15_TTBR1(r5)
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/* Set the TTB control register (TTBCR) to indicate that we are using
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* TTBR0. r0 still holds the value of zero.
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@ -457,64 +488,6 @@ __start:
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* PC_Relative Data
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****************************************************************************/
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/* The virtual start address of the second phase boot logic */
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.type .LCvstart, %object
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.LCvstart:
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.long .Lvstart
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.size .LCvstart, . -.LCvstart
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#ifndef CONFIG_ARCH_ROMPGTABLE
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/* The aligned, physical base address of the .text section */
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.type .LCptextbase, %object
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.LCptextbase:
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.long NUTTX_TEXT_PADDR & 0xfff00000
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.size .LCptextbase, . -.LCptextbase
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/* The aligned, virtual base address of the .text section */
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.type .LCvtextbase, %object
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.LCvtextbase:
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.long NUTTX_TEXT_VADDR & 0xfff00000
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.size .LCvtextbase, . -.LCvtextbase
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/* The MMU flags used with the .text mapping */
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.type .LCtextflags, %object
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.LCtextflags:
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#ifdef CONFIG_BOOT_RUNFROMFLASH
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.long MMU_ROMFLAGS /* MMU flags text section in FLASH/ROM */
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#else
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.long MMU_MEMFLAGS /* MMU flags for text section in RAM */
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#endif
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.size .LCtextflags, . -.LCtextflags
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#ifdef CONFIG_BOOT_RUNFROMFLASH
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/* The physical base address of the primary RAM region */
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.type .LCprambase, %object
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.LCprambase:
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.long NUTTX_RAM_PADDR & 0xfff00000
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.size .LCprambase, . -.LCprambase
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/* The virtual base address of the primary RAM region */
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.type .LCvrambase, %object
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.LCvrambase:
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.long NUTTX_RAM_VADDR & 0xfff00000
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.size .LCvrambase, . -.LCvrambase
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/* The MMU flags used with the primary RAM region */
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.type .LCramflags, %object
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.LCramflags:
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.long MMU_MEMFLAGS /* MMU flags for RAM section */
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.size .LCramflags, . -.LCramflags
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#endif /* CONFIG_BOOT_RUNFROMFLASH */
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#endif /* CONFIG_ARCH_ROMPGTABLE */
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/* The physical base address of the page table */
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.type .LCppgtable, %object
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@ -523,15 +496,63 @@ __start:
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.size .LCppgtable, . -.LCppgtable
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#ifndef CONFIG_ARCH_ROMPGTABLE
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/* The virtual base address of the page table */
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/* Text region description. The order of these fields must not change
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* because the values are loaded using ldmia:
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*
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* 1) The aligned, physical base address of the .text section
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* 2) The aligned, virtual base address of the .text section
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* 3) The MMU flags to use with the .text space mapping
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* 4) The number of 1MB sections in the .text region
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*
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* Values provided for NUTTX_TEXT_* must all be properly aligned to 1MB
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* address boundaries
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*/
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.type .LCvpgtable, %object
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.LCvpgtable:
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.long PGTABLE_BASE_VADDR /* Virtual start of page table */
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.size .LCvpgtable, . -.LCvpgtable
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.type .LCtextinfo, %object
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.LCtextinfo:
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.LCptextbase:
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.long NUTTX_TEXT_PADDR /* Physical base address */
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.long NUTTX_TEXT_VADDR /* Virtual base address */
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.LCtextflags:
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#ifdef CONFIG_BOOT_RUNFROMFLASH
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.long MMU_ROMFLAGS /* MMU flags text section in FLASH/ROM */
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#else
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.long MMU_MEMFLAGS /* MMU flags for text section in RAM */
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#endif
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.long (NUTTX_TEXT_SIZE >> 20) /* Number of 1MB read-execute sections */
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.size .LCtextinfo, . -.LCtextinfo
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#ifdef CONFIG_BOOT_RUNFROMFLASH
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/* Primary RAM region description. The order of these fields must not change
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* because the values are loaded using ldmia:
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*
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* 1) The aligned, physical base address of the primary RAM section
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* 2) The aligned, virtual base address of the primary RAM section
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* 3) The MMU flags to use with the primary RAM space mapping
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* 4) The number of 1MB sections in the primary RAM region
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*
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* Values provided for NUTTX_RAM_* must all be properly aligned to 1MB
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* address boundaries
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*/
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.type .LCraminfo, %object
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.LCraminfo:
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.long NUTTX_RAM_PADDR /* Physical base address */
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.long NUTTX_RAM_VADDR /* Virtual base address */
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.long MMU_MEMFLAGS /* MMU flags for primary RAM section */
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.long (NUTTX_RAM_SIZE >> 20) /* Number of 1MB read-execute sections */
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.size .LCraminfo, . -.LCraminfo
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#endif /* CONFIG_BOOT_RUNFROMFLASH */
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#endif /* CONFIG_ARCH_ROMPGTABLE */
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/* The virtual start address of the second phase boot logic */
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.type .LCvstart, %object
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.LCvstart:
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.long .Lvstart
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.size .LCvstart, . -.LCvstart
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.size __start, .-__start
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/****************************************************************************
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@ -552,82 +573,12 @@ __start:
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* cover additional RAM sections.
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*/
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#ifndef CONFIG_ARCH_ROMPGTABLE
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#ifndef CONFIG_IDENTITY_TEXTMAP
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ldr r4, .LCvpgtable /* r4=virtual page table base address */
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ldr r3, .LCvtextbase /* r0=virtual base address of .text section */
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#if !defined(CONFIG_ARCH_ROMPGTABLE) && !defined(CONFIG_IDENTITY_TEXTMAP)
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ldr r5, .LCvpgtable /* r5=Virtual page table base address */
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ldr r3, .LCptextbase /* r0=Physical base address of .text section */
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mov r0, #0 /* flags + base = 0 */
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str r3, [r4, r3, lsr #18] /* identity mapping */
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#endif
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/* Get the following value (if we did not already do so above):
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*
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* R4 = Virtual address of the page table
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* R3 = Physical address of the NuttX execution space (aligned to a
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* one megabyte addres boundary
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*/
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#ifdef CONFIG_IDENTITY_TEXTMAP
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ldr r4, .LCvpgtable /* r4=virtual page table */
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#endif
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ldr r3, .LCptextbase /* r3=Aligned Nuttx start address (physical) */
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/* Now setup the page tables for our normal mapped execution region.
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* We round NUTTX_TEXT_VADDR down to the nearest megabyte boundary.
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*/
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ldr r1, .LCtextflags /* R1=.text section MMU flags */
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add r3, r3, r1 /* r3=flags + base */
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add r0, r4, #(NUTTX_TEXT_VADDR & 0xfff00000) >> 18
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str r3, [r0], #4
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/* Now map the remaining RX_NSECTIONS-1 sections of the executable
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* memory region.
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*/
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.rept RX_NSECTIONS-1
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add r3, r3, #SECTION_SIZE
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str r3, [r0], #4
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.endr
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/* If we are executing from RAM with a fixed page configuration, then
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* we can assume that the above contiguous mapping included all of the
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* .text, .data, .bss, heap, etc. But if we are executing from FLASH,
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* then the RAM area is probably in a separate physical address region
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* and will require a separate mapping. Or, if we are supporting on-demand
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* paging of the .text region, then the RAM-based .data/.bss/heap section
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* will still probably be located in a separate (virtual) address region.
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*
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* Here we still have R4 = The virtual address of the page table.
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*/
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#ifdef CONFIG_BOOT_RUNFROMFLASH
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/* Get R3 = Value of RAM L1 page table entry */
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ldr r3, .LCprambase /* r3=Aligned Nuttx RAM address (physical) */
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ldr r1, .LCramflags /* R1=.bss/.data section MMU flags */
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add r3, r3, r1 /* r3=flags + base */
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/* Now setup the page tables for our normal mapped RAM region.
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* We round NUTTX_RAM_VADDR down to the nearest megabyte boundary.
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*/
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add r0, r4, #(NUTTX_RAM_VADDR & 0xfff00000) >> 18
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str r3, [r0], #4
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/* Now map the remaining WR_NSECTIONS-1 sections of the RAM memory
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* region.
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*/
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.rept WR_NSECTIONS-1
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add r3, r3, #SECTION_SIZE
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str r3, [r0], #4
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.endr
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#endif /* CONFIG_BOOT_RUNFROMFLASH */
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#endif /* CONFIG_ARCH_ROMPGTABLE */
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str r3, [r5, r3, lsr #18] /* identity mapping */
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#endif /* !CONFIG_ARCH_ROMPGTABLE && !CONFIG_IDENTITY_TEXTMAP */
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/* Zero BSS and set up the stack pointer */
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@ -681,6 +632,16 @@ __start:
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* end of memory. See g_idle_topstack below.
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*/
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#ifndef CONFIG_ARCH_ROMPGTABLE
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/* The virtual base address of the page table */
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.type .LCvpgtable, %object
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.LCvpgtable:
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.long PGTABLE_BASE_VADDR /* Virtual start of page table */
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.size .LCvpgtable, . -.LCvpgtable
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#endif /* CONFIG_ARCH_ROMPGTABLE */
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.type .Linitparms, %object
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.Linitparms:
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.long _sbss
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@ -443,7 +443,8 @@
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# define NUTTX_TEXT_VADDR (CONFIG_FLASH_VSTART & 0xfff00000)
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# define NUTTX_TEXT_PADDR (CONFIG_FLASH_START & 0xfff00000)
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# define NUTTX_TEXT_SIZE (CONFIG_FLASH_END - NUTTX_TEXT_VADDR)
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# define NUTTX_TEXT_PEND ((CONFIG_FLASH_END + 0x000fffff) & 0xfff00000)
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# define NUTTX_TEXT_SIZE (NUTTX_TEXT_PEND - NUTTX_TEXT_PADDR)
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/* In the default configuration, the primary RAM use for .bss and .data
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* is the internal SRAM.
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@ -451,7 +452,8 @@
|
||||
|
||||
# define NUTTX_RAM_VADDR (CONFIG_RAM_VSTART & 0xfff00000)
|
||||
# define NUTTX_RAM_PADDR (CONFIG_RAM_START & 0xfff00000)
|
||||
# define NUTTX_RAM_SIZE (CONFIG_RAM_END - NUTTX_RAM_PADDR)
|
||||
# define NUTTX_RAM_PEND ((CONFIG_RAM_END + 0x000fffff) & 0xfff00000)
|
||||
# define NUTTX_RAM_SIZE (NUTTX_RAM_PEND - NUTTX_RAM_PADDR)
|
||||
|
||||
#else
|
||||
/* Otherwise we are running from some kind of RAM (ISRAM or SDRAM).
|
||||
@ -460,7 +462,8 @@
|
||||
|
||||
# define NUTTX_TEXT_VADDR (CONFIG_RAM_VSTART & 0xfff00000)
|
||||
# define NUTTX_TEXT_PADDR (CONFIG_RAM_START & 0xfff00000)
|
||||
# define NUTTX_TEXT_SIZE (CONFIG_RAM_END - NUTTX_TEXT_VADDR)
|
||||
# define NUTTX_TEXT_PEND ((CONFIG_RAM_END + 0x000fffff) & 0xfff00000)
|
||||
# define NUTTX_TEXT_SIZE (NUTTX_TEXT_PEND - NUTTX_TEXT_PADDR)
|
||||
#endif
|
||||
|
||||
/* MMU Page Table Location
|
||||
|
||||
Loading…
Reference in New Issue
Block a user