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documentation: add documentation for ESP32-S2/S3/C3

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Add documentation for ESP32-S2 and ESP32-S2 Saola 1 board
Add links to already existing ESP32-S3 documentation
Add links to already existing ESP32-C3 documentation
This commit is contained in:
Tiago Medicci Serrano 2022-10-12 13:24:00 -03:00 committed by Xiang Xiao
parent 1d0a37cd10
commit b16ed003f1
6 changed files with 610 additions and 1 deletions
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43
Documentation/introduction/detailed_support.rst
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@ -3019,6 +3019,17 @@ LiteX on ARTY A7
Support for the Digilent ARTY_A7 board along with CPU VexRiscV SOC were
added in NuttX-9.0.
ESP32-C3
--------
Initial architectural support for ESP32-C3 (RISC-V) was added in NuttX-10.1.0
**Espressif ESP32-C3 Devkit Board** The NuttX release includes support for
Espressif ESP32-C3 Devkit board.
Please, refer to the :doc:`ESP32-C3 </platforms/risc-v/esp32c3/index>` on NuttX for
further information.
ESP32 (Dual Xtensa LX6)
=======================
@ -3026,7 +3037,7 @@ Xtensa LX6 ESP32
----------------
Initial architectural support for Xtensa LX6 processors for the Espressif
ESP32 were added in NuttX-7.19, enabling both single CPU and dual CPU
ESP32 was added in NuttX-7.19, enabling both single CPU and dual CPU
SMP configurations.
**Espressif ESP32 DevkitC V4 Board** The NuttX release includes support for
@ -3040,6 +3051,36 @@ includes: I2C, SPI, RTC, PM, Timers, Watchdog Timer and Ethernet.
Please, refer to the :doc:`ESP32 </platforms/xtensa/esp32/index>` on NuttX for
further information.
ESP32-S2 (Single Xtensa LX7)
=======================
Xtensa LX7 ESP32-S2
----------------
Initial architectural support for Xtensa LX7 processor for the Espressif
ESP32-S2 was added in NuttX-10.2.
**Espressif ESP32-S2 Saola V1 Board** The NuttX release includes support for
Espressif ESP32-S2 Saola V1 board.
Please, refer to the :doc:`ESP32-S2 </platforms/xtensa/esp32s2/index>` on NuttX for
further information.
ESP32-S3 (Dual Xtensa LX7)
=======================
Xtensa LX7 ESP32-S3
----------------
Initial architectural support for dual Xtensa LX7 processors for the Espressif
ESP32-S3 was added in NuttX-10.3.
**Espressif ESP32-S3 DevKit Board** The NuttX release includes support for
Espressif ESP32-S3 DevKit board.
Please, refer to the :doc:`ESP32-S3 </platforms/xtensa/esp32s3/index>` on NuttX for
further information.
Zilog ZNEO Z16F
===============

9
Documentation/introduction/supported_platforms.rst
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@ -68,11 +68,17 @@ from board-to-board. Follow the links for the details:
- :ref:`introduction/detailed_support:RISC-V` (2)
- :ref:`introduction/detailed_support:LiteX on Arty A7` (1)
- :ref:`introduction/detailed_support:ESP32-C3` (1)
- Xtensa LX6:
- :ref:`introduction/detailed_support:ESP32 (Dual Xtensa LX6)` (1)
- Xtensa LX7:
- :ref:`introduction/detailed_support:ESP32-S2 (Single Xtensa LX7)` (1)
- :ref:`introduction/detailed_support:ESP32-S3 (Dual Xtensa LX7)` (1)
- ZiLOG
- :ref:`introduction/detailed_support:ZiLOG ZNEO Z16F` (2)
@ -103,6 +109,9 @@ MCU. Follow the links for the details:
- Espressif
- :ref:`introduction/detailed_support:Xtensa LX6 ESP32` (Dual Xtensa LX6)
- :ref:`introduction/detailed_support:Xtensa LX7 ESP32-S2` (Single Xtensa LX7)
- :ref:`introduction/detailed_support:Xtensa LX7 ESP32-S3` (Dual Xtensa LX7)
- :ref:`introduction/detailed_support:ESP32-C3` (RISC-V)
- Host PC based simulations

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================
ESP32-S2-Saola-1
================
The `ESP32-S2-Saola-1 <https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-saola-1-v1.2.html>`_
is a development board for the ESP32-S2 SoC from Espressif, based on the following modules:
- ESP32-S2-WROVER
- ESP32-S2-WROVER-I
- ESP32-S2-WROOM
- ESP32-S2-WROOM-I
In this guide, we take ESP32-S2-Saola-1 equipped with ESP32-S2-WROVER as an example.
.. figure:: esp32-s2-saola-1-v1.2-isometric.png
:alt: ESP32-S2-Saola-1
:figclass: align-center
ESP32-S2-Saola-1
Features
========
- ESP32-S2-WROVER
- 4 MB external SPI flash + 2 MB PSRAM
- USB-to-UART bridge via micro USB port
- Power LED
- EN and BOOT buttons
- RGB LED (Addressable RGB LED (WS2812), driven by GPIO18)
Serial Console
==============
UART0 is, by default, the serial console. It connects to the on-board
CP2102 converter and is available on the micro-USB connector (J1).
It will show up as /dev/ttyUSB[n] where [n] will probably be 0.
Buttons and LEDs
================
Buttons
-------
There are two buttons labeled Boot and EN. The EN button is not available
to the software. It pulls the chip enable line that doubles as a reset line.
The BOOT button is connected to IO0. On reset, it is used as a strapping
pin to determine whether the chip boots normally or into the serial
bootloader. After resetting, however, the BOOT button can be used for
software input.
LEDs
----
There are two on-board LEDs. RED_LED (D5) indicates the presence of 3.3V
power and is not controlled by software. RGB LED (U6) is a WS2812 addressable
LED and is driven by GPIO18.
I2S
===
ESP32-S2 has an I2S peripheral accessible using either the generic I2S audio
driver or a specific audio codec driver
(`CS4344 <https://www.cirrus.com/products/cs4344-45-48/>`__ bindings are
available at the moment). Also, it's possible to use the I2S character device
driver to bypass audio systems and write directly to the I2S peripheral.
.. note:: The I2S peripheral is able to work on two functional modes
internally: 16 and 32-bit width.
That limits using the I2S peripheral to play audio files other than 16/32
bit-widths as the internal buffer allocated for the audio content does not
consider the operation modes of the peripheral. This limitation is planned
to be removed soon by copying the buffers internally and making the
necessary adjustments.
.. note:: The above statement is not valid when using the I2S character
device driver.
It's possible to use 8, 16, 24, and 32-bit-widths writing directly to the
I2S character device. Just make sure to set the bit-width::
$ make menuconfig
-> System Type
-> ESP32-S2 Peripheral Selection
-> I2S
-> I2S0/1
-> Bit Witdh
And make sure the data stream buffer being written to the I2S peripheral is
aligned to the next boundary i.e. 16 bits for the 8 and 16-bit-widths and
32 bits for 24 and 32-bit-widths.
Configurations
==============
audio
-----
This configuration uses the I2S0 peripheral and an externally connected audio
codec to play an audio file. The easiest way of playing an uncompressed file
is embedding into the firmware. This configuration selects
`romfs example <https://github.com/apache/incubator-nuttx-apps/tree/master/examples/romfs>`_`
to allow that.
**Audio Codec Setup**
The CS4344 audio codec is connected to the following pins:
============ ========== =========================================
ESP32-S2 Pin CS4344 Pin Description
============ ========== =========================================
33 MCLK Master Clock
35 SCLK Serial Clock
34 LRCK Left Right Clock (Word Select)
36 SDIN Serial Data In on CS4344. (DOUT on ESP32)
============ ========== =========================================
**ROMFS example**
Prepare and build the `audio` defconfig::
$ make -j distclean && ./tools/configure.sh esp32s2-saola-1:audio && make
This will create a temporary folder in `apps/examples/romfs/testdir`. Move
a PCM-encoded (`.wav`) audio file with 16 bits/sample (sampled at 8~48kHz)
to this folder.
.. note:: You can use :download:`this 440 Hz sinusoidal tone <tone.wav>`.
The audio file should be located at `apps/examples/romfs/testdir/tone.wav`
Build the project again and flash it (make sure not to clean it, just build)
After successfully built and flashed, load the romfs and play it::
$ nsh> romfs
$ nsh> nxplayer
$ nxplayer> play /usr/share/local/tone.wav
i2schar
-------
This configuration enables the I2S character device and the i2schar example
app, which provides an easy-to-use way of testing the I2S peripheral.
After successfully built and flashed, run on the board's terminal::
$ i2schar
The corresponding output should show related debug information.
nsh
---
Basic NuttShell configuration (console enabled in UART0, exposed via
USB connection by means of CP2102 converter, at 115200 bps).
timer
-----
This config tests the general-use purpose timers. It includes the 4 timers,
adds driver support, registers the timers as devices and includes the timer
example.
To test it, just run the following::
nsh> timer -d /dev/timerx
Where x in the timer instance.
watchdog
--------
This config test the watchdog timers. It includes the 2 MWDTs,
adds driver support, registers the WDTs as devices and includes the watchdog
example.
To test it, just run the following::
nsh> wdog -d /dev/watchdogx
Where x in the watchdog instance.

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==================
Espressif ESP32-S2
==================
The ESP32-S2 is a series of single-core SoCs from Espressif based on Harvard
architecture Xtensa LX7 CPU and with on-chip support for Wi-Fi.
All embedded memory, external memory and peripherals are located on the
data bus and/or the instruction bus of the CPU. Multiple peripherals in
the system can access embedded memory via DMA.
Toolchain
=========
You can use the prebuilt `toolchain <https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-guides/tools/idf-tools.html#xtensa-esp32-elf>`__
for Xtensa architecture and `OpenOCD <https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-guides/tools/idf-tools.html#openocd-esp32>`__
for ESP32-S2 by Espressif.
For flashing firmware, you will need to install ``esptool.py`` by running::
$ pip install esptool
Building from source
--------------------
You can also build the toolchain yourself. The steps to
build the toolchain with crosstool-NG on Linux are as follows
.. code-block:: console
$ git clone https://github.com/espressif/crosstool-NG.git
$ cd crosstool-NG
$ git checkout esp-2021r1
$ git submodule update --init
$ ./bootstrap && ./configure --enable-local && make
$ ./ct-ng xtensa-esp32-elf
$ ./ct-ng build
$ chmod -R u+w builds/xtensa-esp32-elf
$ export PATH="crosstool-NG/builds/xtensa-esp32-elf/bin:$PATH"
Alternatively, you may follow the steps in
`ESP-IDF documentation <https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/get-started/linux-macos-setup.html>`_.
Flashing
========
Firmware for ESP32-S2 is flashed via the USB/UART or internal USB DEVICE JTAG interface using the
``esptool.py`` tool.
It's a two-step process where the first converts the ELF file into a ESP32-S2 compatible binary
and the second flashes it to the board. These steps are included in the build system and you can
flash your NuttX firmware simply by running::
$ make flash ESPTOOL_PORT=<port>
where ``<port>`` is typically ``/dev/ttyUSB0`` or similar. You can change the baudrate by passing ``ESPTOOL_BAUD``.
Bootloader and partitions
-------------------------
ESP32-S2 requires a bootloader to be flashed as well as a set of FLASH partitions. This is only needed the first time
(or any time you which to modify either of these).
An easy way is to use prebuilt binaries for NuttX `from here <https://github.com/espressif/esp-nuttx-bootloader>`_.
In there you will find instructions to rebuild these if necessary.
Once you downloaded both binaries, you can flash them by adding an ``ESPTOOL_BINDIR`` parameter, pointing to the directory where these binaries were downloaded:
.. code-block:: console
$ make flash ESPTOOL_PORT=<port> ESPTOOL_BINDIR=<dir>
.. note:: It is recommended that if this is the first time you are using the board with NuttX that you perform a complete
SPI FLASH erase.
.. code-block:: console
$ esptool.py erase_flash
.. note:: Alternatively, you can automatically download the bootloader/partitions from the NuttX build system
by using the following command:
.. code-block:: console
$ make bootloader
The binaries will be downloaded to the project's main folder and ``ESPTOOL_BINDIR`` may be set as ``.``
Peripheral Support
==================
The following list indicates the state of peripherals' support in NuttX:
========== ======= =====
Peripheral Support NOTES
========== ======= =====
GPIO Yes
UART Yes
SPI Yes
I2C Yes
DMA Yes
Wifi No
Ethernet No
SPIFLASH Yes
SPIRAM Yes
Timers Yes
Watchdog Yes
RTC Yes
RNG Yes
AES No
eFuse No
ADC No
I2S Yes
LED_PWM No
RMT No
Pulse_CNT No
SHA No
RSA No
CAN/TWAI No
========== ======= =====
Memory Map
==========
Address Mapping
---------------
================== ========== ========== =============== ===============
BUS TYPE START LAST DESCRIPTION NOTES
================== ========== ========== =============== ===============
. 0x00000000 0x3EFFFFFF Reserved
Data 0x3F000000 0x3F3FFFFF External Memory
Data 0x3F400000 0x3F4FFFFF Peripheral
Data 0x3F500000 0x3FF7FFFF External Memory
. 0x3FF80000 0x3FF9DFFF Reserved
Data 0x3FF9E000 0x3FFFFFFF Embedded Memory
Instruction 0x40000000 0x40071FFF Embedded Memory
. 0x40072000 0x4007FFFF Reserved
Instruction 0x40080000 0x407FFFFF External Memory
. 0x40800000 0x4FFFFFFF Reserved
Data / Instruction 0x50000000 0x50001FFF Embedded Memory
. 0x50002000 0x5FFFFFFF Reserved
Data / Instruction 0x60000000 0x600BFFFF Peripheral
. 0x600C0000 0x617FFFFF Reserved
Data / Instruction 0x61800000 0x61803FFF Peripheral
. 0x61804000 0xFFFFFFFF Reserved
================== ========== ========== =============== ===============
Embedded Memory
---------------
=========== ========== ========== =============== ================== =====
BUS TYPE START LAST DESCRIPTION PERMISSION CONTROL NOTES
=========== ========== ========== =============== ================== =====
Data 0x3FF9E000 0x3FF9FFFF RTC FAST Memory YES
Data 0x3FFA0000 0x3FFAFFFF Internal ROM 1 NO
Data 0x3FFB0000 0x3FFB7FFF Internal SRAM 0 YES DMA
Data 0x3FFB8000 0x3FFFFFFF Internal SRAM 1 YES DMA
=========== ========== ========== =============== ================== =====
Boundary Address (Embedded)
---------------------------
====================== ========== ========== =============== ================== ===============
BUS TYPE START LAST DESCRIPTION PERMISSION CONTROL NOTES
====================== ========== ========== =============== ================== ===============
Instruction 0x40000000 0x4000FFFF Internal ROM 0 NO
Instruction 0x40010000 0x4001FFFF Internal ROM 1 NO
Instruction 0x40020000 0x40027FFF Internal SRAM 0 YES
Instruction 0x40028000 0x4006FFFF Internal SRAM 1 YES
Instruction 0x40070000 0x40071FFF RTC FAST Memory YES
Data / Instruction 0x50000000 0x50001FFF RTC SLOW Memory YES
====================== ========== ========== =============== ================== ===============
External Memory
---------------
=========== ========== ========== =============== ================== ===============
BUS TYPE START LAST DESCRIPTION PERMISSION CONTROL NOTES
=========== ========== ========== =============== ================== ===============
Data 0x3F000000 0x3F3FFFFF ICache YES Read
Data 0x3F500000 0x3FF7FFFF DCache YES Read and Write
=========== ========== ========== =============== ================== ===============
Boundary Address (External)
---------------------------
=========== ========== ========== =============== ================== ===============
BUS TYPE START LAST DESCRIPTION PERMISSION CONTROL NOTES
=========== ========== ========== =============== ================== ===============
Instruction 0x40080000 0x407FFFFF ICache YES Read
=========== ========== ========== =============== ================== ===============
Linker Segments
---------------
+---------------------+------------+-------------------+------+------------------------------+
| DESCRIPTION | START | END | ATTR | LINKER SEGMENT NAME |
+=====================+============+===================+======+==============================+
| FLASH mapped data: | 0X3F000020 | 0X3F000020 + | R | drom0_0_seg (NOTE 1) |
| - .rodata | | FLASH_SIZE - 0x20 | | |
| - Constructors | | | | |
| /destructors | | | | |
+---------------------+------------+-------------------+------+------------------------------+
| COMMON data RAM: | 0X3FFB0000 | 0x3FFDE000 | RW | dram0_0_seg (NOTE 2) |
| - .bss/.data | | | | |
+---------------------+------------+-------------------+------+------------------------------+
| IRAM for PRO cpu: | 0x40022000 | 0x40050000 | RX | iram0_0_seg |
| - Interrupt Vectors| | | | |
| - Low level | | | | |
| handlers | | | | |
| - Xtensa/Espressif | | | | |
| libraries | | | | |
+---------------------+------------+-------------------+------+------------------------------+
| RTC fast memory: | 0x40070000 | 0x40072000 | RWX | rtc_iram_seg |
| - .rtc.text | | | | |
| (unused?) | | | | |
+---------------------+------------+-------------------+------+------------------------------+
| FLASH: | 0x40080020 | 0x40080020 + | RX | irom0_0_seg (actually FLASH) |
| - .text | | FLASH_SIZE | | |
| | | (NOTE 3) | | |
+---------------------+------------+-------------------+------+------------------------------+
| RTC slow memory: | 0x50000000 | 0x50002000 | RW | rtc_slow_seg (NOTE 4) |
| - .rtc.data/rodata | | | | |
| (unused?) | | | | |
+---------------------+------------+-------------------+------+------------------------------+
.. note::
(1) The linker script will reserve space at the beginning of the segment
for MCUboot header if ESP32S2_APP_FORMAT_MCUBOOT flag is active.
(2) Heap starts at the end of dram_0_seg.
(3) Subtract 0x20 if ESP32S2_APP_FORMAT_MCUBOOT is not active.
(4) Linker script will reserve space at the beginning and at the end
of the segment for ULP coprocessor reserve memory.
64-bit Timers
=============
ESP32-S2 has 4 generic timers of 64 bits (2 from Group 0 and 2 from Group 1).
They're accessible as character drivers, the configuration along with a
guidance on how to run the example and the description of the application level
interface can be found :doc:`here </components/drivers/character/timer>`.
Watchdog Timers
===============
ESP32-S2 has 3 WDTs. 2 MWDTs from the Timers Module and 1 RWDT from the RTC Module
(Currently not supported yet). They're accessible as character drivers,
The configuration along with a guidance on how to run the example and the description
of the application level interface can be found
:doc:`here </components/drivers/character/watchdog>`.
I2S
===
The I2S peripheral is accessible using either the generic I2S audio driver or a specific
audio codec driver. Also, it's possible to use the I2S character driver to bypass the
audio subsystem and develop specific usages of the I2S peripheral.
.. note:: Note that the bit-width and sample rate can be modified "on-the-go" when using
audio-related drivers. That is not the case for the I2S character device driver and
such parameters are set on compile time through `make menuconfig`.
Please check for usage examples using the :doc:`ESP32-S2-Saola-1 </platforms/xtensa/esp32s2/boards/esp32s2-saola-1/index>`.
Secure Boot and Flash Encryption
================================
Secure Boot
-----------
Secure Boot protects a device from running any unauthorized (i.e., unsigned) code by checking that
each piece of software that is being booted is signed. On an ESP32-S2, these pieces of software include
the second stage bootloader and each application binary. Note that the first stage bootloader does not
require signing as it is ROM code thus cannot be changed. This is achieved using specific hardware in
conjunction with MCUboot (read more about MCUboot `here <https://docs.mcuboot.com/>`_).
The Secure Boot process on the ESP32-S2 involves the following steps performed:
1. The first stage bootloader verifies the second stage bootloader's RSA-PSS signature. If the verification is successful,
the first stage bootloader loads and executes the second stage bootloader.
2. When the second stage bootloader loads a particular application image, the application's signature (RSA, ECDSA or ED25519) is verified
by MCUboot.
If the verification is successful, the application image is executed.
.. warning:: Once enabled, Secure Boot will not boot a modified bootloader. The bootloader will only boot an
application firmware image if it has a verified digital signature. There are implications for reflashing
updated images once Secure Boot is enabled. You can find more information about the ESP32-S2's Secure boot
`here <https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/security/secure-boot-v2.html>`_.
.. note:: As the bootloader image is built on top of the Hardware Abstraction Layer component
of `ESP-IDF <https://github.com/espressif/esp-idf>`_, the
`API port by Espressif <https://docs.mcuboot.com/readme-espressif.html>`_ will be used
by MCUboot rather than the original NuttX port.
Flash Encryption
----------------
Flash encryption is intended for encrypting the contents of the ESP32-S2's off-chip flash memory. Once this feature is enabled,
firmware is flashed as plaintext, and then the data is encrypted in place on the first boot. As a result, physical readout
of flash will not be sufficient to recover most flash contents.
.. warning:: After enabling Flash Encryption, an encryption key is generated internally by the device and
cannot be accessed by the user for re-encrypting data and re-flashing the system, hence it will be permanently encrypted.
Re-flashing an encrypted system is complicated and not always possible. You can find more information about the ESP32-S2's Flash Encryption
`here <https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/security/flash-encryption.html>`_.
Prerequisites
-------------
First of all, we need to install ``imgtool`` (a MCUboot utiliy application to manipulate binary images) and
``esptool`` (the ESP32-S2 toolkit)::
$ pip install imgtool esptool
We also need to make sure that the python modules are added to ``PATH``::
$ echo "PATH=$PATH:/home/$USER/.local/bin" >> ~/.bashrc
Now, we will create a folder to store the generated keys (such as ``~/signing_keys``)::
$ mkdir ~/signing_keys && cd ~/signing_keys
With all set up, we can now generate keys to sign the bootloader and application binary images,
respectively, of the compiled project::
$ espsecure.py generate_signing_key --version 2 bootloader_signing_key.pem
$ imgtool keygen --key app_signing_key.pem --type rsa-3072
.. important:: The contents of the key files must be stored securely and kept secret.
Enabling Secure Boot and Flash Encryption
-----------------------------------------
To enable Secure Boot for the current project, go to the project's NuttX directory, execute ``make menuconfig`` and the following steps::
1. Enable experimental features in :menuselection:`Build Setup --> Show experimental options`;
2. Enable MCUboot in :menuselection:`Application Configuration --> Bootloader Utilities --> MCUboot`;
3. Change image type to ``MCUboot-bootable format`` in :menuselection:`System Type --> Application Image Configuration --> Application Image Format`;
4. Enable building MCUboot from the source code by selecting ``Build binaries from source``;
in :menuselection:`System Type --> Application Image Configuration --> Source for bootloader binaries`;
5. Enable Secure Boot in :menuselection:`System Type --> Application Image Configuration --> Enable hardware Secure Boot in bootloader`;
6. If you want to protect the SPI Bus against data sniffing, you can enable Flash Encryption in
:menuselection:`System Type --> Application Image Configuration --> Enable Flash Encryption on boot`.
Now you can design an update and confirm agent to your application. Check the `MCUboot design guide <https://docs.mcuboot.com/design.html>`_ and the
`MCUboot Espressif port documentation <https://docs.mcuboot.com/readme-espressif.html>`_ for
more information on how to apply MCUboot. Also check some `notes about the NuttX MCUboot port <https://github.com/mcu-tools/mcuboot/blob/main/docs/readme-nuttx.md>`_,
the `MCUboot porting guide <https://github.com/mcu-tools/mcuboot/blob/main/docs/PORTING.md>`_ and some
`examples of MCUboot applied in Nuttx applications <https://github.com/apache/incubator-nuttx-apps/tree/master/examples/mcuboot>`_.
After you developed an application which implements all desired functions, you need to flash it into the primary image slot
of the device (it will automatically be in the confirmed state, you can learn more about image
confirmation `here <https://docs.mcuboot.com/design.html#image-swapping>`_).
To flash to the primary image slot, select ``Application image primary slot`` in
:menuselection:`System Type --> Application Image Configuration --> Target slot for image flashing`
and compile it using ``make -j ESPSEC_KEYDIR=~/signing_keys``.
When creating update images, make sure to change :menuselection:`System Type --> Application Image Configuration --> Target slot for image flashing`
to ``Application image secondary slot``.
.. important:: When deploying your application, make sure to disable UART Download Mode by selecting ``Permanently disabled`` in
:menuselection:`System Type --> Application Image Configuration --> UART ROM download mode`
and change usage mode to ``Release`` in `System Type --> Application Image Configuration --> Enable usage mode`.
**After disabling UART Download Mode you will not be able to flash other images through UART.**
Supported Boards
================
.. toctree::
:glob:
:maxdepth: 1
boards/*/*