Move all SAMA5 EHCI interrupt handling to the worker thread
This commit is contained in:
Gregory Nutt
parent
e5208a6e92
commit
b1864a995e
@ -386,14 +386,14 @@ config SAMA5_EHCI_NQHS
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default 4
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---help---
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Configurable number of Queue Head (QH) structures. The default is
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one per Root hub port plus one for EP0.
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one per Root hub port plus one for EP0 (4).
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config SAMA5_EHCI_NQTDS
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int "Number of Queue Element Transfer Descriptor (qTDs)"
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default 4
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default 6
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---help---
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Configurable number of Queue Element Transfer Descriptor (qTDs).
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The default is one per root hub plus three from EP0.
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The default is one per root hub plus three from EP0 (6).
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config SAMA5_EHCI_BUFSIZE
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int "Size of one request/descriptor buffer"
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@ -49,6 +49,7 @@
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#include <nuttx/arch.h>
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#include <nuttx/kmalloc.h>
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#include <nuttx/wqueue.h>
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#include <nuttx/usb/usb.h>
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#include <nuttx/usb/usbhost.h>
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#include <nuttx/usb/ehci.h>
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@ -67,6 +68,11 @@
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* Pre-processor Definitions
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*******************************************************************************/
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/* Configuration ***************************************************************/
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/* Pre-requisites */
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#ifndef CONFIG_SCHED_WORKQUEUE
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# error Work queue support is required (CONFIG_SCHED_WORKQUEUE)
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#endif
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/* Configurable number of Queue Head (QH) structures. The default is one per
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* Root hub port plus one for EP0.
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@ -96,6 +102,12 @@
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# undef CONFIG_SAMA5_EHCI_REGDEBUG
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#endif
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/* Driver-private Definitions **************************************************/
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#define EHCI_HANDLED_INTS (EHCI_INT_USBINT | EHCI_INT_USBERRINT | \
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EHCI_INT_PORTSC | EHCI_INT_SYSERROR | \
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EHCI_INT_AAINT)
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/*******************************************************************************
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* Private Types
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*******************************************************************************/
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@ -140,11 +152,12 @@ typedef int (*foreach_qtd_t)(struct sam_qtd_s *qtd, uint32_t **bp, void *arg);
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struct sam_epinfo_s
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{
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uint8_t epno; /* Endpoint number */
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uint8_t devaddr; /* Device address */
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uint8_t xfrtype; /* See USB_EP_ATTR_XFER_* definitions in usb.h */
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uint8_t speed; /* See USB_*_SPEED definitions in ehci.h */
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uint8_t flags; /* See EPINFO_FLAG_* definitions above */
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uint8_t epno:7; /* Endpoint number */
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uint8_t dirin:1; /* 1:IN endpoint 0:OUT endpoint */
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uint8_t devaddr:7; /* Device address */
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uint8_t toggle:1; /* Next data toggle */
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uint8_t xfrtype:2; /* See USB_EP_ATTR_XFER_* definitions in usb.h */
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uint8_t speed:2; /* See USB_*_SPEED definitions in ehci.h */
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volatile bool wait; /* TRUE: Thread is waiting for transfer completion */
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uint16_t maxpacket; /* Maximum packet size */
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sem_t wsem; /* Semaphore used to wait for transfer completion */
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@ -176,13 +189,14 @@ struct sam_rhport_s
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struct sam_ehci_s
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{
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volatile bool rhwait; /* TRUE: Thread is waiting for root hub event */
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volatile bool pscwait; /* TRUE: Thread is waiting for port status change event */
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sem_t exclsem; /* Support mutually exclusive access */
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sem_t rhsem; /* Semaphore to wait for root hub events */
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sem_t pscsem; /* Semaphore to wait for port status change events */
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struct sam_epinfo_s ep0; /* Endpoint 0 */
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struct sam_list_s *qhfree; /* List of free Queue Head (QH) structures */
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struct sam_list_s *qtdfree; /* List of free Queue Element Transfer Descriptor (qTD) */
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struct work_s work; /* Supports interrupt bottom half */
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/* Root hub ports */
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@ -251,7 +265,13 @@ static int sam_qh_flush(struct sam_qh_s *qh);
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/* Interrupt Handling **********************************************************/
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static int sam_ehci_interrupt(int irq, FAR void *context);
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static inline void sam_ioc_bottomhalf(void);
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static inline void sam_err_bottomhalf(void);
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static inline void sam_portsc_bottomhalf(void);
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static inline void sam_syserr_bottomhalf(void);
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static inline void sam_async_advance_bottomhalf(void);
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static void sam_ehci_bottomhalf(FAR void *arg);
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static int sam_ehci_tophalf(int irq, FAR void *context);
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/* USB Host Controller Operations **********************************************/
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@ -587,7 +607,7 @@ static int ehci_wait_usbsts(uint32_t maskbits, uint32_t donebits,
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/* We got here because either the waited for condition or a timeout
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* occurred. Return a value to indicate which.
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*/
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return (regval == donebits) ? OK : -ETIMEDOUT;
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}
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@ -1000,16 +1020,374 @@ static int sam_qh_flush(struct sam_qh_s *qh)
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*******************************************************************************/
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/*******************************************************************************
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* Name: sam_ehci_interrupt
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* Name: sam_ioc_bottomhalf
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*
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* Description:
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* EHCI interrupt handler
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* EHCI USB Interrupt (USBINT) "Bottom Half" interrupt handler
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*
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* "The Host Controller sets this bit to 1 on the completion of a USB
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* transaction, which results in the retirement of a Transfer Descriptor that
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* had its IOC bit set.
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*
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* "The Host Controller also sets this bit to 1 when a short packet is detected
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* (actual number of bytes received was less than the expected number of
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* bytes)."
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*
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*******************************************************************************/
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static int sam_ehci_interrupt(int irq, FAR void *context)
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static inline void sam_ioc_bottomhalf(void)
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{
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#warning "Missing logic"
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ullvdbg("USB Interrupt (USBINT) Interrupt\n");
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}
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/*******************************************************************************
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* Name: sam_ioc_bottomhalf
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*
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* Description:
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* EHCI USB Error Interrupt (USBERRINT) "Bottom Half" interrupt handler
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*
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* "The Host Controller sets this bit to 1 when completion of a USB transaction
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* results in an error condition (e.g., error counter underflow). If the TD on
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* which the error interrupt occurred also had its IOC bit set, both this bit
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* and USBINT bit are set. ..."
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*
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*******************************************************************************/
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static inline void sam_err_bottomhalf(void)
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{
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ulldbg("USB Error Interrupt (USBERRINT) Interrupt\n");
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/* Remove all queued transfers */
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#warning Missing logic
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}
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/*******************************************************************************
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* Name: sam_portsc_bottomhalf
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*
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* Description:
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* EHCI Port Change Detect "Bottom Half" interrupt handler
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*
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* "The Host Controller sets this bit to a one when any port for which the Port
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* Owner bit is set to zero ... has a change bit transition from a zero to a
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* one or a Force Port Resume bit transition from a zero to a one as a result
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* of a J-K transition detected on a suspended port. This bit will also be set
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* as a result of the Connect Status Change being set to a one after system
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* software has relinquished ownership of a connected port by writing a one
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* to a port's Port Owner bit...
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*
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* "This bit is allowed to be maintained in the Auxiliary power well.
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* Alternatively, it is also acceptable that on a D3 to D0 transition of the
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* EHCI HC device, this bit is loaded with the OR of all of the PORTSC change
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* bits (including: Force port resume, over-current change, enable/disable
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* change and connect status change)."
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*
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*******************************************************************************/
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static inline void sam_portsc_bottomhalf(void)
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{
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struct sam_rhport_s *rhport;
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uint32_t portsc;
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int rhpndx;
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/* Handle root hub status change on each root port */
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for (rhpndx = 0; rhpndx < SAM_EHCI_NRHPORT; rhpndx++)
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{
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rhport = &g_ehci.rhport[rhpndx];
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portsc = sam_getreg(&HCOR->portsc[rhpndx]);
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ullvdbg("PORTSC%d: %08x\n", rhpndx + 1, portsc);
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/* Handle port connection status change (CSC) events */
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if ((portsc & EHCI_PORTSC_CSC) != 0)
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{
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ullvdbg("Connect Status Change\n");
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/* Check current connect status */
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if ((portsc & EHCI_PORTSC_CCS) != 0)
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{
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/* Connected ... Did we just become connected? */
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if (!rhport->connected)
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{
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/* Yes.. connected. */
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rhport->connected = true;
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ullvdbg("RHPort%d connected, pscwait: %d\n",
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rhpndx + 1, g_ehci.pscwait);
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/* Notify any waiters */
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if (g_ehci.pscwait)
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{
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sam_givesem(&g_ehci.pscsem);
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g_ehci.pscwait = false;
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}
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}
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else
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{
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ulldbg("Already connected\n");
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}
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}
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else
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{
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/* Disconnected... Did we just become disconnected? */
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if (rhport->connected)
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{
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/* Yes.. disconnect the device */
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ullvdbg("RHport%d disconnected\n", rhpndx+1);
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rhport->connected = false;
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rhport->lowspeed = false;
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/* Are we bound to a class instance? */
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if (rhport->class)
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{
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/* Yes.. Disconnect the class */
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CLASS_DISCONNECTED(rhport->class);
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rhport->class = NULL;
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}
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/* Notify any waiters for the Root Hub Status change
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* event.
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*/
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if (g_ehci.pscwait)
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{
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sam_givesem(&g_ehci.pscsem);
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g_ehci.pscwait = false;
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}
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}
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else
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{
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ulldbg("Already disconnected\n");
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}
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}
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}
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/* Clear all pending port interrupt sources by writing a '1' to the
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* corresponding bit in the PORTSC register.
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*/
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sam_putreg(portsc & EHCI_PORTSC_ALLINTS, &HCOR->portsc[rhpndx]);
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}
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}
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/*******************************************************************************
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* Name: sam_syserr_bottomhalf
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*
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* Description:
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* EHCI Host System Error "Bottom Half" interrupt handler
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*
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* "The Host Controller sets this bit to 1 when a serious error occurs during a
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* host system access involving the Host Controller module. ... When this
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* error occurs, the Host Controller clears the Run/Stop bit in the Command
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* register to prevent further execution of the scheduled TDs."
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*
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*******************************************************************************/
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static inline void sam_syserr_bottomhalf(void)
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{
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ulldbg("Host System Error Interrupt\n");
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PANIC();
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}
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/*******************************************************************************
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* Name: sam_async_advance_bottomhalf
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*
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* Description:
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* EHCI Async Advance "Bottom Half" interrupt handler
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*
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* "System software can force the host controller to issue an interrupt the
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* next time the host controller advances the asynchronous schedule by writing
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* a one to the Interrupt on Async Advance Doorbell bit in the USBCMD
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* register. This status bit indicates the assertion of that interrupt
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* source."
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*
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*******************************************************************************/
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static inline void sam_async_advance_bottomhalf(void)
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{
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ulldbg("Async Advance Interrupt\n");
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/* Remove all tagged QH entries */
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#warning Missing logic
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}
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/*******************************************************************************
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* Name: sam_ehci_bottomhalf
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*
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* Description:
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* EHCI "Bottom Half" interrupt handler
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*
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*******************************************************************************/
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static void sam_ehci_bottomhalf(FAR void *arg)
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{
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uint32_t pending = (uint32_t)arg;
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uint32_t regval;
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/* Handle all unmasked interrupt sources */
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/* USB Interrupt (USBINT)
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*
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* "The Host Controller sets this bit to 1 on the completion of a USB
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* transaction, which results in the retirement of a Transfer Descriptor
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* that had its IOC bit set.
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*
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* "The Host Controller also sets this bit to 1 when a short packet is
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* detected (actual number of bytes received was less than the expected
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* number of bytes)."
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*/
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if ((pending & EHCI_INT_USBINT) != 0)
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{
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sam_ioc_bottomhalf();
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}
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/* USB Error Interrupt (USBERRINT)
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*
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* "The Host Controller sets this bit to 1 when completion of a USB
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* transaction results in an error condition (e.g., error counter
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* underflow). If the TD on which the error interrupt occurred also
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* had its IOC bit set, both this bit and USBINT bit are set. ..."
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*/
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if ((pending & EHCI_INT_USBERRINT) != 0)
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{
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sam_err_bottomhalf();
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}
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/* Port Change Detect
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*
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* "The Host Controller sets this bit to a one when any port for which
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* the Port Owner bit is set to zero ... has a change bit transition
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* from a zero to a one or a Force Port Resume bit transition from a zero
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* to a one as a result of a J-K transition detected on a suspended port.
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* This bit will also be set as a result of the Connect Status Change
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* being set to a one after system software has relinquished ownership
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* of a connected port by writing a one to a port's Port Owner bit...
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*
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* "This bit is allowed to be maintained in the Auxiliary power well.
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* Alternatively, it is also acceptable that on a D3 to D0 transition
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* of the EHCI HC device, this bit is loaded with the OR of all of the
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* PORTSC change bits (including: Force port resume, over-current change,
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* enable/disable change and connect status change)."
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*/
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if ((pending & EHCI_INT_PORTSC) != 0)
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{
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sam_portsc_bottomhalf();
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}
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/* Frame List Rollover
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*
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* "The Host Controller sets this bit to a one when the Frame List Index ...
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* rolls over from its maximum value to zero. The exact value at which
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* the rollover occurs depends on the frame list size. For example, if
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* the frame list size (as programmed in the Frame List Size field of the
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* USBCMD register) is 1024, the Frame Index Register rolls over every
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* time FRINDEX[13] toggles. Similarly, if the size is 512, the Host
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* Controller sets this bit to a one every time FRINDEX[12] toggles."
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*/
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#if 0 /* Not used */
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if ((pending & EHCI_INT_FLROLL) != 0)
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{
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sam_flroll_bottomhalf();
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}
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#endif
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/* Host System Error
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*
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* "The Host Controller sets this bit to 1 when a serious error occurs
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* during a host system access involving the Host Controller module. ...
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* When this error occurs, the Host Controller clears the Run/Stop bit
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* in the Command register to prevent further execution of the scheduled
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* TDs."
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*/
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if ((pending & EHCI_INT_SYSERROR) != 0)
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{
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sam_syserr_bottomhalf();
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}
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/* Interrupt on Async Advance
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*
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* "System software can force the host controller to issue an interrupt
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* the next time the host controller advances the asynchronous schedule
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* by writing a one to the Interrupt on Async Advance Doorbell bit in
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* the USBCMD register. This status bit indicates the assertion of that
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* interrupt source."
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*/
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if ((pending & EHCI_INT_AAINT) != 0)
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{
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sam_async_advance_bottomhalf();
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}
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/* Re-enable relevant EHCI interrupts. Interrupts should still be enabled
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* at the level of the AIC.
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*/
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sam_putreg(EHCI_HANDLED_INTS, &HCOR->usbintr);
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}
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/*******************************************************************************
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* Name: sam_ehci_tophalf
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*
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* Description:
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* EHCI "Top Half" interrupt handler
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*
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*******************************************************************************/
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static int sam_ehci_tophalf(int irq, FAR void *context)
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{
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uint32_t usbsts;
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uint32_t pending;
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uint32_t regval;
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/* Read Interrupt Status and mask out interrupts that are not enabled. */
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usbsts = sam_getreg(&HCOR->usbsts);
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regval = sam_getreg(&HCOR->usbintr);
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ullvdbg("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
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/* Handle all unmasked interrupt sources */
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pending = usbsts & regval;
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if (pending != 0)
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{
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/* Schedule interrupt handling work for the high priority worker thread
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* so that we are not pressed for time and so that we can interrupt with
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* other USB threads gracefully.
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*
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* The worker should be available now because we implement a handshake
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* by controlling the EHCI interrupts.
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*/
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DEBUGASSERT(work_available(&g_ehci.work));
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DEBUGVERIFY(work_queue(HPWORK, &g_ehci.work, sam_ehci_bottomhalf,
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(FAR void *)pending, 0));
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/* Disable further EHCI interrupts so that we do not overrun the work
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* queue.
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*/
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sam_putreg(0, &HCOR->usbintr);
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/* Clear all pending status bits by writing the value of the pending
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* interrupt bits back to the status register.
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*/
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sam_putreg(usbsts & ECHI_INT_ALLINTS, &HCOR->usbsts);
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}
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return OK;
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}
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@ -1080,8 +1458,8 @@ static int sam_wait(FAR struct usbhost_connection_s *conn,
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* and check again
|
||||
*/
|
||||
|
||||
g_ehci.rhwait = true;
|
||||
sam_takesem(&g_ehci.rhsem);
|
||||
g_ehci.pscwait = true;
|
||||
sam_takesem(&g_ehci.pscsem);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1833,7 +2211,7 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
|
||||
/* Initialize the EHCI state data structure */
|
||||
|
||||
sem_init(&g_ehci.exclsem, 0, 1);
|
||||
sem_init(&g_ehci.rhsem, 0, 0);
|
||||
sem_init(&g_ehci.pscsem, 0, 0);
|
||||
|
||||
/* Initialize EP0 */
|
||||
|
||||
@ -1894,20 +2272,26 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
|
||||
|
||||
/* Interrupt Configuration ***************************************************/
|
||||
|
||||
/* Clear pending interrupts */
|
||||
#warning Missing logic
|
||||
|
||||
/* Enable EHCI interrupts */
|
||||
#warning Missing logic
|
||||
|
||||
/* Attach USB host controller interrupt handler */
|
||||
|
||||
if (irq_attach(SAM_IRQ_UHPHS, sam_ehci_interrupt) != 0)
|
||||
if (irq_attach(SAM_IRQ_UHPHS, sam_ehci_tophalf) != 0)
|
||||
{
|
||||
udbg("ERROR: Failed to attach IRQ\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Clear pending interrupts. Bits in the USBSTS register are cleared by
|
||||
* writing a '1' to the corresponding bit.
|
||||
*/
|
||||
|
||||
sam_putreg(ECHI_INT_ALLINTS, &HCOR->usbsts);
|
||||
|
||||
/* Enable EHCI interrupts. Interrupts are still disabled at the level of
|
||||
* the AIC.
|
||||
*/
|
||||
|
||||
sam_putreg(EHCI_HANDLED_INTS, &HCOR->usbintr);
|
||||
|
||||
/* Drive Vbus +5V (the smoke test). Should be done elsewhere in OTG
|
||||
* mode.
|
||||
*/
|
||||
|
||||
@ -1166,7 +1166,7 @@ Configurations
|
||||
volume when it is removed. But those callbacks are not used in
|
||||
this configuration.
|
||||
|
||||
10) Support the USB full-speed OHCI host driver can be enabled by change
|
||||
10) Support the USB full-speed OHCI host driver can be enabled by changing
|
||||
the NuttX configuration file as follows:
|
||||
|
||||
System Type -> ATSAMA5 Peripheral Support
|
||||
@ -1193,6 +1193,28 @@ Configurations
|
||||
multiple of the 48MHz needed for OHCI. The delay loop calibration
|
||||
values that are used will be off slightly because of this.
|
||||
|
||||
10) Support the USB high-speed EHCI host driver can be enabled by changing
|
||||
the NuttX configuration file as follows:
|
||||
|
||||
System Type -> ATSAMA5 Peripheral Support
|
||||
CONFIG_SAMA5_UHPHS=y : USB Host High Speed
|
||||
|
||||
System Type -> USB High Speed Host driver options
|
||||
CONFIG_SAMA5_EHCI=y : High-speed EHCI support
|
||||
: Defaults for values probably OK
|
||||
Device Drivers
|
||||
CONFIG_USBHOST=y : Enable USB host support
|
||||
|
||||
Device Drivers -> USB Host Driver Support
|
||||
CONFIG_USBHOST_ISOC_DISABLE=y : Isochronous endpoints not used
|
||||
CONFIG_USBHOST_MSC=y : Enable the mass storage class driver
|
||||
|
||||
Library Routines
|
||||
CONFIG_SCHED_WORKQUEUE : Worker thread support is required
|
||||
|
||||
Application Configuration -> NSH Library
|
||||
CONFIG_NSH_ARCHINIT=y : NSH board-initialization
|
||||
|
||||
STATUS:
|
||||
2013-7-19: This configuration (as do the others) run at 396MHz.
|
||||
The SAMA5D3 can run at 536MHz. I still need to figure out the
|
||||
@ -1255,6 +1277,10 @@ Configurations
|
||||
d) OHCI will support 3 downstream points, but I currently have only
|
||||
one enabled.
|
||||
|
||||
2013-8-20: Added description to add EHCI to the configuration. At
|
||||
present, however, EHCI is still a work in progress and not ready for
|
||||
prime time.
|
||||
|
||||
ostest:
|
||||
This configuration directory, performs a simple OS test using
|
||||
examples/ostest.
|
||||
|
||||
@ -282,11 +282,11 @@
|
||||
|
||||
#define EHCI_INT_USBINT (1 << 0) /* Bit 0: USB Interrupt */
|
||||
#define EHCI_INT_USBERRINT (1 << 1) /* Bit 1: USB Error Interrupt */
|
||||
#define EHCI_INT_PCHG (1 << 2) /* Bit 2: Port Change Detect */
|
||||
#define EHCI_INT_PORTSC (1 << 2) /* Bit 2: Port Change Detect */
|
||||
#define EHCI_INT_FLROLL (1 << 3) /* Bit 3: Frame List Rollover */
|
||||
#define EHCI_INT_SYSERROR (1 << 4) /* Bit 4: Host System Error */
|
||||
#define EHCI_INT_AAINT (1 << 5) /* Bit 5: Interrupt on Async Advance */
|
||||
|
||||
#define ECHI_INT_ALLINTS (0x3f) /* Bits 0-5: All interrupts */
|
||||
/* Bits 6-11: Reserved */
|
||||
#define EHCI_USBSTS_HALTED (1 << 12) /* Bit 12: HC Halted */
|
||||
#define EHCI_USBSTS_RECLAM (1 << 13) /* Bit 13: Reclamation */
|
||||
@ -352,6 +352,9 @@
|
||||
#define EHCI_PORTSC_WKOCE (1 << 22) /* Bit 22: Wake on Over-current Enable */
|
||||
/* Bits 23-31: Reserved */
|
||||
|
||||
#define EHCI_PORTSC_ALLINTS (EHCI_PORTSC_CSC | EHCI_PORTSC_PEC | \
|
||||
EHCI_PORTSC_OCC | EHCI_PORTSC_RESUME)
|
||||
|
||||
/* Data Structures **************************************************************************/
|
||||
/* Paragraph 3 */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user