diff --git a/ChangeLog b/ChangeLog
index a0add2bfba..6c42733427 100755
--- a/ChangeLog
+++ b/ChangeLog
@@ -8897,4 +8897,9 @@
* arch/arm/include/efm32, src/efm32, and configs/efm32-gxxx-stk:
The EFM32 Gecko Starter Kit port is now functional. At least
NSH is running over LEUART0 on the board (2014-10-29).
+ * arch/arm/src/sm34/sam_serial.c and Kconfig: Add support for SAM3/4
+ basic TERMIOS and flow control. There are issues with IFLOW control:
+ PDC or DMAC support is required (2014-10-29).
+ * configs/sam4e-ek/src/sam4e-ek.h: Fix an error in a USART1 pin number
+ (2014-10-29).
diff --git a/Documentation/NuttX.html b/Documentation/NuttX.html
index 3ced5565ac..a4f4cd3a8a 100644
--- a/Documentation/NuttX.html
+++ b/Documentation/NuttX.html
@@ -8,7 +8,7 @@
NuttX RTOS
- Last Updated: September 28, 2014
+ Last Updated: October 30, 2014
|
@@ -1262,7 +1262,7 @@
ARM Cortex-A5 (2)
ARM Cortex-A8 (1)
ARM Cortex-M0/M0+ (3)
- ARM Cortex-M3 (27)
+ ARM Cortex-M3 (29)
ARM Cortex-M4 (16)
Atmel AVR
@@ -1391,6 +1391,12 @@
Renesas M16C/26
+ Silicon Laboratories
+
+
STMicroelectronics
+
+
+
+
-
- |
-
Texas Instruments (some formerly Luminary)
- TI TMS320-C5471 (ARM7TDMI)
@@ -2270,6 +2278,93 @@ nsh>
|
|
+
+
|
+
+
+ SiLabs EFM32 Gecko.
+ This is a port for the Silicon Laboraties EFM32 Gecko family.
+ Board support is available for the following:
+
+
+ -
+
+ SiLabs EFM32 Gecko Starter Kit t (EFM32-G8XX-STK).
+ The Gecko Starter Kit features:
+
+
+ - EFM32G890F128 MCU with 128 kB flash and 16 kB RAM
+
- 32.768 kHz crystal (LXFO) and 32 MHz crystal (HXFO)
+
- Advanced Energy Monitoring
+
- Touch slider
+
- 4x40 LCD
+
- 4 User LEDs
+
- 2 pushbutton switches
+
- Reset button and a switch to disconnect the battery.
+
- On-board SEGGER J-Link USB emulator
+
- ARM 20 pin JTAG/SWD standard Debug in/out connector
+
+
+ STATUS.
+ The basic port is verified and available now. This includes
+ on-board LED and button support and a serial console available
+ on LEUART0. A single configuration is available using the
+ NuttShell NSH and the LEUART0 serial console.
+
+
+ Refer to the EFM32 Gecko Starter Kit README.txt file for further information.
+
+
+ -
+
+ Olimex EFM32G880F120-STK.
+ This board features:
+
+
+ - EFM32G880F128 with 128 kB flash and 16 kB RAM
+
- 32.768 kHz crystal (LXFO) and 32 MHz crystal (HXFO)
+
- LCD custom display
+
- DEBUG connector with ARM 2x10 pin layout for programming/debugging with ARM-JTAG-EW
+
- UEXT connector
+
- EXT extension connector
+
- RS232 connector and driver
+
- Four user buttons
+
- Buzzer
+
+
+ STATUS.
+ The board suppport is complete but untested because of tool-related issues. An OpenOCD compatible, SWD debugger would be required to make further progress in testing.
+
+
+ Refer to the Olimex EFM32G880F120-STK README.txt for further information.
+
+
+
+ |
+
+
+
|
+
|
+
+
+
|
+
+
+ SiLabs EFM32 Giant Gecko.
+ This is a port for the Silicon Laboraties EFM32 Giant Gecko family.
+
+
+
+ STATUS.
+ At this time there are no board support packages for the Giant Gecko in the NuttX source tree (there are ports to proprietary Giant Gecko hardware, howevever).
+
+
+ |
+
+
+
|
+
|
+
|
diff --git a/arch/arm/src/sam34/Kconfig b/arch/arm/src/sam34/Kconfig
index fa4b7bd999..464bec6b7c 100644
--- a/arch/arm/src/sam34/Kconfig
+++ b/arch/arm/src/sam34/Kconfig
@@ -583,12 +583,14 @@ config SAM34_UART0
default y
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4CM || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
select ARCH_HAVE_UART0
+ select ARCH_HAVE_SERIAL_TERMIOS
config SAM34_UART1
bool "UART 1"
default n
depends on ARCH_CHIP_SAM4CM || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
select ARCH_HAVE_UART1
+ select ARCH_HAVE_SERIAL_TERMIOS
config SAM34_UDP
bool "USB Device Full Speed (UDP)"
@@ -615,23 +617,27 @@ config SAM34_USART0
bool "USART 0"
default n
select ARCH_HAVE_USART0
+ select ARCH_HAVE_SERIAL_TERMIOS
config SAM34_USART1
bool "USART 1"
default n
select ARCH_HAVE_USART1
+ select ARCH_HAVE_SERIAL_TERMIOS
config SAM34_USART2
bool "USART 2"
default n
- select ARCH_HAVE_USART2
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4CM || ARCH_CHIP_SAM4L
+ select ARCH_HAVE_USART2
+ select ARCH_HAVE_SERIAL_TERMIOS
config SAM34_USART3
bool "USART 3"
default n
- select ARCH_HAVE_USART3
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4CM || ARCH_CHIP_SAM4L
+ select ARCH_HAVE_USART3
+ select ARCH_HAVE_SERIAL_TERMIOS
config SAM34_WDT
bool "Watchdog Timer (WDT)"
diff --git a/arch/arm/src/sam34/sam_serial.c b/arch/arm/src/sam34/sam_serial.c
index 6aec44070a..b558ae7f94 100644
--- a/arch/arm/src/sam34/sam_serial.c
+++ b/arch/arm/src/sam34/sam_serial.c
@@ -48,6 +48,10 @@
#include
#include
+#ifdef CONFIG_SERIAL_TERMIOS
+# include
+#endif
+
#include
#include
#include
@@ -71,7 +75,7 @@
#endif
/****************************************************************************
- * Definitions
+ * Pre-processor Definitions
****************************************************************************/
/* Some sanity checks *******************************************************/
@@ -106,6 +110,17 @@
# define HAVE_USART
#endif
+/* Hardware flow control requires using the PDC or DMAC channel for reception */
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+# warning PDC or DMAC support is required for RTS hardware flow control
+# undef CONFIG_SERIAL_IFLOWCONTROL
+# undef CONFIG_USART0_IFLOWCONTROL
+# undef CONFIG_USART1_IFLOWCONTROL
+# undef CONFIG_USART2_IFLOWCONTROL
+# undef CONFIG_USART3_IFLOWCONTROL
+#endif
+
/* Is there a serial console? It could be on UART0-1 or USART0-3 */
#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART0)
@@ -339,13 +354,16 @@
struct up_dev_s
{
- uint32_t usartbase; /* Base address of USART registers */
- uint32_t baud; /* Configured baud */
- uint32_t sr; /* Saved status bits */
- uint8_t irq; /* IRQ associated with this USART */
- uint8_t parity; /* 0=none, 1=odd, 2=even */
- uint8_t bits; /* Number of bits (7 or 8) */
- bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
+ const uint32_t usartbase; /* Base address of USART registers */
+ uint32_t baud; /* Configured baud */
+ uint32_t sr; /* Saved status bits */
+ uint8_t irq; /* IRQ associated with this USART */
+ uint8_t parity; /* 0=none, 1=odd, 2=even */
+ uint8_t bits; /* Number of bits (5-9) */
+ bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
+#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
+ bool flowc; /* input flow control (RTS) enabled */
+#endif
};
/****************************************************************************
@@ -487,6 +505,9 @@ static struct up_dev_s g_usart0priv =
.parity = CONFIG_USART0_PARITY,
.bits = CONFIG_USART0_BITS,
.stopbits2 = CONFIG_USART0_2STOP,
+#if defined(CONFIG_USART0_OFLOWCONTROL) || defined(CONFIG_USART0_IFLOWCONTROL)
+ .flowc = true,
+#endif
};
static uart_dev_t g_usart0port =
@@ -517,6 +538,9 @@ static struct up_dev_s g_usart1priv =
.parity = CONFIG_USART1_PARITY,
.bits = CONFIG_USART1_BITS,
.stopbits2 = CONFIG_USART1_2STOP,
+#if defined(CONFIG_USART1_OFLOWCONTROL) || defined(CONFIG_USART1_IFLOWCONTROL)
+ .flowc = true,
+#endif
};
static uart_dev_t g_usart1port =
@@ -547,6 +571,9 @@ static struct up_dev_s g_usart2priv =
.parity = CONFIG_USART2_PARITY,
.bits = CONFIG_USART2_BITS,
.stopbits2 = CONFIG_USART2_2STOP,
+#if defined(CONFIG_USART2_OFLOWCONTROL) || defined(CONFIG_USART2_IFLOWCONTROL)
+ .flowc = true,
+#endif
};
static uart_dev_t g_usart2port =
@@ -577,6 +604,9 @@ static struct up_dev_s g_usart3priv =
.parity = CONFIG_USART3_PARITY,
.bits = CONFIG_USART3_BITS,
.stopbits2 = CONFIG_USART3_2STOP,
+#if defined(CONFIG_USART3_OFLOWCONTROL) || defined(CONFIG_USART3_IFLOWCONTROL)
+ .flowc = true,
+#endif
};
static uart_dev_t g_usart3port =
@@ -680,7 +710,28 @@ static int up_setup(struct uart_dev_s *dev)
* as the timing source
*/
- regval = (UART_MR_MODE_NORMAL | SAM_MR_USCLKS);
+#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
+ /* "Setting the USART to operate with hardware handshaking is performed by
+ * writing the USART_MODE field in the Mode Register (US_MR) to the value
+ * 0x2. ... Using this mode requires using the PDC or DMAC channel for
+ * reception. The transmitter can handle hardware handshaking in any case."
+ */
+
+ if (priv->flowc)
+ {
+ /* Enable hardware flow control and MCK as the timing source */
+
+ regval = (UART_MR_MODE_HWHS | SAM_MR_USCLKS);
+ }
+ else
+#endif
+ {
+ /* Set up the mode register. Start with normal UART mode and the MCK
+ * as the timing source
+ */
+
+ regval = (UART_MR_MODE_NORMAL | SAM_MR_USCLKS);
+ }
/* OR in settings for the selected number of bits */
@@ -760,6 +811,7 @@ static int up_setup(struct uart_dev_s *dev)
up_serialout(priv, SAM_UART_CR_OFFSET, (UART_CR_RXEN|UART_CR_TXEN));
#endif
+
return OK;
}
@@ -959,7 +1011,7 @@ static int up_interrupt(int irq, void *context)
static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
{
-#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
+#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT)
struct inode *inode = filep->f_inode;
struct uart_dev_s *dev = inode->i_private;
#endif
@@ -983,6 +1035,160 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
break;
#endif
+#ifdef CONFIG_SERIAL_TERMIOS
+ case TCGETS:
+ {
+ struct termios *termiosp = (struct termios*)arg;
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+
+ if (!termiosp)
+ {
+ ret = -EINVAL;
+ break;
+ }
+
+ /* Return baud */
+
+ cfsetispeed(termiosp, priv->baud);
+
+ /* Return parity */
+
+ termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) |
+ ((priv->parity == 1) ? PARODD : 0);
+
+ /* Return stop bits */
+
+ termiosp->c_cflag |= (priv->stopbits2) ? CSTOPB : 0;
+
+ /* Return flow control */
+
+#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
+ termiosp->c_cflag |= (priv->flowc) ? (CCTS_OFLOW | CRTS_IFLOW): 0;
+#endif
+ /* Return number of bits */
+
+ switch (priv->bits)
+ {
+ case 5:
+ termiosp->c_cflag |= CS5;
+ break;
+
+ case 6:
+ termiosp->c_cflag |= CS6;
+ break;
+
+ case 7:
+ termiosp->c_cflag |= CS7;
+ break;
+
+ default:
+ case 8:
+ termiosp->c_cflag |= CS8;
+ break;
+
+ case 9:
+ termiosp->c_cflag |= CS8 /* CS9 */;
+ break;
+ }
+ }
+ break;
+
+ case TCSETS:
+ {
+ struct termios *termiosp = (struct termios*)arg;
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ uint32_t baud;
+ uint8_t parity;
+ uint8_t nbits;
+ bool stop2;
+#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
+ bool flowc;
+#endif
+
+ if (!termiosp)
+ {
+ ret = -EINVAL;
+ break;
+ }
+
+ /* Decode baud. */
+
+ ret = OK;
+ baud = cfgetispeed(termiosp);
+
+ /* Decode number of bits */
+
+ switch (priv->bits)
+ {
+ case CS5:
+ nbits = 5;
+ break;
+
+ case CS6:
+ nbits = 6;
+ break;
+
+ case CS7:
+ nbits = 7;
+ break;
+
+ case CS8:
+ nbits = 8;
+ break;
+#if 0
+ case CS9:
+ nbits = 9;
+ break;
+#endif
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ /* Decode parity */
+
+ if (termiosp->c_cflag & PARENB)
+ {
+ parity = (termiosp->c_cflag & PARODD) ? 1 : 2;
+ }
+ else
+ {
+ parity = 0;
+ }
+
+ /* Decode stop bits */
+
+ stop2 = (termiosp->c_cflag & CSTOPB) != 0;
+
+ /* Decode flow control */
+
+#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
+ flowc = (termiosp->c_cflag & (CCTS_OFLOW | CRTS_IFLOW)) != 0;
+#endif
+ /* Verify that all settings are valid before committing */
+
+ if (ret == OK)
+ {
+ /* Commit */
+
+ priv->baud = baud;
+ priv->parity = parity;
+ priv->bits = nbits;
+ priv->stopbits2 = stop2;
+#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
+ priv->flowc = flowc;
+#endif
+
+ /* effect the changes immediately - note that we do not
+ * implement TCSADRAIN / TCSAFLUSH
+ */
+
+ up_setup(dev);
+ }
+ }
+ break;
+#endif /* CONFIG_SERIAL_TERMIOS */
+
default:
ret = -ENOTTY;
break;
diff --git a/configs/efm32-g8xx-stk/README.txt b/configs/efm32-g8xx-stk/README.txt
index 0f6f3cab55..ade1f7c6e9 100644
--- a/configs/efm32-g8xx-stk/README.txt
+++ b/configs/efm32-g8xx-stk/README.txt
@@ -28,14 +28,33 @@ CONTENTS
STATUS
======
- 2014-10-28. Testing is still in progress. At this point all basic boot
- operations are successful: The LEDs work and the application tasks appear
- to be successfully started. LED2 is on and LED0 is glowing (meaning that
- interrupts are being processed). However, I get no output on PE0. Data
- appears to be sent (at least by efm32_lowputc()). However, no signal
- activity is present on PE0.
+ 2014-10-28. At this point all basic boot operations are successful: The
+ LEDs work and the application tasks appear to be successfully started.
+ LED2 is on and LED0 is glowing (meaning that interrupts are being
+ processed). However, I get no output on PE0. Data appears to be sent
+ (at least by efm32_lowputc()). However, no signal activity is present
+ on PE0.
- I am, of course, thinking that this is a pin configuration issue.
+ 2014-10-29: The NuttX is running on the EFM32 Gecko Starter Kit. There
+ are not many peripherals to test in that configuration, but the NuttShell
+ (NSH) is working over LEUART0 at 2400 baud (certainly that could go up
+ to 4800. The documentation says that 9600 is also possible on the
+ LEUART, but I am not sure how).
+
+ I originally planned to use UART0 at 115200 baud, but I never could get
+ any output from the board. I reviewd my pin configuration and clocking
+ carefully and the USART seems to think it is working correctly. So I
+ am thinking that there is some board issue that prohibits that option
+ (probably because UART0 is used with the board controller???). Pins
+ are not available for other U[S]ARTs on the board.
+
+ 2014-10-29: Calibrated the delays loops.
+
+ 2014-10-29: The start-up time is long -- about a second. I have traced
+ this to the default delay in bringing up the LFCLK in efm32_clockconfig.
+ The default, reset setting of the LFXOTIMEOUT field of the CMU_CTRL
+ register is 3 which corresponds to a delay of 32768 cycles, or a full
+ second. I have not experimented to see if this delay can be reduced.
LEDs
====
diff --git a/configs/efm32-g8xx-stk/nsh/defconfig b/configs/efm32-g8xx-stk/nsh/defconfig
index a1433dc710..afcc123422 100644
--- a/configs/efm32-g8xx-stk/nsh/defconfig
+++ b/configs/efm32-g8xx-stk/nsh/defconfig
@@ -192,7 +192,7 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y
#
# Board Settings
#
-CONFIG_BOARD_LOOPSPERMSEC=4531
+CONFIG_BOARD_LOOPSPERMSEC=2662
# CONFIG_ARCH_CALIBRATION is not set
#
diff --git a/configs/olimex-efm32g880f128-stk/nsh/defconfig b/configs/olimex-efm32g880f128-stk/nsh/defconfig
index 065e7ffabc..b7a8dd3109 100644
--- a/configs/olimex-efm32g880f128-stk/nsh/defconfig
+++ b/configs/olimex-efm32g880f128-stk/nsh/defconfig
@@ -189,7 +189,7 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y
#
# Board Settings
#
-CONFIG_BOARD_LOOPSPERMSEC=4531
+CONFIG_BOARD_LOOPSPERMSEC=2662
# CONFIG_ARCH_CALIBRATION is not set
#
diff --git a/configs/sam4e-ek/src/sam4e-ek.h b/configs/sam4e-ek/src/sam4e-ek.h
index 25184e5892..ff642b9fc2 100644
--- a/configs/sam4e-ek/src/sam4e-ek.h
+++ b/configs/sam4e-ek/src/sam4e-ek.h
@@ -304,9 +304,9 @@
*/
#define GPIO_RS232_ENABLE (GPIO_OUTPUT | GPIO_CFG_DEFAULT | \
- GPIO_OUTPUT_CLEAR | GPIO_PORT_PIOA | GPIO_PIN21)
+ GPIO_OUTPUT_CLEAR | GPIO_PORT_PIOA | GPIO_PIN23)
#define GPIO_RS485_ENABLE (GPIO_OUTPUT | GPIO_CFG_DEFAULT | \
- GPIO_OUTPUT_SET | GPIO_PORT_PIOA | GPIO_PIN21)
+ GPIO_OUTPUT_SET | GPIO_PORT_PIOA | GPIO_PIN23)
/* HSMCI SD Card Detect
*
| |