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/arch/arm/src/tiva/hardware: Add CC13x0 and CC13x2 UART header files.

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This commit is contained in:
Gregory Nutt 2018-12-04 08:40:29 -06:00
parent c9ca9ced72
commit b2013df856
8 changed files with 556 additions and 205 deletions
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262
arch/arm/src/tiva/hardware/cc13x0/cc13x0_uart.h Normal file
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@ -0,0 +1,262 @@
/************************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_uart.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_UART_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_UART_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <arch/chip/chip.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* UART register offsets ************************************************************/
#define TIVA_UART_DR_OFFSET 0x0000 /* UART Data */
#define TIVA_UART_RSR_OFFSET 0x0004 /* UART Receive Status */
#define TIVA_UART_ECR_OFFSET 0x0004 /* UART Error Clear */
#define TIVA_UART_FR_OFFSET 0x0018 /* UART Flag */
#define TIVA_UART_IBRD_OFFSET 0x0024 /* UART Integer Baud-Rate Divisor*/
#define TIVA_UART_FBRD_OFFSET 0x0028 /* UART Fractional Baud-Rate Divisor */
#define TIVA_UART_LCRH_OFFSET 0x002c /* UART Line Control */
#define TIVA_UART_CTL_OFFSET 0x0030 /* UART Control */
#define TIVA_UART_IFLS_OFFSET 0x0034 /* UART Interrupt FIFO Level Select */
#define TIVA_UART_IM_OFFSET 0x0038 /* UART Interrupt Mask */
#define TIVA_UART_RIS_OFFSET 0x003c /* UART Raw Interrupt Status */
#define TIVA_UART_MIS_OFFSET 0x0040 /* UART Masked Interrupt Status */
#define TIVA_UART_ICR_OFFSET 0x0044 /* UART Interrupt Clear */
#define TIVA_UART_DMACTL_OFFSET 0x0048 /* UART DMA Control */
#define TIVA_UART_PERIPHID4_OFFSET 0x0fd0 /* UART Peripheral Identification 4 */
#define TIVA_UART_PERIPHID5_OFFSET 0x0fd4 /* UART Peripheral Identification 5 */
#define TIVA_UART_PERIPHID6_OFFSET 0x0fd8 /* UART Peripheral Identification 6 */
#define TIVA_UART_PERIPHID7_OFFSET 0x0fdc /* UART Peripheral Identification 7 */
#define TIVA_UART_PERIPHID0_OFFSET 0x0fe0 /* UART Peripheral Identification 0 */
#define TIVA_UART_PERIPHID1_OFFSET 0x0fe4 /* UART Peripheral Identification 1 */
#define TIVA_UART_PERIPHID2_OFFSET 0x0fe8 /* UART Peripheral Identification 2 */
#define TIVA_UART_PERIPHID3_OFFSET 0x0fec /* UART Peripheral Identification 3 */
#define TIVA_UART_PCELLID0_OFFSET 0x0ff0 /* UART PrimeCell Identification 0 */
#define TIVA_UART_PCELLID1_OFFSET 0x0ff4 /* UART PrimeCell Identification 1 */
#define TIVA_UART_PCELLID2_OFFSET 0x0ff8 /* UART PrimeCell Identification 2 */
#define TIVA_UART_PCELLID3_OFFSET 0x0ffc /* UART PrimeCell Identification 3 */
/* UART register addresses **********************************************************/
#define TIVA_UART_BASE(n) (TIVA_UART0_BASE + (n)*0x01000)
#define TIVA_UART_DR(n) (TIVA_UART_BASE(n) + TIVA_UART_DR_OFFSET)
#define TIVA_UART_RSR(n) (TIVA_UART_BASE(n) + TIVA_UART_RSR_OFFSET)
#define TIVA_UART_ECR(n) (TIVA_UART_BASE(n) + TIVA_UART_ECR_OFFSET)
#define TIVA_UART_FR(n) (TIVA_UART_BASE(n) + TIVA_UART_FR_OFFSET)
#define TIVA_UART_IBRD(n) (TIVA_UART_BASE(n) + TIVA_UART_IBRD_OFFSET)
#define TIVA_UART_FBRD(n) (TIVA_UART_BASE(n) + TIVA_UART_FBRD_OFFSET)
#define TIVA_UART_LCRH(n) (TIVA_UART_BASE(n) + TIVA_UART_LCRH_OFFSET)
#define TIVA_UART_CTL(n) (TIVA_UART_BASE(n) + TIVA_UART_CTL_OFFSET)
#define TIVA_UART_IFLS(n) (TIVA_UART_BASE(n) + TIVA_UART_IFLS_OFFSET)
#define TIVA_UART_IM(n) (TIVA_UART_BASE(n) + TIVA_UART_IM_OFFSET)
#define TIVA_UART_RIS(n) (TIVA_UART_BASE(n) + TIVA_UART_RIS_OFFSET)
#define TIVA_UART_MIS(n) (TIVA_UART_BASE(n) + TIVA_UART_MIS_OFFSET)
#define TIVA_UART_ICR(n) (TIVA_UART_BASE(n) + TIVA_UART_ICR_OFFSET)
#define TIVA_UART_DMACTL(n) (TIVA_UART_BASE(n) + TIVA_UART_DMACTL_OFFSET)
#if TIVA_NUARTS > 0
# define TIVA_UART0_DR (TIVA_UART0_BASE + TIVA_UART_DR_OFFSET)
# define TIVA_UART0_RSR (TIVA_UART0_BASE + TIVA_UART_RSR_OFFSET)
# define TIVA_UART0_ECR (TIVA_UART0_BASE + TIVA_UART_ECR_OFFSET)
# define TIVA_UART0_FR (TIVA_UART0_BASE + TIVA_UART_FR_OFFSET)
# define TIVA_UART0_IBRD (TIVA_UART0_BASE + TIVA_UART_IBRD_OFFSET)
# define TIVA_UART0_FBRD (TIVA_UART0_BASE + TIVA_UART_FBRD_OFFSET)
# define TIVA_UART0_LCRH (TIVA_UART0_BASE + TIVA_UART_LCRH_OFFSET)
# define TIVA_UART0_CTL (TIVA_UART0_BASE + TIVA_UART_CTL_OFFSET)
# define TIVA_UART0_IFLS (TIVA_UART0_BASE + TIVA_UART_IFLS_OFFSET)
# define TIVA_UART0_IM (TIVA_UART0_BASE + TIVA_UART_IM_OFFSET)
# define TIVA_UART0_RIS (TIVA_UART0_BASE + TIVA_UART_RIS_OFFSET)
# define TIVA_UART0_MIS (TIVA_UART0_BASE + TIVA_UART_MIS_OFFSET)
# define TIVA_UART0_ICR (TIVA_UART0_BASE + TIVA_UART_ICR_OFFSET)
# define TIVA_UART0_DMACTL (TIVA_UART0_BASE + TIVA_UART_DMACTL_OFFSET)
#endif
/* UART register bit settings *******************************************************/
/* UART Data (DR) */
#define UART_DR_DATA_SHIFT 0 /* Bits 7-0: Data Transmitted or Received */
#define UART_DR_DATA_MASK (0xff << UART_DR_DATA_SHIFT)
#define UART_DR_FE (1 << 8) /* Bit 8: UART Framing Error */
#define UART_DR_PE (1 << 9) /* Bit 9: UART Parity Error */
#define UART_DR_BE (1 << 10) /* Bit 10: UART Break Error */
#define UART_DR_OE (1 << 11) /* Bit 11: UART Overrun Error */
/* UART Receive Status (RSR) */
#define UART_RSR_FE (1 << 0) /* Bit 0: UART Framing Error */
#define UART_RSR_PE (1 << 1) /* Bit 1: UART Parity Error */
#define UART_RSR_BE (1 << 2) /* Bit 2: UART Break Error */
#define UART_RSR_OE (1 << 3) /* Bit 3: UART Overrun Error */
/* UART Error Clear (ECR) */
#define UART_ECR_FE (1 << 0) /* Bit 0: UART Clear Framing Error */
#define UART_ECR_PE (1 << 1) /* Bit 1: UART Clear Parity Error */
#define UART_ECR_BE (1 << 2) /* Bit 2: UART Clear Break Error */
#define UART_ECR_OE (1 << 3) /* Bit 3: UART Clear Overrun Error */
/* UART Flag (FR) */
#define UART_FR_CTS (1 << 0) /* Bit 0: Clear to Send */
#define UART_FR_BUSY (1 << 3) /* Bit 3: UART Busy */
#define UART_FR_RXFE (1 << 4) /* Bit 4: UART Receive FIFO Empty */
#define UART_FR_TXFF (1 << 5) /* Bit 5: UART Transmit FIFO Full */
#define UART_FR_RXFF (1 << 6) /* Bit 6: UART Receive FIFO Full */
#define UART_FR_TXFE (1 << 7) /* Bit 7: UART Transmit FIFO Empty */
/* UART Integer Baud-Rate Divisor (IBRD) */
#define UART_IBRD_DIVINT_MASK (0xffff) /* Bits 15-0: Integer Baud-Rate Divisor */
/* UART Fractional Baud-Rate Divisor (UARTFBRD) */
#define UART_FBRD_DIVFRAC_MASK (0x3f) /* Bits 5-0: Fractional Baud-Rate Divisor */
/* Register 7: UART Line Control (LCRH) */
#define UART_LCRH_BRK (1 << 0) /* Bit 0: UART Send Break */
#define UART_LCRH_PEN (1 << 1) /* Bit 1: UART Parity Enable */
#define UART_LCRH_EPS (1 << 2) /* Bit 2: UART Even Parity Select */
#define UART_LCRH_STP2 (1 << 3) /* Bit 3: UART Two Stop Bits Select */
#define UART_LCRH_FEN (1 << 4) /* Bit 4: UART Enable FIFOs */
#define UART_LCRH_WLEN_SHIFT 5 /* Bits 6-5: UART Word Length */
#define UART_LCRH_WLEN_MASK (3 << UART_LCRH_WLEN_SHIFT)
# define UART_LCRH_WLEN_5BITS (0 << UART_LCRH_WLEN_SHIFT) /* 5-bits (reset) */
# define UART_LCRH_WLEN_6BITS (1 << UART_LCRH_WLEN_SHIFT) /* 6-bits */
# define UART_LCRH_WLEN_7BITS (2 << UART_LCRH_WLEN_SHIFT) /* 7-bits */
# define UART_LCRH_WLEN_8BITS (3 << UART_LCRH_WLEN_SHIFT) /* 8-bits */
#define UART_LCRH_SPS (1 << 7) /* Bit 7: UART Stick Parity Select */
/* UART Control (CTL) */
#define UART_CTL_UARTEN (1 << 0) /* Bit 0: UART Enable */
#define UART_CTL_LBE (1 << 7) /* Bit 7: UART Loop Back Enable */
#define UART_CTL_TXE (1 << 8) /* Bit 8: UART Transmit Enable */
#define UART_CTL_RXE (1 << 9) /* Bit 9: UART Receive Enable */
#define UART_CTL_RTS (1 << 11) /* Bit 11: Request to Send */
#define UART_CTL_RTSEN (1 << 14) /* Bit 14: Enable Request to Send */
#define UART_CTL_CTSEN (1 << 15) /* Bit 15: Enable Clear To Send */
/* UART Interrupt FIFO Level Select (IFLS) */
#define UART_IFLS_TXIFLSEL_SHIFT 0 /* Bits 0-2: UART Transmit Interrupt FIFO Level Select */
#define UART_IFLS_TXIFLSEL_MASK (7 << UART_IFLS_TXIFLSEL_SHIFT)
# define UART_IFLS_TXIFLSEL_18th (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */
# define UART_IFLS_TXIFLSEL_14th (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */
# define UART_IFLS_TXIFLSEL_half (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */
# define UART_IFLS_TXIFLSEL_34th (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */
# define UART_IFLS_TXIFLSEL_78th (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */
#define UART_IFLS_RXIFLSEL_SHIFT 3 /* Bits 3-5: UART Receive Interrupt FIFO Level Select */
#define UART_IFLS_RXIFLSEL_MASK (7 << UART_IFLS_RXIFLSEL_SHIFT)
# define UART_IFLS_RXIFLSEL_18th (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */
# define UART_IFLS_RXIFLSEL_14th (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */
# define UART_IFLS_RXIFLSEL_half (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */
# define UART_IFLS_RXIFLSEL_34th (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */
# define UART_IFLS_RXIFLSEL_78th (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */
/* UART Interrupt Mask (IM) */
#define UART_IM_CTSIM (1 << 1) /* Bit 1: UART Clear to Send Modem Interrupt Mask */
#define UART_IM_RXIM (1 << 4) /* Bit 4: UART Receive Interrupt Mask */
#define UART_IM_TXIM (1 << 5) /* Bit 5: UART Transmit Interrupt Mask */
#define UART_IM_RTIM (1 << 6) /* Bit 6: UART Receive Time-Out Interrupt Mask */
#define UART_IM_FEIM (1 << 7) /* Bit 7: UART Framing Error Interrupt Mask */
#define UART_IM_PEIM (1 << 8) /* Bit 8: UART Parity Error Interrupt Mask */
#define UART_IM_BEIM (1 << 9) /* Bit 9: UART Break Error Interrupt Mask */
#define UART_IM_OEIM (1 << 10) /* Bit 10: UART Overrun Error Interrupt Mask */
/* UART Raw Interrupt Status (RIS) */
#define UART_RIS_CTSIS (1 << 1) /* Bit 1: UART Clear to Send Modem Raw Interrupt Status */
#define UART_RIS_RXRIS (1 << 4) /* Bit 4: UART Receive Raw Interrupt Status */
#define UART_RIS_TXRIS (1 << 5) /* Bit 5: UART Transmit Raw Interrupt Status */
#define UART_RIS_RTRIS (1 << 6) /* Bit 6: UART Receive Time-Out Raw Interrupt Status */
#define UART_RIS_FERIS (1 << 7) /* Bit 7: UART Framing Error Raw Interrupt Status */
#define UART_RIS_PERIS (1 << 8) /* Bit 8: UART Parity Error Raw Interrupt Status */
#define UART_RIS_BERIS (1 << 9) /* Bit 9: UART Break Error Raw Interrupt Status */
#define UART_RIS_OERIS (1 << 10) /* Bit 10: UART Overrun Error Raw Interrupt Status */
/* UART Masked Interrupt Status (MIS) */
#define UART_MIS_CTSIS (1 << 1) /* Bit 1: UART Clear to Send Modem Masked Interrupt Status */
#define UART_MIS_RXMIS (1 << 4) /* Bit 4: UART Receive Masked Interrupt Status */
#define UART_MIS_TXMIS (1 << 5) /* Bit 5: UART Transmit Masked Interrupt Status */
#define UART_MIS_RTMIS (1 << 6) /* Bit 6: UART Receive Time-Out Masked Interrupt Status */
#define UART_MIS_FEMIS (1 << 7) /* Bit 7: UART Framing Error Masked Interrupt Status */
#define UART_MIS_PEMIS (1 << 8) /* Bit 8: UART Parity Error Masked Interrupt Status */
#define UART_MIS_BEMIS (1 << 9) /* Bit 9: UART Break Error Masked Interrupt Status */
#define UART_MIS_OEMIS (1 << 10) /* Bit 10: UART Overrun Error Masked Interrupt Status */
/* UART Interrupt Clear (ICR) */
#define UART_ICR_CTSIC (1 << 1) /* Bit 1: UART Clear to Send Modem Interrupt Clear */
#define UART_ICR_RXIC (1 << 4) /* Bit 4: Receive Interrupt Clear */
#define UART_ICR_TXIC (1 << 5) /* Bit 5: Transmit Interrupt Clear */
#define UART_ICR_RTIC (1 << 6) /* Bit 6: Receive Time-Out Interrupt Clear */
#define UART_ICR_FEIC (1 << 7) /* Bit 7: Framing Error Interrupt Clear */
#define UART_ICR_PEIC (1 << 8) /* Bit 8: Parity Error Interrupt Clear */
#define UART_ICR_BEIC (1 << 9) /* Bit 9: Break Error Interrupt Clear */
#define UART_ICR_OEIC (1 << 10) /* Bit 10: Overrun Error Interrupt Clear */
/* UART DMA Control (DMACTL) */
#define UART_DMACTL_RXDMAE (1 << 0) /* Bit 0: Receive DMA Enable */
#define UART_DMACTL_TXDMAE (1 << 1) /* Bit 1: Transmit DMA Enable */
#define UART_DMACTL_DMAERR (1 << 2) /* Bit 2: DMA on Error */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_UART_H */

8
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_v1_memorymap.h → arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_memorymap.h
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@ -1,5 +1,5 @@
/******************************************************************************
* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_v1_memorymap.h
* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_memorymap.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -41,8 +41,8 @@
*
******************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_V1_MEMORYMAP_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_V1_MEMORYMAP_H
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_MEMORYMAP_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_MEMORYMAP_H
/******************************************************************************
* Pre-processor Definitions
@ -183,4 +183,4 @@
#define CPU_TIPROP_BASE 0xe00fe000 /* CPU_TIPROP */
#define CPU_ROM_TABLE_BASE 0xe00ff000 /* CPU_ROM_TABLE */
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_V1_MEMORYMAP_H */
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_MEMORYMAP_H */

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arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_uart.h Normal file
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@ -0,0 +1,271 @@
/************************************************************************************
* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_uart.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2CC13X20_CC26X2UART_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2CC13X20_CC26X2UART_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <arch/chip/chip.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* UART register offsets ************************************************************/
#define TIVA_UART_DR_OFFSET 0x0000 /* UART Data */
#define TIVA_UART_RSR_OFFSET 0x0004 /* UART Receive Status */
#define TIVA_UART_ECR_OFFSET 0x0004 /* UART Error Clear */
#define TIVA_UART_FR_OFFSET 0x0018 /* UART Flag */
#define TIVA_UART_IBRD_OFFSET 0x0024 /* UART Integer Baud-Rate Divisor*/
#define TIVA_UART_FBRD_OFFSET 0x0028 /* UART Fractional Baud-Rate Divisor */
#define TIVA_UART_LCRH_OFFSET 0x002c /* UART Line Control */
#define TIVA_UART_CTL_OFFSET 0x0030 /* UART Control */
#define TIVA_UART_IFLS_OFFSET 0x0034 /* UART Interrupt FIFO Level Select */
#define TIVA_UART_IM_OFFSET 0x0038 /* UART Interrupt Mask */
#define TIVA_UART_RIS_OFFSET 0x003c /* UART Raw Interrupt Status */
#define TIVA_UART_MIS_OFFSET 0x0040 /* UART Masked Interrupt Status */
#define TIVA_UART_ICR_OFFSET 0x0044 /* UART Interrupt Clear */
#define TIVA_UART_DMACTL_OFFSET 0x0048 /* UART DMA Control */
/* UART register addresses **********************************************************/
#define TIVA_UART_BASE(n) (TIVA_UART0_BASE + (n)*0x01000)
#define TIVA_UART_DR(n) (TIVA_UART_BASE(n) + TIVA_UART_DR_OFFSET)
#define TIVA_UART_RSR(n) (TIVA_UART_BASE(n) + TIVA_UART_RSR_OFFSET)
#define TIVA_UART_ECR(n) (TIVA_UART_BASE(n) + TIVA_UART_ECR_OFFSET)
#define TIVA_UART_FR(n) (TIVA_UART_BASE(n) + TIVA_UART_FR_OFFSET)
#define TIVA_UART_IBRD(n) (TIVA_UART_BASE(n) + TIVA_UART_IBRD_OFFSET)
#define TIVA_UART_FBRD(n) (TIVA_UART_BASE(n) + TIVA_UART_FBRD_OFFSET)
#define TIVA_UART_LCRH(n) (TIVA_UART_BASE(n) + TIVA_UART_LCRH_OFFSET)
#define TIVA_UART_CTL(n) (TIVA_UART_BASE(n) + TIVA_UART_CTL_OFFSET)
#define TIVA_UART_IFLS(n) (TIVA_UART_BASE(n) + TIVA_UART_IFLS_OFFSET)
#define TIVA_UART_IM(n) (TIVA_UART_BASE(n) + TIVA_UART_IM_OFFSET)
#define TIVA_UART_RIS(n) (TIVA_UART_BASE(n) + TIVA_UART_RIS_OFFSET)
#define TIVA_UART_MIS(n) (TIVA_UART_BASE(n) + TIVA_UART_MIS_OFFSET)
#define TIVA_UART_ICR(n) (TIVA_UART_BASE(n) + TIVA_UART_ICR_OFFSET)
#define TIVA_UART_DMACTL(n) (TIVA_UART_BASE(n) + TIVA_UART_DMACTL_OFFSET)
#if TIVA_NUARTS > 0
# define TIVA_UART0_DR (TIVA_UART0_BASE + TIVA_UART_DR_OFFSET)
# define TIVA_UART0_RSR (TIVA_UART0_BASE + TIVA_UART_RSR_OFFSET)
# define TIVA_UART0_ECR (TIVA_UART0_BASE + TIVA_UART_ECR_OFFSET)
# define TIVA_UART0_FR (TIVA_UART0_BASE + TIVA_UART_FR_OFFSET)
# define TIVA_UART0_IBRD (TIVA_UART0_BASE + TIVA_UART_IBRD_OFFSET)
# define TIVA_UART0_FBRD (TIVA_UART0_BASE + TIVA_UART_FBRD_OFFSET)
# define TIVA_UART0_LCRH (TIVA_UART0_BASE + TIVA_UART_LCRH_OFFSET)
# define TIVA_UART0_CTL (TIVA_UART0_BASE + TIVA_UART_CTL_OFFSET)
# define TIVA_UART0_IFLS (TIVA_UART0_BASE + TIVA_UART_IFLS_OFFSET)
# define TIVA_UART0_IM (TIVA_UART0_BASE + TIVA_UART_IM_OFFSET)
# define TIVA_UART0_RIS (TIVA_UART0_BASE + TIVA_UART_RIS_OFFSET)
# define TIVA_UART0_MIS (TIVA_UART0_BASE + TIVA_UART_MIS_OFFSET)
# define TIVA_UART0_ICR (TIVA_UART0_BASE + TIVA_UART_ICR_OFFSET)
# define TIVA_UART0_DMACTL (TIVA_UART0_BASE + TIVA_UART_DMACTL_OFFSET)
#endif
#if TIVA_NUARTS > 1
# define TIVA_UART1_DR (TIVA_UART1_BASE + TIVA_UART_DR_OFFSET)
# define TIVA_UART1_RSR (TIVA_UART1_BASE + TIVA_UART_RSR_OFFSET)
# define TIVA_UART1_ECR (TIVA_UART1_BASE + TIVA_UART_ECR_OFFSET)
# define TIVA_UART1_FR (TIVA_UART1_BASE + TIVA_UART_FR_OFFSET)
# define TIVA_UART1_IBRD (TIVA_UART1_BASE + TIVA_UART_IBRD_OFFSET)
# define TIVA_UART1_FBRD (TIVA_UART1_BASE + TIVA_UART_FBRD_OFFSET)
# define TIVA_UART1_LCRH (TIVA_UART1_BASE + TIVA_UART_LCRH_OFFSET)
# define TIVA_UART1_CTL (TIVA_UART1_BASE + TIVA_UART_CTL_OFFSET)
# define TIVA_UART1_IFLS (TIVA_UART1_BASE + TIVA_UART_IFLS_OFFSET)
# define TIVA_UART1_IM (TIVA_UART1_BASE + TIVA_UART_IM_OFFSET)
# define TIVA_UART1_RIS (TIVA_UART1_BASE + TIVA_UART_RIS_OFFSET)
# define TIVA_UART1_MIS (TIVA_UART1_BASE + TIVA_UART_MIS_OFFSET)
# define TIVA_UART1_ICR (TIVA_UART1_BASE + TIVA_UART_ICR_OFFSET)
# define TIVA_UART1_DMACTL (TIVA_UART1_BASE + TIVA_UART_DMACTL_OFFSET)
#endif
/* UART register bit settings *******************************************************/
/* UART Data (DR) */
#define UART_DR_DATA_SHIFT 0 /* Bits 7-0: Data Transmitted or Received */
#define UART_DR_DATA_MASK (0xff << UART_DR_DATA_SHIFT)
#define UART_DR_FE (1 << 8) /* Bit 8: UART Framing Error */
#define UART_DR_PE (1 << 9) /* Bit 9: UART Parity Error */
#define UART_DR_BE (1 << 10) /* Bit 10: UART Break Error */
#define UART_DR_OE (1 << 11) /* Bit 11: UART Overrun Error */
/* UART Receive Status (RSR) */
#define UART_RSR_FE (1 << 0) /* Bit 0: UART Framing Error */
#define UART_RSR_PE (1 << 1) /* Bit 1: UART Parity Error */
#define UART_RSR_BE (1 << 2) /* Bit 2: UART Break Error */
#define UART_RSR_OE (1 << 3) /* Bit 3: UART Overrun Error */
/* UART Error Clear (ECR) */
#define UART_ECR_FE (1 << 0) /* Bit 0: UART Clear Framing Error */
#define UART_ECR_PE (1 << 1) /* Bit 1: UART Clear Parity Error */
#define UART_ECR_BE (1 << 2) /* Bit 2: UART Clear Break Error */
#define UART_ECR_OE (1 << 3) /* Bit 3: UART Clear Overrun Error */
/* UART Flag (FR) */
#define UART_FR_CTS (1 << 0) /* Bit 0: Data Set Ready */
#define UART_FR_BUSY (1 << 3) /* Bit 3: UART Busy */
#define UART_FR_RXFE (1 << 4) /* Bit 4: UART Receive FIFO Empty */
#define UART_FR_TXFF (1 << 5) /* Bit 5: UART Transmit FIFO Full */
#define UART_FR_RXFF (1 << 6) /* Bit 6: UART Receive FIFO Full */
#define UART_FR_TXFE (1 << 7) /* Bit 7: UART Transmit FIFO Empty */
/* UART Integer Baud-Rate Divisor (IBRD) */
#define UART_IBRD_DIVINT_MASK (0xffff) /* Bits 15-0: Integer Baud-Rate Divisor */
/* UART Fractional Baud-Rate Divisor (UARTFBRD) */
#define UART_FBRD_DIVFRAC_MASK (0x3f) /* Bits 5-0: Fractional Baud-Rate Divisor */
/* Register 7: UART Line Control (LCRH) */
#define UART_LCRH_BRK (1 << 0) /* Bit 0: UART Send Break */
#define UART_LCRH_PEN (1 << 1) /* Bit 1: UART Parity Enable */
#define UART_LCRH_EPS (1 << 2) /* Bit 2: UART Even Parity Select */
#define UART_LCRH_STP2 (1 << 3) /* Bit 3: UART Two Stop Bits Select */
#define UART_LCRH_FEN (1 << 4) /* Bit 4: UART Enable FIFOs */
#define UART_LCRH_WLEN_SHIFT 5 /* Bits 6-5: UART Word Length */
#define UART_LCRH_WLEN_MASK (3 << UART_LCRH_WLEN_SHIFT)
# define UART_LCRH_WLEN_5BITS (0 << UART_LCRH_WLEN_SHIFT) /* 5-bits (reset) */
# define UART_LCRH_WLEN_6BITS (1 << UART_LCRH_WLEN_SHIFT) /* 6-bits */
# define UART_LCRH_WLEN_7BITS (2 << UART_LCRH_WLEN_SHIFT) /* 7-bits */
# define UART_LCRH_WLEN_8BITS (3 << UART_LCRH_WLEN_SHIFT) /* 8-bits */
#define UART_LCRH_SPS (1 << 7) /* Bit 7: UART Stick Parity Select */
/* UART Control (CTL) */
#define UART_CTL_UARTEN (1 << 0) /* Bit 0: UART Enable */
#define UART_CTL_LBE (1 << 7) /* Bit 7: UART Loop Back Enable */
#define UART_CTL_TXE (1 << 8) /* Bit 8: UART Transmit Enable */
#define UART_CTL_RXE (1 << 9) /* Bit 9: UART Receive Enable */
#define UART_CTL_DTR (1 << 10) /* Bit 10: Data Terminal Ready */
#define UART_CTL_RTS (1 << 11) /* Bit 11: Request to Send */
#define UART_CTL_RTSEN (1 << 14) /* Bit 14: Enable Request to Send */
#define UART_CTL_CTSEN (1 << 15) /* Bit 15: Enable Clear To Send */
/* UART Interrupt FIFO Level Select (IFLS) */
#define UART_IFLS_TXIFLSEL_SHIFT 0 /* Bits 0-2: UART Transmit Interrupt FIFO Level Select */
#define UART_IFLS_TXIFLSEL_MASK (7 << UART_IFLS_TXIFLSEL_SHIFT)
# define UART_IFLS_TXIFLSEL_18th (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */
# define UART_IFLS_TXIFLSEL_14th (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */
# define UART_IFLS_TXIFLSEL_half (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */
# define UART_IFLS_TXIFLSEL_34th (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */
# define UART_IFLS_TXIFLSEL_78th (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */
#define UART_IFLS_RXIFLSEL_SHIFT 3 /* Bits 3-5: UART Receive Interrupt FIFO Level Select */
#define UART_IFLS_RXIFLSEL_MASK (7 << UART_IFLS_RXIFLSEL_SHIFT)
# define UART_IFLS_RXIFLSEL_18th (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */
# define UART_IFLS_RXIFLSEL_14th (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */
# define UART_IFLS_RXIFLSEL_half (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */
# define UART_IFLS_RXIFLSEL_34th (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */
# define UART_IFLS_RXIFLSEL_78th (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */
/* UART Interrupt Mask (IM) */
#define UART_IM_CTSIM (1 << 1) /* Bit 1: UART Clear to Send Modem Interrupt Mask */
#define UART_IM_RXIM (1 << 4) /* Bit 4: UART Receive Interrupt Mask */
#define UART_IM_TXIM (1 << 5) /* Bit 5: UART Transmit Interrupt Mask */
#define UART_IM_RTIM (1 << 6) /* Bit 6: UART Receive Time-Out Interrupt Mask */
#define UART_IM_FEIM (1 << 7) /* Bit 7: UART Framing Error Interrupt Mask */
#define UART_IM_PEIM (1 << 8) /* Bit 8: UART Parity Error Interrupt Mask */
#define UART_IM_BEIM (1 << 9) /* Bit 9: UART Break Error Interrupt Mask */
#define UART_IM_OEIM (1 << 10) /* Bit 10: UART Overrun Error Interrupt Mask */
#define UART_IM_EOTIM (1 << 11) /* Bit 11: End of Transmission Interrupt Mask */
/* UART Raw Interrupt Status (RIS) */
#define UART_RIS_CTSIS (1 << 1) /* Bit 1: UART Clear to Send Modem Raw Interrupt Status */
#define UART_RIS_RXRIS (1 << 4) /* Bit 4: UART Receive Raw Interrupt Status */
#define UART_RIS_TXRIS (1 << 5) /* Bit 5: UART Transmit Raw Interrupt Status */
#define UART_RIS_RTRIS (1 << 6) /* Bit 6: UART Receive Time-Out Raw Interrupt Status */
#define UART_RIS_FERIS (1 << 7) /* Bit 7: UART Framing Error Raw Interrupt Status */
#define UART_RIS_PERIS (1 << 8) /* Bit 8: UART Parity Error Raw Interrupt Status */
#define UART_RIS_BERIS (1 << 9) /* Bit 9: UART Break Error Raw Interrupt Status */
#define UART_RIS_OERIS (1 << 10) /* Bit 10: UART Overrun Error Raw Interrupt Status */
#define UART_RIS_EOTIS (1 << 11) /* Bit 11: End of Transmission Raw Interrupt Status */
/* UART Masked Interrupt Status (MIS) */
#define UART_MIS_CTSIS (1 << 1) /* Bit 1: UART Clear to Send Modem Masked Interrupt Status */
#define UART_MIS_RXMIS (1 << 4) /* Bit 4: UART Receive Masked Interrupt Status */
#define UART_MIS_TXMIS (1 << 5) /* Bit 5: UART Transmit Masked Interrupt Status */
#define UART_MIS_RTMIS (1 << 6) /* Bit 6: UART Receive Time-Out Masked Interrupt Status */
#define UART_MIS_FEMIS (1 << 7) /* Bit 7: UART Framing Error Masked Interrupt Status */
#define UART_MIS_PEMIS (1 << 8) /* Bit 8: UART Parity Error Masked Interrupt Status */
#define UART_MIS_BEMIS (1 << 9) /* Bit 9: UART Break Error Masked Interrupt Status */
#define UART_MIS_OEMIS (1 << 10) /* Bit 10: UART Overrun Error Masked Interrupt Status */
#define UART_MIS_EOTIS (1 << 11) /* Bit 11: End of Transmission Masked Interrupt Status */
/* UART Interrupt Clear (ICR) */
#define UART_ICR_CTSIC (1 << 1) /* Bit 1: UART Clear to Send Modem Interrupt Clear */
#define UART_ICR_RXIC (1 << 4) /* Bit 4: Receive Interrupt Clear */
#define UART_ICR_TXIC (1 << 5) /* Bit 5: Transmit Interrupt Clear */
#define UART_ICR_RTIC (1 << 6) /* Bit 6: Receive Time-Out Interrupt Clear */
#define UART_ICR_FEIC (1 << 7) /* Bit 7: Framing Error Interrupt Clear */
#define UART_ICR_PEIC (1 << 8) /* Bit 8: Parity Error Interrupt Clear */
#define UART_ICR_BEIC (1 << 9) /* Bit 9: Break Error Interrupt Clear */
#define UART_ICR_OEIC (1 << 10) /* Bit 10: Overrun Error Interrupt Clear */
#define UART_ICR_EOTIC (1 << 11) /* Bit 11: End of Transmission Interrupt Clear */
/* UART DMA Control (DMACTL) */
#define UART_DMACTL_RXDMAE (1 << 0) /* Bit 0: Receive DMA Enable */
#define UART_DMACTL_TXDMAE (1 << 1) /* Bit 1: Transmit DMA Enable */
#define UART_DMACTL_DMAERR (1 << 2) /* Bit 2: DMA on Error */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2CC13X20_CC26X2UART_H */

186
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_v2_memorymap.h
View File

@ -1,186 +0,0 @@
/******************************************************************************
* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_v2_memorymap.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Derives for a TI header file that has a compatible BSD license:
*
* Filename: hw_memmap_h
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name NuttX nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_V2_MEMORYMAP_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_V2_MEMORYMAP_H
/******************************************************************************
* Pre-processor Definitions
******************************************************************************/
/******************************************************************************
*
* The following are defines for the base address of the memories and
* peripherals on the CPU_MMAP interface
*
******************************************************************************/
#define FLASHMEM_BASE 0x00000000 /* FLASHMEM */
#define BROM_BASE 0x10000000 /* BROM */
#define GPRAM_BASE 0x11000000 /* GPRAM */
#define SRAM_BASE 0x20000000 /* SRAM */
#define RFC_RAM_BASE 0x21000000 /* RFC_RAM */
#define RFC_ULLRAM_BASE 0x21004000 /* RFC_ULLRAM */
#define SSI0_BASE 0x40000000 /* SSI */
#define UART0_BASE 0x40001000 /* UART */
#define I2C0_BASE 0x40002000 /* I2C */
#define SSI1_BASE 0x40008000 /* SSI */
#define UART1_BASE 0x4000b000 /* UART */
#define GPT0_BASE 0x40010000 /* GPT */
#define GPT1_BASE 0x40011000 /* GPT */
#define GPT2_BASE 0x40012000 /* GPT */
#define GPT3_BASE 0x40013000 /* GPT */
#define UDMA0_BASE 0x40020000 /* UDMA */
#define I2S0_BASE 0x40021000 /* I2S */
#define GPIO_BASE 0x40022000 /* GPIO */
#define CRYPTO_BASE 0x40024000 /* CRYPTO */
#define PKA_BASE 0x40025000 /* PKA */
#define PKA_RAM_BASE 0x40026000 /* PKA_RAM */
#define PKA_INT_BASE 0x40027000 /* PKA_INT */
#define TRNG_BASE 0x40028000 /* TRNG */
#define FLASH_BASE 0x40030000 /* FLASH */
#define VIMS_BASE 0x40034000 /* VIMS */
#define SRAM_MMR_BASE 0x40035000 /* SRAM_MMR */
#define RFC_PWR_BASE 0x40040000 /* RFC_PWR */
#define RFC_DBELL_BASE 0x40041000 /* RFC_DBELL */
#define RFC_RAT_BASE 0x40043000 /* RFC_RAT */
#define RFC_FSCA_BASE 0x40044000 /* RFC_FSCA */
#define WDT_BASE 0x40080000 /* WDT */
#define IOC_BASE 0x40081000 /* IOC */
#define PRCM_BASE 0x40082000 /* PRCM */
#define EVENT_BASE 0x40083000 /* EVENT */
#define SMPH_BASE 0x40084000 /* SMPH */
#define ADI2_BASE 0x40086000 /* ADI */
#define ADI3_BASE 0x40086200 /* ADI */
#define AON_PMCTL_BASE 0x40090000 /* AON_PMCTL */
#define AON_RTC_BASE 0x40092000 /* AON_RTC */
#define AON_EVENT_BASE 0x40093000 /* AON_EVENT */
#define AON_IOC_BASE 0x40094000 /* AON_IOC */
#define AON_BATMON_BASE 0x40095000 /* AON_BATMON */
#define AUX_SPIM_BASE 0x400c1000 /* AUX_SPIM */
#define AUX_MAC_BASE 0x400c2000 /* AUX_MAC */
#define AUX_TIMER2_BASE 0x400c3000 /* AUX_TIMER2 */
#define AUX_TDC_BASE 0x400c4000 /* AUX_TDC */
#define AUX_EVCTL_BASE 0x400c5000 /* AUX_EVCTL */
#define AUX_SYSIF_BASE 0x400c6000 /* AUX_SYSIF */
#define AUX_TIMER01_BASE 0x400c7000 /* AUX_TIMER01 */
#define AUX_SMPH_BASE 0x400c8000 /* AUX_SMPH */
#define AUX_ANAIF_BASE 0x400c9000 /* AUX_ANAIF */
#define AUX_DDI0_OSC_BASE 0x400ca000 /* DDI */
#define AUX_ADI4_BASE 0x400cb000 /* ADI */
#define AUX_AIODIO0_BASE 0x400cc000 /* AUX_AIODIO */
#define AUX_AIODIO1_BASE 0x400cd000 /* AUX_AIODIO */
#define AUX_AIODIO2_BASE 0x400ce000 /* AUX_AIODIO */
#define AUX_AIODIO3_BASE 0x400cf000 /* AUX_AIODIO */
#define AUX_RAM_BASE 0x400e0000 /* AUX_RAM */
#define AUX_SCE_BASE 0x400e1000 /* AUX_SCE */
#define FLASH_CFG_BASE 0x50000000 /* CC26_DUMMY_COMP */
#define FCFG1_BASE 0x50001000 /* FCFG1 */
#define FCFG2_BASE 0x50002000 /* FCFG2 */
#ifndef CCFG_BASE
# define CCFG_BASE 0x50003000 /* CCFG */
#endif
#define CCFG_BASE_DEFAULT 0x50003000 /* CCFG */
#define SSI0_NONBUF_BASE 0x60000000 /* SSI CPU nonbuf base */
#define UART0_NONBUF_BASE 0x60001000 /* UART CPU nonbuf base */
#define I2C0_NONBUF_BASE 0x60002000 /* I2C CPU nonbuf base */
#define SSI1_NONBUF_BASE 0x60008000 /* SSI CPU nonbuf base */
#define UART1_NONBUF_BASE 0x6000b000 /* UART CPU nonbuf base */
#define GPT0_NONBUF_BASE 0x60010000 /* GPT CPU nonbuf base */
#define GPT1_NONBUF_BASE 0x60011000 /* GPT CPU nonbuf base */
#define GPT2_NONBUF_BASE 0x60012000 /* GPT CPU nonbuf base */
#define GPT3_NONBUF_BASE 0x60013000 /* GPT CPU nonbuf base */
#define UDMA0_NONBUF_BASE 0x60020000 /* UDMA CPU nonbuf base */
#define I2S0_NONBUF_BASE 0x60021000 /* I2S CPU nonbuf base */
#define GPIO_NONBUF_BASE 0x60022000 /* GPIO CPU nonbuf base */
#define CRYPTO_NONBUF_BASE 0x60024000 /* CRYPTO CPU nonbuf base */
#define PKA_NONBUF_BASE 0x60025000 /* PKA CPU nonbuf base */
#define PKA_RAM_NONBUF_BASE 0x60026000 /* PKA_RAM CPU nonbuf base */
#define PKA_INT_NONBUF_BASE 0x60027000 /* PKA_INT CPU nonbuf base */
#define TRNG_NONBUF_BASE 0x60028000 /* TRNG CPU nonbuf base */
#define FLASH_NONBUF_BASE 0x60030000 /* FLASH CPU nonbuf base */
#define VIMS_NONBUF_BASE 0x60034000 /* VIMS CPU nonbuf base */
#define SRAM_MMR_NONBUF_BASE 0x60035000 /* SRAM_MMR CPU nonbuf base */
#define RFC_PWR_NONBUF_BASE 0x60040000 /* RFC_PWR CPU nonbuf base */
#define RFC_DBELL_NONBUF_BASE 0x60041000 /* RFC_DBELL CPU nonbuf base */
#define RFC_RAT_NONBUF_BASE 0x60043000 /* RFC_RAT CPU nonbuf base */
#define RFC_FSCA_NONBUF_BASE 0x60044000 /* RFC_FSCA CPU nonbuf base */
#define WDT_NONBUF_BASE 0x60080000 /* WDT CPU nonbuf base */
#define IOC_NONBUF_BASE 0x60081000 /* IOC CPU nonbuf base */
#define PRCM_NONBUF_BASE 0x60082000 /* PRCM CPU nonbuf base */
#define EVENT_NONBUF_BASE 0x60083000 /* EVENT CPU nonbuf base */
#define SMPH_NONBUF_BASE 0x60084000 /* SMPH CPU nonbuf base */
#define ADI2_NONBUF_BASE 0x60086000 /* ADI CPU nonbuf base */
#define ADI3_NONBUF_BASE 0x60086200 /* ADI CPU nonbuf base */
#define AON_PMCTL_NONBUF_BASE 0x60090000 /* AON_PMCTL CPU nonbuf base */
#define AON_RTC_NONBUF_BASE 0x60092000 /* AON_RTC CPU nonbuf base */
#define AON_EVENT_NONBUF_BASE 0x60093000 /* AON_EVENT CPU nonbuf base */
#define AON_IOC_NONBUF_BASE 0x60094000 /* AON_IOC CPU nonbuf base */
#define AON_BATMON_NONBUF_BASE 0x60095000 /* AON_BATMON CPU nonbuf base */
#define AUX_SPIM_NONBUF_BASE 0x600c1000 /* AUX_SPIM CPU nonbuf base */
#define AUX_MAC_NONBUF_BASE 0x600c2000 /* AUX_MAC CPU nonbuf base */
#define AUX_TIMER2_NONBUF_BASE 0x600c3000 /* AUX_TIMER2 CPU nonbuf base */
#define AUX_TDC_NONBUF_BASE 0x600c4000 /* AUX_TDC CPU nonbuf base */
#define AUX_EVCTL_NONBUF_BASE 0x600c5000 /* AUX_EVCTL CPU nonbuf base */
#define AUX_SYSIF_NONBUF_BASE 0x600c6000 /* AUX_SYSIF CPU nonbuf base */
#define AUX_TIMER01_NONBUF_BASE 0x600c7000 /* AUX_TIMER01 CPU nonbuf base */
#define AUX_SMPH_NONBUF_BASE 0x600c8000 /* AUX_SMPH CPU nonbuf base */
#define AUX_ANAIF_NONBUF_BASE 0x600c9000 /* AUX_ANAIF CPU nonbuf base */
#define AUX_DDI0_OSC_NONBUF_BASE 0x600ca000 /* DDI CPU nonbuf base */
#define AUX_ADI4_NONBUF_BASE 0x600cb000 /* ADI CPU nonbuf base */
#define AUX_AIODIO0_NONBUF_BASE 0x600cc000 /* AUX_AIODIO CPU nonbuf base */
#define AUX_AIODIO1_NONBUF_BASE 0x600cd000 /* AUX_AIODIO CPU nonbuf base */
#define AUX_AIODIO2_NONBUF_BASE 0x600ce000 /* AUX_AIODIO CPU nonbuf base */
#define AUX_AIODIO3_NONBUF_BASE 0x600cf000 /* AUX_AIODIO CPU nonbuf base */
#define AUX_RAM_NONBUF_BASE 0x600e0000 /* AUX_RAM CPU nonbuf base */
#define AUX_SCE_NONBUF_BASE 0x600e1000 /* AUX_SCE CPU nonbuf base */
#define FLASHMEM_ALIAS_BASE 0xa0000000 /* FLASHMEM Alias base */
#define CPU_ITM_BASE 0xe0000000 /* CPU_ITM */
#define CPU_DWT_BASE 0xe0001000 /* CPU_DWT */
#define CPU_FPB_BASE 0xe0002000 /* CPU_FPB */
#define CPU_SCS_BASE 0xe000e000 /* CPU_SCS */
#define CPU_TPIU_BASE 0xe0040000 /* CPU_TPIU */
#define CPU_TIPROP_BASE 0xe00fe000 /* CPU_TIPROP */
#define CPU_ROM_TABLE_BASE 0xe00ff000 /* CPU_ROM_TABLE */
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_V2_MEMORYMAP_H */

8
arch/arm/src/tiva/hardware/lm/lm_uart.h
View File

@ -367,8 +367,12 @@
#define UART_RSR_BE (1 << 2) /* Bit 2: UART Break Error */
#define UART_RSR_OE (1 << 3) /* Bit 3: UART Overrun Error */
/* UART Error Clear (ECR), offset 0x004 */
/* Writing any value to this register clears pending error indications */
/* UART Error Clear (ECR) */
#define UART_ECR_FE (1 << 0) /* Bit 0: UART Clear Framing Error */
#define UART_ECR_PE (1 << 1) /* Bit 1: UART Clear Parity Error */
#define UART_ECR_BE (1 << 2) /* Bit 2: UART Clear Break Error */
#define UART_ECR_OE (1 << 3) /* Bit 3: UART Clear Overrun Error */
/* UART Flag (FR) */

6
arch/arm/src/tiva/hardware/tiva_memorymap.h
View File

@ -52,10 +52,8 @@
# include "hardware/tm4c/tm4c_memorymap.h"
#elif defined(CONFIG_ARCH_CHIP_CC13X0)
# include "hardware/cc13x0/cc13x0_memorymap.h"
#elif defined(CONFIG_ARCH_CHIP_CC13X2_V1)
# include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_v1_memorymap.h"
#elif defined(CONFIG_ARCH_CHIP_CC13X2_V2)
# include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_v2_memorymap.h"
#elif defined(CONFIG_ARCH_CHIP_CC13X2)
# include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_memorymap.h"
#else
# error "Unsupported Tiva/Stellaris memory map"
#endif

6
arch/arm/src/tiva/hardware/tiva_uart.h
View File

@ -54,10 +54,8 @@
# include "hardware/tm4c/tm4c_uart.h"
#elif defined(CONFIG_ARCH_CHIP_CC13X0)
# include "hardware/cc13x0/cc13x0_uart.h"
#elif defined(CONFIG_ARCH_CHIP_CC13X2_V1)
# include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_v1_uart.h"
#elif defined(CONFIG_ARCH_CHIP_CC13X2_V2)
# include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_v2_uart.h"
#elif defined(CONFIG_ARCH_CHIP_CC13X2)
# include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_uart.h"
#else
# error "Unsupported Tiva/Stellaris memory map"
#endif

14
arch/arm/src/tiva/hardware/tm4c/tm4c_uart.h
View File

@ -447,15 +447,19 @@
#define UART_RSR_BE (1 << 2) /* Bit 2: UART Break Error */
#define UART_RSR_OE (1 << 3) /* Bit 3: UART Overrun Error */
/* UART Error Clear (ECR), offset 0x004 */
/* Writing any value to this register clears pending error indications */
/* UART Error Clear (ECR) */
#define UART_ECR_FE (1 << 0) /* Bit 0: UART Clear Framing Error */
#define UART_ECR_PE (1 << 1) /* Bit 1: UART Clear Parity Error */
#define UART_ECR_BE (1 << 2) /* Bit 2: UART Clear Break Error */
#define UART_ECR_OE (1 << 3) /* Bit 3: UART Clear Overrun Error */
/* UART Flag (FR) */
#if defined(CONFIG_ARCH_CHIP_TM4C129)
# define UART_FR_CTS (1 << 0) /* Bit 0: Data Set Ready */
# define UART_FR_DSR (1 << 1) /* Bit 1: Data Set Ready */
# define UART_FR_DCD (1 << 2) /* Bit 2: Data Carrier Detect */
# define UART_FR_CTS (1 << 0) /* Bit 0: Data Set Ready */
# define UART_FR_DSR (1 << 1) /* Bit 1: Data Set Ready */
# define UART_FR_DCD (1 << 2) /* Bit 2: Data Carrier Detect */
#endif
#define UART_FR_BUSY (1 << 3) /* Bit 3: UART Busy */