Add interrupt decode logic for i.MX
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1701 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -1,7 +1,8 @@
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/********************************************************************************
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* dm320/dm320_decodeirq.c
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* arch/arm/src/dm320/dm320_decodeirq.c
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* arch/arm/src/chip/dm320_decodeirq.c
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*
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* Copyright (C) 2007 Gregory Nutt. All rights reserved.
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* Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -14,7 +15,7 @@
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name Gregory Nutt nor the names of its contributors may be
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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@ -43,6 +44,7 @@
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#include <nuttx/arch.h>
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#include <assert.h>
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#include <debug.h>
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#include "up_arch.h"
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#include "os_internal.h"
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#include "up_internal.h"
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@ -86,7 +88,7 @@ void up_decodeirq(uint32* regs)
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int irq = (irqentry >> 2) - 1;
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/* Verify that the resulting IRQ number is valie */
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/* Verify that the resulting IRQ number is valid */
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if ((unsigned)irq < NR_IRQS)
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{
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@ -47,7 +47,7 @@ CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
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CHIP_ASRCS = imx_lowputc.S
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CHIP_CSRCS = imx_boot.c imx_gpio.c imx_allocateheap.c imx_irq.c \
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imx_serial.c imx_timerisr.c # imx_decodeirq.c imx_framebuffer.c
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imx_serial.c imx_timerisr.c imx_decodeirq.c #imx_framebuffer.c
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ifeq ($(CONFIG_USBDEV),y)
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CHIP_CSRCS += imx_usbdev.c
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@ -106,6 +106,12 @@
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/* AITC Register Bit Definitions ****************************************************/
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#define AITC_NIVECSR_NIPRILVL_SHIFT 0 /* Bits 15–0: Priority of highest priority interrupt */
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#define AITC_NIVECSR_NIPRILVL_MASK (0x0000ffff << AITC_NIVECSR_NIPRILVL_SHIFT);
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#define AITC_NIVECSR_NIVECTOR_SHIFT 16 /* Bits 31–16: Vector index of highest priority interrupt */
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#define AITC_NIVECSR_NIVECTOR_MASK (0x0000ffff << AITC_NIVECSR_NIVECTOR_SHIFT);
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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123
arch/arm/src/imx/imx_decodeirq.c
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123
arch/arm/src/imx/imx_decodeirq.c
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@ -0,0 +1,123 @@
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/********************************************************************************
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* arch/arm/src/imx/imx_decodeirq.c
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* arch/arm/src/chip/imx_decodeirq.c
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************/
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/********************************************************************************
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* Included Files
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********************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <assert.h>
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#include <debug.h>
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#include "up_arch.h"
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#include "os_internal.h"
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#include "up_internal.h"
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/********************************************************************************
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* Definitions
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********************************************************************************/
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/********************************************************************************
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* Public Data
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********************************************************************************/
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/********************************************************************************
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* Private Data
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********************************************************************************/
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/********************************************************************************
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* Private Functions
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********************************************************************************/
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/********************************************************************************
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* Public Funtions
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********************************************************************************/
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void up_decodeirq(uint32* regs)
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{
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#ifdef CONFIG_SUPPRESS_INTERRUPTS
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lib_lowprintf("Unexpected IRQ\n");
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current_regs = regs;
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PANIC(OSERR_ERREXCEPTION);
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#else
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uint32 regval;
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int irq;
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/* Decode the interrupt. First, fetch the NIVECSR register. */
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regval = getreg32(IMX_AITC_NIVECSR);
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/* The MS 16 bits of the NIVECSR register contains vector index for the
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* highest pending normal interrupt.
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*/
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irq = regval >> AITC_NIVECSR_NIVECTOR_SHIFT;
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/* If irq < 64, then this is the IRQ. If there is no pending interrupt,
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* then irq will be >= 64 (it will be 0xffff for illegal source).
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*/
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if (irq < NR_IRQS)
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{
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/* Mask and acknowledge the interrupt */
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up_maskack_irq(irq);
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/* Current regs non-zero indicates that we are processing an interrupt;
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* current_regs is also used to manage interrupt level context switches.
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*/
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current_regs = regs;
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/* Deliver the IRQ */
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irq_dispatch(irq, regs);
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/* Indicate that we are no long in an interrupt handler */
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current_regs = NULL;
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/* Unmask the last interrupt (global interrupts are still
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* disabled.
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*/
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up_enable_irq(irq);
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}
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#endif
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}
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