stm32f30xxx_rcc.c: remove code that refers to STM32F1 specific definitions
This commit is contained in:
raiden00pl
Xiang Xiao
parent
8021dfece6
commit
b239985037
@ -416,124 +416,13 @@ static inline void rcc_enableapb2(void)
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* Name: stm32_stdclockconfig
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* Name: stm32_stdclockconfig
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*
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*
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* Description:
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* Description:
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* Called to change to new clock based on settings in board.h. This
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* Called to change to new clock based on settings in board.h.
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* version is for the Connectivity Line parts.
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*
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*
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* NOTE: This logic would need to be extended if you need to select low-
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* NOTE: This logic would need to be extended if you need to select low-
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* power clocking modes!
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* power clocking modes!
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****************************************************************************/
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****************************************************************************/
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#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) && defined(CONFIG_STM32_CONNECTIVITYLINE)
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#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
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static void stm32_stdclockconfig(void)
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{
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uint32_t regval;
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/* Enable HSE */
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regval = getreg32(STM32_RCC_CR);
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regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
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regval |= RCC_CR_HSEON; /* Enable HSE */
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putreg32(regval, STM32_RCC_CR);
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/* Enable FLASH prefetch buffer and set FLASH wait states */
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regval = getreg32(STM32_FLASH_ACR);
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regval &= ~FLASH_ACR_LATENCY_MASK;
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regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE);
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putreg32(regval, STM32_FLASH_ACR);
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/* Set up PLL input scaling (with source = PLL2) */
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regval = getreg32(STM32_RCC_CFGR2);
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regval &= ~(RCC_CFGR2_PREDIV2_MASK | RCC_CFGR2_PLL2MUL_MASK |
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RCC_CFGR2_PREDIV1SRC_MASK | RCC_CFGR2_PREDIV1_MASK);
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regval |= (STM32_PLL_PREDIV2 | STM32_PLL_PLL2MUL |
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RCC_CFGR2_PREDIV1SRC_PLL2 | STM32_PLL_PREDIV1);
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putreg32(regval, STM32_RCC_CFGR2);
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/* Set the PCLK2 divider */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~(RCC_CFGR_PPRE2_MASK | RCC_CFGR_HPRE_MASK);
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regval |= STM32_RCC_CFGR_PPRE2;
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regval |= RCC_CFGR_HPRE_SYSCLK;
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putreg32(regval, STM32_RCC_CFGR);
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/* Set the PCLK1 divider */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_PPRE1_MASK;
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regval |= STM32_RCC_CFGR_PPRE1;
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putreg32(regval, STM32_RCC_CFGR);
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/* Enable PLL2 */
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regval = getreg32(STM32_RCC_CR);
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regval |= RCC_CR_PLL2ON;
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putreg32(regval, STM32_RCC_CR);
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/* Wait for PLL2 ready */
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while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL2RDY) == 0);
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/* Setup PLL3 for MII/RMII clock on MCO */
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#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO)
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regval = getreg32(STM32_RCC_CFGR2);
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regval &= ~(RCC_CFGR2_PLL3MUL_MASK);
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regval |= STM32_PLL_PLL3MUL;
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putreg32(regval, STM32_RCC_CFGR2);
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/* Switch PLL3 on */
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regval = getreg32(STM32_RCC_CR);
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regval |= RCC_CR_PLL3ON;
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putreg32(regval, STM32_RCC_CR);
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while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL3RDY) == 0);
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#endif
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/* Set main PLL source and multiplier */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL_MASK);
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regval |= (RCC_CFGR_PLLSRC | STM32_PLL_PLLMUL);
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putreg32(regval, STM32_RCC_CFGR);
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/* Switch main PLL on */
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regval = getreg32(STM32_RCC_CR);
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regval |= RCC_CR_PLLON;
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putreg32(regval, STM32_RCC_CR);
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while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
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/* Select PLL as system clock source */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_SW_MASK;
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regval |= RCC_CFGR_SW_PLL;
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putreg32(regval, STM32_RCC_CFGR);
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/* Wait until PLL is used as the system clock source */
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while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_PLL) == 0);
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}
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#endif
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/****************************************************************************
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* Name: stm32_stdclockconfig
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*
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* Description:
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* Called to change to new clock based on settings in board.h. This
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* version is for the non-Connectivity Line parts.
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*
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* NOTE: This logic would need to be extended if you need to select low-
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* power clocking modes!
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****************************************************************************/
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#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) && \
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!defined(CONFIG_STM32_CONNECTIVITYLINE)
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static void stm32_stdclockconfig(void)
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static void stm32_stdclockconfig(void)
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{
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{
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uint32_t regval;
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uint32_t regval;
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@ -576,30 +465,6 @@ static void stm32_stdclockconfig(void)
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}
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}
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}
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}
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# if defined(CONFIG_STM32_VALUELINE) && (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC)
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/* If this is a value-line part and we are using the HSE as the PLL */
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# if (STM32_CFGR_PLLXTPRE >> 17) != (STM32_CFGR2_PREDIV1 & 1)
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# error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV1
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# endif
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/* Set the HSE prescaler */
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regval = STM32_CFGR2_PREDIV1;
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putreg32(regval, STM32_RCC_CFGR2);
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# endif
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#endif
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#ifndef CONFIG_STM32_VALUELINE
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/* Value-line devices don't implement flash prefetch/waitstates */
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/* Enable FLASH prefetch buffer and set FLASH wait states */
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regval = getreg32(STM32_FLASH_ACR);
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regval &= ~FLASH_ACR_LATENCY_MASK;
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regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE);
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putreg32(regval, STM32_FLASH_ACR);
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#endif
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#endif
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/* Set the HCLK source/divider */
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/* Set the HCLK source/divider */
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