xtensa/esp32s3: Support 32MB SPI flash
This commit is contained in:
Dong Heng
Xiang Xiao
parent
69081a72d7
commit
b24f931aca
@ -230,6 +230,11 @@ config ESP32S3_FLASH_16M
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bool
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default n
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config ESP32S3_FLASH_32M
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bool
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default n
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select ESP32S3S_SPI_FLASH_USE_32BIT_ADDRESS
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config ESP32S3_ESPTOOLPY_NO_STUB
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bool "Disable download stub"
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default n
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@ -1036,6 +1041,23 @@ choice ESP32S3_FLASH_SAMPLE_MODE
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bool "STR Mode"
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endchoice
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config ESP32S3_SPI_FLASH_DONT_USE_ROM_CODE
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bool "Don't use SPI flash driver in ROM"
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default n
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help
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Use source code for SPI flash driver instead of functions
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in ROM.
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config ESP32S3S_SPI_FLASH_USE_32BIT_ADDRESS
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bool "SPI flash uses 32-bit address"
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default n
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select ESP32S3_SPI_FLASH_DONT_USE_ROM_CODE
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help
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SPI flash driver in ROM only support 24-bit address access,
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if select the option, it will force to use source code instead
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of functions in ROM, so that SPI flash driver can access full
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32-bit address.
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config ESP32S3_HAVE_OTA_PARTITION
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bool
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default n
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@ -29,16 +29,19 @@
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#include <debug.h>
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#include <string.h>
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#include <sys/types.h>
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#include <sys/param.h>
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#include <inttypes.h>
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#include <errno.h>
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#include <nuttx/arch.h>
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#include <nuttx/init.h>
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#include "hardware/esp32s3_soc.h"
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#include "xtensa.h"
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#include "xtensa_attr.h"
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#include "hardware/esp32s3_spi_mem_reg.h"
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#include "rom/esp32s3_spiflash.h"
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#include "rom/esp32s3_opi_flash.h"
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#include "esp32s3_irq.h"
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#include "esp32s3_spiflash.h"
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/****************************************************************************
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@ -71,6 +74,99 @@
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#define MMU_BYTES2PAGES(_n) (((_n) + SPI_FLASH_MMU_PAGE_SIZE - 1) / \
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SPI_FLASH_MMU_PAGE_SIZE)
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#ifdef CONFIG_ESP32S3_SPI_FLASH_DONT_USE_ROM_CODE
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/* SPI port number */
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# define SPI_PORT (1)
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/* SPI buffer size */
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# define SPI_BUFFER_WORDS (16)
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# define SPI_BUFFER_BYTES (SPI_BUFFER_WORDS * 4)
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/* SPI flash hardware definition */
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# define FLASH_SECTOR_SIZE (4096)
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/* SPI flash command */
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# define FLASH_CMD_WRDI ROM_FLASH_CMD_WRDI
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# define FLASH_CMD_WREN ROM_FLASH_CMD_WREN
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# define FLASH_CMD_RDSR ROM_FLASH_CMD_RDSR
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# define FLASH_CMD_SE4B ROM_FLASH_CMD_SE4B
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# define FLASH_CMD_SE ROM_FLASH_CMD_ERASE_SEC
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# define FLASH_CMD_PP4B ROM_FLASH_CMD_PP4B
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# define FLASH_CMD_PP 0x02
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# define FLASH_CMD_FSTRD4B ROM_FLASH_CMD_FSTRD4B
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# define FLASH_CMD_FSTRD 0x0B
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/* SPI flash SR1 bits */
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# define FLASH_SR1_BUSY ESP_ROM_SPIFLASH_BUSY_FLAG
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# define FLASH_SR1_WREN ESP_ROM_SPIFLASH_WRENABLE_FLAG
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/* SPI flash operation */
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# ifdef CONFIG_ESP32S3S_SPI_FLASH_USE_32BIT_ADDRESS
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# define ADDR_BITS(addr) (((addr) & 0xff000000) ? 32 : 24)
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# define READ_CMD(addr) (ADDR_BITS(addr) == 32 ? FLASH_CMD_FSTRD4B : \
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FLASH_CMD_FSTRD)
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# define WRITE_CMD(addr) (ADDR_BITS(addr) == 32 ? FLASH_CMD_PP4B : \
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FLASH_CMD_PP)
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# define ERASE_CMD(addr) (ADDR_BITS(addr) == 32 ? FLASH_CMD_SE4B : \
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FLASH_CMD_SE)
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# define READ_DUMMY(addr) (8)
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# else
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# define ADDR_BITS(addr) 24
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# define READ_CMD(addr) FLASH_CMD_FSTRD
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# define WRITE_CMD(addr) FLASH_CMD_PP
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# define ERASE_CMD(addr) FLASH_CMD_SE
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# define READ_DUMMY(addr) (8)
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# endif
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# define SEND_CMD8_TO_FLASH(cmd) \
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esp32s3_spi_trans((cmd), 8, \
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0, 0, \
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NULL, 0, \
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NULL, 0, \
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0, \
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false)
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# define READ_SR1_FROM_FLASH(cmd, status) \
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esp32s3_spi_trans((cmd), 8, \
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0, 0, \
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NULL, 0, \
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(status), 1, \
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0, \
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false)
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# define ERASE_FLASH_SECTOR(addr) \
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esp32s3_spi_trans(ERASE_CMD(addr), 8, \
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(addr), ADDR_BITS(addr), \
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NULL, 0, \
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NULL, 0, \
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0, \
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true)
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# define WRITE_DATA_TO_FLASH(addr, buffer, size) \
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esp32s3_spi_trans(WRITE_CMD(addr), 8, \
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(addr), ADDR_BITS(addr), \
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buffer, size, \
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NULL, 0, \
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0, \
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true)
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# define READ_DATA_FROM_FLASH(addr, buffer, size) \
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esp32s3_spi_trans(READ_CMD(addr), 8, \
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(addr), ADDR_BITS(addr), \
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NULL, 0, \
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buffer, size, \
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READ_DUMMY(addr), \
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false)
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#endif /* CONFIG_ESP32S3_SPI_FLASH_DONT_USE_ROM_CODE */
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/****************************************************************************
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* Private Types
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****************************************************************************/
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@ -100,24 +196,6 @@ struct spiflash_map_req_s
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uint32_t page_cnt;
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};
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/* Structure holding SPI flash access critical sections management
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* functions.
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*/
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struct spiflash_guard_funcs_s
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{
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void (*start)(void); /* critical section start function */
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void (*end)(void); /* critical section end function */
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void (*op_lock)(void); /* flash access API lock function */
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void (*op_unlock)(void); /* flash access API unlock function */
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/* checks flash write addresses */
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bool (*address_is_safe)(size_t addr, size_t size);
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void (*yield)(void); /* yield to the OS during flash erase */
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};
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struct spiflash_cachestate_s
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{
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uint32_t value;
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@ -139,7 +217,6 @@ static void spiflash_end(void);
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* Public Functions Declaration
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****************************************************************************/
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extern void spi_flash_guard_set(const struct spiflash_guard_funcs_s *funcs);
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extern uint32_t cache_suspend_icache(void);
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extern uint32_t cache_suspend_dcache(void);
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extern void cache_resume_icache(uint32_t val);
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@ -150,7 +227,7 @@ extern int cache_invalidate_addr(uint32_t addr, uint32_t size);
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* Private Data
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****************************************************************************/
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static struct spiflash_guard_funcs_s g_spi_flash_guard_funcs =
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static struct spiflash_guard_funcs g_spi_flash_guard_funcs =
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{
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.start = spiflash_start,
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.end = spiflash_end,
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@ -216,6 +293,258 @@ static IRAM_ATTR void spiflash_end(void)
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leave_critical_section(g_state.flags);
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}
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/****************************************************************************
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* Name: esp32s3_spi_trans
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*
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* Description:
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* Transmit given command, address and data.
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*
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* Input Parameters:
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* command - command value
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* command_bits - command bits
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* address - address value
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* address_bits - address bits
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* tx_buffer - write buffer
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* tx_bytes - write buffer size
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* rx_buffer - read buffer
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* rx_bytes - read buffer size
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* dummy_bits - dummy bits
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* is_program - true if operation is program or erase
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*
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* Returned Value:
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* 0 if success or a negative value if fail.
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*
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****************************************************************************/
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#ifdef CONFIG_ESP32S3_SPI_FLASH_DONT_USE_ROM_CODE
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static IRAM_ATTR void esp32s3_spi_trans(uint32_t command,
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uint32_t command_bits,
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uint32_t address,
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uint32_t address_bits,
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uint32_t *tx_buffer,
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uint32_t tx_bytes,
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uint32_t *rx_buffer,
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uint32_t rx_bytes,
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uint32_t dummy_bits,
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bool is_program)
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{
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uint32_t regval;
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uint32_t cmd_reg;
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uint32_t user1_reg = getreg32(SPI_MEM_USER1_REG(SPI_PORT));
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uint32_t user_reg = getreg32(SPI_MEM_USER_REG(SPI_PORT));
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/* Initiliaze SPI user register */
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user_reg &= ~(SPI_MEM_USR_ADDR_M | SPI_MEM_USR_DUMMY_M |
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SPI_MEM_USR_MOSI_M | SPI_MEM_USR_MISO_M);
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user_reg |= SPI_MEM_USR_COMMAND_M;
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/* Wait until SPI is idle */
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do
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{
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cmd_reg = getreg32(SPI_MEM_CMD_REG(SPI_PORT));
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}
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while ((cmd_reg & SPI_MEM_USR_M) != 0);
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/* Set command bits and value, and command is always needed */
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regval = getreg32(SPI_MEM_USER2_REG(SPI_PORT));
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regval &= ~(SPI_MEM_USR_COMMAND_BITLEN_M | SPI_MEM_USR_COMMAND_VALUE_M);
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regval |= ((command_bits - 1) << SPI_MEM_USR_COMMAND_BITLEN_S) |
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(command << SPI_MEM_USR_COMMAND_VALUE_S);
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putreg32(regval, SPI_MEM_USER2_REG(SPI_PORT));
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/* Set address bits and value */
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if (address_bits)
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{
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user1_reg &= ~SPI_MEM_USR_ADDR_BITLEN_M;
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user1_reg |= (address_bits - 1) << SPI_MEM_USR_ADDR_BITLEN_S;
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putreg32(address, SPI_MEM_ADDR_REG(SPI_PORT));
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user_reg |= SPI_MEM_USR_ADDR_M;
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regval = getreg32(SPI_MEM_CACHE_FCTRL_REG(SPI_PORT));
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if (address_bits > 24)
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{
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regval |= SPI_MEM_CACHE_USR_CMD_4BYTE_M;
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}
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else
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{
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regval &= ~SPI_MEM_CACHE_USR_CMD_4BYTE_M;
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}
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putreg32(regval, SPI_MEM_CACHE_FCTRL_REG(SPI_PORT));
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}
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/* Set dummy */
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if (dummy_bits)
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{
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user1_reg &= ~SPI_MEM_USR_DUMMY_CYCLELEN_M;
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user1_reg |= (dummy_bits - 1) << SPI_MEM_USR_DUMMY_CYCLELEN_S;
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user_reg |= SPI_MEM_USR_DUMMY_M;
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}
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/* Set TX data */
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if (tx_bytes)
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{
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putreg32(tx_bytes * 8 - 1, SPI_MEM_MOSI_DLEN_REG(SPI_PORT));
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for (uint32_t i = 0; i < tx_bytes; i += 4)
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{
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putreg32(tx_buffer[i / 4], SPI_MEM_W0_REG(SPI_PORT) + i);
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}
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user_reg |= SPI_MEM_USR_MOSI_M;
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}
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/* Set RX data */
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if (rx_bytes)
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{
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putreg32(rx_bytes * 8 - 1, SPI_MEM_MISO_DLEN_REG(SPI_PORT));
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user_reg |= SPI_MEM_USR_MISO_M;
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}
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putreg32(user_reg, SPI_MEM_USER_REG(SPI_PORT));
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putreg32(user1_reg, SPI_MEM_USER1_REG(SPI_PORT));
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/* Set I/O mode */
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regval = getreg32(SPI_MEM_CTRL_REG(SPI_PORT));
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regval &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_DIO_M |
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SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DUAL_M |
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SPI_MEM_FCMD_OCT_M | SPI_MEM_FCMD_QUAD_M |
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SPI_MEM_FCMD_DUAL_M | SPI_MEM_FADDR_OCT_M |
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SPI_MEM_FDIN_OCT_M | SPI_MEM_FDOUT_OCT_M |
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SPI_MEM_FDUMMY_OUT_M | SPI_MEM_RESANDRES_M |
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SPI_MEM_WP_REG_M | SPI_MEM_WRSR_2B_M);
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regval |= SPI_MEM_FASTRD_MODE_M;
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putreg32(regval, SPI_MEM_CTRL_REG(SPI_PORT));
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/* Set clock and delay */
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regval = SPI_MEM_FLASH_PES_WAIT_EN_M |
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SPI_MEM_FLASH_PER_WAIT_EN_M;
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putreg32(regval, SPI_MEM_FLASH_SUS_CMD_REG(SPI_PORT));
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putreg32(0, SPI_MEM_CLOCK_GATE_REG(SPI_PORT));
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/* Set if this is program or erase operation */
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if (is_program)
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{
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cmd_reg |= SPI_MEM_FLASH_PE_M;
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}
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/* Start transmision */
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cmd_reg |= SPI_MEM_USR_M;
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putreg32(cmd_reg, SPI_MEM_CMD_REG(SPI_PORT));
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/* Wait until transmission is done */
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while ((getreg32(SPI_MEM_CMD_REG(SPI_PORT)) & SPI_MEM_USR_M) != 0)
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{
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;
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}
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/* Get read data */
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if (rx_bytes)
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{
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for (uint32_t i = 0; i < rx_bytes; i += 4)
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{
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rx_buffer[i / 4] = getreg32(SPI_MEM_W0_REG(SPI_PORT) + i);
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}
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}
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}
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/****************************************************************************
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* Name: wait_flash_idle
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*
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* Description:
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* Wait until flash enters idle state
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*
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* Returned Value:
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* None.
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*
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****************************************************************************/
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static IRAM_ATTR void wait_flash_idle(void)
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{
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uint32_t status;
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do
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{
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READ_SR1_FROM_FLASH(FLASH_CMD_RDSR, &status);
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if ((status & FLASH_SR1_BUSY) == 0)
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{
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break;
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}
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}
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while (1);
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}
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/****************************************************************************
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* Name: enable_flash_write
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*
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* Description:
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* Enable Flash write mode
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*
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* Returned Value:
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* None.
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*
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****************************************************************************/
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static IRAM_ATTR void enable_flash_write(void)
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{
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uint32_t status;
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do
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{
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SEND_CMD8_TO_FLASH(FLASH_CMD_WREN);
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READ_SR1_FROM_FLASH(FLASH_CMD_RDSR, &status);
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if ((status & FLASH_SR1_WREN) != 0)
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{
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break;
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}
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}
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while (1);
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}
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/****************************************************************************
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* Name: disable_flash_write
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*
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* Description:
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* Disable Flash write mode
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*
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* Returned Value:
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* None.
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*
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****************************************************************************/
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static IRAM_ATTR void disable_flash_write(void)
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{
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uint32_t status;
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do
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{
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SEND_CMD8_TO_FLASH(FLASH_CMD_WRDI);
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READ_SR1_FROM_FLASH(FLASH_CMD_RDSR, &status);
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if ((status & FLASH_SR1_WREN) == 0)
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{
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break;
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}
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}
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while (1);
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}
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#endif /* CONFIG_ESP32S3_SPI_FLASH_DONT_USE_ROM_CODE */
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/****************************************************************************
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* Name: esp32s3_mmap
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*
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@ -357,6 +686,178 @@ int spi_flash_read_encrypted(uint32_t addr, void *buffer, uint32_t size)
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return OK;
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}
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/****************************************************************************
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* Name: spi_flash_erase_sector
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*
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* Description:
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* Erase the Flash sector.
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*
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* Parameters:
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* sector - Sector number, the count starts at sector 0, 4KB per sector.
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*
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* Returned Values: esp_err_t
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* Zero (OK) is returned or a negative error.
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*
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****************************************************************************/
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#ifdef CONFIG_ESP32S3_SPI_FLASH_DONT_USE_ROM_CODE
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IRAM_ATTR int spi_flash_erase_sector(uint32_t sector)
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{
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int ret = OK;
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uint32_t addr = sector * FLASH_SECTOR_SIZE;
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spiflash_start();
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wait_flash_idle();
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enable_flash_write();
|
||||
|
||||
ERASE_FLASH_SECTOR(addr);
|
||||
|
||||
wait_flash_idle();
|
||||
disable_flash_write();
|
||||
|
||||
spiflash_end();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: spi_flash_erase_range
|
||||
*
|
||||
* Description:
|
||||
* Erase a range of flash sectors
|
||||
*
|
||||
* Parameters:
|
||||
* start_address - Address where erase operation has to start.
|
||||
* Must be 4kB-aligned
|
||||
* size - Size of erased range, in bytes. Must be divisible by
|
||||
* 4kB.
|
||||
*
|
||||
* Returned Values:
|
||||
* Zero (OK) is returned or a negative error.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
IRAM_ATTR int spi_flash_erase_range(uint32_t start_address, uint32_t size)
|
||||
{
|
||||
int ret = OK;
|
||||
uint32_t addr = start_address;
|
||||
|
||||
spiflash_start();
|
||||
|
||||
for (uint32_t i = 0; i < size; i += FLASH_SECTOR_SIZE)
|
||||
{
|
||||
wait_flash_idle();
|
||||
enable_flash_write();
|
||||
|
||||
ERASE_FLASH_SECTOR(addr);
|
||||
addr += FLASH_SECTOR_SIZE;
|
||||
}
|
||||
|
||||
wait_flash_idle();
|
||||
disable_flash_write();
|
||||
|
||||
spiflash_end();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: spi_flash_write
|
||||
*
|
||||
* Description:
|
||||
* Write data to Flash.
|
||||
*
|
||||
* Parameters:
|
||||
* dest_addr - Destination address in Flash.
|
||||
* src - Pointer to the source buffer.
|
||||
* size - Length of data, in bytes.
|
||||
*
|
||||
* Returned Values:
|
||||
* Zero (OK) is returned or a negative error.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
IRAM_ATTR int spi_flash_write(uint32_t dest_addr,
|
||||
const void *buffer,
|
||||
uint32_t size)
|
||||
{
|
||||
int ret = OK;
|
||||
const uint8_t *tx_buf = (const uint8_t *)buffer;
|
||||
uint32_t tx_bytes = size;
|
||||
uint32_t tx_addr = dest_addr;
|
||||
|
||||
spiflash_start();
|
||||
|
||||
for (int i = 0; i < size; i += SPI_BUFFER_BYTES)
|
||||
{
|
||||
uint32_t spi_buffer[SPI_BUFFER_WORDS];
|
||||
uint32_t n = MIN(tx_bytes, SPI_BUFFER_BYTES);
|
||||
|
||||
memcpy(spi_buffer, tx_buf, n);
|
||||
|
||||
wait_flash_idle();
|
||||
enable_flash_write();
|
||||
|
||||
WRITE_DATA_TO_FLASH(tx_addr, spi_buffer, n);
|
||||
|
||||
tx_bytes -= n;
|
||||
tx_buf += n;
|
||||
tx_addr += n;
|
||||
}
|
||||
|
||||
wait_flash_idle();
|
||||
disable_flash_write();
|
||||
|
||||
spiflash_end();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: spi_flash_read
|
||||
*
|
||||
* Description:
|
||||
* Read data from Flash.
|
||||
*
|
||||
* Parameters:
|
||||
* src_addr - source address of the data in Flash.
|
||||
* dest - pointer to the destination buffer
|
||||
* size - length of data
|
||||
*
|
||||
* Returned Values:
|
||||
* Zero (OK) is returned or a negative error.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
IRAM_ATTR int spi_flash_read(uint32_t src_addr, void *dest, uint32_t size)
|
||||
{
|
||||
int ret = OK;
|
||||
uint8_t *rx_buf = (uint8_t *)dest;
|
||||
uint32_t rx_bytes = size;
|
||||
uint32_t rx_addr = src_addr;
|
||||
|
||||
spiflash_start();
|
||||
|
||||
for (uint32_t i = 0; i < size; i += SPI_BUFFER_BYTES)
|
||||
{
|
||||
uint32_t spi_buffer[SPI_BUFFER_WORDS];
|
||||
uint32_t n = MIN(rx_bytes, SPI_BUFFER_BYTES);
|
||||
|
||||
READ_DATA_FROM_FLASH(rx_addr, spi_buffer, n);
|
||||
|
||||
memcpy(rx_buf, spi_buffer, n);
|
||||
rx_bytes -= n;
|
||||
rx_buf += n;
|
||||
rx_addr += n;
|
||||
}
|
||||
|
||||
spiflash_end();
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif /* CONFIG_ESP32S3_SPI_FLASH_DONT_USE_ROM_CODE */
|
||||
|
||||
/****************************************************************************
|
||||
* Name: esp32s3_spiflash_init
|
||||
*
|
||||
|
||||
@ -36,6 +36,41 @@
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register Bits */
|
||||
|
||||
#define BIT31 0x80000000
|
||||
#define BIT30 0x40000000
|
||||
#define BIT29 0x20000000
|
||||
#define BIT28 0x10000000
|
||||
#define BIT27 0x08000000
|
||||
#define BIT26 0x04000000
|
||||
#define BIT25 0x02000000
|
||||
#define BIT24 0x01000000
|
||||
#define BIT23 0x00800000
|
||||
#define BIT22 0x00400000
|
||||
#define BIT21 0x00200000
|
||||
#define BIT20 0x00100000
|
||||
#define BIT19 0x00080000
|
||||
#define BIT18 0x00040000
|
||||
#define BIT17 0x00020000
|
||||
#define BIT16 0x00010000
|
||||
#define BIT15 0x00008000
|
||||
#define BIT14 0x00004000
|
||||
#define BIT13 0x00002000
|
||||
#define BIT12 0x00001000
|
||||
#define BIT11 0x00000800
|
||||
#define BIT10 0x00000400
|
||||
#define BIT9 0x00000200
|
||||
#define BIT8 0x00000100
|
||||
#define BIT7 0x00000080
|
||||
#define BIT6 0x00000040
|
||||
#define BIT5 0x00000020
|
||||
#define BIT4 0x00000010
|
||||
#define BIT3 0x00000008
|
||||
#define BIT2 0x00000004
|
||||
#define BIT1 0x00000002
|
||||
#define BIT0 0x00000001
|
||||
|
||||
#define PRO_CPU_NUM (0)
|
||||
#define APP_CPU_NUM (1)
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user