arch/arm/src/tiva: Flesh out a little more of the GPIO interrupt logic

arch/arm/src/tiva/cc13xx/cc13xx_gpioirq.c

@@ -90,20 +90,40 @@ static struct gpio_handler_s g_gpio_inthandler[TIVA_NIRQ_PINS];
 
 static int cc13xx_gpio_interrupt)(int irq, FAR void *context, FAR void *arg)
 {
+  uint32_t evflags;
+  uint32_t regval;
   unsigned int dio;
+  int irq;
+
+  /* Get pending events */
+
+  evflags = getreg32(TIVA_GPIO_EVFLAGS);
+
+  /* Clear pending events that will be processing here */
 #warning Missing logic
 
-  /* Clear pending interrupts */
+  /* Now process each pending DIO edge event */
 
-  /* Now process each pending interrupt */
+  for (dio = 0, irq = TIVA_IRQ_DIO_0;
+       dio < TIVA_NDIO && evflags != 0;
+       dio++, irq++)
+    {
+      uint32_t diomask = (1 << dio);
 
-  /* Call any handler registered for each pending DIO interrupt */
+      /* Is an event pending on this DIO? */
 
-  FAR struct gpio_handler_s *handler = &g_gpio_inthandler[dio];
+      if ((evflags & diomask) != 0)
+        {
+          /* Call any handler registered for each pending DIO interrupt */
 
-  gpioinfo("dio=%d isr=%p arg=%p\n", dio, handler->isr, handler->arg);
+          FAR struct gpio_handler_s *handler = &g_gpio_inthandler[dio];
 
-  handler->isr(irq, context, handler->arg);
+          gpioinfo("dio=%d isr=%p arg=%p\n", dio, handler->isr, handler->arg);
+          handler->isr(irq, context, handler->arg);
+
+          evflags &= ~diomask;
+        }
+    }
 
   return OK;
 }
@@ -209,10 +229,16 @@ int tiva_gpioirqattach(pinconfig_t pinconfig, xcpt_t isr, void *arg)
 
 void tiva_gpioirqenable(pinconfig_t pinconfig)
 {
+  uintptr_t regaddr;
   unsigned int dio;
+
+  /* Enable edge interrupt generation */
+
   dio = (pinconfig->gpio & GPIO_DIO_MASK) >> GPIO_DIO_SHIFT;
   DEBUGASSERT(dio < TIVA_NDIO);
-#warning Missing logic
+
+  regaddr = TIVA_IOC_IOCFG_OFFSET(dio);
+  modifyreg32(regaddr, 0, IOC_IOCFG_EDGE_IRQEN);
 }
 
 /****************************************************************************
@@ -225,10 +251,16 @@ void tiva_gpioirqenable(pinconfig_t pinconfig)
 
 void tiva_gpioirqdisable(pinconfig_t pinconfig)
 {
+  uintptr_t regaddr;
   unsigned int dio;
+
+  /* Disable edge interrupt generation */
+
   dio = (pinconfig->gpio & GPIO_DIO_MASK) >> GPIO_DIO_SHIFT;
   DEBUGASSERT(dio < TIVA_NDIO);
-#warning Missing logic
+
+  regaddr = TIVA_IOC_IOCFG_OFFSET(dio);
+  modifyreg32(regaddr, IOC_IOCFG_EDGE_IRQEN, 0);
 }
 
 /****************************************************************************
@@ -242,9 +274,13 @@ void tiva_gpioirqdisable(pinconfig_t pinconfig)
 void tiva_gpioirqclear(pinconfig_t pinconfig)
 {
   unsigned int dio;
+
+  /* Clear pending edge events */
+
   dio = (pinconfig->gpio & GPIO_DIO_MASK) >> GPIO_DIO_SHIFT;
   DEBUGASSERT(dio < TIVA_NDIO);
-#warning Missing logic
+
+  modifyreg32(TIVA_GPIO_EVFLAGS, (1 << dio), 0);
 }
 
 #endif /* CONFIG_TIVA_GPIO_IRQS */

arch/arm/src/tiva/common/tiva_lowputc.c

@@ -57,7 +57,8 @@
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
-/* Configuration **********************************************************/
+
+/* Configuration ************************************************************/
 
 /* Select UART parameters for the selected console */
 
@@ -158,42 +159,56 @@
 
 /* Calculate BAUD rate from the SYS clock:
  *
- * "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit
+ * "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer
- *  fractional part. The number formed by these two values is used by the baud-rate generator
+ *  and a 6-bit fractional part. The number formed by these two values is
- *  to determine the bit period. Having a fractional baud-rate divider allows the UART to
+ *  used by the baud-rate generator to determine the bit period. Having a
- *  generate all the standard baud rates.
+ *  fractional baud-rate divider allows the UART to generate all the
+ *  standard baud rates.
  *
- * "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD)
+ * "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor
- *  register ... and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate
+ *  (UARTIBRD) register ... and the 6-bit fractional part is loaded with the
- *  Divisor (UARTFBRD) register... The baud-rate divisor (BRD) has the following relationship
+ *  UART Fractional Baud-Rate Divisor (UARTFBRD) register... The baud-rate
- *  to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional
+ *  divisor (BRD) has the following relationship to the system clock (where
- *  part, separated by a decimal place.):
+ *  BRDI is the integer part of the BRD and BRDF is the fractional part,
+ *  separated by a decimal place.):
  *
  *    "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate)
  *
- * "where UARTSysClk is the system clock connected to the UART. The 6-bit fractional number
+ * "where UARTSysClk is the system clock connected to the UART. The 6-bit
- *  (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated
+ *  fractional number (that is to be loaded into the DIVFRAC bit field in
- *  by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5
+ *  the UARTFBRD register) can be calculated taking the fractional part of
- *  to account for rounding errors:
+ *  the baud-rate divisor, multiplying it by 64, and adding 0.5 to account
+ *  for rounding errors:
  *
  *    "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
  *
- * "The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred
+ * "The UART generates an internal baud-rate reference clock at 16x the
- *  to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is
+ *  baud-rate (referred to as Baud16). This reference clock is divided by 16
- *  used for error detection during receive operations.
+ *  to generate the transmit clock, and is used for error detection during
+ *  receive operations.
  *
- * "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the UARTIBRD and
+ * "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the
- *  UARTFBRD registers form an internal 30-bit register. This internal register is only
+ *  UARTIBRD and UARTFBRD registers form an internal 30-bit register.  This
- *  updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate
+ *  internal register is only updated when a write operation to UARTLCRH is
- *  divisor must be followed by a write to the UARTLCRH register for the changes to take effect. ..."
+ *  performed, so any changes to the baud-rate divisor must be followed by a
+ *  write to the UARTLCRH register for the changes to take effect. ..."
+ *
+ * Some parts support dividing done SYSCLK to generate a lower peripheral
+ * clock frequency.  Here we use some called PCLK_FREQUENCY which must be
+ * defined in the board.h header file.  Normally, PCLK_FREQUENCY is simply
+ * defined to by SYSCLK_FREQUENCY.
+ *
+ * TM4C129 supports an ALTCLOCK that may also be the UART source clock.  The
+ * default source for the ALTCLK is the 160MHz Precision Internal Oscillator
+ * (PIOSC).
  */
 
 #define TIVA_BRDDEN     (16 * TIVA_CONSOLE_BAUD)
-#define TIVA_BRDI       (SYSCLK_FREQUENCY / TIVA_BRDDEN)
+#define TIVA_BRDI       (PCLK_FREQUENCY / TIVA_BRDDEN)
-#define TIVA_REMAINDER  (SYSCLK_FREQUENCY - TIVA_BRDDEN * TIVA_BRDI)
+#define TIVA_REMAINDER  (PCLK_FREQUENCY - TIVA_BRDDEN * TIVA_BRDI)
 #define TIVA_DIVFRAC    ((TIVA_REMAINDER * 64 + (TIVA_BRDDEN/2)) / TIVA_BRDDEN)
 
-/* For example: TIVA_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000:
+/* For example: TIVA_CONSOLE_BAUD = 115,200, PCLK_FREQUENCY = 50,000,000:
  *
  * TIVA_BRDDEN    = (16 * 115,200)                           = 1,843,200
  * TIVA_BRDI      = 50,000,000 / 1,843,200                   = 27

configs/dk-tm4c129x/include/board.h

@@ -100,6 +100,13 @@
 #define BOARD_PLL_SYSDIV     4         /* Sysclk = Fvco / 4 = 120MHz */
 #define SYSCLK_FREQUENCY     120000000 /* Resulting SysClk frequency */
 
+/* Peripheral Clock (PCLK)
+ *
+ * Same frequency as the SYSCLK
+ */
+
+#define PCLK_FREQUENCY       SYSCLK_FREQUENCY
+
 /* Alternate Clock (ALTCLK)
  *
  * The ALTCLK provides a clock source of numerous frequencies to the general-purpose

configs/eagle100/include/board.h

@@ -66,6 +66,13 @@
 #define TIVA_SYSDIV          4
 #define SYSCLK_FREQUENCY     50000000  /* 50MHz */
 
+/* Peripheral Clock (PCLK)
+ *
+ * Same frequency as the SYSCLK
+ */
+
+#define PCLK_FREQUENCY       SYSCLK_FREQUENCY
+
 /* Other RCC settings:
  *
  * - Main and internal oscillators enabled.

configs/ekk-lm3s9b96/include/board.h

@@ -67,6 +67,13 @@
 #define TIVA_SYSDIV          4
 #define SYSCLK_FREQUENCY     50000000  /* 50MHz */
 
+/* Peripheral Clock (PCLK)
+ *
+ * Same frequency as the SYSCLK
+ */
+
+#define PCLK_FREQUENCY       SYSCLK_FREQUENCY
+
 /* Other RCC settings:
  *
  * - Main and internal oscillators enabled.

configs/launchxl-cc1312r1/include/board.h

@@ -52,6 +52,13 @@
 
 #define SYSCLK_FREQUENCY      48000000
 
+/* Peripheral Clock (PCLK)
+ *
+ * Same frequency as the SYSCLK
+ */
+
+#define PCLK_FREQUENCY       SYSCLK_FREQUENCY
+
 /* LED definitions **********************************************************/
 
 /* The LaunchXL-cc1312R1 and two LEDs controlled by software: DIO7_GLED (CR1)

configs/lm3s6432-s2e/include/board.h

@@ -66,6 +66,13 @@
 #define TIVA_SYSDIV          4
 #define SYSCLK_FREQUENCY     50000000  /* 50MHz */
 
+/* Peripheral Clock (PCLK)
+ *
+ * Same frequency as the SYSCLK
+ */
+
+#define PCLK_FREQUENCY       SYSCLK_FREQUENCY
+
 /* Other RCC settings:
  *
  * - Main and internal oscillators enabled.

configs/lm3s6965-ek/include/board.h

@@ -66,6 +66,13 @@
 #define TIVA_SYSDIV          4
 #define SYSCLK_FREQUENCY     50000000  /* 50MHz */
 
+/* Peripheral Clock (PCLK)
+ *
+ * Same frequency as the SYSCLK
+ */
+
+#define PCLK_FREQUENCY       SYSCLK_FREQUENCY
+
 /* Other RCC settings:
  *
  * - Main and internal oscillators enabled.

configs/lm3s8962-ek/include/board.h

@@ -66,6 +66,13 @@
 #define TIVA_SYSDIV          4
 #define SYSCLK_FREQUENCY     50000000  /* 50MHz */
 
+/* Peripheral Clock (PCLK)
+ *
+ * Same frequency as the SYSCLK
+ */
+
+#define PCLK_FREQUENCY       SYSCLK_FREQUENCY
+
 /* Other RCC settings:
  *
  * - Main and internal oscillators enabled.

configs/lm4f120-launchpad/include/board.h

@@ -68,6 +68,13 @@
 #define TIVA_SYSDIV          5
 #define SYSCLK_FREQUENCY     80000000  /* 80MHz */
 
+/* Peripheral Clock (PCLK)
+ *
+ * Same frequency as the SYSCLK
+ */
+
+#define PCLK_FREQUENCY       SYSCLK_FREQUENCY
+
 /* Other RCC settings:
  *
  * - Main and internal oscillators enabled.

configs/tm4c123g-launchpad/include/board.h

@@ -68,6 +68,13 @@
 #define TIVA_SYSDIV          5
 #define SYSCLK_FREQUENCY     80000000  /* 80MHz */
 
+/* Peripheral Clock (PCLK)
+ *
+ * Same frequency as the SYSCLK
+ */
+
+#define PCLK_FREQUENCY       SYSCLK_FREQUENCY
+
 /* Other RCC settings:
  *
  * - Main and internal oscillators enabled.

configs/tm4c1294-launchpad/include/board.h

@@ -100,6 +100,13 @@
 #define BOARD_PLL_SYSDIV     4         /* Sysclk = Fvco / 4 = 120MHz */
 #define SYSCLK_FREQUENCY     120000000 /* Resulting SysClk frequency */
 
+/* Peripheral Clock (PCLK)
+ *
+ * Same frequency as the SYSCLK
+ */
+
+#define PCLK_FREQUENCY       SYSCLK_FREQUENCY
+
 /* Alternate Clock (ALTCLK)
  *
  * The ALTCLK provides a clock source of numerous frequencies to the general-purpose