Add support for hpm6360evk
This commit is contained in:
freakishness
Xiang Xiao
parent
02b418a7ea
commit
b283e39eb5
@ -238,6 +238,17 @@ config ARCH_CHIP_QEMU_RV
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---help---
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QEMU Generic RV32/RV64 processor
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config ARCH_CHIP_HPM6000
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bool "Hpmicro HPM6000"
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select ARCH_RV32
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_C
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select ONESHOT
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select ALARM_ARCH
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---help---
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Hpmicro HPM6000 processor (D45 RISC-V Core with MAC extensions).
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config ARCH_CHIP_HPM6750
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bool "Hpmicro HPM6750"
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select ARCH_RV32
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@ -399,6 +410,7 @@ config ARCH_CHIP
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default "mpfs" if ARCH_CHIP_MPFS
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default "rv32m1" if ARCH_CHIP_RV32M1
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default "qemu-rv" if ARCH_CHIP_QEMU_RV
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default "hpm6000" if ARCH_CHIP_HPM6000
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default "hpm6750" if ARCH_CHIP_HPM6750
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default "jh7110" if ARCH_CHIP_JH7110
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default "bl808" if ARCH_CHIP_BL808
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@ -566,6 +578,9 @@ endif
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if ARCH_CHIP_QEMU_RV
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source "arch/risc-v/src/qemu-rv/Kconfig"
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endif
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if ARCH_CHIP_HPM6000
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source "arch/risc-v/src/hpm6000/Kconfig"
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endif
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if ARCH_CHIP_HPM6750
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source "arch/risc-v/src/hpm6750/Kconfig"
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endif
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24
arch/risc-v/include/hpm6000/chip.h
Normal file
24
arch/risc-v/include/hpm6000/chip.h
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@ -0,0 +1,24 @@
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/****************************************************************************
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* arch/risc-v/include/hpm6000/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_INCLUDE_HPM6000_CHIP_H
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#define __ARCH_RISCV_INCLUDE_HPM6000_CHIP_H
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#endif /* __ARCH_RISCV_INCLUDE_HPM6000_CHIP_H */
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119
arch/risc-v/include/hpm6000/hpm_irq.h
Normal file
119
arch/risc-v/include/hpm6000/hpm_irq.h
Normal file
@ -0,0 +1,119 @@
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/****************************************************************************
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* arch/risc-v/include/hpm6000/hpm_irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_INCLUDE_HPM6000_HPM_IRQ_H
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#define __ARCH_RISCV_INCLUDE_HPM6000_HPM_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* Map RISC-V exception code to NuttX IRQ */
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#define HPM_IRQ_PERI_START (RISCV_IRQ_ASYNC + 20)
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/* Machine Global External Interrupt */
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#define HPM_IRQ_GPIO0_A (HPM_IRQ_PERI_START + 1)
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#define HPM_IRQ_GPIO0_B (HPM_IRQ_PERI_START + 2)
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#define HPM_IRQ_GPIO0_C (HPM_IRQ_PERI_START + 3)
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#define HPM_IRQ_GPIO0_D (HPM_IRQ_PERI_START + 4)
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#define HPM_IRQ_GPIO0_X (HPM_IRQ_PERI_START + 5)
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#define HPM_IRQ_GPIO0_Y (HPM_IRQ_PERI_START + 6)
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#define HPM_IRQ_GPIO0_Z (HPM_IRQ_PERI_START + 7)
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#define HPM_IRQ_ADC0 (HPM_IRQ_PERI_START + 8)
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#define HPM_IRQ_ADC1 (HPM_IRQ_PERI_START + 9)
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#define HPM_IRQ_ADC2 (HPM_IRQ_PERI_START + 10)
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#define HPM_IRQ_DAC (HPM_IRQ_PERI_START + 11)
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#define HPM_IRQ_ACMP0 (HPM_IRQ_PERI_START + 12)
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#define HPM_IRQ_ACMP1 (HPM_IRQ_PERI_START + 13)
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#define HPM_IRQ_SPI0 (HPM_IRQ_PERI_START + 14)
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#define HPM_IRQ_SPI1 (HPM_IRQ_PERI_START + 15)
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#define HPM_IRQ_SPI2 (HPM_IRQ_PERI_START + 16)
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#define HPM_IRQ_SPI3 (HPM_IRQ_PERI_START + 17)
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#define HPM_IRQ_UART0 (HPM_IRQ_PERI_START + 18)
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#define HPM_IRQ_UART1 (HPM_IRQ_PERI_START + 19)
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#define HPM_IRQ_UART2 (HPM_IRQ_PERI_START + 20)
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#define HPM_IRQ_UART3 (HPM_IRQ_PERI_START + 21)
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#define HPM_IRQ_UART4 (HPM_IRQ_PERI_START + 22)
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#define HPM_IRQ_UART5 (HPM_IRQ_PERI_START + 23)
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#define HPM_IRQ_UART6 (HPM_IRQ_PERI_START + 24)
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#define HPM_IRQ_UART7 (HPM_IRQ_PERI_START + 25)
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#define HPM_IRQ_CAN0 (HPM_IRQ_PERI_START + 26)
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#define HPM_IRQ_CAN1 (HPM_IRQ_PERI_START + 27)
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#define HPM_IRQ_PTPC (HPM_IRQ_PERI_START + 28)
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#define HPM_IRQ_WDG0 (HPM_IRQ_PERI_START + 29)
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#define HPM_IRQ_WDG1 (HPM_IRQ_PERI_START + 30)
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#define HPM_IRQ_TSNS (HPM_IRQ_PERI_START + 31)
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#define HPM_IRQ_MBX0A (HPM_IRQ_PERI_START + 32)
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#define HPM_IRQ_MBX0B (HPM_IRQ_PERI_START + 33)
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#define HPM_IRQ_GPTMR0 (HPM_IRQ_PERI_START + 34)
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#define HPM_IRQ_GPTMR1 (HPM_IRQ_PERI_START + 35)
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#define HPM_IRQ_GPTMR2 (HPM_IRQ_PERI_START + 36)
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#define HPM_IRQ_GPTMR3 (HPM_IRQ_PERI_START + 37)
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#define HPM_IRQ_I2C0 (HPM_IRQ_PERI_START + 38)
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#define HPM_IRQ_I2C1 (HPM_IRQ_PERI_START + 39)
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#define HPM_IRQ_I2C2 (HPM_IRQ_PERI_START + 40)
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#define HPM_IRQ_I2C3 (HPM_IRQ_PERI_START + 41)
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#define HPM_IRQ_PWM0 (HPM_IRQ_PERI_START + 42)
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#define HPM_IRQ_HALL0 (HPM_IRQ_PERI_START + 43)
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#define HPM_IRQ_QEI0 (HPM_IRQ_PERI_START + 44)
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#define HPM_IRQ_PWM1 (HPM_IRQ_PERI_START + 45)
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#define HPM_IRQ_HALL1 (HPM_IRQ_PERI_START + 46)
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#define HPM_IRQ_QEI1 (HPM_IRQ_PERI_START + 47)
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#define HPM_IRQ_SDP (HPM_IRQ_PERI_START + 48)
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#define HPM_IRQ_XPI0 (HPM_IRQ_PERI_START + 49)
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#define HPM_IRQ_XPI1 (HPM_IRQ_PERI_START + 50)
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#define HPM_IRQ_XDMA (HPM_IRQ_PERI_START + 51)
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#define HPM_IRQ_HDMA (HPM_IRQ_PERI_START + 52)
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#define HPM_IRQ_FEMC (HPM_IRQ_PERI_START + 53)
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#define HPM_IRQ_RNG (HPM_IRQ_PERI_START + 54)
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#define HPM_IRQ_I2S0 (HPM_IRQ_PERI_START + 55)
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#define HPM_IRQ_I2S1 (HPM_IRQ_PERI_START + 56)
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#define HPM_IRQ_DAO (HPM_IRQ_PERI_START + 57)
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#define HPM_IRQ_PDM (HPM_IRQ_PERI_START + 58)
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#define HPM_IRQ_EFA (HPM_IRQ_PERI_START + 59)
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#define HPM_IRQ_NTMR0 (HPM_IRQ_PERI_START + 60)
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#define HPM_IRQ_USB0 (HPM_IRQ_PERI_START + 61)
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#define HPM_IRQ_ENET0 (HPM_IRQ_PERI_START + 62)
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#define HPM_IRQ_SDXC0 (HPM_IRQ_PERI_START + 63)
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#define HPM_IRQ_PSEC (HPM_IRQ_PERI_START + 64)
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#define HPM_IRQ_PGPIO (HPM_IRQ_PERI_START + 65)
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#define HPM_IRQ_PWDG (HPM_IRQ_PERI_START + 66)
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#define HPM_IRQ_PTMR (HPM_IRQ_PERI_START + 67)
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#define HPM_IRQ_PUART (HPM_IRQ_PERI_START + 68)
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#define HPM_IRQ_FUSE (HPM_IRQ_PERI_START + 69)
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#define HPM_IRQ_SECMON (HPM_IRQ_PERI_START + 70)
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#define HPM_IRQ_RTC (HPM_IRQ_PERI_START + 71)
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#define HPM_IRQ_BUTN (HPM_IRQ_PERI_START + 72)
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#define HPM_IRQ_BGPIO (HPM_IRQ_PERI_START + 73)
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#define HPM_IRQ_BVIO (HPM_IRQ_PERI_START + 74)
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#define HPM_IRQ_BROWNOUT (HPM_IRQ_PERI_START + 75)
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#define HPM_IRQ_SYSCTL (HPM_IRQ_PERI_START + 76)
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/* Total number of IRQs */
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#define NR_IRQS (HPM_IRQ_PERI_START + 76)
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#endif /* __ARCH_RISCV_INCLUDE_HPM6000_HPM_IRQ_H */
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34
arch/risc-v/include/hpm6000/irq.h
Normal file
34
arch/risc-v/include/hpm6000/irq.h
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@ -0,0 +1,34 @@
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/****************************************************************************
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* arch/risc-v/include/hpm6000/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_INCLUDE_HPM6000_IRQ_H
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#define __ARCH_RISCV_INCLUDE_HPM6000_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "hpm_irq.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#endif /* __ARCH_RISCV_INCLUDE_HPM6000_IRQ_H */
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36
arch/risc-v/src/hpm6000/CMakeLists.txt
Normal file
36
arch/risc-v/src/hpm6000/CMakeLists.txt
Normal file
@ -0,0 +1,36 @@
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# ##############################################################################
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# arch/arm/src/qemu-rv/CMakeLists.txt
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#
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# Licensed to the Apache Software Foundation (ASF) under one or more contributor
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# license agreements. See the NOTICE file distributed with this work for
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# additional information regarding copyright ownership. The ASF licenses this
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# file to you under the Apache License, Version 2.0 (the "License"); you may not
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# use this file except in compliance with the License. You may obtain a copy of
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# the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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# License for the specific language governing permissions and limitations under
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# the License.
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#
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# ##############################################################################
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set(SRCS hpm_head.S)
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list(
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APPEND
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SRCS
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hpm_clockconfig.c
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hpm_gpio.c
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hpm_ioc.c
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hpm_irq.c
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hpm_irq_dispatch.c
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hpm_lowputc.c
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hpm_serial.c
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hpm_start.c
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hpm_timerisr.c)
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target_sources(arch PRIVATE ${SRCS})
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116
arch/risc-v/src/hpm6000/Kconfig
Normal file
116
arch/risc-v/src/hpm6000/Kconfig
Normal file
@ -0,0 +1,116 @@
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#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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comment "HPM6000 Configuration Options"
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choice
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prompt "HPM6000 Chip Selection"
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default ARCH_CHIP_HPM6360IPA
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depends on ARCH_CHIP_HPM6000
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config ARCH_CHIP_HPM6360IPA
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bool "HPM6360IPA"
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select ARCH_FAMILY_HPM6360
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endchoice # HPM6000 Chip Selection
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# HPM6000 Families
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config ARCH_FAMILY_HPM6360
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bool
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default n
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select ARCH_FAMILY_HPM6300
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# Peripheral support
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menu "HPM6000 Peripheral Selection"
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config HPM_ENET
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bool "Ethernet"
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default n
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menu "Watchdog"
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config HPM_WDOG0
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bool "WathDog"
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default n
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config HPM_WDOG1
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bool "WathDog"
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default n
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config HPM_WDOG2
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bool "WathDog"
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default n
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endmenu # Watchdog
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menu "UART Peripherals"
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config HPM_UART0
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bool "UART0"
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default n
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select UART0_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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select HPM_HAVE_UART
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config HPM_UART1
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bool "UART1"
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default n
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select UART1_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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select HPM_HAVE_UART
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config HPM_UART2
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bool "UART2"
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default n
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select UART2_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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select HPM_HAVE_UART
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config HPM_UART3
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bool "UART3"
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default n
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select UART3_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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select HPM_HAVE_UART
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config HPM_UART4
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bool "UART4"
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default n
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select UART4_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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select HPM_HAVE_UART
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config HPM_UART5
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bool "UART5"
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default n
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select UART5_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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select HPM_HAVE_UART
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config HPM_UART6
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bool "UART6"
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default n
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select UART6_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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select HPM_HAVE_UART
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config HPM_UART7
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bool "UART7"
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default n
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select UART7_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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select HPM_HAVE_UART
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config HPM_PUART
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bool "PUART"
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default n
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select PUART_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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select HPM_HAVE_UART
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endmenu # UART Peripherals
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endmenu # HPM6000 Peripheral Selection
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32
arch/risc-v/src/hpm6000/Make.defs
Normal file
32
arch/risc-v/src/hpm6000/Make.defs
Normal file
@ -0,0 +1,32 @@
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############################################################################
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# arch/risc-v/src/hpm6000/Make.defs
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#
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# Licensed to the Apache Software Foundation (ASF) under one or more
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# contributor license agreements. See the NOTICE file distributed with
|
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# this work for additional information regarding copyright ownership. The
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# ASF licenses this file to you under the Apache License, Version 2.0 (the
|
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# "License"); you may not use this file except in compliance with the
|
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# License. You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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# License for the specific language governing permissions and limitations
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# under the License.
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#
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############################################################################
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include common/Make.defs
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# Specify our HEAD assembly file. This will be linked as
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# the first object file, so it will appear at address 0
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HEAD_ASRC = hpm_head.S
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# Specify our C code within this directory to be included
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CHIP_CSRCS = hpm_clockconfig.c
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CHIP_CSRCS += hpm_irq.c hpm_irq_dispatch.c
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CHIP_CSRCS += hpm_lowputc.c hpm_serial.c
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CHIP_CSRCS += hpm_start.c hpm_timerisr.c
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CHIP_CSRCS += hpm_ioc.c hpm_gpio.c
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32
arch/risc-v/src/hpm6000/chip.h
Normal file
32
arch/risc-v/src/hpm6000/chip.h
Normal file
@ -0,0 +1,32 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/chip.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_CHIP_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_CHIP_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "hpm_memorymap.h"
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_CHIP_H */
|
||||
489
arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_gpio.h
Normal file
489
arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_gpio.h
Normal file
@ -0,0 +1,489 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_gpio.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_GPIO_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_GPIO_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "hardware/hpm_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
#define HPM_GPIOA_OFFSET 0x0000 /* GPIOA Register Offset */
|
||||
#define HPM_GPIOB_OFFSET 0x0010 /* GPIOB Register Offset */
|
||||
#define HPM_GPIOC_OFFSET 0x0020 /* GPIOC Register Offset */
|
||||
#define HPM_GPIOX_OFFSET 0x00d0 /* GPIOX Register Offset */
|
||||
#define HPM_GPIOY_OFFSET 0x00e0 /* GPIOY Register Offset */
|
||||
#define HPM_GPIOZ_OFFSET 0x00f0 /* GPIOZ Register Offset */
|
||||
|
||||
#define HPM_GPIO_VAL_OFFSET 0x0000 /* GPIO Value Register Offset */
|
||||
#define HPM_GPIO_SET_OFFSET 0x0004 /* GPIO Set Register Offset */
|
||||
#define HPM_GPIO_CLR_OFFSET 0x0008 /* GPIO Clear Register Offset */
|
||||
#define HPM_GPIO_TGL_OFFSET 0x000c /* GPIO Toggle Register Offset */
|
||||
|
||||
#define HPM_GPIO_DI_OFFSET 0x0000 /* GPIO Data Input Register Offset */
|
||||
#define HPM_GPIO_DO_OFFSET 0x0100 /* GPIO Data Output Register Offset */
|
||||
#define HPM_GPIO_OE_OFFSET 0x0200 /* GPIO Output Enable Register Offset */
|
||||
#define HPM_GPIO_IF_OFFSET 0x0300 /* GPIO Interrupt Flag Register Offset */
|
||||
#define HPM_GPIO_IE_OFFSET 0x0400 /* GPIO Interrupt Enable Register Offset */
|
||||
#define HPM_GPIO_PL_OFFSET 0x0500 /* GPIO Interrupt Edge Register Offset */
|
||||
#define HPM_GPIO_TP_OFFSET 0x0600 /* GPIO Interrupt Type Offset */
|
||||
#define HPM_GPIO_AS_OFFSET 0x0700 /* GPIO Async Interrupt Offset */
|
||||
|
||||
#define HPM_GPIO_DI_VAL_OFFSET (HPM_GPIO_DI_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIO_DI_SET_OFFSET (HPM_GPIO_DI_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIO_DI_CLR_OFFSET (HPM_GPIO_DI_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIO_DI_TGL_OFFSET (HPM_GPIO_DI_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIO_DO_VAL_OFFSET (HPM_GPIO_DO_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIO_DO_SET_OFFSET (HPM_GPIO_DO_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIO_DO_CLR_OFFSET (HPM_GPIO_DO_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIO_DO_TGL_OFFSET (HPM_GPIO_DO_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIO_OE_VAL_OFFSET (HPM_GPIO_OE_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIO_OE_SET_OFFSET (HPM_GPIO_OE_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIO_OE_CLR_OFFSET (HPM_GPIO_OE_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIO_OE_TGL_OFFSET (HPM_GPIO_OE_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIO_IF_VAL_OFFSET (HPM_GPIO_IF_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIO_IF_SET_OFFSET (HPM_GPIO_IF_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIO_IF_CLR_OFFSET (HPM_GPIO_IF_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIO_IF_TGL_OFFSET (HPM_GPIO_IF_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIO_IE_VAL_OFFSET (HPM_GPIO_IE_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIO_IE_SET_OFFSET (HPM_GPIO_IE_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIO_IE_CLR_OFFSET (HPM_GPIO_IE_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIO_IE_TGL_OFFSET (HPM_GPIO_IE_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIO_PL_VAL_OFFSET (HPM_GPIO_PL_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIO_PL_SET_OFFSET (HPM_GPIO_PL_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIO_PL_CLR_OFFSET (HPM_GPIO_PL_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIO_PL_TGL_OFFSET (HPM_GPIO_PL_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIO_TP_VAL_OFFSET (HPM_GPIO_TP_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIO_TP_SET_OFFSET (HPM_GPIO_TP_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIO_TP_CLR_OFFSET (HPM_GPIO_TP_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIO_TP_TGL_OFFSET (HPM_GPIO_TP_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIO_AS_VAL_OFFSET (HPM_GPIO_AS_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIO_AS_SET_OFFSET (HPM_GPIO_AS_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIO_AS_CLR_OFFSET (HPM_GPIO_AS_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIO_AS_TGL_OFFSET (HPM_GPIO_AS_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
|
||||
#define HPM_GPIOA_DI_VAL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOA_DI_SET_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOA_DI_CLR_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOA_DI_TGL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOA_DO_VAL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOA_DO_SET_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOA_DO_CLR_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOA_DO_TGL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOA_OE_VAL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOA_OE_SET_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOA_OE_CLR_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOA_OE_TGL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOA_IF_VAL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOA_IF_SET_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOA_IF_CLR_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOA_IF_TGL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOA_IE_VAL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOA_IE_SET_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOA_IE_CLR_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOA_IE_TGL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOA_PL_VAL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOA_PL_SET_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOA_PL_CLR_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOA_PL_TGL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOA_TP_VAL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOA_TP_SET_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOA_TP_CLR_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOA_TP_TGL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOA_AS_VAL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOA_AS_SET_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOA_AS_CLR_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOA_AS_TGL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
|
||||
#define HPM_GPIOB_DI_VAL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOB_DI_SET_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOB_DI_CLR_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOB_DI_TGL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOB_DO_VAL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOB_DO_SET_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOB_DO_CLR_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOB_DO_TGL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOB_OE_VAL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOB_OE_SET_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOB_OE_CLR_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOB_OE_TGL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOB_IF_VAL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOB_IF_SET_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOB_IF_CLR_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOB_IF_TGL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOB_IE_VAL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOB_IE_SET_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOB_IE_CLR_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOB_IE_TGL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOB_PL_VAL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOB_PL_SET_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOB_PL_CLR_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOB_PL_TGL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOB_TP_VAL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOB_TP_SET_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOB_TP_CLR_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOB_TP_TGL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOB_AS_VAL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOB_AS_SET_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOB_AS_CLR_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOB_AS_TGL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
|
||||
#define HPM_GPIOC_DI_VAL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOC_DI_SET_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOC_DI_CLR_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOC_DI_TGL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOC_DO_VAL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOC_DO_SET_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOC_DO_CLR_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOC_DO_TGL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOC_OE_VAL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOC_OE_SET_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOC_OE_CLR_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOC_OE_TGL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOC_IF_VAL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOC_IF_SET_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOC_IF_CLR_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOC_IF_TGL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOC_IE_VAL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOC_IE_SET_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOC_IE_CLR_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOC_IE_TGL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOC_PL_VAL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOC_PL_SET_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOC_PL_CLR_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOC_PL_TGL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOC_TP_VAL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOC_TP_SET_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOC_TP_CLR_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOC_TP_TGL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOC_AS_VAL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOC_AS_SET_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOC_AS_CLR_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOC_AS_TGL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
|
||||
#define HPM_GPIOX_DI_VAL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOX_DI_SET_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOX_DI_CLR_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOX_DI_TGL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOX_DO_VAL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOX_DO_SET_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOX_DO_CLR_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOX_DO_TGL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOX_OE_VAL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOX_OE_SET_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOX_OE_CLR_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOX_OE_TGL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOX_IF_VAL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOX_IF_SET_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOX_IF_CLR_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOX_IF_TGL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOX_IE_VAL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOX_IE_SET_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOX_IE_CLR_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOX_IE_TGL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOX_PL_VAL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOX_PL_SET_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOX_PL_CLR_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOX_PL_TGL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOX_TP_VAL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOX_TP_SET_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOX_TP_CLR_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOX_TP_TGL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOX_AS_VAL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOX_AS_SET_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOX_AS_CLR_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOX_AS_TGL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
|
||||
#define HPM_GPIOY_DI_VAL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOY_DI_SET_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOY_DI_CLR_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOY_DI_TGL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOY_DO_VAL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOY_DO_SET_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOY_DO_CLR_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOY_DO_TGL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOY_OE_VAL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOY_OE_SET_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOY_OE_CLR_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOY_OE_TGL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOY_IF_VAL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOY_IF_SET_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOY_IF_CLR_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOY_IF_TGL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOY_IE_VAL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOY_IE_SET_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOY_IE_CLR_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOY_IE_TGL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOY_PL_VAL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOY_PL_SET_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOY_PL_CLR_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOY_PL_TGL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOY_TP_VAL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOY_TP_SET_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOY_TP_CLR_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOY_TP_TGL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOY_AS_VAL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOY_AS_SET_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOY_AS_CLR_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOY_AS_TGL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
|
||||
#define HPM_GPIOZ_DI_VAL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOZ_DI_SET_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOZ_DI_CLR_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOZ_DI_TGL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOZ_DO_VAL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOZ_DO_SET_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOZ_DO_CLR_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOZ_DO_TGL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOZ_OE_VAL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOZ_OE_SET_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOZ_OE_CLR_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOZ_OE_TGL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOZ_IF_VAL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOZ_IF_SET_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOZ_IF_CLR_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOZ_IF_TGL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOZ_IE_VAL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOZ_IE_SET_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOZ_IE_CLR_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOZ_IE_TGL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOZ_PL_VAL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOZ_PL_SET_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOZ_PL_CLR_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOZ_PL_TGL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOZ_TP_VAL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOZ_TP_SET_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOZ_TP_CLR_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOZ_TP_TGL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
#define HPM_GPIOZ_AS_VAL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_VAL_OFFSET)
|
||||
#define HPM_GPIOZ_AS_SET_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_SET_OFFSET)
|
||||
#define HPM_GPIOZ_AS_CLR_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_CLR_OFFSET)
|
||||
#define HPM_GPIOZ_AS_TGL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_TGL_OFFSET)
|
||||
|
||||
/* Register addresses *******************************************************/
|
||||
|
||||
#define HPM_GPIOA_DI_VAL (HPM_GPIO0_BASE + HPM_GPIOA_DI_VAL_OFFSET)
|
||||
#define HPM_GPIOA_DI_SET (HPM_GPIO0_BASE + HPM_GPIOA_DI_SET_OFFSET)
|
||||
#define HPM_GPIOA_DI_CLR (HPM_GPIO0_BASE + HPM_GPIOA_DI_CLR_OFFSET)
|
||||
#define HPM_GPIOA_DI_TGL (HPM_GPIO0_BASE + HPM_GPIOA_DI_TGL_OFFSET)
|
||||
#define HPM_GPIOA_DO_VAL (HPM_GPIO0_BASE + HPM_GPIOA_DO_VAL_OFFSET)
|
||||
#define HPM_GPIOA_DO_SET (HPM_GPIO0_BASE + HPM_GPIOA_DO_SET_OFFSET)
|
||||
#define HPM_GPIOA_DO_CLR (HPM_GPIO0_BASE + HPM_GPIOA_DO_CLR_OFFSET)
|
||||
#define HPM_GPIOA_DO_TGL (HPM_GPIO0_BASE + HPM_GPIOA_DO_TGL_OFFSET)
|
||||
#define HPM_GPIOA_OE_VAL (HPM_GPIO0_BASE + HPM_GPIOA_OE_VAL_OFFSET)
|
||||
#define HPM_GPIOA_OE_SET (HPM_GPIO0_BASE + HPM_GPIOA_OE_SET_OFFSET)
|
||||
#define HPM_GPIOA_OE_CLR (HPM_GPIO0_BASE + HPM_GPIOA_OE_CLR_OFFSET)
|
||||
#define HPM_GPIOA_OE_TGL (HPM_GPIO0_BASE + HPM_GPIOA_OE_TGL_OFFSET)
|
||||
#define HPM_GPIOA_IF_VAL (HPM_GPIO0_BASE + HPM_GPIOA_IF_VAL_OFFSET)
|
||||
#define HPM_GPIOA_IF_SET (HPM_GPIO0_BASE + HPM_GPIOA_IF_SET_OFFSET)
|
||||
#define HPM_GPIOA_IF_CLR (HPM_GPIO0_BASE + HPM_GPIOA_IF_CLR_OFFSET)
|
||||
#define HPM_GPIOA_IF_TGL (HPM_GPIO0_BASE + HPM_GPIOA_IF_TGL_OFFSET)
|
||||
#define HPM_GPIOA_IE_VAL (HPM_GPIO0_BASE + HPM_GPIOA_IE_VAL_OFFSET)
|
||||
#define HPM_GPIOA_IE_SET (HPM_GPIO0_BASE + HPM_GPIOA_IE_SET_OFFSET)
|
||||
#define HPM_GPIOA_IE_CLR (HPM_GPIO0_BASE + HPM_GPIOA_IE_CLR_OFFSET)
|
||||
#define HPM_GPIOA_IE_TGL (HPM_GPIO0_BASE + HPM_GPIOA_IE_TGL_OFFSET)
|
||||
#define HPM_GPIOA_PL_VAL (HPM_GPIO0_BASE + HPM_GPIOA_PL_VAL_OFFSET)
|
||||
#define HPM_GPIOA_PL_SET (HPM_GPIO0_BASE + HPM_GPIOA_PL_SET_OFFSET)
|
||||
#define HPM_GPIOA_PL_CLR (HPM_GPIO0_BASE + HPM_GPIOA_PL_CLR_OFFSET)
|
||||
#define HPM_GPIOA_PL_TGL (HPM_GPIO0_BASE + HPM_GPIOA_PL_TGL_OFFSET)
|
||||
#define HPM_GPIOA_TP_VAL (HPM_GPIO0_BASE + HPM_GPIOA_TP_VAL_OFFSET)
|
||||
#define HPM_GPIOA_TP_SET (HPM_GPIO0_BASE + HPM_GPIOA_TP_SET_OFFSET)
|
||||
#define HPM_GPIOA_TP_CLR (HPM_GPIO0_BASE + HPM_GPIOA_TP_CLR_OFFSET)
|
||||
#define HPM_GPIOA_TP_TGL (HPM_GPIO0_BASE + HPM_GPIOA_TP_TGL_OFFSET)
|
||||
#define HPM_GPIOA_AS_VAL (HPM_GPIO0_BASE + HPM_GPIOA_AS_VAL_OFFSET)
|
||||
#define HPM_GPIOA_AS_SET (HPM_GPIO0_BASE + HPM_GPIOA_AS_SET_OFFSET)
|
||||
#define HPM_GPIOA_AS_CLR (HPM_GPIO0_BASE + HPM_GPIOA_AS_CLR_OFFSET)
|
||||
#define HPM_GPIOA_AS_TGL (HPM_GPIO0_BASE + HPM_GPIOA_AS_TGL_OFFSET)
|
||||
|
||||
#define HPM_GPIOB_DI_VAL (HPM_GPIO0_BASE + HPM_GPIOB_DI_VAL_OFFSET)
|
||||
#define HPM_GPIOB_DI_SET (HPM_GPIO0_BASE + HPM_GPIOB_DI_SET_OFFSET)
|
||||
#define HPM_GPIOB_DI_CLR (HPM_GPIO0_BASE + HPM_GPIOB_DI_CLR_OFFSET)
|
||||
#define HPM_GPIOB_DI_TGL (HPM_GPIO0_BASE + HPM_GPIOB_DI_TGL_OFFSET)
|
||||
#define HPM_GPIOB_DO_VAL (HPM_GPIO0_BASE + HPM_GPIOB_DO_VAL_OFFSET)
|
||||
#define HPM_GPIOB_DO_SET (HPM_GPIO0_BASE + HPM_GPIOB_DO_SET_OFFSET)
|
||||
#define HPM_GPIOB_DO_CLR (HPM_GPIO0_BASE + HPM_GPIOB_DO_CLR_OFFSET)
|
||||
#define HPM_GPIOB_DO_TGL (HPM_GPIO0_BASE + HPM_GPIOB_DO_TGL_OFFSET)
|
||||
#define HPM_GPIOB_OE_VAL (HPM_GPIO0_BASE + HPM_GPIOB_OE_VAL_OFFSET)
|
||||
#define HPM_GPIOB_OE_SET (HPM_GPIO0_BASE + HPM_GPIOB_OE_SET_OFFSET)
|
||||
#define HPM_GPIOB_OE_CLR (HPM_GPIO0_BASE + HPM_GPIOB_OE_CLR_OFFSET)
|
||||
#define HPM_GPIOB_OE_TGL (HPM_GPIO0_BASE + HPM_GPIOB_OE_TGL_OFFSET)
|
||||
#define HPM_GPIOB_IF_VAL (HPM_GPIO0_BASE + HPM_GPIOB_IF_VAL_OFFSET)
|
||||
#define HPM_GPIOB_IF_SET (HPM_GPIO0_BASE + HPM_GPIOB_IF_SET_OFFSET)
|
||||
#define HPM_GPIOB_IF_CLR (HPM_GPIO0_BASE + HPM_GPIOB_IF_CLR_OFFSET)
|
||||
#define HPM_GPIOB_IF_TGL (HPM_GPIO0_BASE + HPM_GPIOB_IF_TGL_OFFSET)
|
||||
#define HPM_GPIOB_IE_VAL (HPM_GPIO0_BASE + HPM_GPIOB_IE_VAL_OFFSET)
|
||||
#define HPM_GPIOB_IE_SET (HPM_GPIO0_BASE + HPM_GPIOB_IE_SET_OFFSET)
|
||||
#define HPM_GPIOB_IE_CLR (HPM_GPIO0_BASE + HPM_GPIOB_IE_CLR_OFFSET)
|
||||
#define HPM_GPIOB_IE_TGL (HPM_GPIO0_BASE + HPM_GPIOB_IE_TGL_OFFSET)
|
||||
#define HPM_GPIOB_PL_VAL (HPM_GPIO0_BASE + HPM_GPIOB_PL_VAL_OFFSET)
|
||||
#define HPM_GPIOB_PL_SET (HPM_GPIO0_BASE + HPM_GPIOB_PL_SET_OFFSET)
|
||||
#define HPM_GPIOB_PL_CLR (HPM_GPIO0_BASE + HPM_GPIOB_PL_CLR_OFFSET)
|
||||
#define HPM_GPIOB_PL_TGL (HPM_GPIO0_BASE + HPM_GPIOB_PL_TGL_OFFSET)
|
||||
#define HPM_GPIOB_TP_VAL (HPM_GPIO0_BASE + HPM_GPIOB_TP_VAL_OFFSET)
|
||||
#define HPM_GPIOB_TP_SET (HPM_GPIO0_BASE + HPM_GPIOB_TP_SET_OFFSET)
|
||||
#define HPM_GPIOB_TP_CLR (HPM_GPIO0_BASE + HPM_GPIOB_TP_CLR_OFFSET)
|
||||
#define HPM_GPIOB_TP_TGL (HPM_GPIO0_BASE + HPM_GPIOB_TP_TGL_OFFSET)
|
||||
#define HPM_GPIOB_AS_VAL (HPM_GPIO0_BASE + HPM_GPIOB_AS_VAL_OFFSET)
|
||||
#define HPM_GPIOB_AS_SET (HPM_GPIO0_BASE + HPM_GPIOB_AS_SET_OFFSET)
|
||||
#define HPM_GPIOB_AS_CLR (HPM_GPIO0_BASE + HPM_GPIOB_AS_CLR_OFFSET)
|
||||
#define HPM_GPIOB_AS_TGL (HPM_GPIO0_BASE + HPM_GPIOB_AS_TGL_OFFSET)
|
||||
|
||||
#define HPM_GPIOC_DI_VAL (HPM_GPIO0_BASE + HPM_GPIOC_DI_VAL_OFFSET)
|
||||
#define HPM_GPIOC_DI_SET (HPM_GPIO0_BASE + HPM_GPIOC_DI_SET_OFFSET)
|
||||
#define HPM_GPIOC_DI_CLR (HPM_GPIO0_BASE + HPM_GPIOC_DI_CLR_OFFSET)
|
||||
#define HPM_GPIOC_DI_TGL (HPM_GPIO0_BASE + HPM_GPIOC_DI_TGL_OFFSET)
|
||||
#define HPM_GPIOC_DO_VAL (HPM_GPIO0_BASE + HPM_GPIOC_DO_VAL_OFFSET)
|
||||
#define HPM_GPIOC_DO_SET (HPM_GPIO0_BASE + HPM_GPIOC_DO_SET_OFFSET)
|
||||
#define HPM_GPIOC_DO_CLR (HPM_GPIO0_BASE + HPM_GPIOC_DO_CLR_OFFSET)
|
||||
#define HPM_GPIOC_DO_TGL (HPM_GPIO0_BASE + HPM_GPIOC_DO_TGL_OFFSET)
|
||||
#define HPM_GPIOC_OE_VAL (HPM_GPIO0_BASE + HPM_GPIOC_OE_VAL_OFFSET)
|
||||
#define HPM_GPIOC_OE_SET (HPM_GPIO0_BASE + HPM_GPIOC_OE_SET_OFFSET)
|
||||
#define HPM_GPIOC_OE_CLR (HPM_GPIO0_BASE + HPM_GPIOC_OE_CLR_OFFSET)
|
||||
#define HPM_GPIOC_OE_TGL (HPM_GPIO0_BASE + HPM_GPIOC_OE_TGL_OFFSET)
|
||||
#define HPM_GPIOC_IF_VAL (HPM_GPIO0_BASE + HPM_GPIOC_IF_VAL_OFFSET)
|
||||
#define HPM_GPIOC_IF_SET (HPM_GPIO0_BASE + HPM_GPIOC_IF_SET_OFFSET)
|
||||
#define HPM_GPIOC_IF_CLR (HPM_GPIO0_BASE + HPM_GPIOC_IF_CLR_OFFSET)
|
||||
#define HPM_GPIOC_IF_TGL (HPM_GPIO0_BASE + HPM_GPIOC_IF_TGL_OFFSET)
|
||||
#define HPM_GPIOC_IE_VAL (HPM_GPIO0_BASE + HPM_GPIOC_IE_VAL_OFFSET)
|
||||
#define HPM_GPIOC_IE_SET (HPM_GPIO0_BASE + HPM_GPIOC_IE_SET_OFFSET)
|
||||
#define HPM_GPIOC_IE_CLR (HPM_GPIO0_BASE + HPM_GPIOC_IE_CLR_OFFSET)
|
||||
#define HPM_GPIOC_IE_TGL (HPM_GPIO0_BASE + HPM_GPIOC_IE_TGL_OFFSET)
|
||||
#define HPM_GPIOC_PL_VAL (HPM_GPIO0_BASE + HPM_GPIOC_PL_VAL_OFFSET)
|
||||
#define HPM_GPIOC_PL_SET (HPM_GPIO0_BASE + HPM_GPIOC_PL_SET_OFFSET)
|
||||
#define HPM_GPIOC_PL_CLR (HPM_GPIO0_BASE + HPM_GPIOC_PL_CLR_OFFSET)
|
||||
#define HPM_GPIOC_PL_TGL (HPM_GPIO0_BASE + HPM_GPIOC_PL_TGL_OFFSET)
|
||||
#define HPM_GPIOC_TP_VAL (HPM_GPIO0_BASE + HPM_GPIOC_TP_VAL_OFFSET)
|
||||
#define HPM_GPIOC_TP_SET (HPM_GPIO0_BASE + HPM_GPIOC_TP_SET_OFFSET)
|
||||
#define HPM_GPIOC_TP_CLR (HPM_GPIO0_BASE + HPM_GPIOC_TP_CLR_OFFSET)
|
||||
#define HPM_GPIOC_TP_TGL (HPM_GPIO0_BASE + HPM_GPIOC_TP_TGL_OFFSET)
|
||||
#define HPM_GPIOC_AS_VAL (HPM_GPIO0_BASE + HPM_GPIOC_AS_VAL_OFFSET)
|
||||
#define HPM_GPIOC_AS_SET (HPM_GPIO0_BASE + HPM_GPIOC_AS_SET_OFFSET)
|
||||
#define HPM_GPIOC_AS_CLR (HPM_GPIO0_BASE + HPM_GPIOC_AS_CLR_OFFSET)
|
||||
#define HPM_GPIOC_AS_TGL (HPM_GPIO0_BASE + HPM_GPIOC_AS_TGL_OFFSET)
|
||||
|
||||
#define HPM_GPIOX_DI_VAL (HPM_GPIO0_BASE + HPM_GPIOX_DI_VAL_OFFSET)
|
||||
#define HPM_GPIOX_DI_SET (HPM_GPIO0_BASE + HPM_GPIOX_DI_SET_OFFSET)
|
||||
#define HPM_GPIOX_DI_CLR (HPM_GPIO0_BASE + HPM_GPIOX_DI_CLR_OFFSET)
|
||||
#define HPM_GPIOX_DI_TGL (HPM_GPIO0_BASE + HPM_GPIOX_DI_TGL_OFFSET)
|
||||
#define HPM_GPIOX_DO_VAL (HPM_GPIO0_BASE + HPM_GPIOX_DO_VAL_OFFSET)
|
||||
#define HPM_GPIOX_DO_SET (HPM_GPIO0_BASE + HPM_GPIOX_DO_SET_OFFSET)
|
||||
#define HPM_GPIOX_DO_CLR (HPM_GPIO0_BASE + HPM_GPIOX_DO_CLR_OFFSET)
|
||||
#define HPM_GPIOX_DO_TGL (HPM_GPIO0_BASE + HPM_GPIOX_DO_TGL_OFFSET)
|
||||
#define HPM_GPIOX_OE_VAL (HPM_GPIO0_BASE + HPM_GPIOX_OE_VAL_OFFSET)
|
||||
#define HPM_GPIOX_OE_SET (HPM_GPIO0_BASE + HPM_GPIOX_OE_SET_OFFSET)
|
||||
#define HPM_GPIOX_OE_CLR (HPM_GPIO0_BASE + HPM_GPIOX_OE_CLR_OFFSET)
|
||||
#define HPM_GPIOX_OE_TGL (HPM_GPIO0_BASE + HPM_GPIOX_OE_TGL_OFFSET)
|
||||
#define HPM_GPIOX_IF_VAL (HPM_GPIO0_BASE + HPM_GPIOX_IF_VAL_OFFSET)
|
||||
#define HPM_GPIOX_IF_SET (HPM_GPIO0_BASE + HPM_GPIOX_IF_SET_OFFSET)
|
||||
#define HPM_GPIOX_IF_CLR (HPM_GPIO0_BASE + HPM_GPIOX_IF_CLR_OFFSET)
|
||||
#define HPM_GPIOX_IF_TGL (HPM_GPIO0_BASE + HPM_GPIOX_IF_TGL_OFFSET)
|
||||
#define HPM_GPIOX_IE_VAL (HPM_GPIO0_BASE + HPM_GPIOX_IE_VAL_OFFSET)
|
||||
#define HPM_GPIOX_IE_SET (HPM_GPIO0_BASE + HPM_GPIOX_IE_SET_OFFSET)
|
||||
#define HPM_GPIOX_IE_CLR (HPM_GPIO0_BASE + HPM_GPIOX_IE_CLR_OFFSET)
|
||||
#define HPM_GPIOX_IE_TGL (HPM_GPIO0_BASE + HPM_GPIOX_IE_TGL_OFFSET)
|
||||
#define HPM_GPIOX_PL_VAL (HPM_GPIO0_BASE + HPM_GPIOX_PL_VAL_OFFSET)
|
||||
#define HPM_GPIOX_PL_SET (HPM_GPIO0_BASE + HPM_GPIOX_PL_SET_OFFSET)
|
||||
#define HPM_GPIOX_PL_CLR (HPM_GPIO0_BASE + HPM_GPIOX_PL_CLR_OFFSET)
|
||||
#define HPM_GPIOX_PL_TGL (HPM_GPIO0_BASE + HPM_GPIOX_PL_TGL_OFFSET)
|
||||
#define HPM_GPIOX_TP_VAL (HPM_GPIO0_BASE + HPM_GPIOX_TP_VAL_OFFSET)
|
||||
#define HPM_GPIOX_TP_SET (HPM_GPIO0_BASE + HPM_GPIOX_TP_SET_OFFSET)
|
||||
#define HPM_GPIOX_TP_CLR (HPM_GPIO0_BASE + HPM_GPIOX_TP_CLR_OFFSET)
|
||||
#define HPM_GPIOX_TP_TGL (HPM_GPIO0_BASE + HPM_GPIOX_TP_TGL_OFFSET)
|
||||
#define HPM_GPIOX_AS_VAL (HPM_GPIO0_BASE + HPM_GPIOX_AS_VAL_OFFSET)
|
||||
#define HPM_GPIOX_AS_SET (HPM_GPIO0_BASE + HPM_GPIOX_AS_SET_OFFSET)
|
||||
#define HPM_GPIOX_AS_CLR (HPM_GPIO0_BASE + HPM_GPIOX_AS_CLR_OFFSET)
|
||||
#define HPM_GPIOX_AS_TGL (HPM_GPIO0_BASE + HPM_GPIOX_AS_TGL_OFFSET)
|
||||
|
||||
#define HPM_GPIOY_DI_VAL (HPM_GPIO0_BASE + HPM_GPIOY_DI_VAL_OFFSET)
|
||||
#define HPM_GPIOY_DI_SET (HPM_GPIO0_BASE + HPM_GPIOY_DI_SET_OFFSET)
|
||||
#define HPM_GPIOY_DI_CLR (HPM_GPIO0_BASE + HPM_GPIOY_DI_CLR_OFFSET)
|
||||
#define HPM_GPIOY_DI_TGL (HPM_GPIO0_BASE + HPM_GPIOY_DI_TGL_OFFSET)
|
||||
#define HPM_GPIOY_DO_VAL (HPM_GPIO0_BASE + HPM_GPIOY_DO_VAL_OFFSET)
|
||||
#define HPM_GPIOY_DO_SET (HPM_GPIO0_BASE + HPM_GPIOY_DO_SET_OFFSET)
|
||||
#define HPM_GPIOY_DO_CLR (HPM_GPIO0_BASE + HPM_GPIOY_DO_CLR_OFFSET)
|
||||
#define HPM_GPIOY_DO_TGL (HPM_GPIO0_BASE + HPM_GPIOY_DO_TGL_OFFSET)
|
||||
#define HPM_GPIOY_OE_VAL (HPM_GPIO0_BASE + HPM_GPIOY_OE_VAL_OFFSET)
|
||||
#define HPM_GPIOY_OE_SET (HPM_GPIO0_BASE + HPM_GPIOY_OE_SET_OFFSET)
|
||||
#define HPM_GPIOY_OE_CLR (HPM_GPIO0_BASE + HPM_GPIOY_OE_CLR_OFFSET)
|
||||
#define HPM_GPIOY_OE_TGL (HPM_GPIO0_BASE + HPM_GPIOY_OE_TGL_OFFSET)
|
||||
#define HPM_GPIOY_IF_VAL (HPM_GPIO0_BASE + HPM_GPIOY_IF_VAL_OFFSET)
|
||||
#define HPM_GPIOY_IF_SET (HPM_GPIO0_BASE + HPM_GPIOY_IF_SET_OFFSET)
|
||||
#define HPM_GPIOY_IF_CLR (HPM_GPIO0_BASE + HPM_GPIOY_IF_CLR_OFFSET)
|
||||
#define HPM_GPIOY_IF_TGL (HPM_GPIO0_BASE + HPM_GPIOY_IF_TGL_OFFSET)
|
||||
#define HPM_GPIOY_IE_VAL (HPM_GPIO0_BASE + HPM_GPIOY_IE_VAL_OFFSET)
|
||||
#define HPM_GPIOY_IE_SET (HPM_GPIO0_BASE + HPM_GPIOY_IE_SET_OFFSET)
|
||||
#define HPM_GPIOY_IE_CLR (HPM_GPIO0_BASE + HPM_GPIOY_IE_CLR_OFFSET)
|
||||
#define HPM_GPIOY_IE_TGL (HPM_GPIO0_BASE + HPM_GPIOY_IE_TGL_OFFSET)
|
||||
#define HPM_GPIOY_PL_VAL (HPM_GPIO0_BASE + HPM_GPIOY_PL_VAL_OFFSET)
|
||||
#define HPM_GPIOY_PL_SET (HPM_GPIO0_BASE + HPM_GPIOY_PL_SET_OFFSET)
|
||||
#define HPM_GPIOY_PL_CLR (HPM_GPIO0_BASE + HPM_GPIOY_PL_CLR_OFFSET)
|
||||
#define HPM_GPIOY_PL_TGL (HPM_GPIO0_BASE + HPM_GPIOY_PL_TGL_OFFSET)
|
||||
#define HPM_GPIOY_TP_VAL (HPM_GPIO0_BASE + HPM_GPIOY_TP_VAL_OFFSET)
|
||||
#define HPM_GPIOY_TP_SET (HPM_GPIO0_BASE + HPM_GPIOY_TP_SET_OFFSET)
|
||||
#define HPM_GPIOY_TP_CLR (HPM_GPIO0_BASE + HPM_GPIOY_TP_CLR_OFFSET)
|
||||
#define HPM_GPIOY_TP_TGL (HPM_GPIO0_BASE + HPM_GPIOY_TP_TGL_OFFSET)
|
||||
#define HPM_GPIOY_AS_VAL (HPM_GPIO0_BASE + HPM_GPIOY_AS_VAL_OFFSET)
|
||||
#define HPM_GPIOY_AS_SET (HPM_GPIO0_BASE + HPM_GPIOY_AS_SET_OFFSET)
|
||||
#define HPM_GPIOY_AS_CLR (HPM_GPIO0_BASE + HPM_GPIOY_AS_CLR_OFFSET)
|
||||
#define HPM_GPIOY_AS_TGL (HPM_GPIO0_BASE + HPM_GPIOY_AS_TGL_OFFSET)
|
||||
|
||||
#define HPM_GPIOZ_DI_VAL (HPM_GPIO0_BASE + HPM_GPIOZ_DI_VAL_OFFSET)
|
||||
#define HPM_GPIOZ_DI_SET (HPM_GPIO0_BASE + HPM_GPIOZ_DI_SET_OFFSET)
|
||||
#define HPM_GPIOZ_DI_CLR (HPM_GPIO0_BASE + HPM_GPIOZ_DI_CLR_OFFSET)
|
||||
#define HPM_GPIOZ_DI_TGL (HPM_GPIO0_BASE + HPM_GPIOZ_DI_TGL_OFFSET)
|
||||
#define HPM_GPIOZ_DO_VAL (HPM_GPIO0_BASE + HPM_GPIOZ_DO_VAL_OFFSET)
|
||||
#define HPM_GPIOZ_DO_SET (HPM_GPIO0_BASE + HPM_GPIOZ_DO_SET_OFFSET)
|
||||
#define HPM_GPIOZ_DO_CLR (HPM_GPIO0_BASE + HPM_GPIOZ_DO_CLR_OFFSET)
|
||||
#define HPM_GPIOZ_DO_TGL (HPM_GPIO0_BASE + HPM_GPIOZ_DO_TGL_OFFSET)
|
||||
#define HPM_GPIOZ_OE_VAL (HPM_GPIO0_BASE + HPM_GPIOZ_OE_VAL_OFFSET)
|
||||
#define HPM_GPIOZ_OE_SET (HPM_GPIO0_BASE + HPM_GPIOZ_OE_SET_OFFSET)
|
||||
#define HPM_GPIOZ_OE_CLR (HPM_GPIO0_BASE + HPM_GPIOZ_OE_CLR_OFFSET)
|
||||
#define HPM_GPIOZ_OE_TGL (HPM_GPIO0_BASE + HPM_GPIOZ_OE_TGL_OFFSET)
|
||||
#define HPM_GPIOZ_IF_VAL (HPM_GPIO0_BASE + HPM_GPIOZ_IF_VAL_OFFSET)
|
||||
#define HPM_GPIOZ_IF_SET (HPM_GPIO0_BASE + HPM_GPIOZ_IF_SET_OFFSET)
|
||||
#define HPM_GPIOZ_IF_CLR (HPM_GPIO0_BASE + HPM_GPIOZ_IF_CLR_OFFSET)
|
||||
#define HPM_GPIOZ_IF_TGL (HPM_GPIO0_BASE + HPM_GPIOZ_IF_TGL_OFFSET)
|
||||
#define HPM_GPIOZ_IE_VAL (HPM_GPIO0_BASE + HPM_GPIOZ_IE_VAL_OFFSET)
|
||||
#define HPM_GPIOZ_IE_SET (HPM_GPIO0_BASE + HPM_GPIOZ_IE_SET_OFFSET)
|
||||
#define HPM_GPIOZ_IE_CLR (HPM_GPIO0_BASE + HPM_GPIOZ_IE_CLR_OFFSET)
|
||||
#define HPM_GPIOZ_IE_TGL (HPM_GPIO0_BASE + HPM_GPIOZ_IE_TGL_OFFSET)
|
||||
#define HPM_GPIOZ_PL_VAL (HPM_GPIO0_BASE + HPM_GPIOZ_PL_VAL_OFFSET)
|
||||
#define HPM_GPIOZ_PL_SET (HPM_GPIO0_BASE + HPM_GPIOZ_PL_SET_OFFSET)
|
||||
#define HPM_GPIOZ_PL_CLR (HPM_GPIO0_BASE + HPM_GPIOZ_PL_CLR_OFFSET)
|
||||
#define HPM_GPIOZ_PL_TGL (HPM_GPIO0_BASE + HPM_GPIOZ_PL_TGL_OFFSET)
|
||||
#define HPM_GPIOZ_TP_VAL (HPM_GPIO0_BASE + HPM_GPIOZ_TP_VAL_OFFSET)
|
||||
#define HPM_GPIOZ_TP_SET (HPM_GPIO0_BASE + HPM_GPIOZ_TP_SET_OFFSET)
|
||||
#define HPM_GPIOZ_TP_CLR (HPM_GPIO0_BASE + HPM_GPIOZ_TP_CLR_OFFSET)
|
||||
#define HPM_GPIOZ_TP_TGL (HPM_GPIO0_BASE + HPM_GPIOZ_TP_TGL_OFFSET)
|
||||
#define HPM_GPIOZ_AS_VAL (HPM_GPIO0_BASE + HPM_GPIOZ_AS_VAL_OFFSET)
|
||||
#define HPM_GPIOZ_AS_SET (HPM_GPIO0_BASE + HPM_GPIOZ_AS_SET_OFFSET)
|
||||
#define HPM_GPIOZ_AS_CLR (HPM_GPIO0_BASE + HPM_GPIOZ_AS_CLR_OFFSET)
|
||||
#define HPM_GPIOZ_AS_TGL (HPM_GPIO0_BASE + HPM_GPIOZ_AS_TGL_OFFSET)
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_GPIO_H */
|
||||
641
arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_ioc.h
Normal file
641
arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_ioc.h
Normal file
@ -0,0 +1,641 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_ioc.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_IOC_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_IOC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "hardware/hpm_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* PAD register group index macro definition */
|
||||
#define HPM_IOC_PAD_PA00_INDEX (0UL)
|
||||
#define HPM_IOC_PAD_PA01_INDEX (1UL)
|
||||
#define HPM_IOC_PAD_PA02_INDEX (2UL)
|
||||
#define HPM_IOC_PAD_PA03_INDEX (3UL)
|
||||
#define HPM_IOC_PAD_PA04_INDEX (4UL)
|
||||
#define HPM_IOC_PAD_PA05_INDEX (5UL)
|
||||
#define HPM_IOC_PAD_PA06_INDEX (6UL)
|
||||
#define HPM_IOC_PAD_PA07_INDEX (7UL)
|
||||
#define HPM_IOC_PAD_PA08_INDEX (8UL)
|
||||
#define HPM_IOC_PAD_PA09_INDEX (9UL)
|
||||
#define HPM_IOC_PAD_PA10_INDEX (10UL)
|
||||
#define HPM_IOC_PAD_PA11_INDEX (11UL)
|
||||
#define HPM_IOC_PAD_PA12_INDEX (12UL)
|
||||
#define HPM_IOC_PAD_PA13_INDEX (13UL)
|
||||
#define HPM_IOC_PAD_PA14_INDEX (14UL)
|
||||
#define HPM_IOC_PAD_PA15_INDEX (15UL)
|
||||
#define HPM_IOC_PAD_PA16_INDEX (16UL)
|
||||
#define HPM_IOC_PAD_PA17_INDEX (17UL)
|
||||
#define HPM_IOC_PAD_PA18_INDEX (18UL)
|
||||
#define HPM_IOC_PAD_PA19_INDEX (19UL)
|
||||
#define HPM_IOC_PAD_PA20_INDEX (20UL)
|
||||
#define HPM_IOC_PAD_PA21_INDEX (21UL)
|
||||
#define HPM_IOC_PAD_PA22_INDEX (22UL)
|
||||
#define HPM_IOC_PAD_PA23_INDEX (23UL)
|
||||
#define HPM_IOC_PAD_PA24_INDEX (24UL)
|
||||
#define HPM_IOC_PAD_PA25_INDEX (25UL)
|
||||
#define HPM_IOC_PAD_PA26_INDEX (26UL)
|
||||
#define HPM_IOC_PAD_PA27_INDEX (27UL)
|
||||
#define HPM_IOC_PAD_PA28_INDEX (28UL)
|
||||
#define HPM_IOC_PAD_PA29_INDEX (29UL)
|
||||
#define HPM_IOC_PAD_PA30_INDEX (30UL)
|
||||
#define HPM_IOC_PAD_PA31_INDEX (31UL)
|
||||
#define HPM_IOC_PAD_PB00_INDEX (32UL)
|
||||
#define HPM_IOC_PAD_PB01_INDEX (33UL)
|
||||
#define HPM_IOC_PAD_PB02_INDEX (34UL)
|
||||
#define HPM_IOC_PAD_PB03_INDEX (35UL)
|
||||
#define HPM_IOC_PAD_PB04_INDEX (36UL)
|
||||
#define HPM_IOC_PAD_PB05_INDEX (37UL)
|
||||
#define HPM_IOC_PAD_PB06_INDEX (38UL)
|
||||
#define HPM_IOC_PAD_PB07_INDEX (39UL)
|
||||
#define HPM_IOC_PAD_PB08_INDEX (40UL)
|
||||
#define HPM_IOC_PAD_PB09_INDEX (41UL)
|
||||
#define HPM_IOC_PAD_PB10_INDEX (42UL)
|
||||
#define HPM_IOC_PAD_PB11_INDEX (43UL)
|
||||
#define HPM_IOC_PAD_PB12_INDEX (44UL)
|
||||
#define HPM_IOC_PAD_PB13_INDEX (45UL)
|
||||
#define HPM_IOC_PAD_PB14_INDEX (46UL)
|
||||
#define HPM_IOC_PAD_PB15_INDEX (47UL)
|
||||
#define HPM_IOC_PAD_PB16_INDEX (48UL)
|
||||
#define HPM_IOC_PAD_PB17_INDEX (49UL)
|
||||
#define HPM_IOC_PAD_PB18_INDEX (50UL)
|
||||
#define HPM_IOC_PAD_PB19_INDEX (51UL)
|
||||
#define HPM_IOC_PAD_PB20_INDEX (52UL)
|
||||
#define HPM_IOC_PAD_PB21_INDEX (53UL)
|
||||
#define HPM_IOC_PAD_PB22_INDEX (54UL)
|
||||
#define HPM_IOC_PAD_PB23_INDEX (55UL)
|
||||
#define HPM_IOC_PAD_PB24_INDEX (56UL)
|
||||
#define HPM_IOC_PAD_PB25_INDEX (57UL)
|
||||
#define HPM_IOC_PAD_PB26_INDEX (58UL)
|
||||
#define HPM_IOC_PAD_PB27_INDEX (59UL)
|
||||
#define HPM_IOC_PAD_PB28_INDEX (60UL)
|
||||
#define HPM_IOC_PAD_PB29_INDEX (61UL)
|
||||
#define HPM_IOC_PAD_PB30_INDEX (62UL)
|
||||
#define HPM_IOC_PAD_PB31_INDEX (63UL)
|
||||
#define HPM_IOC_PAD_PC00_INDEX (64UL)
|
||||
#define HPM_IOC_PAD_PC01_INDEX (65UL)
|
||||
#define HPM_IOC_PAD_PC02_INDEX (66UL)
|
||||
#define HPM_IOC_PAD_PC03_INDEX (67UL)
|
||||
#define HPM_IOC_PAD_PC04_INDEX (68UL)
|
||||
#define HPM_IOC_PAD_PC05_INDEX (69UL)
|
||||
#define HPM_IOC_PAD_PC06_INDEX (70UL)
|
||||
#define HPM_IOC_PAD_PC07_INDEX (71UL)
|
||||
#define HPM_IOC_PAD_PC08_INDEX (72UL)
|
||||
#define HPM_IOC_PAD_PC09_INDEX (73UL)
|
||||
#define HPM_IOC_PAD_PC10_INDEX (74UL)
|
||||
#define HPM_IOC_PAD_PC11_INDEX (75UL)
|
||||
#define HPM_IOC_PAD_PC12_INDEX (76UL)
|
||||
#define HPM_IOC_PAD_PC13_INDEX (77UL)
|
||||
#define HPM_IOC_PAD_PC14_INDEX (78UL)
|
||||
#define HPM_IOC_PAD_PC15_INDEX (79UL)
|
||||
#define HPM_IOC_PAD_PC16_INDEX (80UL)
|
||||
#define HPM_IOC_PAD_PC17_INDEX (81UL)
|
||||
#define HPM_IOC_PAD_PC18_INDEX (82UL)
|
||||
#define HPM_IOC_PAD_PC19_INDEX (83UL)
|
||||
#define HPM_IOC_PAD_PC20_INDEX (84UL)
|
||||
#define HPM_IOC_PAD_PC21_INDEX (85UL)
|
||||
#define HPM_IOC_PAD_PC22_INDEX (86UL)
|
||||
#define HPM_IOC_PAD_PC23_INDEX (87UL)
|
||||
#define HPM_IOC_PAD_PC24_INDEX (88UL)
|
||||
#define HPM_IOC_PAD_PC25_INDEX (89UL)
|
||||
#define HPM_IOC_PAD_PC26_INDEX (90UL)
|
||||
#define HPM_IOC_PAD_PC27_INDEX (91UL)
|
||||
#define HPM_IOC_PAD_PX00_INDEX (416UL)
|
||||
#define HPM_IOC_PAD_PX01_INDEX (417UL)
|
||||
#define HPM_IOC_PAD_PX02_INDEX (418UL)
|
||||
#define HPM_IOC_PAD_PX03_INDEX (419UL)
|
||||
#define HPM_IOC_PAD_PX04_INDEX (420UL)
|
||||
#define HPM_IOC_PAD_PX05_INDEX (421UL)
|
||||
#define HPM_IOC_PAD_PX06_INDEX (422UL)
|
||||
#define HPM_IOC_PAD_PX07_INDEX (423UL)
|
||||
#define HPM_IOC_PAD_PY00_INDEX (448UL)
|
||||
#define HPM_IOC_PAD_PY01_INDEX (449UL)
|
||||
#define HPM_IOC_PAD_PY02_INDEX (450UL)
|
||||
#define HPM_IOC_PAD_PY03_INDEX (451UL)
|
||||
#define HPM_IOC_PAD_PY04_INDEX (452UL)
|
||||
#define HPM_IOC_PAD_PY05_INDEX (453UL)
|
||||
#define HPM_IOC_PAD_PY06_INDEX (454UL)
|
||||
#define HPM_IOC_PAD_PY07_INDEX (455UL)
|
||||
#define HPM_IOC_PAD_PZ00_INDEX (480UL)
|
||||
#define HPM_IOC_PAD_PZ01_INDEX (481UL)
|
||||
#define HPM_IOC_PAD_PZ02_INDEX (482UL)
|
||||
#define HPM_IOC_PAD_PZ03_INDEX (483UL)
|
||||
#define HPM_IOC_PAD_PZ04_INDEX (484UL)
|
||||
#define HPM_IOC_PAD_PZ05_INDEX (485UL)
|
||||
#define HPM_IOC_PAD_PZ06_INDEX (486UL)
|
||||
#define HPM_IOC_PAD_PZ07_INDEX (487UL)
|
||||
|
||||
#define HPM_IOC_PAD_NREGISTERS 116
|
||||
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
#define HPM_IOC_PAD_FUNC_CTL_OFFSET(n) (0x0000 + ((unsigned int)(n) * 0x0008))
|
||||
#define HPM_IOC_PAD_PAD_CTL_OFFSET(n) (0x0004 + ((unsigned int)(n) * 0x0008))
|
||||
|
||||
#define HPM_IOC_PAD_PA00_FUNC_CTL_OFFSET 0x0000
|
||||
#define HPM_IOC_PAD_PA00_PAD_CTL_OFFSET 0x0004
|
||||
#define HPM_IOC_PAD_PA01_FUNC_CTL_OFFSET 0x0008
|
||||
#define HPM_IOC_PAD_PA01_PAD_CTL_OFFSET 0x000c
|
||||
#define HPM_IOC_PAD_PA02_FUNC_CTL_OFFSET 0x0010
|
||||
#define HPM_IOC_PAD_PA02_PAD_CTL_OFFSET 0x0014
|
||||
#define HPM_IOC_PAD_PA03_FUNC_CTL_OFFSET 0x0018
|
||||
#define HPM_IOC_PAD_PA03_PAD_CTL_OFFSET 0x001c
|
||||
#define HPM_IOC_PAD_PA04_FUNC_CTL_OFFSET 0x0020
|
||||
#define HPM_IOC_PAD_PA04_PAD_CTL_OFFSET 0x0024
|
||||
#define HPM_IOC_PAD_PA05_FUNC_CTL_OFFSET 0x0028
|
||||
#define HPM_IOC_PAD_PA05_PAD_CTL_OFFSET 0x002c
|
||||
#define HPM_IOC_PAD_PA06_FUNC_CTL_OFFSET 0x0030
|
||||
#define HPM_IOC_PAD_PA06_PAD_CTL_OFFSET 0x0034
|
||||
#define HPM_IOC_PAD_PA07_FUNC_CTL_OFFSET 0x0038
|
||||
#define HPM_IOC_PAD_PA07_PAD_CTL_OFFSET 0x003c
|
||||
#define HPM_IOC_PAD_PA08_FUNC_CTL_OFFSET 0x0040
|
||||
#define HPM_IOC_PAD_PA08_PAD_CTL_OFFSET 0x0044
|
||||
#define HPM_IOC_PAD_PA09_FUNC_CTL_OFFSET 0x0048
|
||||
#define HPM_IOC_PAD_PA09_PAD_CTL_OFFSET 0x004c
|
||||
#define HPM_IOC_PAD_PA10_FUNC_CTL_OFFSET 0x0050
|
||||
#define HPM_IOC_PAD_PA10_PAD_CTL_OFFSET 0x0054
|
||||
#define HPM_IOC_PAD_PA11_FUNC_CTL_OFFSET 0x0058
|
||||
#define HPM_IOC_PAD_PA11_PAD_CTL_OFFSET 0x005c
|
||||
#define HPM_IOC_PAD_PA12_FUNC_CTL_OFFSET 0x0060
|
||||
#define HPM_IOC_PAD_PA12_PAD_CTL_OFFSET 0x0064
|
||||
#define HPM_IOC_PAD_PA13_FUNC_CTL_OFFSET 0x0068
|
||||
#define HPM_IOC_PAD_PA13_PAD_CTL_OFFSET 0x006c
|
||||
#define HPM_IOC_PAD_PA14_FUNC_CTL_OFFSET 0x0070
|
||||
#define HPM_IOC_PAD_PA14_PAD_CTL_OFFSET 0x0074
|
||||
#define HPM_IOC_PAD_PA15_FUNC_CTL_OFFSET 0x0078
|
||||
#define HPM_IOC_PAD_PA15_PAD_CTL_OFFSET 0x007c
|
||||
#define HPM_IOC_PAD_PA16_FUNC_CTL_OFFSET 0x0080
|
||||
#define HPM_IOC_PAD_PA16_PAD_CTL_OFFSET 0x0084
|
||||
#define HPM_IOC_PAD_PA17_FUNC_CTL_OFFSET 0x0088
|
||||
#define HPM_IOC_PAD_PA17_PAD_CTL_OFFSET 0x008c
|
||||
#define HPM_IOC_PAD_PA18_FUNC_CTL_OFFSET 0x0090
|
||||
#define HPM_IOC_PAD_PA18_PAD_CTL_OFFSET 0x0094
|
||||
#define HPM_IOC_PAD_PA19_FUNC_CTL_OFFSET 0x0098
|
||||
#define HPM_IOC_PAD_PA19_PAD_CTL_OFFSET 0x009c
|
||||
#define HPM_IOC_PAD_PA20_FUNC_CTL_OFFSET 0x00a0
|
||||
#define HPM_IOC_PAD_PA20_PAD_CTL_OFFSET 0x00a4
|
||||
#define HPM_IOC_PAD_PA21_FUNC_CTL_OFFSET 0x00a8
|
||||
#define HPM_IOC_PAD_PA21_PAD_CTL_OFFSET 0x00ac
|
||||
#define HPM_IOC_PAD_PA22_FUNC_CTL_OFFSET 0x00b0
|
||||
#define HPM_IOC_PAD_PA22_PAD_CTL_OFFSET 0x00b4
|
||||
#define HPM_IOC_PAD_PA23_FUNC_CTL_OFFSET 0x00b8
|
||||
#define HPM_IOC_PAD_PA23_PAD_CTL_OFFSET 0x00bc
|
||||
#define HPM_IOC_PAD_PA24_FUNC_CTL_OFFSET 0x00c0
|
||||
#define HPM_IOC_PAD_PA24_PAD_CTL_OFFSET 0x00c4
|
||||
#define HPM_IOC_PAD_PA25_FUNC_CTL_OFFSET 0x00c8
|
||||
#define HPM_IOC_PAD_PA25_PAD_CTL_OFFSET 0x00cc
|
||||
#define HPM_IOC_PAD_PA26_FUNC_CTL_OFFSET 0x00d0
|
||||
#define HPM_IOC_PAD_PA26_PAD_CTL_OFFSET 0x00d4
|
||||
#define HPM_IOC_PAD_PA27_FUNC_CTL_OFFSET 0x00d8
|
||||
#define HPM_IOC_PAD_PA27_PAD_CTL_OFFSET 0x00dc
|
||||
#define HPM_IOC_PAD_PA28_FUNC_CTL_OFFSET 0x00e0
|
||||
#define HPM_IOC_PAD_PA28_PAD_CTL_OFFSET 0x00e4
|
||||
#define HPM_IOC_PAD_PA29_FUNC_CTL_OFFSET 0x00e8
|
||||
#define HPM_IOC_PAD_PA29_PAD_CTL_OFFSET 0x00ec
|
||||
#define HPM_IOC_PAD_PA30_FUNC_CTL_OFFSET 0x00f0
|
||||
#define HPM_IOC_PAD_PA30_PAD_CTL_OFFSET 0x00f4
|
||||
#define HPM_IOC_PAD_PA31_FUNC_CTL_OFFSET 0x00f8
|
||||
#define HPM_IOC_PAD_PA31_PAD_CTL_OFFSET 0x00fc
|
||||
#define HPM_IOC_PAD_PB00_FUNC_CTL_OFFSET 0x0100
|
||||
#define HPM_IOC_PAD_PB00_PAD_CTL_OFFSET 0x0104
|
||||
#define HPM_IOC_PAD_PB01_FUNC_CTL_OFFSET 0x0108
|
||||
#define HPM_IOC_PAD_PB01_PAD_CTL_OFFSET 0x010c
|
||||
#define HPM_IOC_PAD_PB02_FUNC_CTL_OFFSET 0x0110
|
||||
#define HPM_IOC_PAD_PB02_PAD_CTL_OFFSET 0x0114
|
||||
#define HPM_IOC_PAD_PB03_FUNC_CTL_OFFSET 0x0118
|
||||
#define HPM_IOC_PAD_PB03_PAD_CTL_OFFSET 0x011c
|
||||
#define HPM_IOC_PAD_PB04_FUNC_CTL_OFFSET 0x0120
|
||||
#define HPM_IOC_PAD_PB04_PAD_CTL_OFFSET 0x0124
|
||||
#define HPM_IOC_PAD_PB05_FUNC_CTL_OFFSET 0x0128
|
||||
#define HPM_IOC_PAD_PB05_PAD_CTL_OFFSET 0x012c
|
||||
#define HPM_IOC_PAD_PB06_FUNC_CTL_OFFSET 0x0130
|
||||
#define HPM_IOC_PAD_PB06_PAD_CTL_OFFSET 0x0134
|
||||
#define HPM_IOC_PAD_PB07_FUNC_CTL_OFFSET 0x0138
|
||||
#define HPM_IOC_PAD_PB07_PAD_CTL_OFFSET 0x013c
|
||||
#define HPM_IOC_PAD_PB08_FUNC_CTL_OFFSET 0x0140
|
||||
#define HPM_IOC_PAD_PB08_PAD_CTL_OFFSET 0x0144
|
||||
#define HPM_IOC_PAD_PB09_FUNC_CTL_OFFSET 0x0148
|
||||
#define HPM_IOC_PAD_PB09_PAD_CTL_OFFSET 0x014c
|
||||
#define HPM_IOC_PAD_PB10_FUNC_CTL_OFFSET 0x0150
|
||||
#define HPM_IOC_PAD_PB10_PAD_CTL_OFFSET 0x0154
|
||||
#define HPM_IOC_PAD_PB11_FUNC_CTL_OFFSET 0x0158
|
||||
#define HPM_IOC_PAD_PB11_PAD_CTL_OFFSET 0x015c
|
||||
#define HPM_IOC_PAD_PB12_FUNC_CTL_OFFSET 0x0160
|
||||
#define HPM_IOC_PAD_PB12_PAD_CTL_OFFSET 0x0164
|
||||
#define HPM_IOC_PAD_PB13_FUNC_CTL_OFFSET 0x0168
|
||||
#define HPM_IOC_PAD_PB13_PAD_CTL_OFFSET 0x016c
|
||||
#define HPM_IOC_PAD_PB14_FUNC_CTL_OFFSET 0x0170
|
||||
#define HPM_IOC_PAD_PB14_PAD_CTL_OFFSET 0x0174
|
||||
#define HPM_IOC_PAD_PB15_FUNC_CTL_OFFSET 0x0178
|
||||
#define HPM_IOC_PAD_PB15_PAD_CTL_OFFSET 0x017c
|
||||
#define HPM_IOC_PAD_PB16_FUNC_CTL_OFFSET 0x0180
|
||||
#define HPM_IOC_PAD_PB16_PAD_CTL_OFFSET 0x0184
|
||||
#define HPM_IOC_PAD_PB17_FUNC_CTL_OFFSET 0x0188
|
||||
#define HPM_IOC_PAD_PB17_PAD_CTL_OFFSET 0x018c
|
||||
#define HPM_IOC_PAD_PB18_FUNC_CTL_OFFSET 0x0190
|
||||
#define HPM_IOC_PAD_PB18_PAD_CTL_OFFSET 0x0194
|
||||
#define HPM_IOC_PAD_PB19_FUNC_CTL_OFFSET 0x0198
|
||||
#define HPM_IOC_PAD_PB19_PAD_CTL_OFFSET 0x019c
|
||||
#define HPM_IOC_PAD_PB20_FUNC_CTL_OFFSET 0x01a0
|
||||
#define HPM_IOC_PAD_PB20_PAD_CTL_OFFSET 0x01a4
|
||||
#define HPM_IOC_PAD_PB21_FUNC_CTL_OFFSET 0x01a8
|
||||
#define HPM_IOC_PAD_PB21_PAD_CTL_OFFSET 0x01ac
|
||||
#define HPM_IOC_PAD_PB22_FUNC_CTL_OFFSET 0x01b0
|
||||
#define HPM_IOC_PAD_PB22_PAD_CTL_OFFSET 0x01b4
|
||||
#define HPM_IOC_PAD_PB23_FUNC_CTL_OFFSET 0x01b8
|
||||
#define HPM_IOC_PAD_PB23_PAD_CTL_OFFSET 0x01bc
|
||||
#define HPM_IOC_PAD_PB24_FUNC_CTL_OFFSET 0x01c0
|
||||
#define HPM_IOC_PAD_PB24_PAD_CTL_OFFSET 0x01c4
|
||||
#define HPM_IOC_PAD_PB25_FUNC_CTL_OFFSET 0x01c8
|
||||
#define HPM_IOC_PAD_PB25_PAD_CTL_OFFSET 0x01cc
|
||||
#define HPM_IOC_PAD_PB26_FUNC_CTL_OFFSET 0x01d0
|
||||
#define HPM_IOC_PAD_PB26_PAD_CTL_OFFSET 0x01d4
|
||||
#define HPM_IOC_PAD_PB27_FUNC_CTL_OFFSET 0x01d8
|
||||
#define HPM_IOC_PAD_PB27_PAD_CTL_OFFSET 0x01dc
|
||||
#define HPM_IOC_PAD_PB28_FUNC_CTL_OFFSET 0x01e0
|
||||
#define HPM_IOC_PAD_PB28_PAD_CTL_OFFSET 0x01e4
|
||||
#define HPM_IOC_PAD_PB29_FUNC_CTL_OFFSET 0x01e8
|
||||
#define HPM_IOC_PAD_PB29_PAD_CTL_OFFSET 0x01ec
|
||||
#define HPM_IOC_PAD_PB30_FUNC_CTL_OFFSET 0x01f0
|
||||
#define HPM_IOC_PAD_PB30_PAD_CTL_OFFSET 0x01f4
|
||||
#define HPM_IOC_PAD_PB31_FUNC_CTL_OFFSET 0x01f8
|
||||
#define HPM_IOC_PAD_PB31_PAD_CTL_OFFSET 0x01fc
|
||||
#define HPM_IOC_PAD_PC00_FUNC_CTL_OFFSET 0x0200
|
||||
#define HPM_IOC_PAD_PC00_PAD_CTL_OFFSET 0x0204
|
||||
#define HPM_IOC_PAD_PC01_FUNC_CTL_OFFSET 0x0208
|
||||
#define HPM_IOC_PAD_PC01_PAD_CTL_OFFSET 0x020c
|
||||
#define HPM_IOC_PAD_PC02_FUNC_CTL_OFFSET 0x0210
|
||||
#define HPM_IOC_PAD_PC02_PAD_CTL_OFFSET 0x0214
|
||||
#define HPM_IOC_PAD_PC03_FUNC_CTL_OFFSET 0x0218
|
||||
#define HPM_IOC_PAD_PC03_PAD_CTL_OFFSET 0x021c
|
||||
#define HPM_IOC_PAD_PC04_FUNC_CTL_OFFSET 0x0220
|
||||
#define HPM_IOC_PAD_PC04_PAD_CTL_OFFSET 0x0224
|
||||
#define HPM_IOC_PAD_PC05_FUNC_CTL_OFFSET 0x0228
|
||||
#define HPM_IOC_PAD_PC05_PAD_CTL_OFFSET 0x022c
|
||||
#define HPM_IOC_PAD_PC06_FUNC_CTL_OFFSET 0x0230
|
||||
#define HPM_IOC_PAD_PC06_PAD_CTL_OFFSET 0x0234
|
||||
#define HPM_IOC_PAD_PC07_FUNC_CTL_OFFSET 0x0238
|
||||
#define HPM_IOC_PAD_PC07_PAD_CTL_OFFSET 0x023c
|
||||
#define HPM_IOC_PAD_PC08_FUNC_CTL_OFFSET 0x0240
|
||||
#define HPM_IOC_PAD_PC08_PAD_CTL_OFFSET 0x0244
|
||||
#define HPM_IOC_PAD_PC09_FUNC_CTL_OFFSET 0x0248
|
||||
#define HPM_IOC_PAD_PC09_PAD_CTL_OFFSET 0x024c
|
||||
#define HPM_IOC_PAD_PC10_FUNC_CTL_OFFSET 0x0250
|
||||
#define HPM_IOC_PAD_PC10_PAD_CTL_OFFSET 0x0254
|
||||
#define HPM_IOC_PAD_PC11_FUNC_CTL_OFFSET 0x0258
|
||||
#define HPM_IOC_PAD_PC11_PAD_CTL_OFFSET 0x025c
|
||||
#define HPM_IOC_PAD_PC12_FUNC_CTL_OFFSET 0x0260
|
||||
#define HPM_IOC_PAD_PC12_PAD_CTL_OFFSET 0x0264
|
||||
#define HPM_IOC_PAD_PC13_FUNC_CTL_OFFSET 0x0268
|
||||
#define HPM_IOC_PAD_PC13_PAD_CTL_OFFSET 0x026c
|
||||
#define HPM_IOC_PAD_PC14_FUNC_CTL_OFFSET 0x0270
|
||||
#define HPM_IOC_PAD_PC14_PAD_CTL_OFFSET 0x0274
|
||||
#define HPM_IOC_PAD_PC15_FUNC_CTL_OFFSET 0x0278
|
||||
#define HPM_IOC_PAD_PC15_PAD_CTL_OFFSET 0x027c
|
||||
#define HPM_IOC_PAD_PC16_FUNC_CTL_OFFSET 0x0280
|
||||
#define HPM_IOC_PAD_PC16_PAD_CTL_OFFSET 0x0284
|
||||
#define HPM_IOC_PAD_PC17_FUNC_CTL_OFFSET 0x0288
|
||||
#define HPM_IOC_PAD_PC17_PAD_CTL_OFFSET 0x028c
|
||||
#define HPM_IOC_PAD_PC18_FUNC_CTL_OFFSET 0x0290
|
||||
#define HPM_IOC_PAD_PC18_PAD_CTL_OFFSET 0x0294
|
||||
#define HPM_IOC_PAD_PC19_FUNC_CTL_OFFSET 0x0298
|
||||
#define HPM_IOC_PAD_PC19_PAD_CTL_OFFSET 0x029c
|
||||
#define HPM_IOC_PAD_PC20_FUNC_CTL_OFFSET 0x02a0
|
||||
#define HPM_IOC_PAD_PC20_PAD_CTL_OFFSET 0x02a4
|
||||
#define HPM_IOC_PAD_PC21_FUNC_CTL_OFFSET 0x02a8
|
||||
#define HPM_IOC_PAD_PC21_PAD_CTL_OFFSET 0x02ac
|
||||
#define HPM_IOC_PAD_PC22_FUNC_CTL_OFFSET 0x02b0
|
||||
#define HPM_IOC_PAD_PC22_PAD_CTL_OFFSET 0x02b4
|
||||
#define HPM_IOC_PAD_PC23_FUNC_CTL_OFFSET 0x02b8
|
||||
#define HPM_IOC_PAD_PC23_PAD_CTL_OFFSET 0x02bc
|
||||
#define HPM_IOC_PAD_PC24_FUNC_CTL_OFFSET 0x02c0
|
||||
#define HPM_IOC_PAD_PC24_PAD_CTL_OFFSET 0x02c4
|
||||
#define HPM_IOC_PAD_PC25_FUNC_CTL_OFFSET 0x02c8
|
||||
#define HPM_IOC_PAD_PC25_PAD_CTL_OFFSET 0x02cc
|
||||
#define HPM_IOC_PAD_PC26_FUNC_CTL_OFFSET 0x02d0
|
||||
#define HPM_IOC_PAD_PC26_PAD_CTL_OFFSET 0x02d4
|
||||
#define HPM_IOC_PAD_PC27_FUNC_CTL_OFFSET 0x02d8
|
||||
#define HPM_IOC_PAD_PC27_PAD_CTL_OFFSET 0x02dc
|
||||
#define HPM_IOC_PAD_PX00_FUNC_CTL_OFFSET 0x0d00
|
||||
#define HPM_IOC_PAD_PX00_PAD_CTL_OFFSET 0x0d04
|
||||
#define HPM_IOC_PAD_PX01_FUNC_CTL_OFFSET 0x0d08
|
||||
#define HPM_IOC_PAD_PX01_PAD_CTL_OFFSET 0x0d0c
|
||||
#define HPM_IOC_PAD_PX02_FUNC_CTL_OFFSET 0x0d10
|
||||
#define HPM_IOC_PAD_PX02_PAD_CTL_OFFSET 0x0d14
|
||||
#define HPM_IOC_PAD_PX03_FUNC_CTL_OFFSET 0x0d18
|
||||
#define HPM_IOC_PAD_PX03_PAD_CTL_OFFSET 0x0d1c
|
||||
#define HPM_IOC_PAD_PX04_FUNC_CTL_OFFSET 0x0d20
|
||||
#define HPM_IOC_PAD_PX04_PAD_CTL_OFFSET 0x0d24
|
||||
#define HPM_IOC_PAD_PX05_FUNC_CTL_OFFSET 0x0d28
|
||||
#define HPM_IOC_PAD_PX05_PAD_CTL_OFFSET 0x0d2c
|
||||
#define HPM_IOC_PAD_PX06_FUNC_CTL_OFFSET 0x0d30
|
||||
#define HPM_IOC_PAD_PX06_PAD_CTL_OFFSET 0x0d34
|
||||
#define HPM_IOC_PAD_PX07_FUNC_CTL_OFFSET 0x0d38
|
||||
#define HPM_IOC_PAD_PX07_PAD_CTL_OFFSET 0x0d3c
|
||||
#define HPM_IOC_PAD_PY00_FUNC_CTL_OFFSET 0x0e00
|
||||
#define HPM_IOC_PAD_PY00_PAD_CTL_OFFSET 0x0e04
|
||||
#define HPM_IOC_PAD_PY01_FUNC_CTL_OFFSET 0x0e08
|
||||
#define HPM_IOC_PAD_PY01_PAD_CTL_OFFSET 0x0e0c
|
||||
#define HPM_IOC_PAD_PY02_FUNC_CTL_OFFSET 0x0e10
|
||||
#define HPM_IOC_PAD_PY02_PAD_CTL_OFFSET 0x0e14
|
||||
#define HPM_IOC_PAD_PY03_FUNC_CTL_OFFSET 0x0e18
|
||||
#define HPM_IOC_PAD_PY03_PAD_CTL_OFFSET 0x0e1c
|
||||
#define HPM_IOC_PAD_PY04_FUNC_CTL_OFFSET 0x0e20
|
||||
#define HPM_IOC_PAD_PY04_PAD_CTL_OFFSET 0x0e24
|
||||
#define HPM_IOC_PAD_PY05_FUNC_CTL_OFFSET 0x0e28
|
||||
#define HPM_IOC_PAD_PY05_PAD_CTL_OFFSET 0x0e2c
|
||||
#define HPM_IOC_PAD_PY06_FUNC_CTL_OFFSET 0x0e30
|
||||
#define HPM_IOC_PAD_PY06_PAD_CTL_OFFSET 0x0e34
|
||||
#define HPM_IOC_PAD_PY07_FUNC_CTL_OFFSET 0x0e38
|
||||
#define HPM_IOC_PAD_PY07_PAD_CTL_OFFSET 0x0e3c
|
||||
#define HPM_IOC_PAD_PZ00_FUNC_CTL_OFFSET 0x0f00
|
||||
#define HPM_IOC_PAD_PZ00_PAD_CTL_OFFSET 0x0f04
|
||||
#define HPM_IOC_PAD_PZ01_FUNC_CTL_OFFSET 0x0f08
|
||||
#define HPM_IOC_PAD_PZ01_PAD_CTL_OFFSET 0x0f0c
|
||||
#define HPM_IOC_PAD_PZ02_FUNC_CTL_OFFSET 0x0f10
|
||||
#define HPM_IOC_PAD_PZ02_PAD_CTL_OFFSET 0x0f14
|
||||
#define HPM_IOC_PAD_PZ03_FUNC_CTL_OFFSET 0x0f18
|
||||
#define HPM_IOC_PAD_PZ03_PAD_CTL_OFFSET 0x0f1c
|
||||
#define HPM_IOC_PAD_PZ04_FUNC_CTL_OFFSET 0x0f20
|
||||
#define HPM_IOC_PAD_PZ04_PAD_CTL_OFFSET 0x0f24
|
||||
#define HPM_IOC_PAD_PZ05_FUNC_CTL_OFFSET 0x0f28
|
||||
#define HPM_IOC_PAD_PZ05_PAD_CTL_OFFSET 0x0f2c
|
||||
#define HPM_IOC_PAD_PZ06_FUNC_CTL_OFFSET 0x0f30
|
||||
#define HPM_IOC_PAD_PZ06_PAD_CTL_OFFSET 0x0f34
|
||||
#define HPM_IOC_PAD_PZ07_FUNC_CTL_OFFSET 0x0f38
|
||||
#define HPM_IOC_PAD_PZ07_PAD_CTL_OFFSET 0x0f3c
|
||||
|
||||
#define HPM_IOC_PAD_FUNC_CTL_ADDRESS(n) (HPM_IOC_BASE + HPM_IOC_PAD_FUNC_CTL_OFFSET(n))
|
||||
#define HPM_IOC_PAD_PAD_CTL_ADDRESS(n) (HPM_IOC_BASE + HPM_IOC_PAD_PAD_CTL_OFFSET(n))
|
||||
|
||||
#define HPM_IOC_PAD_PA00_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA00_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA00_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA00_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA01_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA01_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA01_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA01_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA02_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA02_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA02_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA02_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA03_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA03_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA03_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA03_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA04_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA04_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA04_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA04_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA05_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA05_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA05_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA05_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA06_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA06_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA06_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA06_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA07_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA07_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA07_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA07_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA08_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA08_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA08_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA08_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA09_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA09_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA09_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA09_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA10_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA10_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA10_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA10_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA11_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA11_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA11_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA11_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA12_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA12_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA12_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA12_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA13_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA13_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA13_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA13_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA14_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA14_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA14_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA14_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA15_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA15_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA15_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA15_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA16_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA16_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA16_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA16_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA17_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA17_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA17_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA17_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA18_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA18_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA18_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA18_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA19_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA19_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA19_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA19_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA20_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA20_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA20_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA20_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA21_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA21_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA21_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA21_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA22_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA22_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA22_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA22_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA23_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA23_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA23_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA23_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA24_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA24_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA24_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA24_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA25_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA25_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA25_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA25_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA26_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA26_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA26_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA26_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA27_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA27_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA27_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA27_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA28_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA28_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA28_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA28_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA29_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA29_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA29_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA29_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA30_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA30_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA30_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA30_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PA31_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA31_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PA31_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA31_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB00_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB00_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB00_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB00_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB01_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB01_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB01_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB01_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB02_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB02_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB02_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB02_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB03_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB03_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB03_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB03_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB04_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB04_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB04_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB04_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB05_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB05_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB05_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB05_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB06_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB06_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB06_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB06_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB07_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB07_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB07_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB07_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB08_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB08_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB08_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB08_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB09_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB09_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB09_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB09_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB10_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB10_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB10_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB10_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB11_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB11_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB11_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB11_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB12_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB12_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB12_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB12_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB13_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB13_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB13_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB13_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB14_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB14_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB14_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB14_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB15_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB15_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB15_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB15_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB16_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB16_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB16_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB16_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB17_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB17_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB17_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB17_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB18_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB18_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB18_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB18_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB19_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB19_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB19_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB19_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB20_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB20_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB20_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB20_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB21_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB21_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB21_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB21_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB22_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB22_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB22_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB22_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB23_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB23_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB23_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB23_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB24_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB24_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB24_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB24_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB25_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB25_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB25_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB25_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB26_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB26_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB26_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB26_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB27_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB27_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB27_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB27_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB28_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB28_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB28_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB28_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB29_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB29_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB29_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB29_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB30_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB30_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB30_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB30_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PB31_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB31_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PB31_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB31_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC00_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC00_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC00_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC00_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC01_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC01_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC01_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC01_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC02_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC02_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC02_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC02_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC03_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC03_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC03_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC03_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC04_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC04_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC04_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC04_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC05_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC05_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC05_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC05_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC06_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC06_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC06_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC06_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC07_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC07_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC07_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC07_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC08_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC08_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC08_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC08_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC09_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC09_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC09_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC09_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC10_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC10_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC10_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC10_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC11_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC11_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC11_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC11_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC12_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC12_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC12_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC12_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC13_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC13_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC13_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC13_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC14_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC14_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC14_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC14_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC15_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC15_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC15_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC15_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC16_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC16_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC16_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC16_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC17_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC17_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC17_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC17_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC18_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC18_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC18_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC18_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC19_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC19_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC19_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC19_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC20_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC20_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC20_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC20_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC21_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC21_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC21_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC21_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC22_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC22_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC22_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC22_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC23_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC23_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC23_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC23_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC24_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC24_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC24_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC24_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC25_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC25_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC25_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC25_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC26_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC26_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC26_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC26_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PC27_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC27_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PC27_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC27_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PX00_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX00_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PX00_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX00_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PX01_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX01_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PX01_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX01_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PX02_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX02_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PX02_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX02_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PX03_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX03_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PX03_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX03_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PX04_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX04_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PX04_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX04_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PX05_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX05_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PX05_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX05_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PX06_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX06_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PX06_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX06_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PX07_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX07_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PX07_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX07_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PY00_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY00_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PY00_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY00_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PY01_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY01_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PY01_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY01_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PY02_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY02_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PY02_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY02_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PY03_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY03_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PY03_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY03_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PY04_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY04_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PY04_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY04_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PY05_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY05_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PY05_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY05_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PY06_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY06_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PY06_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY06_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PY07_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY07_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PY07_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY07_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PZ00_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ00_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PZ00_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ00_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PZ01_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ01_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PZ01_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ01_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PZ02_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ02_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PZ02_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ02_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PZ03_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ03_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PZ03_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ03_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PZ04_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ04_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PZ04_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ04_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PZ05_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ05_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PZ05_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ05_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PZ06_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ06_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PZ06_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ06_PAD_CTL_OFFSET )
|
||||
#define HPM_IOC_PAD_PZ07_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ07_FUNC_CTL_OFFSET)
|
||||
#define HPM_IOC_PAD_PZ07_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ07_PAD_CTL_OFFSET )
|
||||
|
||||
#define HPM_PIOC_PAD_FUNC_CTL_ADDRESS(n) (HPM_PIOC_BASE + HPM_IOC_PAD_FUNC_CTL_OFFSET(n))
|
||||
#define HPM_PIOC_PAD_PAD_CTL_ADDRESS(n) (HPM_PIOC_BASE + HPM_IOC_PAD_PAD_CTL_OFFSET(n))
|
||||
|
||||
#define HPM_PIOC_PAD_PY00_FUNC_CTL (HPM_PIOC_BASE + HPM_IOC_PAD_PY00_FUNC_CTL_OFFSET)
|
||||
#define HPM_PIOC_PAD_PY01_FUNC_CTL (HPM_PIOC_BASE + HPM_IOC_PAD_PY01_FUNC_CTL_OFFSET)
|
||||
#define HPM_PIOC_PAD_PY02_FUNC_CTL (HPM_PIOC_BASE + HPM_IOC_PAD_PY02_FUNC_CTL_OFFSET)
|
||||
#define HPM_PIOC_PAD_PY03_FUNC_CTL (HPM_PIOC_BASE + HPM_IOC_PAD_PY03_FUNC_CTL_OFFSET)
|
||||
#define HPM_PIOC_PAD_PY04_FUNC_CTL (HPM_PIOC_BASE + HPM_IOC_PAD_PY04_FUNC_CTL_OFFSET)
|
||||
#define HPM_PIOC_PAD_PY05_FUNC_CTL (HPM_PIOC_BASE + HPM_IOC_PAD_PY05_FUNC_CTL_OFFSET)
|
||||
#define HPM_PIOC_PAD_PY06_FUNC_CTL (HPM_PIOC_BASE + HPM_IOC_PAD_PY06_FUNC_CTL_OFFSET)
|
||||
#define HPM_PIOC_PAD_PY07_FUNC_CTL (HPM_PIOC_BASE + HPM_IOC_PAD_PY07_FUNC_CTL_OFFSET)
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_IOC_H */
|
||||
141
arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_memorymap.h
Normal file
141
arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_memorymap.h
Normal file
@ -0,0 +1,141 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_memorymap.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_MEMORYMAP_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_MEMORYMAP_H
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register Base Address ****************************************************/
|
||||
|
||||
#define HPM_PLIC_BASE 0xE4000000
|
||||
#define HPM_MCHTMR_BASE 0xE6000000
|
||||
#define HPM_GPIO0_BASE 0xF0000000
|
||||
|
||||
#define HPM_GPIOM_BASE 0xF0008000
|
||||
#define HPM_ADC0_BASE 0xF0010000
|
||||
#define HPM_ADC1_BASE 0xF0014000
|
||||
#define HPM_ADC2_BASE 0xF0018000
|
||||
|
||||
#define HPM_ACMP_BASE 0xF0020000
|
||||
#define HPM_DAC_BASE 0Xf0024000
|
||||
#define HPM_SPI0_BASE 0xF0030000
|
||||
#define HPM_SPI1_BASE 0xF0034000
|
||||
#define HPM_SPI2_BASE 0xF0038000
|
||||
#define HPM_SPI3_BASE 0xF003c000
|
||||
#define HPM_UART0_BASE 0xF0040000
|
||||
#define HPM_UART1_BASE 0xF0044000
|
||||
#define HPM_UART2_BASE 0xF0048000
|
||||
#define HPM_UART3_BASE 0xF004C000
|
||||
#define HPM_UART4_BASE 0xF0050000
|
||||
#define HPM_UART5_BASE 0xF0054000
|
||||
#define HPM_UART6_BASE 0xF0058000
|
||||
#define HPM_UART7_BASE 0xF005C000
|
||||
|
||||
#define HPM_CAN0_BASE 0xF0080000
|
||||
#define HPM_CAN1_BASE 0xF0084000
|
||||
|
||||
#define HPM_WDG0_BASE 0xF0090000
|
||||
#define HPM_WDG1_BASE 0xF0094000
|
||||
|
||||
#define HPM_MBX0A_BASE 0xF00A0000
|
||||
#define HPM_MBX0B_BASE 0xF00A4000
|
||||
|
||||
#define HPM_PTPC_BASE 0xF00B0000
|
||||
#define HPM_DMAMUX_BASE 0xF00C0000
|
||||
#define HPM_HDMA_BASE 0xF00C4000
|
||||
#define HPM_RNG_BASE 0xF00C8000
|
||||
#define HPM_KEYM_BASE 0xF00CC000
|
||||
#define HPM_I2S0_BASE 0xF0100000
|
||||
#define HPM_I2S1_BASE 0xF0104000
|
||||
|
||||
#define HPM_DAO_BASE 0xF0110000
|
||||
#define HPM_PDM_BASE 0xF0114000
|
||||
#define HPM_PWM0_BASE 0xF0200000
|
||||
#define HPM_HALL0_BASE 0xF0204000
|
||||
#define HPM_QEI0_BASE 0xF0208000
|
||||
#define HPM_TRGM0_BASE 0xF020C000
|
||||
#define HPM_PWM1_BASE 0xF0210000
|
||||
#define HPM_HALL1_BASE 0xF0214000
|
||||
#define HPM_QEI1_BASE 0xF0218000
|
||||
#define HPM_TRGM1_BASE 0xF021C000
|
||||
|
||||
#define HPM_SYNT_BASE 0xF0240000
|
||||
|
||||
#define HPM_ENET0_BASE 0xF2000000
|
||||
|
||||
#define HPM_NTMR0_BASE 0xF2010000
|
||||
|
||||
#define HPM_USB0_BASE 0xF2020000
|
||||
|
||||
#define HPM_SDXC0_BASE 0xF2030000
|
||||
|
||||
#define HPM_CONCTL_BASE 0xF2040000
|
||||
#define HPM_GPTMR0_BASE 0xF3000000
|
||||
#define HPM_GPTMR1_BASE 0xF3004000
|
||||
#define HPM_GPTMR2_BASE 0xF3008000
|
||||
#define HPM_GPTMR3_BASE 0xF300C000
|
||||
|
||||
#define HPM_I2C0_BASE 0xF3020000
|
||||
#define HPM_I2C1_BASE 0xF3020000
|
||||
#define HPM_I2C2_BASE 0xF3020000
|
||||
#define HPM_I2C3_BASE 0xF3020000
|
||||
#define HPM_XPI0_BASE 0xF3040000
|
||||
#define HPM_XPI1_BASE 0xF3044000
|
||||
#define HPM_XDMA_BASE 0xF3048000
|
||||
#define HPM_SDP_BASE 0xF304C000
|
||||
#define HPM_FEMC_BASE 0xF3050000
|
||||
#define HPM_ROMC_BASE 0xF3054000
|
||||
#define HPM_FFA_BASE 0xF3058000
|
||||
#define HPM_SYSCTL_BASE 0xF4000000
|
||||
#define HPM_IOC_BASE 0xF4040000
|
||||
#define HPM_OTPSHW_BASE 0xF4080000
|
||||
#define HPM_PPOR_BASE 0xF40C0000
|
||||
#define HPM_PCFG_BASE 0xF40C4000
|
||||
#define HPM_OTP_BASE 0xF40C8000
|
||||
#define HPM_PSEC_BASE 0xF40CC000
|
||||
#define HPM_PMON_BASE 0xF40D0000
|
||||
#define HPM_PGPR_BASE 0xF40D4000
|
||||
#define HPM_PIOC_BASE 0xF40D8000
|
||||
#define HPM_PGPIO_BASE 0xF40DC000
|
||||
#define HPM_PTMR_BASE 0xF40E0000
|
||||
#define HPM_PUART_BASE 0xF40E4000
|
||||
#define HPM_PWDG_BASE 0xF40E8000
|
||||
|
||||
#define HPM_PLLCTL_BASE 0xF4100000
|
||||
#define HPM_TSNS_BASE 0xF4104000
|
||||
#define HPM_BACC_BASE 0xF5000000
|
||||
#define HPM_BPOR_BASE 0xF5004000
|
||||
#define HPM_BCFG_BASE 0xF5008000
|
||||
#define HPM_BUTN_BASE 0xF500C000
|
||||
#define HPM_BIOC_BASE 0xF5010000
|
||||
#define HPM_BGPIO_BASE 0xF5014000
|
||||
#define HPM_BGPR_BASE 0xF5018000
|
||||
#define HPM_RTCSHW_BASE 0xF501C000
|
||||
#define HPM_BSEC_BASE 0xF5040000
|
||||
#define HPM_RTC_BASE 0xF5044000
|
||||
#define HPM_BKEY_BASE 0xF5048000
|
||||
#define HPM_BMON_BASE 0xF504C000
|
||||
#define HPM_TAMP_BASE 0xF5050000
|
||||
#define HPM_MONO_BASE 0xF5054000
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_MEMORYMAP_H */
|
||||
118
arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_pcfg.h
Normal file
118
arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_pcfg.h
Normal file
@ -0,0 +1,118 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_pcfg.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_PCFG_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_PCFG_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "hpm_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define HPM_PCFG_BANDGAP (HPM_PCFG_BASE + 0x0000)
|
||||
#define HPM_PCFG_LDO1P1 (HPM_PCFG_BASE + 0x0004)
|
||||
#define HPM_PCFG_LDO2P5 (HPM_PCFG_BASE + 0x0008)
|
||||
#define HPM_PCFG_DCDC_MODE (HPM_PCFG_BASE + 0x0010)
|
||||
#define HPM_PCFG_DCDC_LPMODE (HPM_PCFG_BASE + 0x0014)
|
||||
#define HPM_PCFG_DCDC_PROT (HPM_PCFG_BASE + 0x0018)
|
||||
#define HPM_PCFG_DCDC_CURRENT (HPM_PCFG_BASE + 0x001C)
|
||||
#define HPM_PCFG_DCDC_ADVMODE (HPM_PCFG_BASE + 0x0020)
|
||||
#define HPM_PCFG_DCDC_ADVPARAM (HPM_PCFG_BASE + 0x0024)
|
||||
#define HPM_PCFG_DCDC_MISC (HPM_PCFG_BASE + 0x0028)
|
||||
#define HPM_PCFG_DCDC_DEBUG (HPM_PCFG_BASE + 0x002C)
|
||||
#define HPM_PCFG_DCDC_START_TIME (HPM_PCFG_BASE + 0x0030)
|
||||
#define HPM_PCFG_DCDC_RESUME_TIME (HPM_PCFG_BASE + 0x0034)
|
||||
#define HPM_PCFG_POWER_TRAP (HPM_PCFG_BASE + 0x0040)
|
||||
#define HPM_PCFG_WAKE_CAUSE (HPM_PCFG_BASE + 0x0044)
|
||||
#define HPM_PCFG_WAK_MASK (HPM_PCFG_BASE + 0x0048)
|
||||
#define HPM_PCFG_SCG_CTRL (HPM_PCFG_BASE + 0x004C)
|
||||
#define HPM_PCFG_DEBUG_STOP (HPM_PCFG_BASE + 0x0050)
|
||||
#define HPM_PCFG_RC24M (HPM_PCFG_BASE + 0x0060)
|
||||
#define HPM_PCFG_RC24M_TRACK (HPM_PCFG_BASE + 0x0064)
|
||||
#define HPM_PCFG_TRACK_TARGET (HPM_PCFG_BASE + 0x0068)
|
||||
#define HPM_PCFG_STATUS (HPM_PCFG_BASE + 0x006C)
|
||||
|
||||
#define HPM_PCFG_BANDGAP_VBG_P50_TRIM_SHIFT (0)
|
||||
#define HPM_PCFG_BANDGAP_VBG_P50_TRIM_MASK (0x1F << HPM_PCFG_BANDGAP_VBG_P50_TRIM_SHIFT)
|
||||
#define HPM_PCFG_BANDGAP_VBG_P50_TRIM(n) ((n) << HPM_PCFG_BANDGAP_VBG_P50_TRIM_SHIFT)
|
||||
|
||||
#define HPM_PCFG_BANDGAP_VBG_P65_TRIM_SHIFT (8)
|
||||
#define HPM_PCFG_BANDGAP_VBG_P65_TRIM_MASK (0x1F << HPM_PCFG_BANDGAP_VBG_P65_TRIM_SHIFT)
|
||||
#define HPM_PCFG_BANDGAP_VBG_P65_TRIM(n) ((n) << HPM_PCFG_BANDGAP_VBG_P65_TRIM_SHIFT)
|
||||
|
||||
#define HPM_PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT (16)
|
||||
#define HPM_PCFG_BANDGAP_VBG_1P0_TRIM_MASK (0x1F << HPM_PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT)
|
||||
#define HPM_PCFG_BANDGAP_VBG_1P0_TRIM(n) ((n) << HPM_PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT)
|
||||
|
||||
#define HPM_PCFG_BANDGAP_POWER_SAVE_SHIFT (24)
|
||||
#define HPM_PCFG_BANDGAP_POWER_SAVE_NORMAL (0 << HPM_PCFG_BANDGAP_POWER_SAVE_SHIFT)
|
||||
#define HPM_PCFG_BANDGAP_POWER_SAVE_LOW (1 << HPM_PCFG_BANDGAP_POWER_SAVE_SHIFT)
|
||||
|
||||
#define HPM_PCFG_BANDGAP_LOWPOWER_MODE_SHIFT (25)
|
||||
#define HPM_PCFG_BANDGAP_LOWPOWER_MODE_NORMAL (0 << HPM_PCFG_BANDGAP_LOWPOWER_MODE_SHIFT)
|
||||
#define HPM_PCFG_BANDGAP_LOWPOWER_MODE_LOW (1 << HPM_PCFG_BANDGAP_LOWPOWER_MODE_SHIFT)
|
||||
|
||||
#define HPM_PCFG_BANDGAP_VBG_TRIMMED_SHIFT (31)
|
||||
#define HPM_PCFG_BANDGAP_VBG_TRIMMED_UNCALIBRATED (0 << HPM_PCFG_BANDGAP_VBG_TRIMMED_SHIFT)
|
||||
#define HPM_PCFG_BANDGAP_VBG_TRIMMED_CALIBRATED (1 << HPM_PCFG_BANDGAP_VBG_TRIMMED_SHIFT)
|
||||
|
||||
#define HPM_PCFG_LDO1P1_VOLT_SHIFT (0)
|
||||
#define HPM_PCFG_LDO1P1_VOLT_MASK (0x7FF << HPM_PCFG_LDO1P1_VOLT_SHIFT)
|
||||
#define HPM_PCFG_LDO1P1_VOLT(n) ((n) << HPM_PCFG_LDO1P1_VOLT_SHIFT)
|
||||
|
||||
#define HPM_PCFG_LDO2P5_VOLT_SHIFT (0)
|
||||
#define HPM_PCFG_LDO2P5_VOLT_MASK (0x7FF << HPM_PCFG_LDO2P5_VOLT_SHIFT)
|
||||
#define HPM_PCFG_LDO2P5_VOLT(n) ((n) << HPM_PCFG_LDO2P5_VOLT_SHIFT)
|
||||
|
||||
#define HPM_PCFG_LDO2P5_ENABLE_SHIFT (16)
|
||||
#define HPM_PCFG_LDO2P5_ENABLE_DISABL (0 << HPM_PCFG_LDO2P5_ENABLE_SHIFT)
|
||||
#define HPM_PCFG_LDO2P5_ENABLE_ENABLE (1 << HPM_PCFG_LDO2P5_ENABLE_SHIFT)
|
||||
|
||||
#define HPM_PCFG_LDO2P5_READY_SHIFT (28)
|
||||
#define HPM_PCFG_LDO2P5_READY_NOT_RE (0 << HPM_PCFG_LDO2P5_READY_SHIFT)
|
||||
#define HPM_PCFG_LDO2P5_READY_READY (1 << HPM_PCFG_LDO2P5_READY_SHIFT)
|
||||
|
||||
#define HPM_PCFG_DCDC_MODE_VOLT_SHIFT (0)
|
||||
#define HPM_PCFG_DCDC_MODE_VOLT_MASK (0x7FF << HPM_PCFG_DCDC_MODE_VOLT_SHIFT)
|
||||
#define HPM_PCFG_DCDC_MODE_VOLT(n) ((n) << HPM_PCFG_DCDC_MODE_VOLT_SHIFT)
|
||||
|
||||
#define HPM_PCFG_DCDC_MODE_MODE_SHIFT (16)
|
||||
#define HPM_PCFG_DCDC_MODE_MODE_MASK (0x07 << HPM_PCFG_DCDC_MODE_MODE_SHIFT)
|
||||
#define HPM_PCFG_DCDC_MODE_MODE(n) ((n) << HPM_PCFG_DCDC_MODE_MODE_SHIFT)
|
||||
#define HPM_PCFG_DCDC_MODE_CLOSE (0 << HPM_PCFG_DCDC_MODE_MODE_SHIFT)
|
||||
#define HPM_PCFG_DCDC_MODE_NORMAL (1 << HPM_PCFG_DCDC_MODE_MODE_SHIFT)
|
||||
#define HPM_PCFG_DCDC_MODE_UNIVERSAL (3 << HPM_PCFG_DCDC_MODE_MODE_SHIFT)
|
||||
#define HPM_PCFG_DCDC_MODE_PRO (7 << HPM_PCFG_DCDC_MODE_MODE_SHIFT)
|
||||
|
||||
#define HPM_PCFG_DCDC_MODE_READY_SHIFT (28)
|
||||
#define HPM_PCFG_DCDC_MODE_READY_NOT_READY (0 << HPM_PCFG_DCDC_MODE_READY_SHIFT)
|
||||
#define HPM_PCFG_DCDC_MODE_READY_READY (1 << HPM_PCFG_DCDC_MODE_READY_SHIFT)
|
||||
|
||||
#define HPM_PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT (0)
|
||||
#define HPM_PCFG_DCDC_LPMODE_STBY_VOLT_MASK (0x7FF << HPM_PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT)
|
||||
#define HPM_PCFG_DCDC_LPMODE_STBY_VOLT(n) ((n) << HPM_PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT)
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_PCFG_H */
|
||||
112
arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_pinmux.h
Normal file
112
arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_pinmux.h
Normal file
@ -0,0 +1,112 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_pinmux.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_PINMUX_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_PINMUX_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "hpm_ioc.h"
|
||||
#include "hpm_gpio.h"
|
||||
|
||||
#define GPIO_UART0_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA30_INDEX))
|
||||
#define GPIO_UART0_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB22_INDEX))
|
||||
#define GPIO_UART0_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC22_INDEX))
|
||||
#define GPIO_UART0_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PY06_INDEX))
|
||||
|
||||
#define GPIO_UART0_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA31_INDEX))
|
||||
#define GPIO_UART0_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB23_INDEX))
|
||||
#define GPIO_UART0_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC23_INDEX))
|
||||
#define GPIO_UART0_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PY07_INDEX))
|
||||
|
||||
#define GPIO_UART1_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA00_INDEX))
|
||||
#define GPIO_UART1_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB00_INDEX))
|
||||
#define GPIO_UART1_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB24_INDEX))
|
||||
#define GPIO_UART1_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC24_INDEX))
|
||||
|
||||
#define GPIO_UART1_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA01_INDEX))
|
||||
#define GPIO_UART1_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB01_INDEX))
|
||||
#define GPIO_UART1_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB25_INDEX))
|
||||
#define GPIO_UART1_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC25_INDEX))
|
||||
|
||||
#define GPIO_UART2_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA02_INDEX))
|
||||
#define GPIO_UART2_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB02_INDEX))
|
||||
#define GPIO_UART2_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB26_INDEX))
|
||||
#define GPIO_UART2_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC26_INDEX))
|
||||
|
||||
#define GPIO_UART2_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA03_INDEX))
|
||||
#define GPIO_UART2_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB03_INDEX))
|
||||
#define GPIO_UART2_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB27_INDEX))
|
||||
#define GPIO_UART2_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC27_INDEX))
|
||||
|
||||
#define GPIO_UART3_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA04_INDEX))
|
||||
#define GPIO_UART3_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB04_INDEX))
|
||||
#define GPIO_UART3_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB28_INDEX))
|
||||
#define GPIO_UART3_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ00_INDEX))
|
||||
|
||||
#define GPIO_UART3_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA05_INDEX))
|
||||
#define GPIO_UART3_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB05_INDEX))
|
||||
#define GPIO_UART3_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB28_INDEX))
|
||||
#define GPIO_UART3_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ01_INDEX))
|
||||
|
||||
#define GPIO_UART4_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA14_INDEX))
|
||||
#define GPIO_UART4_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB06_INDEX))
|
||||
#define GPIO_UART4_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC06_INDEX))
|
||||
#define GPIO_UART4_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ02_INDEX))
|
||||
|
||||
#define GPIO_UART4_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA15_INDEX))
|
||||
#define GPIO_UART4_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB07_INDEX))
|
||||
#define GPIO_UART4_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC07_INDEX))
|
||||
#define GPIO_UART4_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ03_INDEX))
|
||||
|
||||
#define GPIO_UART5_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA16_INDEX))
|
||||
#define GPIO_UART5_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB08_INDEX))
|
||||
#define GPIO_UART5_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC08_INDEX))
|
||||
#define GPIO_UART5_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ04_INDEX))
|
||||
|
||||
#define GPIO_UART5_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA17_INDEX))
|
||||
#define GPIO_UART5_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB09_INDEX))
|
||||
#define GPIO_UART5_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC09_INDEX))
|
||||
#define GPIO_UART5_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ05_INDEX))
|
||||
|
||||
#define GPIO_UART6_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA18_INDEX))
|
||||
#define GPIO_UART6_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB10_INDEX))
|
||||
#define GPIO_UART6_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC10_INDEX))
|
||||
#define GPIO_UART6_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ06_INDEX))
|
||||
|
||||
#define GPIO_UART6_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA19_INDEX))
|
||||
#define GPIO_UART6_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB11_INDEX))
|
||||
#define GPIO_UART6_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC11_INDEX))
|
||||
#define GPIO_UART6_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ07_INDEX))
|
||||
|
||||
#define GPIO_UART7_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA20_INDEX))
|
||||
#define GPIO_UART7_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB12_INDEX))
|
||||
#define GPIO_UART7_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC12_INDEX))
|
||||
#define GPIO_UART7_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PY04_INDEX))
|
||||
|
||||
#define GPIO_UART7_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA21_INDEX))
|
||||
#define GPIO_UART7_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB13_INDEX))
|
||||
#define GPIO_UART7_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC13_INDEX))
|
||||
#define GPIO_UART7_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PY05_INDEX))
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_PINMUX_H */
|
||||
693
arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_sysctl.h
Normal file
693
arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_sysctl.h
Normal file
@ -0,0 +1,693 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_sysctl.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_SYSCTL_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_SYSCTL_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "hpm6300_memorymap.h"
|
||||
|
||||
#define HPM_SYSCTL_RESOURCE_CPU0 (HPM_SYSCTL_BASE + 0x0000)
|
||||
#define HPM_SYSCTL_RESOURCE_CPX0 (HPM_SYSCTL_BASE + 0x0004)
|
||||
#define HPM_SYSCTL_RESOURCE_POW_CPU0 (HPM_SYSCTL_BASE + 0x0054)
|
||||
#define HPM_SYSCTL_RESOURCE_RST_SOC (HPM_SYSCTL_BASE + 0x0058)
|
||||
#define HPM_SYSCTL_RESOURCE_RST_CPU0 (HPM_SYSCTL_BASE + 0x005c)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_SRC_XTAL (HPM_SYSCTL_BASE + 0x0080)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_SRC_PLL0 (HPM_SYSCTL_BASE + 0x0084)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0 (HPM_SYSCTL_BASE + 0x0088)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0 (HPM_SYSCTL_BASE + 0x008c)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL0 (HPM_SYSCTL_BASE + 0x0090)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_SRC_PLL1 (HPM_SYSCTL_BASE + 0x0094)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1 (HPM_SYSCTL_BASE + 0x0098)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1 (HPM_SYSCTL_BASE + 0x009c)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_SRC_PLL2 (HPM_SYSCTL_BASE + 0x00a0)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2 (HPM_SYSCTL_BASE + 0x00a4)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2 (HPM_SYSCTL_BASE + 0x00a8)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_SRC_PLL0_REF (HPM_SYSCTL_BASE + 0x00ac)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_SRC_PLL1_REF (HPM_SYSCTL_BASE + 0x00b0)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_SRC_PLL2_REF (HPM_SYSCTL_BASE + 0x00b4)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_CPU0 (HPM_SYSCTL_BASE + 0x0100)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_MCT0 (HPM_SYSCTL_BASE + 0x0104)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_FEMC (HPM_SYSCTL_BASE + 0x0108)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_XPI0 (HPM_SYSCTL_BASE + 0x010c)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_XPI1 (HPM_SYSCTL_BASE + 0x0110)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_TMR0 (HPM_SYSCTL_BASE + 0x0114)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_TMR1 (HPM_SYSCTL_BASE + 0x0118)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_TMR2 (HPM_SYSCTL_BASE + 0x011c)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_TMR3 (HPM_SYSCTL_BASE + 0x0120)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART0 (HPM_SYSCTL_BASE + 0x0124)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART1 (HPM_SYSCTL_BASE + 0x0128)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART2 (HPM_SYSCTL_BASE + 0x012c)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART3 (HPM_SYSCTL_BASE + 0x0130)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART4 (HPM_SYSCTL_BASE + 0x0134)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART5 (HPM_SYSCTL_BASE + 0x0138)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART6 (HPM_SYSCTL_BASE + 0x013c)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART7 (HPM_SYSCTL_BASE + 0x0140)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_I2C0 (HPM_SYSCTL_BASE + 0x0144)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_IC21 (HPM_SYSCTL_BASE + 0x0148)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_IC22 (HPM_SYSCTL_BASE + 0x014c)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_IC23 (HPM_SYSCTL_BASE + 0x0150)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_SPI0 (HPM_SYSCTL_BASE + 0x0154)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_SPI1 (HPM_SYSCTL_BASE + 0x0158)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_SPI2 (HPM_SYSCTL_BASE + 0x015c)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_SPI3 (HPM_SYSCTL_BASE + 0x0160)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_CAN0 (HPM_SYSCTL_BASE + 0x0164)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_CAN1 (HPM_SYSCTL_BASE + 0x0168)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_PTPC (HPM_SYSCTL_BASE + 0x016c)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_ANA0 (HPM_SYSCTL_BASE + 0x0170)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_ANA1 (HPM_SYSCTL_BASE + 0x0174)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_ANA2 (HPM_SYSCTL_BASE + 0x0178)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_ANA3 (HPM_SYSCTL_BASE + 0x017c)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_AUD0 (HPM_SYSCTL_BASE + 0x0180)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_AUD1 (HPM_SYSCTL_BASE + 0x0184)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_ETH0 (HPM_SYSCTL_BASE + 0x0188)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_PTP0 (HPM_SYSCTL_BASE + 0x018c)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_REF0 (HPM_SYSCTL_BASE + 0x0190)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_REF1 (HPM_SYSCTL_BASE + 0x0194)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_NTM0 (HPM_SYSCTL_BASE + 0x0198)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_SDC0 (HPM_SYSCTL_BASE + 0x019c)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_ADC0 (HPM_SYSCTL_BASE + 0x0200)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_ADC1 (HPM_SYSCTL_BASE + 0x0204)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_ADC2 (HPM_SYSCTL_BASE + 0x0208)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_DAC0 (HPM_SYSCTL_BASE + 0x020c)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_I2S0 (HPM_SYSCTL_BASE + 0x0210)
|
||||
#define HPM_SYSCTL_RESOURCE_CLK_TOP_I2S1 (HPM_SYSCTL_BASE + 0x0214)
|
||||
#define HPM_SYSCTL_RESOURCE_AHBP (HPM_SYSCTL_BASE + 0x0400)
|
||||
#define HPM_SYSCTL_RESOURCE_AXIS (HPM_SYSCTL_BASE + 0x0404)
|
||||
#define HPM_SYSCTL_RESOURCE_AXIC (HPM_SYSCTL_BASE + 0x0408)
|
||||
#define HPM_SYSCTL_RESOURCE_FEMC (HPM_SYSCTL_BASE + 0x040c)
|
||||
#define HPM_SYSCTL_RESOURCE_ROM0 (HPM_SYSCTL_BASE + 0x0410)
|
||||
#define HPM_SYSCTL_RESOURCE_LMM0 (HPM_SYSCTL_BASE + 0x0414)
|
||||
#define HPM_SYSCTL_RESOURCE_RAM0 (HPM_SYSCTL_BASE + 0x0418)
|
||||
#define HPM_SYSCTL_RESOURCE_MCT0 (HPM_SYSCTL_BASE + 0x041c)
|
||||
#define HPM_SYSCTL_RESOURCE_XPI0 (HPM_SYSCTL_BASE + 0x0420)
|
||||
#define HPM_SYSCTL_RESOURCE_XPI1 (HPM_SYSCTL_BASE + 0x0424)
|
||||
#define HPM_SYSCTL_RESOURCE_SDP0 (HPM_SYSCTL_BASE + 0x0428)
|
||||
#define HPM_SYSCTL_RESOURCE_RNG0 (HPM_SYSCTL_BASE + 0x042c)
|
||||
#define HPM_SYSCTL_RESOURCE_KMAN (HPM_SYSCTL_BASE + 0x0430)
|
||||
#define HPM_SYSCTL_RESOURCE_DMA0 (HPM_SYSCTL_BASE + 0x0434)
|
||||
#define HPM_SYSCTL_RESOURCE_DMA1 (HPM_SYSCTL_BASE + 0x0438)
|
||||
#define HPM_SYSCTL_RESOURCE_FFA0 (HPM_SYSCTL_BASE + 0x043c)
|
||||
#define HPM_SYSCTL_RESOURCE_GPIO (HPM_SYSCTL_BASE + 0x0440)
|
||||
#define HPM_SYSCTL_RESOURCE_MBX0 (HPM_SYSCTL_BASE + 0x0444)
|
||||
#define HPM_SYSCTL_RESOURCE_WDG0 (HPM_SYSCTL_BASE + 0x0448)
|
||||
#define HPM_SYSCTL_RESOURCE_WDG1 (HPM_SYSCTL_BASE + 0x044c)
|
||||
#define HPM_SYSCTL_RESOURCE_TSNS (HPM_SYSCTL_BASE + 0x0450)
|
||||
#define HPM_SYSCTL_RESOURCE_TMR0 (HPM_SYSCTL_BASE + 0x0454)
|
||||
#define HPM_SYSCTL_RESOURCE_TMR1 (HPM_SYSCTL_BASE + 0x0458)
|
||||
#define HPM_SYSCTL_RESOURCE_RMR2 (HPM_SYSCTL_BASE + 0x045c)
|
||||
#define HPM_SYSCTL_RESOURCE_TMR3 (HPM_SYSCTL_BASE + 0x0460)
|
||||
#define HPM_SYSCTL_RESOURCE_URT0 (HPM_SYSCTL_BASE + 0x0464)
|
||||
#define HPM_SYSCTL_RESOURCE_URT1 (HPM_SYSCTL_BASE + 0x0468)
|
||||
#define HPM_SYSCTL_RESOURCE_URT2 (HPM_SYSCTL_BASE + 0x046c)
|
||||
#define HPM_SYSCTL_RESOURCE_URT3 (HPM_SYSCTL_BASE + 0x0470)
|
||||
#define HPM_SYSCTL_RESOURCE_URT4 (HPM_SYSCTL_BASE + 0x0474)
|
||||
#define HPM_SYSCTL_RESOURCE_URT5 (HPM_SYSCTL_BASE + 0x0478)
|
||||
#define HPM_SYSCTL_RESOURCE_URT6 (HPM_SYSCTL_BASE + 0x047c)
|
||||
#define HPM_SYSCTL_RESOURCE_URT7 (HPM_SYSCTL_BASE + 0x0480)
|
||||
#define HPM_SYSCTL_RESOURCE_I2C0 (HPM_SYSCTL_BASE + 0x0484)
|
||||
#define HPM_SYSCTL_RESOURCE_I2C1 (HPM_SYSCTL_BASE + 0x0488)
|
||||
#define HPM_SYSCTL_RESOURCE_I2C2 (HPM_SYSCTL_BASE + 0x048c)
|
||||
#define HPM_SYSCTL_RESOURCE_I2C3 (HPM_SYSCTL_BASE + 0x0490)
|
||||
#define HPM_SYSCTL_RESOURCE_SPI0 (HPM_SYSCTL_BASE + 0x0494)
|
||||
#define HPM_SYSCTL_RESOURCE_SPI1 (HPM_SYSCTL_BASE + 0x0498)
|
||||
#define HPM_SYSCTL_RESOURCE_SPI2 (HPM_SYSCTL_BASE + 0x049c)
|
||||
#define HPM_SYSCTL_RESOURCE_SPI3 (HPM_SYSCTL_BASE + 0x04a0)
|
||||
#define HPM_SYSCTL_RESOURCE_CAN0 (HPM_SYSCTL_BASE + 0x04a4)
|
||||
#define HPM_SYSCTL_RESOURCE_CAN1 (HPM_SYSCTL_BASE + 0x04a8)
|
||||
#define HPM_SYSCTL_RESOURCE_PTPC (HPM_SYSCTL_BASE + 0x04ac)
|
||||
#define HPM_SYSCTL_RESOURCE_ADC0 (HPM_SYSCTL_BASE + 0x04b0)
|
||||
#define HPM_SYSCTL_RESOURCE_ADC1 (HPM_SYSCTL_BASE + 0x04b4)
|
||||
#define HPM_SYSCTL_RESOURCE_ADC2 (HPM_SYSCTL_BASE + 0x04b8)
|
||||
#define HPM_SYSCTL_RESOURCE_DAC0 (HPM_SYSCTL_BASE + 0x04bc)
|
||||
#define HPM_SYSCTL_RESOURCE_ACMP (HPM_SYSCTL_BASE + 0x04c0)
|
||||
#define HPM_SYSCTL_RESOURCE_I2S0 (HPM_SYSCTL_BASE + 0x04c4)
|
||||
#define HPM_SYSCTL_RESOURCE_I2S1 (HPM_SYSCTL_BASE + 0x04c8)
|
||||
#define HPM_SYSCTL_RESOURCE_PDM0 (HPM_SYSCTL_BASE + 0x04cc)
|
||||
#define HPM_SYSCTL_RESOURCE_DAO (HPM_SYSCTL_BASE + 0x04d0)
|
||||
#define HPM_SYSCTL_RESOURCE_MSYN (HPM_SYSCTL_BASE + 0x04d4)
|
||||
#define HPM_SYSCTL_RESOURCE_MOT0 (HPM_SYSCTL_BASE + 0x04d8)
|
||||
#define HPM_SYSCTL_RESOURCE_MOT1 (HPM_SYSCTL_BASE + 0x04dc)
|
||||
#define HPM_SYSCTL_RESOURCE_ETH0 (HPM_SYSCTL_BASE + 0x04e0)
|
||||
#define HPM_SYSCTL_RESOURCE_NTM0 (HPM_SYSCTL_BASE + 0x04e4)
|
||||
#define HPM_SYSCTL_RESOURCE_SDC0 (HPM_SYSCTL_BASE + 0x04e8)
|
||||
#define HPM_SYSCTL_RESOURCE_USB0 (HPM_SYSCTL_BASE + 0x04ec)
|
||||
#define HPM_SYSCTL_RESOURCE_REF0 (HPM_SYSCTL_BASE + 0x04f0)
|
||||
#define HPM_SYSCTL_RESOURCE_REF1 (HPM_SYSCTL_BASE + 0x04f4)
|
||||
#define HPM_SYSCTL_GROUP0_LINK0_VALUE (HPM_SYSCTL_BASE + 0x0800)
|
||||
#define HPM_SYSCTL_GROUP0_LINK0_SET (HPM_SYSCTL_BASE + 0x0804)
|
||||
#define HPM_SYSCTL_GROUP0_LINK0_CLEAR (HPM_SYSCTL_BASE + 0x0808)
|
||||
#define HPM_SYSCTL_GROUP0_LINK0_TOGGLE (HPM_SYSCTL_BASE + 0x080c)
|
||||
#define HPM_SYSCTL_GROUP0_LINK1_VALUE (HPM_SYSCTL_BASE + 0x0810)
|
||||
#define HPM_SYSCTL_GROUP0_LINK1_SET (HPM_SYSCTL_BASE + 0x0814)
|
||||
#define HPM_SYSCTL_GROUP0_LINK1_CLEAR (HPM_SYSCTL_BASE + 0x0818)
|
||||
#define HPM_SYSCTL_GROUP0_LINK1_TOGGLE (HPM_SYSCTL_BASE + 0x081c)
|
||||
#define HPM_SYSCTL_AFFILIATE_CPU0_VALUE (HPM_SYSCTL_BASE + 0x0900)
|
||||
#define HPM_SYSCTL_AFFILIATE_CPU0_SET (HPM_SYSCTL_BASE + 0x0904)
|
||||
#define HPM_SYSCTL_AFFILIATE_CPU0_CLEAR (HPM_SYSCTL_BASE + 0x0908)
|
||||
#define HPM_SYSCTL_AFFILIATE_CPU0_TOGGLE (HPM_SYSCTL_BASE + 0x090c)
|
||||
#define HPM_SYSCTL_RETENTION_CPU0_VALUE (HPM_SYSCTL_BASE + 0x0920)
|
||||
#define HPM_SYSCTL_RETENTION_CPU0_SET (HPM_SYSCTL_BASE + 0x0924)
|
||||
#define HPM_SYSCTL_RETENTION_CPU0_CLEAR (HPM_SYSCTL_BASE + 0x0928)
|
||||
#define HPM_SYSCTL_RETENTION_CPU0_TOGGLE (HPM_SYSCTL_BASE + 0x092c)
|
||||
#define HPM_SYSCTL_POWER_CPU0_STATUS (HPM_SYSCTL_BASE + 0x1000)
|
||||
#define HPM_SYSCTL_POWER_CPU0_LF_WAIT (HPM_SYSCTL_BASE + 0x1004)
|
||||
#define HPM_SYSCTL_POWER_CPU0_OFF_WAIT (HPM_SYSCTL_BASE + 0x100c)
|
||||
#define HPM_SYSCTL_RESET_SOC_CONTROL (HPM_SYSCTL_BASE + 0x1400)
|
||||
#define HPM_SYSCTL_RESET_SOC_CONFIG (HPM_SYSCTL_BASE + 0x1404)
|
||||
#define HPM_SYSCTL_RESET_SOC_COUNTER (HPM_SYSCTL_BASE + 0x140c)
|
||||
#define HPM_SYSCTL_RESET_CPU0_CONTROL (HPM_SYSCTL_BASE + 0x1410)
|
||||
#define HPM_SYSCTL_RESET_CPU0_CONFIG (HPM_SYSCTL_BASE + 0x1414)
|
||||
#define HPM_SYSCTL_RESET_CPU0_COUNTER (HPM_SYSCTL_BASE + 0x141c)
|
||||
#define HPM_SYSCTL_CLOCK_CPU_CLK_TOP_CPU0 (HPM_SYSCTL_BASE + 0x1800)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_MCT0 (HPM_SYSCTL_BASE + 0x1804)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_FEMC (HPM_SYSCTL_BASE + 0x1808)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_XPI0 (HPM_SYSCTL_BASE + 0x180c)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_XPI1 (HPM_SYSCTL_BASE + 0x1810)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_TMR0 (HPM_SYSCTL_BASE + 0x1814)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_TMR1 (HPM_SYSCTL_BASE + 0x1818)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_TMR2 (HPM_SYSCTL_BASE + 0x181c)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_TMR3 (HPM_SYSCTL_BASE + 0x1820)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_UART0 (HPM_SYSCTL_BASE + 0x1824)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_UART1 (HPM_SYSCTL_BASE + 0x1828)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_UART2 (HPM_SYSCTL_BASE + 0x182c)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_UART3 (HPM_SYSCTL_BASE + 0x1830)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_UART4 (HPM_SYSCTL_BASE + 0x1834)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_UART5 (HPM_SYSCTL_BASE + 0x1838)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_UART6 (HPM_SYSCTL_BASE + 0x183c)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_UART7 (HPM_SYSCTL_BASE + 0x1840)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_I2C0 (HPM_SYSCTL_BASE + 0x1844)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_IC21 (HPM_SYSCTL_BASE + 0x1848)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_IC22 (HPM_SYSCTL_BASE + 0x184c)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_IC23 (HPM_SYSCTL_BASE + 0x1850)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_SPI0 (HPM_SYSCTL_BASE + 0x1854)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_SPI1 (HPM_SYSCTL_BASE + 0x1858)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_SPI2 (HPM_SYSCTL_BASE + 0x185c)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_SPI3 (HPM_SYSCTL_BASE + 0x1860)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_CAN0 (HPM_SYSCTL_BASE + 0x1864)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_CAN1 (HPM_SYSCTL_BASE + 0x1868)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_PTPC (HPM_SYSCTL_BASE + 0x186c)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_ANA0 (HPM_SYSCTL_BASE + 0x1870)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_ANA1 (HPM_SYSCTL_BASE + 0x1874)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_ANA2 (HPM_SYSCTL_BASE + 0x1878)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_ANA3 (HPM_SYSCTL_BASE + 0x187c)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_AUD0 (HPM_SYSCTL_BASE + 0x1880)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_AUD1 (HPM_SYSCTL_BASE + 0x1884)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_ETH0 (HPM_SYSCTL_BASE + 0x1888)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_PTP0 (HPM_SYSCTL_BASE + 0x188c)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_REF0 (HPM_SYSCTL_BASE + 0x1890)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_REF1 (HPM_SYSCTL_BASE + 0x1894)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_NTM0 (HPM_SYSCTL_BASE + 0x1898)
|
||||
#define HPM_SYSCTL_CLOCK_CLK_TOP_SDC0 (HPM_SYSCTL_BASE + 0x189c)
|
||||
#define HPM_SYSCTL_ADCCLK_CLK_TOP_ADC0 (HPM_SYSCTL_BASE + 0x1c00)
|
||||
#define HPM_SYSCTL_ADCCLK_CLK_TOP_ADC1 (HPM_SYSCTL_BASE + 0x1c04)
|
||||
#define HPM_SYSCTL_ADCCLK_CLK_TOP_ADC2 (HPM_SYSCTL_BASE + 0x1c08)
|
||||
#define HPM_SYSCTL_ADCCLK_CLK_TOP_DAC0 (HPM_SYSCTL_BASE + 0x1c0c)
|
||||
#define HPM_SYSCTL_I2SCLK_CLK_TOP_I2S0 (HPM_SYSCTL_BASE + 0x1c10)
|
||||
#define HPM_SYSCTL_I2SCLK_CLK_TOP_I2S1 (HPM_SYSCTL_BASE + 0x1c14)
|
||||
#define HPM_SYSCTL_GLOBAL00 (HPM_SYSCTL_BASE + 0x2000)
|
||||
#define HPM_SYSCTL_MONITOR_SLICE0_CONTROL (HPM_SYSCTL_BASE + 0x2400)
|
||||
#define HPM_SYSCTL_MONITOR_SLICE0_CURRENT (HPM_SYSCTL_BASE + 0x2404)
|
||||
#define HPM_SYSCTL_MONITOR_SLICE0_LOW_LIMIT (HPM_SYSCTL_BASE + 0x2408)
|
||||
#define HPM_SYSCTL_MONITOR_SLICE0_HIGH_LIMIT (HPM_SYSCTL_BASE + 0x240c)
|
||||
#define HPM_SYSCTL_MONITOR_SLICE1_CONTROL (HPM_SYSCTL_BASE + 0x2420)
|
||||
#define HPM_SYSCTL_MONITOR_SLICE1_CURRENT (HPM_SYSCTL_BASE + 0x2424)
|
||||
#define HPM_SYSCTL_MONITOR_SLICE1_LOW_LIMIT (HPM_SYSCTL_BASE + 0x2428)
|
||||
#define HPM_SYSCTL_MONITOR_SLICE1_HIGH_LIMIT (HPM_SYSCTL_BASE + 0x242c)
|
||||
#define HPM_SYSCTL_MONITOR_SLICE2_CONTROL (HPM_SYSCTL_BASE + 0x2440)
|
||||
#define HPM_SYSCTL_MONITOR_SLICE2_CURRENT (HPM_SYSCTL_BASE + 0x2444)
|
||||
#define HPM_SYSCTL_MONITOR_SLICE2_LOW_LIMIT (HPM_SYSCTL_BASE + 0x2448)
|
||||
#define HPM_SYSCTL_MONITOR_SLICE2_HIGH_LIMIT (HPM_SYSCTL_BASE + 0x244c)
|
||||
#define HPM_SYSCTL_MONITOR_SLICE3_CONTROL (HPM_SYSCTL_BASE + 0x2460)
|
||||
#define HPM_SYSCTL_MONITOR_SLICE3_CURRENT (HPM_SYSCTL_BASE + 0x2464)
|
||||
#define HPM_SYSCTL_MONITOR_SLICE3_LOW_LIMIT (HPM_SYSCTL_BASE + 0x2468)
|
||||
#define HPM_SYSCTL_MONITOR_SLICE3_HIGH_LIMIT (HPM_SYSCTL_BASE + 0x246c)
|
||||
#define HPM_SYSCTL_CPU_CPU0_LP (HPM_SYSCTL_BASE + 0x2800)
|
||||
#define HPM_SYSCTL_CPU_CPU0_LOCK (HPM_SYSCTL_BASE + 0x2804)
|
||||
#define HPM_SYSCTL_CPU_CPU0_GPR_GPR0 (HPM_SYSCTL_BASE + 0x2808)
|
||||
#define HPM_SYSCTL_CPU_CPU0_GPR_GPR1 (HPM_SYSCTL_BASE + 0x280c)
|
||||
#define HPM_SYSCTL_CPU_CPU0_GPR_GPR2 (HPM_SYSCTL_BASE + 0x2810)
|
||||
#define HPM_SYSCTL_CPU_CPU0_GPR_GPR3 (HPM_SYSCTL_BASE + 0x2814)
|
||||
#define HPM_SYSCTL_CPU_CPU0_GPR_GPR4 (HPM_SYSCTL_BASE + 0x2818)
|
||||
#define HPM_SYSCTL_CPU_CPU0_GPR_GPR5 (HPM_SYSCTL_BASE + 0x281c)
|
||||
#define HPM_SYSCTL_CPU_CPU0_GPR_GPR6 (HPM_SYSCTL_BASE + 0x2820)
|
||||
#define HPM_SYSCTL_CPU_CPU0_GPR_GPR7 (HPM_SYSCTL_BASE + 0x2824)
|
||||
#define HPM_SYSCTL_CPU_CPU0_GPR_GPR8 (HPM_SYSCTL_BASE + 0x2828)
|
||||
#define HPM_SYSCTL_CPU_CPU0_GPR_GPR9 (HPM_SYSCTL_BASE + 0x282c)
|
||||
#define HPM_SYSCTL_CPU_CPU0_GPR_GPR10 (HPM_SYSCTL_BASE + 0x2830)
|
||||
#define HPM_SYSCTL_CPU_CPU0_GPR_GPR11 (HPM_SYSCTL_BASE + 0x2834)
|
||||
#define HPM_SYSCTL_CPU_CPU0_GPR_GPR12 (HPM_SYSCTL_BASE + 0x2838)
|
||||
#define HPM_SYSCTL_CPU_CPU0_GPR_GPR13 (HPM_SYSCTL_BASE + 0x283c)
|
||||
#define HPM_SYSCTL_CPU_CPU0_WAKEUP_STATUS_STATUS0 (HPM_SYSCTL_BASE + 0x2840)
|
||||
#define HPM_SYSCTL_CPU_CPU0_WAKEUP_STATUS_STATUS1 (HPM_SYSCTL_BASE + 0x2844)
|
||||
#define HPM_SYSCTL_CPU_CPU0_WAKEUP_STATUS_STATUS2 (HPM_SYSCTL_BASE + 0x2848)
|
||||
#define HPM_SYSCTL_CPU_CPU0_WAKEUP_STATUS_STATUS3 (HPM_SYSCTL_BASE + 0x284c)
|
||||
#define HPM_SYSCTL_CPU_CPU0_WAKEUP_ENABLE_ENABLE0 (HPM_SYSCTL_BASE + 0x2880)
|
||||
#define HPM_SYSCTL_CPU_CPU0_WAKEUP_ENABLE_ENABLE1 (HPM_SYSCTL_BASE + 0x2884)
|
||||
#define HPM_SYSCTL_CPU_CPU0_WAKEUP_ENABLE_ENABLE2 (HPM_SYSCTL_BASE + 0x2888)
|
||||
#define HPM_SYSCTL_CPU_CPU0_WAKEUP_ENABLE_ENABLE3 (HPM_SYSCTL_BASE + 0x288c)
|
||||
|
||||
#define SYSCTL_RESOURCE_GLB_BUSY (1 << 31)
|
||||
#define SYSCTL_RESOURCE_LOC_BUSY (1 << 30)
|
||||
#define SYSCTL_RESOURCE_MODE_SHIFT (0U)
|
||||
#define SYSCTL_RESOURCE_MODE_MASK (0x3U << SYSCTL_RESOURCE_MODE_SHIFT)
|
||||
# define SYSCTL_RESOURCE_MODE_AUTO (0 << SYSCTL_RESOURCE_MODE_SHIFT)
|
||||
# define SYSCTL_RESOURCE_MODE_ON (1 << SYSCTL_RESOURCE_MODE_SHIFT)
|
||||
# define SYSCTL_RESOURCE_MODE_OFF (2 << SYSCTL_RESOURCE_MODE_SHIFT)
|
||||
# define SYSCTL_RESOURCE_MODE_RESV (3 << SYSCTL_RESOURCE_MODE_SHIFT)
|
||||
|
||||
#define SYSCTL_GROUP0(n) (1U << (n))
|
||||
|
||||
#define SYSCTL_AFFILIATE(n) (1U << (n))
|
||||
|
||||
#define SYSCTL_RETENTION_LINK_SHIFT (0)
|
||||
#define SYSCTL_RETENTION_LINK_MASK (0xffU << SYSCTL_RETENTION_LINK_SHIFT)
|
||||
# define SYSCTL_RETENTION_LINK_SOC_RAM (0 << SYSCTL_RETENTION_LINK_SHIFT)
|
||||
# define SYSCTL_RETENTION_LINK_PERIPH_REG (1 << SYSCTL_RETENTION_LINK_SHIFT)
|
||||
# define SYSCTL_RETENTION_LINK_CPU0_RAM (2 << SYSCTL_RETENTION_LINK_SHIFT)
|
||||
# define SYSCTL_RETENTION_LINK_CPU0_REG (3 << SYSCTL_RETENTION_LINK_SHIFT)
|
||||
# define SYSCTL_RETENTION_LINK_XTAL (4 << SYSCTL_RETENTION_LINK_SHIFT)
|
||||
# define SYSCTL_RETENTION_LINK_PLL0 (5 << SYSCTL_RETENTION_LINK_SHIFT)
|
||||
# define SYSCTL_RETENTION_LINK_PLL1 (6 << SYSCTL_RETENTION_LINK_SHIFT)
|
||||
# define SYSCTL_RETENTION_LINK_PLL2 (7 << SYSCTL_RETENTION_LINK_SHIFT)
|
||||
|
||||
#define SYSCTL_POWER_STATUS_FLAG (1 << 31)
|
||||
#define SYSCTL_POWER_STATUS_FLAG_WAKE (1 << 30)
|
||||
#define SYSCTL_POWER_LF_DISABLE (1 << 12)
|
||||
#define SYSCTL_POWER_LF_ACK (1 << 8)
|
||||
|
||||
#define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0)
|
||||
#define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xfffffU << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT)
|
||||
#define SYSCTL_POWER_LF_WAIT_WAIT(n) ((n) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT)
|
||||
|
||||
#define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0)
|
||||
#define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xfffffU << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT)
|
||||
#define SYSCTL_POWER_OFF_WAIT_WAIT(n) ((n) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT)
|
||||
|
||||
#define SYSCTL_RESET_CONTROL_FLAG (1 << 31)
|
||||
#define SYSCTL_RESET_CONTROL_FLAG_WAKE (1 << 30)
|
||||
#define SYSCTL_RESET_CONTROL_HOLD (1 << 4)
|
||||
#define SYSCTL_RESET_CONTROL_RESET (1 << 0)
|
||||
|
||||
#define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16)
|
||||
#define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xffU << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT)
|
||||
#define SYSCTL_RESET_CONFIG_PRE_WAIT(n) ((n) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT)
|
||||
#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8)
|
||||
#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xffU << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT)
|
||||
#define SYSCTL_RESET_CONFIG_RSTCLK_NUM(n) ((n) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT)
|
||||
#define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0)
|
||||
#define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xffU << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT)
|
||||
#define SYSCTL_RESET_CONFIG_POST_WAIT(n) ((n) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT)
|
||||
|
||||
#define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0)
|
||||
#define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xfffffU << SYSCTL_RESET_COUNTER_COUNTER_SHIFT)
|
||||
#define SYSCTL_RESET_COUNTER_COUNTER(n) ((n) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT)
|
||||
|
||||
#define SYSCTL_CLOCK_CPU_GLB_BUSY (1 << 31)
|
||||
#define SYSCTL_CLOCK_CPU_LOC_BUSY (1 << 30)
|
||||
#define SYSCTL_CLOCK_CPU_PRESERVE (1 << 28)
|
||||
#define SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT (20)
|
||||
#define SYSCTL_CLOCK_CPU_SUB1_DIV_MASK (0xfU << SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT)
|
||||
#define SYSCTL_CLOCK_CPU_SUB1_DIV(n) ((n) << SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT)
|
||||
#define SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT (16)
|
||||
#define SYSCTL_CLOCK_CPU_SUB0_DIV_MASK (0xfU << SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT)
|
||||
#define SYSCTL_CLOCK_CPU_SUB0_DIV(n) ((n) << SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT)
|
||||
#define SYSCTL_CLOCK_CPU_MUX_SHIFT (8)
|
||||
#define SYSCTL_CLOCK_CPU_MUX_MASK (0xfU << SYSCTL_CLOCK_CPU_MUX_SHIFT)
|
||||
# define SYSCTL_CLOCK_CPU_MUX_OSC0_CLK0 (0 << SYSCTL_CLOCK_CPU_MUX_SHIFT)
|
||||
# define SYSCTL_CLOCK_CPU_MUX_PLL0_CLK0 (1 << SYSCTL_CLOCK_CPU_MUX_SHIFT)
|
||||
# define SYSCTL_CLOCK_CPU_MUX_PLL0_CLK1 (2 << SYSCTL_CLOCK_CPU_MUX_SHIFT)
|
||||
# define SYSCTL_CLOCK_CPU_MUX_PLL0_CLK2 (3 << SYSCTL_CLOCK_CPU_MUX_SHIFT)
|
||||
# define SYSCTL_CLOCK_CPU_MUX_PLL1_CLK0 (4 << SYSCTL_CLOCK_CPU_MUX_SHIFT)
|
||||
# define SYSCTL_CLOCK_CPU_MUX_PLL1_CLK1 (5 << SYSCTL_CLOCK_CPU_MUX_SHIFT)
|
||||
# define SYSCTL_CLOCK_CPU_MUX_PLL2_CLK0 (6 << SYSCTL_CLOCK_CPU_MUX_SHIFT)
|
||||
# define SYSCTL_CLOCK_CPU_MUX_PLL2_CLK1 (7 << SYSCTL_CLOCK_CPU_MUX_SHIFT)
|
||||
#define SYSCTL_CLOCK_CPU_DIV_SHIFT (0)
|
||||
#define SYSCTL_CLOCK_CPU_DIV_MASK (0xffU << SYSCTL_CLOCK_CPU_DIV_SHIFT)
|
||||
#define SYSCTL_CLOCK_CPU_DIV(n) ((n) << SYSCTL_CLOCK_CPU_DIV_SHIFT)
|
||||
|
||||
#define SYSCTL_CLOCK_GLB_BUSY (1 << 31)
|
||||
#define SYSCTL_CLOCK_LOC_BUSY (1 << 30)
|
||||
#define SYSCTL_CLOCK_PRESERVE (1 << 28)
|
||||
#define SYSCTL_CLOCK_SUB1_DIV_SHIFT (20)
|
||||
#define SYSCTL_CLOCK_SUB1_DIV_MASK (0xfU << SYSCTL_CLOCK_SUB1_DIV_SHIFT)
|
||||
#define SYSCTL_CLOCK_SUB1_DIV(n) ((n) << SYSCTL_CLOCK_SUB1_DIV_SHIFT)
|
||||
#define SYSCTL_CLOCK_SUB0_DIV_SHIFT (16)
|
||||
#define SYSCTL_CLOCK_SUB0_DIV_MASK (0xfU << SYSCTL_CLOCK_SUB0_DIV_SHIFT)
|
||||
#define SYSCTL_CLOCK_SUB0_DIV(n) ((n) << SYSCTL_CLOCK_SUB0_DIV_SHIFT)
|
||||
#define SYSCTL_CLOCK_MUX_SHIFT (8)
|
||||
#define SYSCTL_CLOCK_MUX_MASK (0xfU << SYSCTL_CLOCK_MUX_SHIFT)
|
||||
# define SYSCTL_CLOCK_MUX_OSC0_CLK0 (0 << SYSCTL_CLOCK_MUX_SHIFT)
|
||||
# define SYSCTL_CLOCK_MUX_PLL0_CLK0 (1 << SYSCTL_CLOCK_MUX_SHIFT)
|
||||
# define SYSCTL_CLOCK_MUX_PLL0_CLK1 (2 << SYSCTL_CLOCK_MUX_SHIFT)
|
||||
# define SYSCTL_CLOCK_MUX_PLL0_CLK2 (3 << SYSCTL_CLOCK_MUX_SHIFT)
|
||||
# define SYSCTL_CLOCK_MUX_PLL1_CLK0 (4 << SYSCTL_CLOCK_MUX_SHIFT)
|
||||
# define SYSCTL_CLOCK_MUX_PLL1_CLK1 (5 << SYSCTL_CLOCK_MUX_SHIFT)
|
||||
# define SYSCTL_CLOCK_MUX_PLL2_CLK0 (6 << SYSCTL_CLOCK_MUX_SHIFT)
|
||||
# define SYSCTL_CLOCK_MUX_PLL2_CLK1 (7 << SYSCTL_CLOCK_MUX_SHIFT)
|
||||
#define SYSCTL_CLOCK_DIV_SHIFT (0)
|
||||
#define SYSCTL_CLOCK_DIV_MASK (0xffU << SYSCTL_CLOCK_DIV_SHIFT)
|
||||
#define SYSCTL_CLOCK_DIV(n) ((n-1) << SYSCTL_CLOCK_DIV_SHIFT)
|
||||
|
||||
#define SYSCTL_ADCCLK_GLB_BUSY (1 << 31)
|
||||
#define SYSCTL_ADCCLK_LOC_BUSY (1 << 30)
|
||||
#define SYSCTL_ADCCLK_PRESERVE (1 << 28)
|
||||
#define SYSCTL_ADCCLK_MUX_ANA_CLOCK (0)
|
||||
#define SYSCTL_ADCCLK_MUX_AHB_CLOCK (1 << 8)
|
||||
|
||||
#define SYSCTL_DACCLK_GLB_BUSY (1 << 31)
|
||||
#define SYSCTL_DACCLK_LOC_BUSY (1 << 30)
|
||||
#define SYSCTL_DACCLK_PRESERVE (1 << 28)
|
||||
#define SYSCTL_DACCLK_MUX_ANA_CLOCK (0)
|
||||
#define SYSCTL_DACCLK_MUX_AHB_CLOCK (1 << 8)
|
||||
|
||||
#define SYSCTL_DACCLK_GLB_BUSY (1 << 31)
|
||||
#define SYSCTL_DACCLK_LOC_BUSY (1 << 30)
|
||||
#define SYSCTL_DACCLK_PRESERVE (1 << 28)
|
||||
#define SYSCTL_DACCLK_MUX_AUD_CLOCK0 (0)
|
||||
#define SYSCTL_DACCLK_MUX_AUD_CLOCK1 (1 << 8)
|
||||
|
||||
#define SYSCTL_GLOBAL00_MUX_SHIFT (0)
|
||||
#define SYSCTL_GLOBAL00_MUX_MASK (3 << SYSCTL_GLOBAL00_MUX_SHIFT)
|
||||
#define SYSCTL_GLOBAL00_MUX(n) ((n) << SYSCTL_GLOBAL00_MUX_SHIFT)
|
||||
#define SYSCTL_GLOBAL00_MUX_24M (0)
|
||||
#define SYSCTL_GLOBAL00_MUX_SUG (1 << 1)
|
||||
|
||||
#define SYSCTL_MONITOR_CONTROL_VALID (1 << 31)
|
||||
#define SYSCTL_MONITOR_CONTROL_DIV_BUSY (1 << 27)
|
||||
#define SYSCTL_MONITOR_CONTROL_OUTEN (1 << 24)
|
||||
#define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16)
|
||||
#define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xffU << SYSCTL_MONITOR_CONTROL_DIV_SHIFT)
|
||||
#define SYSCTL_MONITOR_CONTROL_DIV(n) ((n) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT)
|
||||
#define SYSCTL_MONITOR_CONTROL_HIGH (1 << 15)
|
||||
#define SYSCTL_MONITOR_CONTROL_LOW (1 << 14)
|
||||
#define SYSCTL_MONITOR_CONTROL_START (1 << 12)
|
||||
#define SYSCTL_MONITOR_CONTROL_MODE (1 << 10)
|
||||
#define SYSCTL_MONITOR_CONTROL_ACCURACY (1 << 9)
|
||||
#define SYSCTL_MONITOR_CONTROL_REFERENCE (1 << 8)
|
||||
#define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0)
|
||||
#define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xffU << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT)
|
||||
#define SYSCTL_MONITOR_CONTROL_SELECTION(n) ((n) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT)
|
||||
|
||||
#define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24)
|
||||
#define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xffU << SYSCTL_CPU_LP_WAKE_CNT_SHIFT)
|
||||
#define SYSCTL_CPU_LP_WAKE_CNT_CLEAR (0)
|
||||
#define SYSCTL_CPU_LP_HALT (1 << 16)
|
||||
#define SYSCTL_CPU_LP_WAKE (1 << 13)
|
||||
#define SYSCTL_CPU_LP_EXEC (1 << 12)
|
||||
#define SYSCTL_CPU_LP_WAKE_FLAG (1 << 10)
|
||||
#define SYSCTL_CPU_LP_SLEEP_FLAG (1 << 9)
|
||||
#define SYSCTL_CPU_LP_RESET_FLAG (1 << 8)
|
||||
#define SYSCTL_CPU_LP_MODE_SHIFT (0)
|
||||
#define SYSCTL_CPU_LP_MODE_MASK (0x3 << SYSCTL_CPU_LP_MODE_SHIFT)
|
||||
#define SYSCTL_CPU_LP_MODE_WAIT (0 << SYSCTL_CPU_LP_MODE_SHIFT)
|
||||
#define SYSCTL_CPU_LP_MODE_HALT (1 << SYSCTL_CPU_LP_MODE_SHIFT)
|
||||
#define SYSCTL_CPU_LP_MODE_RUN (2 << SYSCTL_CPU_LP_MODE_SHIFT)
|
||||
|
||||
#define SYSCTL_CPU_LOCK_GPR_SHIFT (2)
|
||||
#define SYSCTL_CPU_LOCK_GPR_MASK (0x3f << SYSCTL_CPU_LOCK_GPR_SHIFT)
|
||||
#define SYSCTL_CPU_LOCK_LOCK (1 << 1)
|
||||
|
||||
#define SYSCTL_CPU_GPR_GPR_MASK (0xffff)
|
||||
|
||||
#define SYSCTL_CPU_WAKEUP_STATUS_MASK (0xffff)
|
||||
|
||||
#define SYSCTL_CPU_WAKEUP_ENABLE_MASK (0xffff)
|
||||
|
||||
#define SYSCTL_GROUP0_LINK0_AHBP (1 << 0)
|
||||
#define SYSCTL_GROUP0_LINK0_AXIS (1 << 1)
|
||||
#define SYSCTL_GROUP0_LINK0_AXIC (1 << 2)
|
||||
#define SYSCTL_GROUP0_LINK0_FEMC (1 << 3)
|
||||
#define SYSCTL_GROUP0_LINK0_ROM0 (1 << 4)
|
||||
#define SYSCTL_GROUP0_LINK0_LMM0 (1 << 5)
|
||||
#define SYSCTL_GROUP0_LINK0_RAM0 (1 << 6)
|
||||
#define SYSCTL_GROUP0_LINK0_MCHTMR0 (1 << 7)
|
||||
#define SYSCTL_GROUP0_LINK0_XPI0 (1 << 8)
|
||||
#define SYSCTL_GROUP0_LINK0_XPI1 (1 << 9)
|
||||
#define SYSCTL_GROUP0_LINK0_SDP0 (1 << 10)
|
||||
#define SYSCTL_GROUP0_LINK0_RNG0 (1 << 11)
|
||||
#define SYSCTL_GROUP0_LINK0_KMAN (1 << 12)
|
||||
#define SYSCTL_GROUP0_LINK0_DMA0 (1 << 13)
|
||||
#define SYSCTL_GROUP0_LINK0_DMA1 (1 << 14)
|
||||
#define SYSCTL_GROUP0_LINK0_FFA0 (1 << 15)
|
||||
#define SYSCTL_GROUP0_LINK0_GPIO (1 << 16)
|
||||
#define SYSCTL_GROUP0_LINK0_MBX0 (1 << 17)
|
||||
#define SYSCTL_GROUP0_LINK0_WDG0 (1 << 18)
|
||||
#define SYSCTL_GROUP0_LINK0_WDG1 (1 << 19)
|
||||
#define SYSCTL_GROUP0_LINK0_TSNS (1 << 20)
|
||||
#define SYSCTL_GROUP0_LINK0_GPTMR0 (1 << 21)
|
||||
#define SYSCTL_GROUP0_LINK0_GPTMR1 (1 << 22)
|
||||
#define SYSCTL_GROUP0_LINK0_GPRMR2 (1 << 23)
|
||||
#define SYSCTL_GROUP0_LINK0_GPTMR3 (1 << 24)
|
||||
#define SYSCTL_GROUP0_LINK0_UART0 (1 << 25)
|
||||
#define SYSCTL_GROUP0_LINK0_UART1 (1 << 26)
|
||||
#define SYSCTL_GROUP0_LINK0_UART2 (1 << 27)
|
||||
#define SYSCTL_GROUP0_LINK0_UART3 (1 << 28)
|
||||
#define SYSCTL_GROUP0_LINK0_UART4 (1 << 29)
|
||||
#define SYSCTL_GROUP0_LINK0_UART5 (1 << 30)
|
||||
#define SYSCTL_GROUP0_LINK0_UART6 (1 << 11)
|
||||
#define SYSCTL_GROUP0_LINK1_UART7 (1 << 0)
|
||||
#define SYSCTL_GROUP0_LINK1_I2C0 (1 << 1)
|
||||
#define SYSCTL_GROUP0_LINK1_I2C1 (1 << 2)
|
||||
#define SYSCTL_GROUP0_LINK1_I2C2 (1 << 3)
|
||||
#define SYSCTL_GROUP0_LINK1_I2C3 (1 << 4)
|
||||
#define SYSCTL_GROUP0_LINK1_SPI0 (1 << 5)
|
||||
#define SYSCTL_GROUP0_LINK1_SPI1 (1 << 6)
|
||||
#define SYSCTL_GROUP0_LINK1_SPI2 (1 << 7)
|
||||
#define SYSCTL_GROUP0_LINK1_SPI3 (1 << 8)
|
||||
#define SYSCTL_GROUP0_LINK1_CAN0 (1 << 9)
|
||||
#define SYSCTL_GROUP0_LINK1_CAN1 (1 << 10)
|
||||
#define SYSCTL_GROUP0_LINK1_PTPC (1 << 11)
|
||||
#define SYSCTL_GROUP0_LINK1_ADC0 (1 << 12)
|
||||
#define SYSCTL_GROUP0_LINK1_ADC1 (1 << 13)
|
||||
#define SYSCTL_GROUP0_LINK1_ADC2 (1 << 14)
|
||||
#define SYSCTL_GROUP0_LINK1_DAC0 (1 << 15)
|
||||
#define SYSCTL_GROUP0_LINK1_ACMP (1 << 16)
|
||||
#define SYSCTL_GROUP0_LINK1_I2S0 (1 << 17)
|
||||
#define SYSCTL_GROUP0_LINK1_I2S1 (1 << 18)
|
||||
#define SYSCTL_GROUP0_LINK1_I2SPDM0 (1 << 19)
|
||||
#define SYSCTL_GROUP0_LINK1_I2SDAO (1 << 20)
|
||||
#define SYSCTL_GROUP0_LINK1_MSYN (1 << 21)
|
||||
#define SYSCTL_GROUP0_LINK1_MOT0 (1 << 22)
|
||||
#define SYSCTL_GROUP0_LINK1_MOT1 (1 << 23)
|
||||
#define SYSCTL_GROUP0_LINK1_ETH0 (1 << 24)
|
||||
#define SYSCTL_GROUP0_LINK1_NTMR0 (1 << 25)
|
||||
#define SYSCTL_GROUP0_LINK1_SDXC0 (1 << 26)
|
||||
#define SYSCTL_GROUP0_LINK1_USB0 (1 << 27)
|
||||
#define SYSCTL_GROUP0_LINK1_REF0 (1 << 28)
|
||||
#define SYSCTL_GROUP0_LINK1_REF1 (1 << 29)
|
||||
|
||||
#define SYSCTL_RESOURCE_CPU0 (0)
|
||||
#define SYSCTL_RESOURCE_CPX1 (1)
|
||||
#define SYSCTL_RESOURCE_EXE0 (2)
|
||||
#define SYSCTL_RESOURCE_WAK0 (3)
|
||||
#define SYSCTL_RESOURCE_CPU0_PER (4)
|
||||
#define SYSCTL_RESOURCE_LOGIC0 (16)
|
||||
#define SYSCTL_RESOURCE_LOGIC1 (17)
|
||||
#define SYSCTL_RESOURCE_LOGIC2 (18)
|
||||
#define SYSCTL_RESOURCE_LOGIC3 (19)
|
||||
#define SYSCTL_RESOURCE_PMIC (20)
|
||||
#define SYSCTL_RESOURCE_POW_CPU0 (21)
|
||||
#define SYSCTL_RESOURCE_RST_SOC (22)
|
||||
#define SYSCTL_RESOURCE_RST_CPU0 (23)
|
||||
#define SYSCTL_RESOURCE_XTAL (32)
|
||||
#define SYSCTL_RESOURCE_PLL0 (33)
|
||||
#define SYSCTL_RESOURCE_CLK0_PLL0 (34)
|
||||
#define SYSCTL_RESOURCE_CLK1_PLL0 (35)
|
||||
#define SYSCTL_RESOURCE_CLK2_PLL0 (36)
|
||||
#define SYSCTL_RESOURCE_PLL1 (37)
|
||||
#define SYSCTL_RESOURCE_CLK0_PLL1 (38)
|
||||
#define SYSCTL_RESOURCE_CLK1_PLL1 (39)
|
||||
#define SYSCTL_RESOURCE_PLL2 (40)
|
||||
#define SYSCTL_RESOURCE_CLK0_PLL2 (41)
|
||||
#define SYSCTL_RESOURCE_CLK1_PLL2 (42)
|
||||
#define SYSCTL_RESOURCE_PLL0_REF (43)
|
||||
#define SYSCTL_RESOURCE_PLL1_REF (44)
|
||||
#define SYSCTL_RESOURCE_PLL2_REF (45)
|
||||
#define SYSCTL_RESOURCE_MBIST_SOC (48)
|
||||
#define SYSCTL_RESOURCE_MBIST_CPU (49)
|
||||
#define SSYCTL_RESOURCE_MBIST_CON (50)
|
||||
#define SYSCTL_RESOURCE_DFT_START_BUS (51)
|
||||
#define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64)
|
||||
#define SYSCTL_RESOURCE_CLK_TOP_MCHTMR0 (65)
|
||||
#define SYSCTL_RESOURCE_CLK_TOP_FEMC (66)
|
||||
#define SYSCTL_RESOURCE_CLK_TOP_XPI0 (67)
|
||||
#define SYSCTL_RESOURCE_CLK_TOP_XPI1 (68)
|
||||
#define SYSCTL_RESOURCE_CLK_TOP_ANA1 (93)
|
||||
#define SYSCTL_RESOURCE_CLK_TOP_ANA2 (94)
|
||||
#define SYSCTL_RESOURCE_CLK_TOP_ANA3 (95)
|
||||
#define SYSCTL_RESOURCE_CLK_TOP_AUD0 (96)
|
||||
#define SYSCTL_RESOURCE_CLK_TOP_AUD1 (97)
|
||||
#define SYSCTL_RESOURCE_CLK_TOP_ETH0 (98)
|
||||
#define SYSCTL_RESOURCE_CLK_TOP_PTP0 (99)
|
||||
#define SYSCTL_RESOURCE_CLK_TOP_REF0 (100)
|
||||
#define SYSCTL_RESOURCE_CLK_TOP_REF1 (101)
|
||||
#define SYSCTL_RESOURCE_CLK_TOP_NTMR0 (102)
|
||||
#define SYSCTL_RESOURCE_CLK_TOP_SDXC0 (103)
|
||||
#define SYSCTL_RESOURCE_CLK_TOP_ADC0 (128)
|
||||
#define SYSCTL_RESOURCE_CLK_TOP_ADC1 (129)
|
||||
#define SYSCTL_RESOURCE_CLK_TOP_ADC2 (130)
|
||||
#define SYSCTL_RESOURCE_CLK_TOP_DAC0 (131)
|
||||
#define SYSCTL_RESOURCE_CLK_TOP_I2S0 (132)
|
||||
#define SYSCTL_RESOURCE_CLK_TOP_I2S1 (133)
|
||||
|
||||
#define SYSCTL_RESOURCE_ETH0_MEM (192)
|
||||
#define SYSCTL_RESOURCE_SDXC0_MEM (193)
|
||||
#define SYSCTL_RESOURCE_USB0_MEM (194)
|
||||
#define SYSCTL_RESOURCE_RAM0_MEM (195)
|
||||
#define SYSCTL_RESOURCE_AHBP_MEM (196)
|
||||
#define SYSCTL_RESOURCE_FEMC_MEM (197)
|
||||
#define SYSCTL_RESOURCE_ROM0_MEM (198)
|
||||
#define SYSCTL_RESOURCE_XPI0_MEM (199)
|
||||
#define SYSCTL_RESOURCE_XPI1_MEM (200)
|
||||
#define SYSCTL_RESOURCE_CAN0_MEM (201)
|
||||
#define SYSCTL_RESOURCE_CAN1_MEM (202)
|
||||
#define SYSCTL_RESOURCE_I2S0_MEM (203)
|
||||
#define SYSCTL_RESOURCE_I2S1_MEM (204)
|
||||
#define SYSCTL_RESOURCE_PDM0_MEM (205)
|
||||
#define SYSCTL_RESOURCE_SDP0_MEM (206)
|
||||
#define SYSCTL_RESOURCE_FFA0_MEM (207)
|
||||
#define SYSCTL_RESOURCE_CPX_MEM (208)
|
||||
#define SYSCTL_RESOURCE_CORE_MEM (209)
|
||||
#define SYSCTL_RESOURCE_LMM0_MEM (210)
|
||||
|
||||
#define SYSCTL_RESOURCE_LINKABLE_START (256)
|
||||
#define SYSCTL_RESOURCE_AHBP (256)
|
||||
#define SYSCTL_RESOURCE_AXIS (257)
|
||||
#define SYSCTL_RESOURCE_AXIC (258)
|
||||
#define SYSCTL_RESOURCE_FEMC (259)
|
||||
#define SYSCTL_RESOURCE_ROM0 (260)
|
||||
#define SYSCTL_RESOURCE_LMM0 (261)
|
||||
#define SYSCTL_RESOURCE_RAM0 (262)
|
||||
#define SYSCTL_RESOURCE_MCHTMR0 (263)
|
||||
#define SYSCTL_RESOURCE_XPI0 (264)
|
||||
#define SYSCTL_RESOURCE_XPI1 (265)
|
||||
#define SYSCTL_RESOURCE_SDP0 (266)
|
||||
#define SYSCTL_RESOURCE_RNG0 (267)
|
||||
#define SYSCTL_RESOURCE_KMAN (268)
|
||||
#define SYSCTL_RESOURCE_DMA0 (269)
|
||||
#define SYSCTL_RESOURCE_DMA1 (270)
|
||||
#define SYSCTL_RESOURCE_FFA0 (271)
|
||||
#define SYSCTL_RESOURCE_GPIO (272)
|
||||
#define SYSCTL_RESOURCE_MBX0 (273)
|
||||
#define SYSCTL_RESOURCE_WDG0 (274)
|
||||
#define SYSCTL_RESOURCE_WDG1 (275)
|
||||
#define SYSCTL_RESOURCE_TSNS (276)
|
||||
#define SYSCTL_RESOURCE_GPTMR0 (277)
|
||||
#define SYSCTL_RESOURCE_GPTMR1 (278)
|
||||
#define SYSCTL_RESOURCE_GPRMR2 (279)
|
||||
#define SYSCTL_RESOURCE_GPTMR3 (280)
|
||||
#define SYSCTL_RESOURCE_UART0 (281)
|
||||
#define SYSCTL_RESOURCE_UART1 (282)
|
||||
#define SYSCTL_RESOURCE_UART2 (283)
|
||||
#define SYSCTL_RESOURCE_UART3 (284)
|
||||
#define SYSCTL_RESOURCE_UART4 (285)
|
||||
#define SYSCTL_RESOURCE_UART5 (286)
|
||||
#define SYSCTL_RESOURCE_UART6 (287)
|
||||
#define SYSCTL_RESOURCE_UART7 (288)
|
||||
#define SYSCTL_RESOURCE_I2C0 (289)
|
||||
#define SYSCTL_RESOURCE_I2C1 (290)
|
||||
#define SYSCTL_RESOURCE_I2C2 (291)
|
||||
#define SYSCTL_RESOURCE_I2C3 (292)
|
||||
#define SYSCTL_RESOURCE_SPI0 (293)
|
||||
#define SYSCTL_RESOURCE_SPI1 (294)
|
||||
#define SYSCTL_RESOURCE_SPI2 (295)
|
||||
#define SYSCTL_RESOURCE_SPI3 (296)
|
||||
#define SYSCTL_RESOURCE_CAN0 (297)
|
||||
#define SYSCTL_RESOURCE_CAN1 (298)
|
||||
#define SYSCTL_RESOURCE_PTPC (299)
|
||||
#define SYSCTL_RESOURCE_ADC0 (300)
|
||||
#define SYSCTL_RESOURCE_ADC1 (301)
|
||||
#define SYSCTL_RESOURCE_ADC2 (302)
|
||||
#define SYSCTL_RESOURCE_DAC0 (303)
|
||||
#define SYSCTL_RESOURCE_ACMP (304)
|
||||
#define SYSCTL_RESOURCE_I2S0 (305)
|
||||
#define SYSCTL_RESOURCE_I2S1 (306)
|
||||
#define SYSCTL_RESOURCE_I2SPDM0 (307)
|
||||
#define SYSCTL_RESOURCE_I2SDAO (308)
|
||||
#define SYSCTL_RESOURCE_MSYN (309)
|
||||
#define SYSCTL_RESOURCE_MOT0 (310)
|
||||
#define SYSCTL_RESOURCE_MOT1 (311)
|
||||
#define SYSCTL_RESOURCE_ETH0 (312)
|
||||
#define SYSCTL_RESOURCE_NTMR0 (313)
|
||||
#define SYSCTL_RESOURCE_SDXC0 (314)
|
||||
#define SYSCTL_RESOURCE_USB0 (315)
|
||||
#define SYSCTL_RESOURCE_REF0 (316)
|
||||
#define SYSCTL_RESOURCE_REF1 (317)
|
||||
#define SYSCTL_RESOURCE_LINKABLE_END (317)
|
||||
|
||||
#define CLOCK_NODE_MCHTMR0 (0)
|
||||
#define CLOCK_NODE_FEMC (1)
|
||||
#define CLOCK_NODE_XPI0 (2)
|
||||
#define CLOCK_NODE_XPI1 (3)
|
||||
#define CLOCK_NODE_GPTMR0 (4)
|
||||
#define CLOCK_NODE_GPTMR1 (5)
|
||||
#define CLOCK_NODE_GPTMR2 (6)
|
||||
#define CLOCK_NODE_GPTMR3 (7)
|
||||
#define CLOCK_NODE_UART0 (8)
|
||||
#define CLOCK_NODE_UART1 (9)
|
||||
#define CLOCK_NODE_UART2 (10)
|
||||
#define CLOCK_NODE_UART3 (11)
|
||||
#define CLOCK_NODE_UART4 (12)
|
||||
#define CLOCK_NODE_UART5 (13)
|
||||
#define CLOCK_NODE_UART6 (14)
|
||||
#define CLOCK_NODE_UART7 (15)
|
||||
#define CLOCK_NODE_I2C0 (16)
|
||||
#define CLOCK_NODE_I2C1 (17)
|
||||
#define CLOCK_NODE_I2C2 (18)
|
||||
#define CLOCK_NODE_I2C3 (19)
|
||||
#define CLOCK_NODE_SPI0 (20)
|
||||
#define CLOCK_NODE_SPI1 (21)
|
||||
#define CLOCK_NODE_SPI2 (22)
|
||||
#define CLOCK_NODE_SPI3 (23)
|
||||
#define CLOCK_NODE_CAN0 (24)
|
||||
#define CLOCK_NODE_CAN1 (25)
|
||||
#define CLOCK_NODE_PTPC (26)
|
||||
#define CLOCK_NODE_ANA0 (27)
|
||||
#define CLOCK_NODE_ANA1 (28)
|
||||
#define CLOCK_NODE_ANA2 (29)
|
||||
#define CLOCK_NODE_ANA3 (30)
|
||||
#define CLOCK_NODE_AUD0 (31)
|
||||
#define CLOCK_NODE_AUD1 (32)
|
||||
#define CLOCK_NODE_ETH0 (33)
|
||||
#define CLOCK_NODE_PTP0 (34)
|
||||
#define CLOCK_NODE_REF0 (35)
|
||||
#define CLOCK_NODE_REF1 (36)
|
||||
#define CLOCK_NODE_NTMR0 (37)
|
||||
#define CLOCK_NODE_SDXC0 (38)
|
||||
|
||||
#define CLOCK_NODE_ADC0 (0)
|
||||
#define CLOCK_NODE_ADC1 (1)
|
||||
#define CLOCK_NODE_ADC2 (2)
|
||||
|
||||
#define CLOCK_NODE_DAC0 (1)
|
||||
|
||||
#define CLOCK_NODE_I2S0 (0)
|
||||
#define CLOCK_NODE_I2S1 (1)
|
||||
|
||||
#define CLOCK_NODE_CORE_START (252)
|
||||
#define CLOCK_NODE_CPU0 (252)
|
||||
#define CLOCK_NODE_AXI (253)
|
||||
#define CLOCK_NODE_AHB (254)
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_SYSCTL_H */
|
||||
59
arch/risc-v/src/hpm6000/hardware/hpm_gpio.h
Normal file
59
arch/risc-v/src/hpm6000/hardware/hpm_gpio.h
Normal file
@ -0,0 +1,59 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hardware/hpm_gpio.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_GPIO_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_GPIO_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "hardware/hpm_memorymap.h"
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_HPM6360IPA)
|
||||
#include "hpm6300/hpm6300_ioc.h"
|
||||
#include "hpm6300/hpm6300_pinmux.h"
|
||||
#else
|
||||
#error The selected HPM variant is not impelemented
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define GPIOA 0
|
||||
#define GPIOB 1
|
||||
#define GPIOC 2
|
||||
#define GPIOD 3
|
||||
#define GPIOE 4
|
||||
#define GPIOF 5
|
||||
#define GPIOX 6
|
||||
#define GPIOY 7
|
||||
#define GPIOZ 8
|
||||
#define HPM_GPIO_NPINS 32
|
||||
|
||||
/* Most registers are laid out simply with one bit per pin */
|
||||
|
||||
#define GPIO_PIN(n) (1 << (n)) /* Bit n: Pin n, n=0-31 */
|
||||
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_GPIO_H */
|
||||
160
arch/risc-v/src/hpm6000/hardware/hpm_ioc.h
Normal file
160
arch/risc-v/src/hpm6000/hardware/hpm_ioc.h
Normal file
@ -0,0 +1,160 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hardware/hpm_ioc.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_IOC_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_IOC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "hpm_ioc.h"
|
||||
|
||||
#define CONFIG_ARCH_FAMILY_HPM6300
|
||||
|
||||
#if defined (CONFIG_ARCH_FAMILY_HPM6300)
|
||||
# include "hardware/hpm6300/hpm6300_ioc.h"
|
||||
#else
|
||||
# error Unrecognized HPM chip
|
||||
#endif
|
||||
|
||||
#define DRIVE_260OHM (1)
|
||||
#define DRIVE_130OHM (2)
|
||||
#define DRIVE_88OHM (3)
|
||||
#define DRIVE_65OHM (4)
|
||||
#define DRIVE_52OHM (5)
|
||||
#define DRIVE_43OHM (6)
|
||||
#define DRIVE_37OHM (7)
|
||||
|
||||
#define SPEED_SLOW (0)
|
||||
#define SPEED_MEDIUM (1)
|
||||
#define SPEED_FAST (2)
|
||||
#define SPEED_MAX (3)
|
||||
|
||||
#define PULL_DOWN_100K (0)
|
||||
#define PULL_UP_100K (1)
|
||||
#define PULL_UP_47K (2)
|
||||
#define PULL_UP_22K (3)
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Pad Alt Registers */
|
||||
|
||||
#define IOC_PAD_FUNC_ALT_SELECT_SHIFT (0)
|
||||
#define IOC_PAD_FUNC_ALT_SELECT_MASK (1f << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT(n) ((uint32_t)(n) << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT0 (0 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT1 (1 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT2 (2 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT3 (3 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT4 (4 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT5 (5 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT6 (6 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT7 (7 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT8 (8 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT9 (9 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT10 (10 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT11 (11 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT12 (12 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT13 (13 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT14 (14 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT15 (15 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT16 (16 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT17 (17 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT18 (18 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT19 (19 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT20 (20 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT21 (21 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT22 (22 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT23 (23 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT24 (24 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT25 (25 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT26 (26 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT27 (27 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT28 (28 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT29 (29 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT30 (30 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
# define IOC_PAD_FUNC_ALT_SELECT_ALT31 (31 << IOC_PAD_FUNC_ALT_SELECT_SHIFT)
|
||||
|
||||
/* Pad Analog Registers */
|
||||
|
||||
#define IOC_PAD_FUNC_ANALOG (1 << 8)
|
||||
|
||||
/* Pad Loop Back Registers */
|
||||
|
||||
#define IOC_PAD_FUNC_LOOP_BACK (1 << 16)
|
||||
|
||||
/* Pad Drive strength Registers */
|
||||
|
||||
#define IOC_PAD_PAD_DS_SHIFT (0)
|
||||
#define IOC_PAD_PAD_DS_MASK (0x7 << IOC_PAD_PAD_DS_SHIFT)
|
||||
# define IOC_PAD_PAD_DS(n) ((uint32_t)(n) << IOC_PAD_PAD_DS_SHIFT)
|
||||
# define IOC_PAD_PAD_DS_1V8_260OHM (1 << IOC_PAD_PAD_DS_SHIFT)
|
||||
# define IOC_PAD_PAD_DS_1V8_130OHM (2 << IOC_PAD_PAD_DS_SHIFT)
|
||||
# define IOC_PAD_PAD_DS_1V8_88OHM (3 << IOC_PAD_PAD_DS_SHIFT)
|
||||
# define IOC_PAD_PAD_DS_1V8_65OHM (4 << IOC_PAD_PAD_DS_SHIFT)
|
||||
# define IOC_PAD_PAD_DS_1V8_52OHM (5 << IOC_PAD_PAD_DS_SHIFT)
|
||||
# define IOC_PAD_PAD_DS_1V8_43OHM (6 << IOC_PAD_PAD_DS_SHIFT)
|
||||
# define IOC_PAD_PAD_DS_1V8_37OHM (7 << IOC_PAD_PAD_DS_SHIFT)
|
||||
# define IOC_PAD_PAD_DS_3V3_157OHM (1 << IOC_PAD_PAD_DS_SHIFT)
|
||||
# define IOC_PAD_PAD_DS_3V3_78OHM (2 << IOC_PAD_PAD_DS_SHIFT)
|
||||
# define IOC_PAD_PAD_DS_3V3_53OHM (3 << IOC_PAD_PAD_DS_SHIFT)
|
||||
# define IOC_PAD_PAD_DS_3V3_39OHM (4 << IOC_PAD_PAD_DS_SHIFT)
|
||||
# define IOC_PAD_PAD_DS_3V3_32OHM (5 << IOC_PAD_PAD_DS_SHIFT)
|
||||
# define IOC_PAD_PAD_DS_3V3_26OHM (6 << IOC_PAD_PAD_DS_SHIFT)
|
||||
# define IOC_PAD_PAD_DS_3V3_23OHM (7 << IOC_PAD_PAD_DS_SHIFT)
|
||||
|
||||
#define IOC_PAD_PAD_SPD_SHIFT (4)
|
||||
#define IOC_PAD_PAD_SPD_MASK (0x3 << IOC_PAD_PAD_SPD_SHIFT)
|
||||
# define IOC_PAD_PAD_SPD(n) ((uint32_t)(n) << IOC_PAD_PAD_SPD_SHIFT)
|
||||
# define IOC_PAD_PAD_SPD_SLOW (0 << IOC_PAD_PAD_SPD_SHIFT)
|
||||
# define IOC_PAD_PAD_SPD_MEDIUM (1 << IOC_PAD_PAD_SPD_SHIFT)
|
||||
# define IOC_PAD_PAD_SPD_FAST (2 << IOC_PAD_PAD_SPD_SHIFT)
|
||||
# define IOC_PAD_PAD_SPD_MAX (3 << IOC_PAD_PAD_SPD_SHIFT)
|
||||
|
||||
#define IOC_PAD_PAD_SR (1 << 6)
|
||||
#define IOC_PAD_PAD_OD (1 << 8)
|
||||
#define IOC_PAD_PAD_KE (1 << 16)
|
||||
#define IOC_PAD_PAD_PE (1 << 17)
|
||||
#define IOC_PAD_PAD_PS (1 << 18)
|
||||
|
||||
#define IOC_PAD_PAD_PRS_SHIFT (20) /* Bit 20-21: Pull up/down internal resistance strength */
|
||||
#define IOC_PAD_PAD_PRS_MASK (0x3 << IOC_PAD_PAD_PRS_SHIFT)
|
||||
# define IOC_PAD_PAD_PRS(n) ((uint32_t)(n) << IOC_PAD_PAD_PRS_SHIFT)
|
||||
# define IOC_PAD_PAD_PRS_DOWN_100K (0 << IOC_PAD_PAD_PRS_SHIFT)
|
||||
# define IOC_PAD_PAD_PRS_UP_100K (0 << IOC_PAD_PAD_PRS_SHIFT)
|
||||
# define IOC_PAD_PAD_PRS_UP_47K (1 << IOC_PAD_PAD_PRS_SHIFT)
|
||||
# define IOC_PAD_PAD_PRS_UP_22K (2 << IOC_PAD_PAD_PRS_SHIFT)
|
||||
|
||||
#define IOC_PAD_PAD_HYS (1 << 24) /* Bit 24: Schmitt Trigger Enable Field */
|
||||
|
||||
/* Defaults for drive conditions for each set of pins. These are a good
|
||||
* starting point but should be updated once you've got real hardware
|
||||
* to measure.
|
||||
*/
|
||||
|
||||
#define IOC_PAD_UART_DEFAULT (PAD_PULL_UP_22K | PAD_DRIVE_43OHM | \
|
||||
PAD_SLEW_SLOW | PAD_SPEED_SLOW | PAD_SCHMITT_TRIGGER)
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_IOC_H */
|
||||
31
arch/risc-v/src/hpm6000/hardware/hpm_mchtmr.h
Normal file
31
arch/risc-v/src/hpm6000/hardware/hpm_mchtmr.h
Normal file
@ -0,0 +1,31 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hardware/hpm_mchtmr.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_MCHTMR_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_MCHTMR_H
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define HPM_MCHTMR_MTIME (HPM_MCHTMR_BASE + 0x0000)
|
||||
#define HPM_MCHTMR_MTIMECMP (HPM_MCHTMR_BASE + 0x0008)
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_MCHTMR_H */
|
||||
38
arch/risc-v/src/hpm6000/hardware/hpm_memorymap.h
Normal file
38
arch/risc-v/src/hpm6000/hardware/hpm_memorymap.h
Normal file
@ -0,0 +1,38 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hardware/hpm_memorymap.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_MEMORYMAP_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_MEMORYMAP_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#define CONFIG_ARCH_FAMILY_HPM6300
|
||||
|
||||
#if defined(CONFIG_ARCH_FAMILY_HPM6300)
|
||||
# include "hpm6300/hpm6300_memorymap.h"
|
||||
#else
|
||||
# error Unrecognized HPM architecture
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_MEMORYMAP_H */
|
||||
40
arch/risc-v/src/hpm6000/hardware/hpm_plic.h
Normal file
40
arch/risc-v/src/hpm6000/hardware/hpm_plic.h
Normal file
@ -0,0 +1,40 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hardware/hpm_plic.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_PLIC_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_PLIC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define HPM_PLIC_PRIORITY (HPM_PLIC_BASE + 0x000000)
|
||||
#define HPM_PLIC_PENDING0 (HPM_PLIC_BASE + 0x001000)
|
||||
#define HPM_PLIC_PENDING1 (HPM_PLIC_BASE + 0x001004)
|
||||
#define HPM_PLIC_PENDING2 (HPM_PLIC_BASE + 0x001008)
|
||||
#define HPM_PLIC_PENDING3 (HPM_PLIC_BASE + 0x00100C)
|
||||
#define HPM_PLIC_INTEN0 (HPM_PLIC_BASE + 0x002000)
|
||||
#define HPM_PLIC_INTEN1 (HPM_PLIC_BASE + 0x002004)
|
||||
#define HPM_PLIC_INTEN2 (HPM_PLIC_BASE + 0x002008)
|
||||
#define HPM_PLIC_INTEN3 (HPM_PLIC_BASE + 0x00200C)
|
||||
#define HPM_PLIC_THRESHOLD (HPM_PLIC_BASE + 0x200000)
|
||||
#define HPM_PLIC_CLAIM (HPM_PLIC_BASE + 0x200004)
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_PLIC_H */
|
||||
131
arch/risc-v/src/hpm6000/hardware/hpm_pllctl.h
Normal file
131
arch/risc-v/src/hpm6000/hardware/hpm_pllctl.h
Normal file
@ -0,0 +1,131 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hardware/hpm_pllctl.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_PLLCTL_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_PLLCTL_H
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define HPM_PLLCTLV2_XTAL (HPM_PLLCTL_BASE + 0x0000)
|
||||
#define HPM_PLLCTLV2_PLL0_MFI (HPM_PLLCTL_BASE + 0x0080)
|
||||
#define HPM_PLLCTLV2_PLL0_MFN (HPM_PLLCTL_BASE + 0x0084)
|
||||
#define HPM_PLLCTLV2_PLL0_MFD (HPM_PLLCTL_BASE + 0x0088)
|
||||
#define HPM_PLLCTLV2_PLL0_SS_STEP (HPM_PLLCTL_BASE + 0x008c)
|
||||
#define HPM_PLLCTLV2_PLL0_SS_STOP (HPM_PLLCTL_BASE + 0x0090)
|
||||
#define HPM_PLLCTLV2_PLL0_CONFIG (HPM_PLLCTL_BASE + 0x0094)
|
||||
#define HPM_PLLCTLV2_PLL0_LOCKTIME (HPM_PLLCTL_BASE + 0x0098)
|
||||
#define HPM_PLLCTLV2_PLL0_STEPTIME (HPM_PLLCTL_BASE + 0x009c)
|
||||
#define HPM_PLLCTLV2_PLL0_ADVANCED (HPM_PLLCTL_BASE + 0x00a0)
|
||||
#define HPM_PLLCTLV2_PLL0_DIV0 (HPM_PLLCTL_BASE + 0x00c0)
|
||||
#define HPM_PLLCTLV2_PLL0_DIV1 (HPM_PLLCTL_BASE + 0x00c4)
|
||||
#define HPM_PLLCTLV2_PLL0_DIV2 (HPM_PLLCTL_BASE + 0x00c8)
|
||||
|
||||
#define HPM_PLLCTLV2_PLL1_MFI (HPM_PLLCTL_BASE + 0x0100)
|
||||
#define HPM_PLLCTLV2_PLL1_MFN (HPM_PLLCTL_BASE + 0x0104)
|
||||
#define HPM_PLLCTLV2_PLL1_MFD (HPM_PLLCTL_BASE + 0x0108)
|
||||
#define HPM_PLLCTLV2_PLL1_SS_STEP (HPM_PLLCTL_BASE + 0x010c)
|
||||
#define HPM_PLLCTLV2_PLL1_SS_STOP (HPM_PLLCTL_BASE + 0x0110)
|
||||
#define HPM_PLLCTLV2_PLL1_CONFIG (HPM_PLLCTL_BASE + 0x0114)
|
||||
#define HPM_PLLCTLV2_PLL1_LOCKTIME (HPM_PLLCTL_BASE + 0x0118)
|
||||
#define HPM_PLLCTLV2_PLL1_STEPTIME (HPM_PLLCTL_BASE + 0x011c)
|
||||
#define HPM_PLLCTLV2_PLL1_ADVANCED (HPM_PLLCTL_BASE + 0x0120)
|
||||
#define HPM_PLLCTLV2_PLL1_DIV0 (HPM_PLLCTL_BASE + 0x0140)
|
||||
#define HPM_PLLCTLV2_PLL1_DIV1 (HPM_PLLCTL_BASE + 0x0144)
|
||||
#define HPM_PLLCTLV2_PLL1_DIV2 (HPM_PLLCTL_BASE + 0x0148)
|
||||
|
||||
#define HPM_PLLCTLV2_PLL2_MFI (HPM_PLLCTL_BASE + 0x0180)
|
||||
#define HPM_PLLCTLV2_PLL2_MFN (HPM_PLLCTL_BASE + 0x0184)
|
||||
#define HPM_PLLCTLV2_PLL2_MFD (HPM_PLLCTL_BASE + 0x0188)
|
||||
#define HPM_PLLCTLV2_PLL2_SS_STEP (HPM_PLLCTL_BASE + 0x018c)
|
||||
#define HPM_PLLCTLV2_PLL2_SS_STOP (HPM_PLLCTL_BASE + 0x0190)
|
||||
#define HPM_PLLCTLV2_PLL2_CONFIG (HPM_PLLCTL_BASE + 0x0194)
|
||||
#define HPM_PLLCTLV2_PLL2_LOCKTIME (HPM_PLLCTL_BASE + 0x0198)
|
||||
#define HPM_PLLCTLV2_PLL2_STEPTIME (HPM_PLLCTL_BASE + 0x019c)
|
||||
#define HPM_PLLCTLV2_PLL2_ADVANCED (HPM_PLLCTL_BASE + 0x01a0)
|
||||
#define HPM_PLLCTLV2_PLL2_DIV(n) (HPM_PLLCTL_BASE + 0x01c0 + n * 0x04)
|
||||
|
||||
#define HPM_PLLCTLV2_XTAL_BUSY (0x80000000UL)
|
||||
#define HPM_PLLCTLV2_XTAL_RESPONSE (0x20000000UL)
|
||||
#define HPM_PLLCTLV2_XTAL_ENABLE (0x10000000UL)
|
||||
#define HPM_PLLCTLV2_XTAL_RAMP_TIME_SHIFT (0U)
|
||||
#define HPM_PLLCTLV2_XTAL_RAMP_TIME_MASK (0xFFFFFUL)
|
||||
#define HPM_PLLCTLV2_XTAL_RAMP_TIME(n) \
|
||||
((uint32_t)(n) << HPM_PLLCTLV2_XTAL_RAMP_TIME_SHIFT)
|
||||
|
||||
#define HPM_PLLCTLV2_PLL_MFI_BUSY (0x80000000UL)
|
||||
#define HPM_PLLCTLV2_PLL_MFI_RESPONSE (0x20000000UL)
|
||||
#define HPM_PLLCTLV2_PLL_MFI_ENABLE (0x10000000UL)
|
||||
#define HPM_PLLCTLV2_PLL_MFI_MFI_MASK (0x7FU)
|
||||
#define HPM_PLLCTLV2_PLL_MFI_MFI_SHIFT (0U)
|
||||
#define HPM_PLLCTLV2_PLL_MFI_MFI(n) \
|
||||
((uint32_t)(n) << HPM_PLLCTLV2_PLL_MFI_MFI_SHIFT)
|
||||
|
||||
#define HPM_PLLCTLV2_PLL_MFN_MFN_MASK (0x3FFFFFFFUL)
|
||||
#define HPM_PLLCTLV2_PLL_MFN_MFN_SHIFT (0U)
|
||||
#define HPM_PLLCTLV2_PLL_MFN_MFN(x) \
|
||||
((uint32_t)(x) << PLLCTLV2_PLL_MFN_MFN_SHIFT)
|
||||
#define HPM_PLLCTLV2_PLL_MFD_MFD_MASK (0x3FFFFFFFUL)
|
||||
#define HPM_PLLCTLV2_PLL_MFD_MFD_SHIFT (0U)
|
||||
#define HPM_PLLCTLV2_PLL_MFD_MFD(n) \
|
||||
((uint32_t)(n) << PLLCTLV2_PLL_MFD_MFD_SHIFT)
|
||||
|
||||
#define HPM_PLLCTLV2_PLL_SS_STEP_STEP_MASK (0x3FFFFFFFUL)
|
||||
#define HPM_PLLCTLV2_PLL_SS_STEP_STEP_SHIFT (0U)
|
||||
#define HPM_PLLCTLV2_PLL_SS_STEP_STEP(n) \
|
||||
((uint32_t)(n) << HPM_PLLCTLV2_PLL_SS_STEP_STEP_SHIFT)
|
||||
#define HPM_PLLCTLV2_PLL_SS_STOP_STOP_MASK (0x3FFFFFFFUL)
|
||||
#define HPM_PLLCTLV2_PLL_SS_STOP_STOP_SHIFT (0U)
|
||||
#define HPM_PLLCTLV2_PLL_SS_STOP_STOP(n) \
|
||||
((uint32_t)(n) << PLLCTLV2_PLL_SS_STOP_STOP_SHIFT)
|
||||
|
||||
#define HPM_PLLCTLV2_PLL_CONFIG_SPREAD (0x100U)
|
||||
#define HPM_PLLCTLV2_PLL_CONFIG_REFSEL (0x1U)
|
||||
|
||||
#define HPM_PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK (0xFFFFU)
|
||||
#define HPM_PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT (0U)
|
||||
#define HPM_PLLCTLV2_PLL_LOCKTIME_LOCKTIME(x) \
|
||||
((uint32_t)(x) << PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT)
|
||||
|
||||
#define HPM_PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK (0xFFFFU)
|
||||
#define HPM_PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT (0U)
|
||||
#define HPM_PLLCTLV2_PLL_STEPTIME_STEPTIME(x) \
|
||||
((uint32_t)(x) << PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT)
|
||||
|
||||
#define HPM_PLLCTLV2_PLL_ADVANCED_SLOW (0x10000000UL)
|
||||
#define HPM_PLLCTLV2_PLL_ADVANCED_DITHER (0x1000000UL)
|
||||
|
||||
#define HPM_PLLCTLV2_PLL_DIV_BUSY (0x80000000UL)
|
||||
#define HPM_PLLCTLV2_PLL_DIV_RESPONSE (0x20000000UL)
|
||||
#define HPM_PLLCTLV2_PLL_DIV_ENABLE (0x10000000UL)
|
||||
#define HPM_PLLCTLV2_PLL_DIV_DIV_MASK (0x3FU)
|
||||
#define HPM_PLLCTLV2_PLL_DIV_DIV_SHIFT (0U)
|
||||
#define HPM_PLLCTLV2_PLL_DIV_DIV(x) \
|
||||
((uint32_t)(x) << HPM_PLLCTLV2_PLL_DIV_DIV_SHIFT)
|
||||
# define HPM_PLLCTLV2_PLL_DIV_DIV0 (0UL)
|
||||
# define HPM_PLLCTLV2_PLL_DIV_DIV1 (1UL)
|
||||
# define HPM_PLLCTLV2_PLL_DIV_DIV2 (2UL)
|
||||
|
||||
#define HPM_PLLCTLV2_PLL_PLL0 (0UL)
|
||||
#define HPM_PLLCTLV2_PLL_PLL1 (1UL)
|
||||
#define HPM_PLLCTLV2_PLL_PLL2 (2UL)
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_PLLCTL_H */
|
||||
42
arch/risc-v/src/hpm6000/hardware/hpm_sysctl.h
Normal file
42
arch/risc-v/src/hpm6000/hardware/hpm_sysctl.h
Normal file
@ -0,0 +1,42 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hardware/hpm_sysctl.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_SYSCTL_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_SYSCTL_H
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#define CONFIG_ARCH_FAMILY_HPM6300
|
||||
|
||||
#if defined(CONFIG_ARCH_FAMILY_HPM6300)
|
||||
# include "hpm6300/hpm6300_sysctl.h"
|
||||
#else
|
||||
# error Unrecognized HPM architecture
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_SYSCTL_H */
|
||||
238
arch/risc-v/src/hpm6000/hardware/hpm_uart.h
Normal file
238
arch/risc-v/src/hpm6000/hardware/hpm_uart.h
Normal file
@ -0,0 +1,238 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hardware/hpm_uart.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_UART_H
|
||||
#define ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_UART_H
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define HPM_UART_MINIMUM_BAUDRATE (200U)
|
||||
#define HPM_UART_BAUDRATE_TOLERANCE (3)
|
||||
#define HPM_UART_OSC_MAX (32U)
|
||||
#define HPM_UART_OSC_MIN (8U)
|
||||
#define HPM_UART_BAUDRATE_DIV_MAX (0xFFFFU)
|
||||
#define HPM_UART_BAUDRATE_DIV_MIN (1U)
|
||||
#define HPM_UART_FREQ 2400000
|
||||
|
||||
#define HPM_UART_OSCR_OFFSET 0x14
|
||||
#define HPM_UART_RBR_OFFSET 0x20
|
||||
#define HPM_UART_THR_OFFSET 0x20
|
||||
#define HPM_UART_DLL_OFFSET 0x20
|
||||
#define HPM_UART_IER_OFFSET 0x24
|
||||
#define HPM_UART_DLM_OFFSET 0x24
|
||||
#define HPM_UART_IIR_OFFSET 0x28
|
||||
#define HPM_UART_FCR_OFFSET 0x28
|
||||
#define HPM_UART_LCR_OFFSET 0x2C
|
||||
#define HPM_UART_MCR_OFFSET 0x30
|
||||
#define HPM_UART_LSR_OFFSET 0x34
|
||||
#define HPM_UART_MSR_OFFSET 0x38
|
||||
|
||||
/* Register addresses *******************************************************/
|
||||
|
||||
#define HPM_UART0_OSC (HPM_UART0_BASE + HPM_UART_OSCR_OFFSET)
|
||||
#define HPM_UART0_RBR (HPM_UART0_BASE + HPM_UART_RBR_OFFSET)
|
||||
#define HPM_UART0_THR (HPM_UART0_BASE + HPM_UART_THR_OFFSET)
|
||||
#define HPM_UART0_DLL (HPM_UART0_BASE + HPM_UART_DLL_OFFSET)
|
||||
#define HPM_UART0_IER (HPM_UART0_BASE + HPM_UART_IER_OFFSET)
|
||||
#define HPM_UART0_DLM (HPM_UART0_BASE + HPM_UART_DLM_OFFSET)
|
||||
#define HPM_UART0_IIR (HPM_UART0_BASE + HPM_UART_IIR_OFFSET)
|
||||
#define HPM_UART0_FCR (HPM_UART0_BASE + HPM_UART_FCR_OFFSET)
|
||||
#define HPM_UART0_LCR (HPM_UART0_BASE + HPM_UART_LCR_OFFSET)
|
||||
#define HPM_UART0_MCR (HPM_UART0_BASE + HPM_UART_MCR_OFFSET)
|
||||
#define HPM_UART0_LSR (HPM_UART0_BASE + HPM_UART_LSR_OFFSET)
|
||||
#define HPM_UART0_MSR (HPM_UART0_BASE + HPM_UART_MSR_OFFSET)
|
||||
|
||||
#define HPM_UART1_OSC (HPM_UART1_BASE + HPM_UART_OSCR_OFFSET)
|
||||
#define HPM_UART1_RBR (HPM_UART1_BASE + HPM_UART_RBR_OFFSET)
|
||||
#define HPM_UART1_THR (HPM_UART1_BASE + HPM_UART_THR_OFFSET)
|
||||
#define HPM_UART1_DLL (HPM_UART1_BASE + HPM_UART_DLL_OFFSET)
|
||||
#define HPM_UART1_IER (HPM_UART1_BASE + HPM_UART_IER_OFFSET)
|
||||
#define HPM_UART1_DLM (HPM_UART1_BASE + HPM_UART_DLM_OFFSET)
|
||||
#define HPM_UART1_IIR (HPM_UART1_BASE + HPM_UART_IIR_OFFSET)
|
||||
#define HPM_UART1_FCR (HPM_UART1_BASE + HPM_UART_FCR_OFFSET)
|
||||
#define HPM_UART1_LCR (HPM_UART1_BASE + HPM_UART_LCR_OFFSET)
|
||||
#define HPM_UART1_MCR (HPM_UART1_BASE + HPM_UART_MCR_OFFSET)
|
||||
#define HPM_UART1_LSR (HPM_UART1_BASE + HPM_UART_LSR_OFFSET)
|
||||
#define HPM_UART1_MSR (HPM_UART1_BASE + HPM_UART_MSR_OFFSET)
|
||||
|
||||
#define HPM_UART2_OSC (HPM_UART2_BASE + HPM_UART_OSCR_OFFSET)
|
||||
#define HPM_UART2_RBR (HPM_UART2_BASE + HPM_UART_RBR_OFFSET)
|
||||
#define HPM_UART2_THR (HPM_UART2_BASE + HPM_UART_THR_OFFSET)
|
||||
#define HPM_UART2_DLL (HPM_UART2_BASE + HPM_UART_DLL_OFFSET)
|
||||
#define HPM_UART2_IER (HPM_UART2_BASE + HPM_UART_IER_OFFSET)
|
||||
#define HPM_UART2_DLM (HPM_UART2_BASE + HPM_UART_DLM_OFFSET)
|
||||
#define HPM_UART2_IIR (HPM_UART2_BASE + HPM_UART_IIR_OFFSET)
|
||||
#define HPM_UART2_FCR (HPM_UART2_BASE + HPM_UART_FCR_OFFSET)
|
||||
#define HPM_UART2_LCR (HPM_UART2_BASE + HPM_UART_LCR_OFFSET)
|
||||
#define HPM_UART2_MCR (HPM_UART2_BASE + HPM_UART_MCR_OFFSET)
|
||||
#define HPM_UART2_LSR (HPM_UART2_BASE + HPM_UART_LSR_OFFSET)
|
||||
#define HPM_UART2_MSR (HPM_UART2_BASE + HPM_UART_MSR_OFFSET)
|
||||
|
||||
#define HPM_UART3_OSC (HPM_UART3_BASE + HPM_UART_OSCR_OFFSET)
|
||||
#define HPM_UART3_RBR (HPM_UART3_BASE + HPM_UART_RBR_OFFSET)
|
||||
#define HPM_UART3_THR (HPM_UART3_BASE + HPM_UART_THR_OFFSET)
|
||||
#define HPM_UART3_DLL (HPM_UART3_BASE + HPM_UART_DLL_OFFSET)
|
||||
#define HPM_UART3_IER (HPM_UART3_BASE + HPM_UART_IER_OFFSET)
|
||||
#define HPM_UART3_DLM (HPM_UART3_BASE + HPM_UART_DLM_OFFSET)
|
||||
#define HPM_UART3_IIR (HPM_UART3_BASE + HPM_UART_IIR_OFFSET)
|
||||
#define HPM_UART3_FCR (HPM_UART3_BASE + HPM_UART_FCR_OFFSET)
|
||||
#define HPM_UART3_LCR (HPM_UART3_BASE + HPM_UART_LCR_OFFSET)
|
||||
#define HPM_UART3_MCR (HPM_UART3_BASE + HPM_UART_MCR_OFFSET)
|
||||
#define HPM_UART3_LSR (HPM_UART3_BASE + HPM_UART_LSR_OFFSET)
|
||||
#define HPM_UART3_MSR (HPM_UART3_BASE + HPM_UART_MSR_OFFSET)
|
||||
|
||||
#define HPM_UART4_OSC (HPM_UART4_BASE + HPM_UART_OSCR_OFFSET)
|
||||
#define HPM_UART4_RBR (HPM_UART4_BASE + HPM_UART_RBR_OFFSET)
|
||||
#define HPM_UART4_THR (HPM_UART4_BASE + HPM_UART_THR_OFFSET)
|
||||
#define HPM_UART4_DLL (HPM_UART4_BASE + HPM_UART_DLL_OFFSET)
|
||||
#define HPM_UART4_IER (HPM_UART4_BASE + HPM_UART_IER_OFFSET)
|
||||
#define HPM_UART4_DLM (HPM_UART4_BASE + HPM_UART_DLM_OFFSET)
|
||||
#define HPM_UART4_IIR (HPM_UART4_BASE + HPM_UART_IIR_OFFSET)
|
||||
#define HPM_UART4_FCR (HPM_UART4_BASE + HPM_UART_FCR_OFFSET)
|
||||
#define HPM_UART4_LCR (HPM_UART4_BASE + HPM_UART_LCR_OFFSET)
|
||||
#define HPM_UART4_MCR (HPM_UART4_BASE + HPM_UART_MCR_OFFSET)
|
||||
#define HPM_UART4_LSR (HPM_UART4_BASE + HPM_UART_LSR_OFFSET)
|
||||
#define HPM_UART4_MSR (HPM_UART4_BASE + HPM_UART_MSR_OFFSET)
|
||||
|
||||
#define HPM_UART5_OSC (HPM_UART5_BASE + HPM_UART_OSCR_OFFSET)
|
||||
#define HPM_UART5_RBR (HPM_UART5_BASE + HPM_UART_RBR_OFFSET)
|
||||
#define HPM_UART5_THR (HPM_UART5_BASE + HPM_UART_THR_OFFSET)
|
||||
#define HPM_UART5_DLL (HPM_UART5_BASE + HPM_UART_DLL_OFFSET)
|
||||
#define HPM_UART5_IER (HPM_UART5_BASE + HPM_UART_IER_OFFSET)
|
||||
#define HPM_UART5_DLM (HPM_UART5_BASE + HPM_UART_DLM_OFFSET)
|
||||
#define HPM_UART5_IIR (HPM_UART5_BASE + HPM_UART_IIR_OFFSET)
|
||||
#define HPM_UART5_FCR (HPM_UART5_BASE + HPM_UART_FCR_OFFSET)
|
||||
#define HPM_UART5_LCR (HPM_UART5_BASE + HPM_UART_LCR_OFFSET)
|
||||
#define HPM_UART5_MCR (HPM_UART5_BASE + HPM_UART_MCR_OFFSET)
|
||||
#define HPM_UART5_LSR (HPM_UART5_BASE + HPM_UART_LSR_OFFSET)
|
||||
#define HPM_UART5_MSR (HPM_UART5_BASE + HPM_UART_MSR_OFFSET)
|
||||
|
||||
#define HPM_UART6_OSC (HPM_UART6_BASE + HPM_UART_OSCR_OFFSET)
|
||||
#define HPM_UART6_RBR (HPM_UART6_BASE + HPM_UART_RBR_OFFSET)
|
||||
#define HPM_UART6_THR (HPM_UART6_BASE + HPM_UART_THR_OFFSET)
|
||||
#define HPM_UART6_DLL (HPM_UART6_BASE + HPM_UART_DLL_OFFSET)
|
||||
#define HPM_UART6_IER (HPM_UART6_BASE + HPM_UART_IER_OFFSET)
|
||||
#define HPM_UART6_DLM (HPM_UART6_BASE + HPM_UART_DLM_OFFSET)
|
||||
#define HPM_UART6_IIR (HPM_UART6_BASE + HPM_UART_IIR_OFFSET)
|
||||
#define HPM_UART6_FCR (HPM_UART6_BASE + HPM_UART_FCR_OFFSET)
|
||||
#define HPM_UART6_LCR (HPM_UART6_BASE + HPM_UART_LCR_OFFSET)
|
||||
#define HPM_UART6_MCR (HPM_UART6_BASE + HPM_UART_MCR_OFFSET)
|
||||
#define HPM_UART6_LSR (HPM_UART6_BASE + HPM_UART_LSR_OFFSET)
|
||||
#define HPM_UART6_MSR (HPM_UART6_BASE + HPM_UART_MSR_OFFSET)
|
||||
|
||||
#define HPM_UART7_OSC (HPM_UART7_BASE + HPM_UART_OSCR_OFFSET)
|
||||
#define HPM_UART7_RBR (HPM_UART7_BASE + HPM_UART_RBR_OFFSET)
|
||||
#define HPM_UART7_THR (HPM_UART7_BASE + HPM_UART_THR_OFFSET)
|
||||
#define HPM_UART7_DLL (HPM_UART7_BASE + HPM_UART_DLL_OFFSET)
|
||||
#define HPM_UART7_IER (HPM_UART7_BASE + HPM_UART_IER_OFFSET)
|
||||
#define HPM_UART7_DLM (HPM_UART7_BASE + HPM_UART_DLM_OFFSET)
|
||||
#define HPM_UART7_IIR (HPM_UART7_BASE + HPM_UART_IIR_OFFSET)
|
||||
#define HPM_UART7_FCR (HPM_UART7_BASE + HPM_UART_FCR_OFFSET)
|
||||
#define HPM_UART7_LCR (HPM_UART7_BASE + HPM_UART_LCR_OFFSET)
|
||||
#define HPM_UART7_MCR (HPM_UART7_BASE + HPM_UART_MCR_OFFSET)
|
||||
#define HPM_UART7_LSR (HPM_UART7_BASE + HPM_UART_LSR_OFFSET)
|
||||
#define HPM_UART7_MSR (HPM_UART7_BASE + HPM_UART_MSR_OFFSET)
|
||||
|
||||
/* Register bit definitions *************************************************/
|
||||
|
||||
#define UART_RXIDLE_CFG_DETECT_COND (1U << 9)
|
||||
#define UART_RXIDLE_CFG_DETECT_EN (1U << 8)
|
||||
#define UART_RXIDLE_CFG_THR_SHIFT (0U)
|
||||
#define UART_RXIDLE_CFG_THR_MASK (0xff << UART_RXIDLE_CFG_THR_SHIFT)
|
||||
#define UART_RXIDLE_CFG_THR(n) ((uint32_t)(n) << UART_RXIDLE_CFG_THR_SHIFT)
|
||||
|
||||
#define UART_CFG_FIFOSIZE_SHIFT (0U)
|
||||
#define UART_CFG_FIFOSIZE_MASK (2 << UART_CFG_FIFOSIZE_SHIFT)
|
||||
# define UART_CFG_FIFOSIZE_16B (0 << UART_CFG_FIFOSIZE_SHIFT)
|
||||
# define UART_CFG_FIFOSIZE_32B (1 << UART_CFG_FIFOSIZE_SHIFT)
|
||||
# define UART_CFG_FIFOSIZE_64B (2 << UART_CFG_FIFOSIZE_SHIFT)
|
||||
# define UART_CFG_FIFOSIZE_128B (3 << UART_CFG_FIFOSIZE_SHIFT)
|
||||
|
||||
#define UART_OSCR_OSC_SHIFT (0U)
|
||||
#define UART_OSCR_OSC_MASK (0x1f << UART_OSCR_OSC_SHIFT)
|
||||
# define UART_OSCR_OSC(n) ((uint32_t)(n) << UART_OSCR_OSC_SHIFT)
|
||||
|
||||
#define UART_RBR_RBR_MASK (0xffff)
|
||||
|
||||
#define UART_IER_ERBI (1 << 0)
|
||||
#define UART_IER_ETHEI (1 << 1)
|
||||
#define UART_IER_ELSI (1 << 2)
|
||||
#define UART_IER_EMSI (1 << 3)
|
||||
#define UART_IER_ERXIDLE (1 << 31)
|
||||
#define UART_ALL_INTS (UART_IER_ERBI | UART_IER_ETHEI | UART_IER_ELSI | UART_IER_EMSI | UART_IER_ERXIDLE)
|
||||
|
||||
#define UART_IIR_INTRID_SHIFT (0U)
|
||||
#define UART_IIR_INTRID_MASK (0xf << UART_IIR_INTRID_SHIFT)
|
||||
#define UART_IIR_INTRID_MODEM_STATE (0x1 << UART_IIR_INTRID_SHIFT)
|
||||
#define UART_IIR_INTRID_TX_AVAILE (0x2 << UART_IIR_INTRID_SHIFT)
|
||||
#define UART_IIR_INTRID_RX_AVAILE (0x4 << UART_IIR_INTRID_SHIFT)
|
||||
#define UART_IIR_INTRID_RX_STATE (0x6 << UART_IIR_INTRID_SHIFT)
|
||||
#define UART_IIR_INTRID_RX_TIMEOUT (0xc << UART_IIR_INTRID_SHIFT)
|
||||
#define UART_IIR_FIFOED_SHIFT (6U)
|
||||
#define UART_IIR_FIFOED_MASK (3 << UART_IIR_FIFOED_SHIFT)
|
||||
#define UART_IIR_DATA_LOST (1 << 27)
|
||||
#define UART_IIR_ADDR_MATCH_IDLE (1 << 28)
|
||||
#define UART_IIR_ADDR_MATCH (1 << 29)
|
||||
#define UART_IIR_TXIDLE_FLAG (1 << 30)
|
||||
#define UART_IIR_RXIDLE_FLAG (1 << 31)
|
||||
|
||||
#define UART_FCR_FIFOE (1 << 0)
|
||||
#define UART_FCR_RXFIFORST (1 << 1)
|
||||
#define UART_FCR_TXFIFORST (1 << 2)
|
||||
#define UART_FCR_DMAE (1 << 3)
|
||||
#define UART_FCR_TFIFOT_SHIFT (4U)
|
||||
#define UART_FCR_TFIFOT_MASK (0x3U << UART_FCR_TFIFO_SHIFT)
|
||||
#define UART_FCR_TFIFOT(n) ((uint32_t)(n) << UART_FCR_TFIFO_SHIFT)
|
||||
#define UART_FCR_RFIFOT_SHIFT (6U)
|
||||
#define UART_FCR_RFIFOT_MASK (0x3U << UART_FCR_RFIFO_SHIFT)
|
||||
#define UART_FCR_RFIFOT(n) ((uint32_t)(n) << UART_FCR_RFIFO_SHIFT)
|
||||
|
||||
#define UART_LCR_WLS_SHIFT (0U)
|
||||
#define UART_LCR_WLS_MASK (0x3U << UART_LCR_WLS_SHIFT)
|
||||
# define UART_LCR_WLS_5BITS (0 << UART_LCR_WLS_SHIFT)
|
||||
# define UART_LCR_WLS_6BITS (1 << UART_LCR_WLS_SHIFT)
|
||||
# define UART_LCR_WLS_7BITS (2 << UART_LCR_WLS_SHIFT)
|
||||
# define UART_LCR_WLS_8BITS (3 << UART_LCR_WLS_SHIFT)
|
||||
#define UART_LCR_STB (1 << 2)
|
||||
#define UART_LCR_PEN (1 << 3)
|
||||
#define UART_LCR_EPS (1 << 4)
|
||||
#define UART_LCR_SPS (1 << 5)
|
||||
#define UART_LCR_BC (1 << 6)
|
||||
#define UART_LCR_DLAB (1 << 7)
|
||||
|
||||
#define UART_MCR_RTS (1 << 0)
|
||||
#define UART_MCR_LOOP (1 << 1)
|
||||
#define UART_MCR_AFE (1 << 5)
|
||||
|
||||
#define UART_LSR_DR (1 << 0)
|
||||
#define UART_LSR_OE (1 << 1)
|
||||
#define UART_LSR_PE (1 << 2)
|
||||
#define UART_LSR_FE (1 << 3)
|
||||
#define UART_LSR_LBREAK (1 << 4)
|
||||
#define UART_LSR_THRE (1 << 5)
|
||||
#define UART_LSR_TEMT (1 << 6)
|
||||
#define UART_LSR_ERRF (1 << 7)
|
||||
|
||||
#define UART_MSR_DCTS (1 << 0)
|
||||
#define UART_MSR_CTS (1 << 4)
|
||||
|
||||
#endif /* ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_UART_H */
|
||||
37
arch/risc-v/src/hpm6000/hpm.h
Normal file
37
arch/risc-v/src/hpm6000/hpm.h
Normal file
@ -0,0 +1,37 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hpm.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HPM_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HPM_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <sys/types.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <arch/irq.h>
|
||||
#include "riscv_internal.h"
|
||||
#include "chip.h"
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_H */
|
||||
210
arch/risc-v/src/hpm6000/hpm_clockconfig.c
Normal file
210
arch/risc-v/src/hpm6000/hpm_clockconfig.c
Normal file
@ -0,0 +1,210 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hpm_clockconfig.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "hardware/hpm6300/hpm6300_sysctl.h"
|
||||
#include "hardware/hpm_memorymap.h"
|
||||
#include "hardware/hpm_pllctl.h"
|
||||
#include "riscv_internal.h"
|
||||
#include "chip.h"
|
||||
#include "hpm.h"
|
||||
#include "hpm_clockconfig.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define EXT_OSC 24000000
|
||||
|
||||
#define PLLCTLV2_PLL_MFN_FACTOR (10U) /* PLLCTLV2 PLL MFN Factor */
|
||||
#define PLLCTLV2_PLL_MFD_DEFAULT (240UL * 1000000UL) /* PLLCTLV2 PLL Default MFD value */
|
||||
|
||||
#define PLLCTLV2_PLL_MFI_MIN (16U)
|
||||
#define PLLCTLV2_PLL_MFI_MAX (42U)
|
||||
#define PLLCTLV2_PLL_XTAL_FREQ (24000000UL)
|
||||
|
||||
#define PLLCTLV2_PLL_FREQ_MIN (PLLCTLV2_PLL_MFI_MIN * PLLCTLV2_PLL_XTAL_FREQ)
|
||||
#define PLLCTLV2_PLL_FREQ_MAX ((PLLCTLV2_PLL_MFI_MAX + 1U) * PLLCTLV2_PLL_XTAL_FREQ)
|
||||
|
||||
#define BUS_FREQ_MAX (166000000UL)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: hpm6750_get_osc_freq
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t hpm_get_osc_freq(void)
|
||||
{
|
||||
return EXT_OSC;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: hpm6750_clockconfig
|
||||
****************************************************************************/
|
||||
|
||||
void hpm_clockconfig(void)
|
||||
{
|
||||
uint32_t value;
|
||||
|
||||
value = getreg32(0xf40c4010);
|
||||
value &= ~0xfff;
|
||||
value |= 0x1044c;
|
||||
putreg32(value, 0xf40c4010);
|
||||
|
||||
/* uart should configure pin function before opening clock */
|
||||
|
||||
value = 0xffffffff &
|
||||
~(SYSCTL_GROUP0_LINK0_UART0 | SYSCTL_GROUP0_LINK0_UART1 |
|
||||
SYSCTL_GROUP0_LINK0_UART2 | SYSCTL_GROUP0_LINK0_UART3 |
|
||||
SYSCTL_GROUP0_LINK0_UART4 | SYSCTL_GROUP0_LINK0_UART5 |
|
||||
SYSCTL_GROUP0_LINK0_UART6);
|
||||
putreg32(0x01f7ffff, HPM_SYSCTL_GROUP0_LINK0_VALUE);
|
||||
|
||||
value = 0xffffffff & ~SYSCTL_GROUP0_LINK1_UART7;
|
||||
putreg32(0x3dfffffe, HPM_SYSCTL_GROUP0_LINK1_VALUE);
|
||||
|
||||
/* Connect Group0 to CPU0 */
|
||||
|
||||
putreg32(1, HPM_SYSCTL_AFFILIATE_CPU0_SET);
|
||||
|
||||
value = getreg32(HPM_SYSCTL_CLOCK_CPU_CLK_TOP_CPU0);
|
||||
if ((value & 0xff) == 1)
|
||||
{
|
||||
value = SYSCTL_CLOCK_CPU_MUX_PLL1_CLK0 |
|
||||
SYSCTL_CLOCK_CPU_DIV(CPU_DIV) |
|
||||
SYSCTL_CLOCK_CPU_SUB0_DIV(AXI_SUB_DIV - 1) |
|
||||
SYSCTL_CLOCK_CPU_SUB1_DIV(AHB_SUB_DIV - 1);
|
||||
putreg32(value, HPM_SYSCTL_CLOCK_CPU_CLK_TOP_CPU0);
|
||||
while (getreg32(HPM_SYSCTL_CLOCK_CPU_CLK_TOP_CPU0) & 0x80000000);
|
||||
}
|
||||
|
||||
/* Configure CPU0 clock & AXI Sub-clock & AHB Sub-clock */
|
||||
|
||||
value = SYSCTL_CLOCK_CPU_MUX_PLL1_CLK0 |
|
||||
SYSCTL_CLOCK_CPU_DIV(CPU_DIV - 1) |
|
||||
SYSCTL_CLOCK_CPU_SUB0_DIV(AXI_SUB_DIV - 1) |
|
||||
SYSCTL_CLOCK_CPU_SUB1_DIV(AHB_SUB_DIV - 1);
|
||||
putreg32(value, HPM_SYSCTL_CLOCK_CPU_CLK_TOP_CPU0);
|
||||
while (getreg32(HPM_SYSCTL_CLOCK_CPU_CLK_TOP_CPU0) & 0x80000000);
|
||||
|
||||
#if defined (CONFIG_ARCH_FAMILY_HPM6300)
|
||||
/* Configure PLL1_CLK0 Post Divider */
|
||||
|
||||
value = (getreg32(HPM_PLLCTLV2_PLL1_DIV0) &
|
||||
~HPM_PLLCTLV2_PLL_DIV_DIV_MASK) |
|
||||
HPM_PLLCTLV2_PLL_DIV_DIV(PLL1_DIV) |
|
||||
HPM_PLLCTLV2_PLL_DIV_ENABLE;
|
||||
putreg32(value, HPM_PLLCTLV2_PLL1_DIV0);
|
||||
while (getreg32(HPM_PLLCTLV2_PLL1_DIV0) & 0x80000000);
|
||||
#endif
|
||||
/* Configure PLL1 clock frequencey */
|
||||
|
||||
value = PLL1_FREQ / PLLCTLV2_PLL_XTAL_FREQ - 1;
|
||||
putreg32(value, HPM_PLLCTLV2_PLL1_MFI);
|
||||
while (getreg32(HPM_PLLCTLV2_PLL1_MFI) & 0x80000000);
|
||||
putreg32(value + 1, HPM_PLLCTLV2_PLL1_MFI);
|
||||
while (getreg32(HPM_PLLCTLV2_PLL1_MFI) & 0x80000000);
|
||||
|
||||
value = PLL1_FREQ % PLLCTLV2_PLL_XTAL_FREQ * PLLCTLV2_PLL_MFN_FACTOR;
|
||||
putreg32(value, HPM_PLLCTLV2_PLL1_MFN);
|
||||
while (getreg32(HPM_PLLCTLV2_PLL1_MFN) & 0x80000000);
|
||||
|
||||
value = (getreg32(HPM_SYSCTL_CLOCK_CLK_TOP_MCT0) &
|
||||
~(SYSCTL_CLOCK_MUX_MASK | SYSCTL_CLOCK_DIV_MASK)) |
|
||||
(SYSCTL_CLOCK_MUX_OSC0_CLK0 | SYSCTL_CLOCK_DIV(1));
|
||||
putreg32(value, HPM_SYSCTL_CLOCK_CLK_TOP_MCT0);
|
||||
while (getreg32(HPM_SYSCTL_CLOCK_CLK_TOP_MCT0) & 0x40000000);
|
||||
}
|
||||
|
||||
void hpm_uart_clockconfig(void)
|
||||
{
|
||||
uint32_t value;
|
||||
|
||||
value = getreg32(HPM_SYSCTL_GROUP0_LINK0_VALUE);
|
||||
|
||||
#ifdef CONFIG_HPM_UART0
|
||||
putreg32(SYSCTL_CLOCK_MUX_OSC0_CLK0 | SYSCTL_CLOCK_DIV(1),
|
||||
HPM_SYSCTL_CLOCK_CLK_TOP_UART0);
|
||||
while (getreg32(HPM_SYSCTL_CLOCK_CLK_TOP_UART0) & 0x40000000);
|
||||
value |= SYSCTL_GROUP0_LINK0_UART0;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HPM_UART1
|
||||
putreg32(SYSCTL_CLOCK_MUX_OSC0_CLK0 | SYSCTL_CLOCK_DIV(1),
|
||||
HPM_SYSCTL_CLOCK_CLK_TOP_UART1);
|
||||
value |= SYSCTL_GROUP0_LINK0_UART1;
|
||||
#endif
|
||||
|
||||
#if defined CONFIG_HPM_UART2
|
||||
putreg32(SYSCTL_CLOCK_MUX_OSC0_CLK0 | SYSCTL_CLOCK_DIV(1),
|
||||
HPM_SYSCTL_CLOCK_CLK_TOP_UART2);
|
||||
value |= SYSCTL_GROUP0_LINK0_UART2;
|
||||
#endif
|
||||
|
||||
#if defined CONFIG_HPM_UART3
|
||||
putreg32(SYSCTL_CLOCK_MUX_OSC0_CLK0 | SYSCTL_CLOCK_DIV(1),
|
||||
HPM_SYSCTL_CLOCK_CLK_TOP_UART3);
|
||||
value |= SYSCTL_GROUP0_LINK0_UART3;
|
||||
#endif
|
||||
|
||||
#if defined CONFIG_HPM_UART4
|
||||
putreg32(SYSCTL_CLOCK_MUX_OSC0_CLK0 | SYSCTL_CLOCK_DIV(1),
|
||||
HPM_SYSCTL_CLOCK_CLK_TOP_UART4);
|
||||
value |= SYSCTL_GROUP0_LINK0_UART4;
|
||||
#endif
|
||||
|
||||
#if defined CONFIG_HPM_UART5
|
||||
putreg32(SYSCTL_CLOCK_MUX_OSC0_CLK0 | SYSCTL_CLOCK_DIV(1),
|
||||
HPM_SYSCTL_CLOCK_CLK_TOP_UART5);
|
||||
value |= SYSCTL_GROUP0_LINK0_UART5;
|
||||
#endif
|
||||
|
||||
#if defined CONFIG_HPM_UART6
|
||||
putreg32(SYSCTL_CLOCK_MUX_OSC0_CLK0 | SYSCTL_CLOCK_DIV(1),
|
||||
HPM_SYSCTL_CLOCK_CLK_TOP_UART6);
|
||||
value |= SYSCTL_GROUP0_LINK0_UART6;
|
||||
#endif
|
||||
|
||||
putreg32(value, HPM_SYSCTL_GROUP0_LINK0_SET);
|
||||
|
||||
#ifdef CONFIG_HPM_UART7
|
||||
putreg32(SYSCTL_CLOCK_MUX_OSC0_CLK0 | SYSCTL_CLOCK_DIV(1),
|
||||
HPM_SYSCTL_CLOCK_CLK_TOP_UART7);
|
||||
value = getreg32(HPM_SYSCTL_GROUP0_LINK1_VALUE);
|
||||
value |= SYSCTL_GROUP0_LINK1_UART7;
|
||||
putreg32(value, HPM_SYSCTL_GROUP0_LINK1_SET);
|
||||
#endif
|
||||
}
|
||||
152
arch/risc-v/src/hpm6000/hpm_clockconfig.h
Normal file
152
arch/risc-v/src/hpm6000/hpm_clockconfig.h
Normal file
@ -0,0 +1,152 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hpm_clockconfig.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HPM_CLOCKCONFIG_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HPM_CLOCKCONFIG_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "hpm_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define CPU_DIV 1
|
||||
#define AXI_SUB_DIV 3
|
||||
#define AHB_SUB_DIV 3
|
||||
#define PLL1_DIV 1
|
||||
#define PLL1_FREQ 576000000
|
||||
#define AUD_DIV 46
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief Clock nodes
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
clock_node_mchtmr0 = 0,
|
||||
clock_node_femc = 1,
|
||||
clock_node_xpi0 = 2,
|
||||
clock_node_xpi1 = 3,
|
||||
clock_node_gptmr0 = 4,
|
||||
clock_node_gptmr1 = 5,
|
||||
clock_node_gptmr2 = 6,
|
||||
clock_node_gptmr3 = 7,
|
||||
clock_node_uart0 = 8,
|
||||
clock_node_uart1 = 9,
|
||||
clock_node_uart2 = 10,
|
||||
clock_node_uart3 = 11,
|
||||
clock_node_uart4 = 12,
|
||||
clock_node_uart5 = 13,
|
||||
clock_node_uart6 = 14,
|
||||
clock_node_uart7 = 15,
|
||||
clock_node_i2c0 = 16,
|
||||
clock_node_i2c1 = 17,
|
||||
clock_node_i2c2 = 18,
|
||||
clock_node_i2c3 = 19,
|
||||
clock_node_spi0 = 20,
|
||||
clock_node_spi1 = 21,
|
||||
clock_node_spi2 = 22,
|
||||
clock_node_spi3 = 23,
|
||||
clock_node_can0 = 24,
|
||||
clock_node_can1 = 25,
|
||||
clock_node_ptpc = 26,
|
||||
clock_node_ana0 = 27,
|
||||
clock_node_ana1 = 28,
|
||||
clock_node_ana2 = 29,
|
||||
clock_node_ana3 = 30,
|
||||
clock_node_aud0 = 31,
|
||||
clock_node_aud1 = 32,
|
||||
clock_node_eth0 = 33,
|
||||
clock_node_ptp0 = 34,
|
||||
clock_node_ref0 = 35,
|
||||
clock_node_ref1 = 36,
|
||||
clock_node_ntmr0 = 37,
|
||||
clock_node_sdxc0 = 38,
|
||||
|
||||
clock_node_adc_i2s_start,
|
||||
clock_node_adc0 = clock_node_adc_i2s_start,
|
||||
clock_node_adc1,
|
||||
clock_node_adc2,
|
||||
|
||||
clock_node_i2s0,
|
||||
clock_node_i2s1,
|
||||
|
||||
clock_node_end,
|
||||
|
||||
clock_node_core_start = 0xfc,
|
||||
clock_node_cpu0 = clock_node_core_start,
|
||||
clock_node_axi,
|
||||
clock_node_ahb,
|
||||
} clock_node_t;
|
||||
|
||||
/**
|
||||
* @brief General clock sources
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
clock_source_osc0_clk0 = 0,
|
||||
clock_source_pll0_clk0 = 1,
|
||||
clock_source_pll0_clk1 = 2,
|
||||
clock_source_pll0_clk2 = 3,
|
||||
clock_source_pll1_clk0 = 4,
|
||||
clock_source_pll1_clk1 = 5,
|
||||
clock_source_pll2_clk0 = 6,
|
||||
clock_source_pll2_clk1 = 7,
|
||||
clock_source_general_source_end,
|
||||
} clock_source_t;
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN uint32_t hpm_get_osc_freq(void);
|
||||
EXTERN void hpm_clockconfig(void);
|
||||
void hpm_uart_clockconfig(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
#undef EXTERN
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_CLOCKCONFIG_H */
|
||||
131
arch/risc-v/src/hpm6000/hpm_config.h
Normal file
131
arch/risc-v/src/hpm6000/hpm_config.h
Normal file
@ -0,0 +1,131 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hpm_config.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HPM_CONFIG_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HPM_CONFIG_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <arch/chip/chip.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
#undef HAVE_UART_DEVICE
|
||||
#if defined(CONFIG_HPM_UART0) || defined(CONFIG_HPM_UART1) || \
|
||||
defined(CONFIG_HPM_UART2) || defined(CONFIG_HPM_UART3) || \
|
||||
defined(CONFIG_HPM_UART4) || defined(CONFIG_HPM_UART5) || \
|
||||
defined(CONFIG_HPM_UART6) || defined(CONFIG_HPM_UART7)
|
||||
# define HAVE_UART_DEVICE 1
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_HPM_UART0)
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART6_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||
# define HAVE_UART_CONSOLE 1
|
||||
#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_HPM_UART1)
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART6_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||
# define HAVE_UART_CONSOLE 1
|
||||
#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_HPM_UART2)
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART6_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||
# define HAVE_UART_CONSOLE 1
|
||||
#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_HPM_UART2)
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART6_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||
# define HAVE_UART_CONSOLE 1
|
||||
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_HPM_UART2)
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART6_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||
# define HAVE_UART_CONSOLE 1
|
||||
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_HPM_UART2)
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART6_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||
# define HAVE_UART_CONSOLE 1
|
||||
#elif defined(CONFIG_UART6_SERIAL_CONSOLE) && defined(CONFIG_HPM_UART2)
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||
# define HAVE_UART_CONSOLE 1
|
||||
#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_HPM_UART2)
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART6_SERIAL_CONSOLE
|
||||
# define HAVE_UART_CONSOLE 1
|
||||
#else
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART6_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||
# undef HAVE_UART_CONSOLE
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_CONFIG_H */
|
||||
294
arch/risc-v/src/hpm6000/hpm_gpio.c
Normal file
294
arch/risc-v/src/hpm6000/hpm_gpio.c
Normal file
@ -0,0 +1,294 @@
|
||||
/***************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hpm_gpio.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
/***************************************************************************
|
||||
* Included Files
|
||||
***************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <assert.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
|
||||
#include <chip.h>
|
||||
|
||||
#include "hardware/hpm_memorymap.h"
|
||||
#include "hardware/hpm_ioc.h"
|
||||
#include "hardware/hpm_gpio.h"
|
||||
#include "hpm_gpio.h"
|
||||
#include "riscv_internal.h"
|
||||
#include "hpm_gpio.h"
|
||||
#include "hpm_ioc.h"
|
||||
|
||||
/***************************************************************************
|
||||
* Pre-processor Definitions
|
||||
***************************************************************************/
|
||||
|
||||
#define HPM_GPIO_NPORTS 6
|
||||
|
||||
/***************************************************************************
|
||||
* Private Functions
|
||||
***************************************************************************/
|
||||
|
||||
/***************************************************************************
|
||||
* Public Data
|
||||
***************************************************************************/
|
||||
|
||||
/***************************************************************************
|
||||
* Name: hpm_gpio_dirout
|
||||
***************************************************************************/
|
||||
|
||||
static inline void hpm_gpio_dirout(int port, int pin)
|
||||
{
|
||||
uint32_t regval = getreg32(HPM_GPIO_OE_SET(port));
|
||||
regval |= GPIO_PIN(pin);
|
||||
putreg32(regval, HPM_GPIO_OE_SET(port));
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
* Name: hpm_gpio_diin
|
||||
***************************************************************************/
|
||||
|
||||
static inline void hpm_gpio_dirin(int port, int pin)
|
||||
{
|
||||
uint32_t regval = getreg32(HPM_GPIO_OE_CLR(port));
|
||||
regval |= GPIO_PIN(pin);
|
||||
putreg32(regval, HPM_GPIO_OE_CLR(port));
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
* Name: hpm_gpio_setoutput
|
||||
***************************************************************************/
|
||||
|
||||
static void hpm_gpio_setoutput(int port, int pin, bool value)
|
||||
{
|
||||
uint32_t regval = 0;
|
||||
|
||||
if (value)
|
||||
{
|
||||
regval = getreg32(HPM_GPIO_DO_SET(port));
|
||||
regval |= GPIO_PIN(pin);
|
||||
putreg32(regval, HPM_GPIO_DO_SET(port));
|
||||
}
|
||||
else
|
||||
{
|
||||
regval = getreg32(HPM_GPIO_DO_CLR(port));
|
||||
regval |= GPIO_PIN(pin);
|
||||
putreg32(regval, HPM_GPIO_DO_CLR(port));
|
||||
}
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
* Name: hpm_gpio_getinput
|
||||
***************************************************************************/
|
||||
|
||||
static inline bool hpm_gpio_getinput(int port, int pin)
|
||||
{
|
||||
uint32_t regval = getreg32(HPM_GPIO_DI_VAL(port));
|
||||
|
||||
return ((regval & GPIO_PIN(pin)) != 0);
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
* Name: hpm_gpio_configinput
|
||||
***************************************************************************/
|
||||
|
||||
static int hpm_gpio_configinput(gpio_pinset_t pinset)
|
||||
{
|
||||
int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
ioc_pinset_t ioset;
|
||||
uintptr_t padctl;
|
||||
|
||||
/* Configure pin as */
|
||||
|
||||
hpm_gpio_dirin(port, pin);
|
||||
|
||||
/* Configure pin as a GPIO */
|
||||
|
||||
putreg32(IOC_PAD_FUNC_ALT_SELECT_ALT0, IOC_FUNC_CTL_(port, pin));
|
||||
|
||||
/* Configure pin pad settings */
|
||||
|
||||
padctl = IOC_PAD_CTL_(port, pin);
|
||||
|
||||
ioset = (ioc_pinset_t)(pinset & GPIO_IOCPAD_MASK) >> GPIO_IOCPAD_SHIFT;
|
||||
|
||||
return hpm_iocpad_configure(padctl, ioset);
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
* Name: hpm_gpio_configoutput
|
||||
***************************************************************************/
|
||||
|
||||
static inline int hpm_gpio_configoutput(gpio_pinset_t pinset)
|
||||
{
|
||||
int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
bool value = ((pinset & GPIO_OUTPUT_ONE) != 0);
|
||||
|
||||
/* Set the output value */
|
||||
|
||||
hpm_gpio_setoutput(port, pin, value);
|
||||
|
||||
/* Convert the configured input GPIO to an poutput */
|
||||
|
||||
hpm_gpio_dirout(port, pin);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
* Name: hpm_gpio_configperiph
|
||||
***************************************************************************/
|
||||
|
||||
static inline int hpm_gpio_configperiph(gpio_pinset_t pinset)
|
||||
{
|
||||
unsigned int index;
|
||||
ioc_pinset_t ioset;
|
||||
uintptr_t regaddr;
|
||||
|
||||
index = ((pinset & GPIO_PADMUX_MASK) >> GPIO_PADMUX_SHIFT);
|
||||
ioset = (ioc_pinset_t)(pinset & GPIO_IOCPAD_MASK) >> GPIO_IOCPAD_SHIFT;
|
||||
|
||||
regaddr = HPM_IOC_PAD_PAD_CTL_ADDRESS(index);
|
||||
|
||||
hpm_iocpad_configure(regaddr, ioset);
|
||||
|
||||
if (index >= HPM_IOC_PAD_PY00_INDEX)
|
||||
{
|
||||
regaddr = HPM_PIOC_PAD_PAD_CTL_ADDRESS(index);
|
||||
hpm_iocpad_configure(regaddr, PAD_ALT3);
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
* Public Functions
|
||||
***************************************************************************/
|
||||
|
||||
/***************************************************************************
|
||||
* Name: hpm_gpio_config
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO pin based on pin-encoded description of the pin.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
int hpm_gpio_config(gpio_pinset_t pinset)
|
||||
{
|
||||
irqstate_t flags;
|
||||
int ret;
|
||||
|
||||
/* Configure the pin as an input initially to avoid any spurious outputs */
|
||||
|
||||
flags = enter_critical_section();
|
||||
|
||||
/* Configure based upon the pin mode */
|
||||
|
||||
switch (pinset & GPIO_MODE_MASK)
|
||||
{
|
||||
case GPIO_INPUT:
|
||||
{
|
||||
/* Configure the pin as a GPIO input */
|
||||
|
||||
ret = hpm_gpio_configinput(pinset);
|
||||
}
|
||||
break;
|
||||
|
||||
case GPIO_OUTPUT:
|
||||
{
|
||||
ret = hpm_gpio_configoutput(pinset);
|
||||
}
|
||||
break;
|
||||
|
||||
case GPIO_PERIPH:
|
||||
{
|
||||
ret = hpm_gpio_configperiph(pinset);
|
||||
}
|
||||
break;
|
||||
|
||||
#ifdef CONFIG_HPM_GPIO_IRQ
|
||||
/* TODO: irq configure */
|
||||
#endif
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
* Name: hpm_gpio_write
|
||||
*
|
||||
* Description:
|
||||
* Write one or zero to the selected GPIO pin
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
void hpm_gpio_write(gpio_pinset_t pinset, bool value)
|
||||
{
|
||||
irqstate_t flags;
|
||||
int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
|
||||
flags = enter_critical_section();
|
||||
hpm_gpio_setoutput(port, pin, value);
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
* Name: hpm_gpio_read
|
||||
*
|
||||
* Description:
|
||||
* Read one or zero from the selected GPIO pin
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
bool hpm_gpio_read(gpio_pinset_t pinset)
|
||||
{
|
||||
irqstate_t flags;
|
||||
int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
bool value;
|
||||
|
||||
flags = enter_critical_section();
|
||||
if ((pinset &(GPIO_OUTPUT | GPIO_LOOP_ENABLE)) ==
|
||||
(GPIO_OUTPUT | GPIO_LOOP_ENABLE))
|
||||
{
|
||||
/* TODO: read input state */
|
||||
}
|
||||
else
|
||||
{
|
||||
value = hpm_gpio_getinput(port, pin);
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
||||
return value;
|
||||
}
|
||||
357
arch/risc-v/src/hpm6000/hpm_gpio.h
Normal file
357
arch/risc-v/src/hpm6000/hpm_gpio.h
Normal file
@ -0,0 +1,357 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hpm_gpio.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HPM_GPIO_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HPM_GPIO_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#endif
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/hpm_gpio.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-Processor Declarations
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* 32-bit Encoding:
|
||||
*
|
||||
* 3322 2222 2222 1111 1111 1100 0000 0000
|
||||
* 1098 7654 3210 9876 5432 1098 7654 3210
|
||||
* ENCODING IIXX XXXX XXXX XXXX MMMM MMMM MMMM MMMM
|
||||
* GPIO INPUT 00.. BEEG GGGP PPPP MMMM MMMM MMMM MMMM
|
||||
* INT INPUT 11.. BEEG GGGP PPPP MMMM MMMM MMMM MMMM
|
||||
* GPIO OUTPUT 01V. ..SG GGGP PPPP MMMM MMMM MMMM MMMM
|
||||
* PERIPHERAL 10AA AAS. IIII IIII MMMM MMMM MMMM MMMM
|
||||
*/
|
||||
|
||||
/* Input/Output Selection:
|
||||
*
|
||||
* 3322 2222 2222 1111 1111 1100 0000 0000
|
||||
* 1098 7654 3210 9876 5432 1098 7654 3210
|
||||
* ENCODING II.. .... .... .... .... .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_MODE_SHIFT (30) /* Bits 30-31: Pin mode */
|
||||
#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT)
|
||||
# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* GPIO input */
|
||||
# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* GPIO output */
|
||||
# define GPIO_PERIPH (2 << GPIO_MODE_SHIFT) /* Peripheral */
|
||||
# define GPIO_INTERRUPT (3 << GPIO_MODE_SHIFT) /* Interrupt input */
|
||||
|
||||
/* Initial Output Value:
|
||||
*
|
||||
* GPIO OUTPUT 01V. .... .... .... .... .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_OUTPUT_ZERO (0) /* Bit 29: 0=Initial output is low */
|
||||
#define GPIO_OUTPUT_ONE (1 << 29) /* Bit 29: 1=Initial output is high */
|
||||
|
||||
/* Loopback On Field:
|
||||
*
|
||||
* 3322 2222 2222 1111 1111 1100 0000 0000
|
||||
* 1098 7654 3210 9876 5432 1098 7654 3210
|
||||
* PERIPHERAL .... ..S. .... .... .... .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_LOOP_SHIFT (24) /* Bits 24: Peripheral SION function */
|
||||
#define GPIO_LOOP_MASK (1 << GPIO_LOOP_SHIFT)
|
||||
# define GPIO_LOOP_ENABLE (1 << GPIO_LOOP_SHIFT) /* enable SION */
|
||||
|
||||
/* Interrupt edge/level configuration
|
||||
*
|
||||
* 3322 2222 2222 1111 1111 1100 0000 0000
|
||||
* 1098 7654 3210 9876 5432 1098 7654 3210
|
||||
* INT INPUT 11.. .EE. .... .... .... .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_INTCFG_SHIFT (24) /* Bits 24-25: Interrupt edge/level configuration */
|
||||
#define GPIO_INTCFG_MASK (3 << GPIO_INTCFG_SHIFT)
|
||||
# define GPIO_INT_LOWLEVEL (GPIO_ICR_LOWLEVEL << GPIO_INTCFG_SHIFT)
|
||||
# define GPIO_INT_HIGHLEVEL (GPIO_ICR_HIGHLEVEL << GPIO_INTCFG_SHIFT)
|
||||
# define GPIO_INT_RISINGEDGE (GPIO_ICR_RISINGEDGE << GPIO_INTCFG_SHIFT)
|
||||
# define GPIO_INT_FALLINGEDGE (GPIO_ICR_FALLINGEDGE << GPIO_INTCFG_SHIFT)
|
||||
|
||||
/* GPIO Port Number
|
||||
*
|
||||
* 3322 2222 2222 1111 1111 1100 0000 0000
|
||||
* 1098 7654 3210 9876 5432 1098 7654 3210
|
||||
* GPIO INPUT 00.. ...G GGG. .... .... .... .... ....
|
||||
* GPIO OUTPUT 01.. ...G GGG. .... .... .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_PORT_SHIFT (21) /* Bits 21-23: GPIO port index */
|
||||
#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORTA (GPIOA << GPIO_PORT_SHIFT) /* GPIO1 */
|
||||
# define GPIO_PORTB (GPIOB << GPIO_PORT_SHIFT) /* GPIO2 */
|
||||
# define GPIO_PORTC (GPIOC << GPIO_PORT_SHIFT) /* GPIO3 */
|
||||
# define GPIO_PORTD (GPIOD << GPIO_PORT_SHIFT) /* GPIO3 */
|
||||
# define GPIO_PORTE (GPIOE << GPIO_PORT_SHIFT) /* GPIO3 */
|
||||
# define GPIO_PORTF (GPIOF << GPIO_PORT_SHIFT) /* GPIO3 */
|
||||
# define GPIO_PORTX (GPIOX << GPIO_PORT_SHIFT) /* GPIO4 */
|
||||
# define GPIO_PORTY (GPIOY << GPIO_PORT_SHIFT) /* GPIO5 */
|
||||
# define GPIO_PORTZ (GPIOZ << GPIO_PORT_SHIFT) /* GPIOZ */
|
||||
|
||||
/* GPIO Pin Number:
|
||||
*
|
||||
* 3322 2222 2222 1111 1111 1100 0000 0000
|
||||
* 1098 7654 3210 9876 5432 1098 7654 3210
|
||||
* GPIO INPUT 00.. .... ...P PPPP .... .... .... ....
|
||||
* GPIO OUTPUT 01.. .... ...P PPPP .... .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_PIN_SHIFT (16) /* Bits 0-4: GPIO number: 0-31 */
|
||||
#define GPIO_PIN_MASK (0x1f << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN16 (16 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN17 (17 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN18 (18 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN19 (19 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN20 (20 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN21 (21 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN22 (22 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN23 (23 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN24 (24 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN25 (25 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN26 (26 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN27 (27 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN28 (28 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN29 (29 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN30 (30 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN31 (31 << GPIO_PIN_SHIFT)
|
||||
|
||||
/* Pad Mux Register Index:
|
||||
*
|
||||
* 3322 2222 2222 1111 1111 1100 0000 0000
|
||||
* 1098 7654 3210 9876 5432 1098 7654 3210
|
||||
* PERIPHERAL .... .... IIII IIII .... .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_PADMUX_SHIFT (16)
|
||||
#define GPIO_PADMUX_MASK (0xfff << GPIO_PADMUX_SHIFT)
|
||||
# define GPIO_PADMUX(n) ((uint32_t)(n) << GPIO_PADMUX_SHIFT)
|
||||
#define GPIO_PADMUX_GET(n) ((n&GPIO_PADMUX_MASK) >> GPIO_PADMUX_SHIFT)
|
||||
|
||||
/* IOC PAD CTL Configuration
|
||||
*
|
||||
* 3322 2222 2222 1111 1111 1100 0000 0000
|
||||
* 1098 7654 3210 9876 5432 1098 7654 3210
|
||||
* ENCODING .... .... .... .... MMMM MMMM MMMM MMMM
|
||||
*
|
||||
*/
|
||||
|
||||
#define GPIO_IOCPAD_SHIFT (0)
|
||||
#define GPIO_IOCPAD_MASK (0xffff << GPIO_IOCPAD_SHIFT)
|
||||
|
||||
#define HPM_GPIO_GPIOA (0)
|
||||
#define HPM_GPIO_GPIOB (1)
|
||||
#define HPM_GPIO_GPIOC (2)
|
||||
#define HPM_GPIO_GPIOX (3)
|
||||
#define HPM_GPIO_GPIOY (4)
|
||||
#define HPM_GPIO_GPIOZ (5)
|
||||
|
||||
#define HPM_GPIO_DI_VAL(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0000)
|
||||
#define HPM_GPIO_DI_SET(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0004)
|
||||
#define HPM_GPIO_DI_CLR(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0008)
|
||||
#define HPM_GPIO_DI_TOG(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x000c)
|
||||
|
||||
#define HPM_GPIO_DO_VAL(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0100)
|
||||
#define HPM_GPIO_DO_SET(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0104)
|
||||
#define HPM_GPIO_DO_CLR(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0108)
|
||||
#define HPM_GPIO_DO_TOG(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x010c)
|
||||
|
||||
#define HPM_GPIO_OE_VAL(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0200)
|
||||
#define HPM_GPIO_OE_SET(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0204)
|
||||
#define HPM_GPIO_OE_CLR(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0208)
|
||||
#define HPM_GPIO_OE_TOG(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x020c)
|
||||
|
||||
#define HPM_GPIO_IF_VAL(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0300)
|
||||
#define HPM_GPIO_IF_SET(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0304)
|
||||
#define HPM_GPIO_IF_CLR(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0308)
|
||||
#define HPM_GPIO_IF_TOG(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x030c)
|
||||
|
||||
#define HPM_GPIO_IE_VAL(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0400)
|
||||
#define HPM_GPIO_IE_SET(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0404)
|
||||
#define HPM_GPIO_IE_CLR(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0408)
|
||||
#define HPM_GPIO_IE_TOG(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x040c)
|
||||
|
||||
#define HPM_GPIO_PL_VAL(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0500)
|
||||
#define HPM_GPIO_PL_SET(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0504)
|
||||
#define HPM_GPIO_PL_CLR(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0508)
|
||||
#define HPM_GPIO_PL_TOG(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x050c)
|
||||
|
||||
#define HPM_GPIO_TP_VAL(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0600)
|
||||
#define HPM_GPIO_TP_SET(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0604)
|
||||
#define HPM_GPIO_TP_CLR(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0608)
|
||||
#define HPM_GPIO_TP_TOG(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x060c)
|
||||
|
||||
#define HPM_GPIO_AS_VAL(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0700)
|
||||
#define HPM_GPIO_AS_SET(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0704)
|
||||
#define HPM_GPIO_AS_CLR(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0708)
|
||||
#define HPM_GPIO_AS_TOG(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x070c)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/* The smallest integer type that can hold the GPIO encoding */
|
||||
|
||||
typedef uint32_t gpio_pinset_t;
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: mpfs_configgpio
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO pin based on bit-encoded description of the pin.
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success
|
||||
* ERROR on invalid port.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int hpm_gpio_config(gpio_pinset_t pinset);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: mpfs_gpiowrite
|
||||
*
|
||||
* Description:
|
||||
* Write one or zero to the selected GPIO pin
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void hpm_gpio_write(gpio_pinset_t pinset, bool value);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: mpfs_gpioread
|
||||
*
|
||||
* Description:
|
||||
* Read one or zero from the selected GPIO pin
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
bool hpm_gpio_read(gpio_pinset_t pinset);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: mpfs_gpiosetevent
|
||||
*
|
||||
* Description:
|
||||
* Sets/clears GPIO based event and interrupt triggers.
|
||||
*
|
||||
* Input Parameters:
|
||||
* - pinset: GPIO pin configuration
|
||||
* - risingedge: Enables interrupt on rising edges
|
||||
* - fallingedge: Enables interrupt on falling edges
|
||||
* - high: Enables interrupt on level high
|
||||
* - low: Enables interrupt on level low
|
||||
* - event: Generate event when set
|
||||
* - func: When non-NULL, generate interrupt
|
||||
* - arg: Argument passed to the interrupt callback
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) on success; a negated errno value on failure indicating the
|
||||
* nature of the failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int hpm_gpiosetevent(gpio_pinset_t pinset, bool risingedge,
|
||||
bool fallingedge, bool high, bool low, bool event,
|
||||
xcpt_t func, void *arg);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: mpfs_gpio_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize GPIO drivers for use with /apps/examples/gpio
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int hpm_gpio_initialize(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Function: mpfs_dumpgpio
|
||||
*
|
||||
* Description:
|
||||
* Dump all GPIO registers associated with the provided base address
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_GPIO_INFO
|
||||
int hpm_dumpgpio(gpio_pinset_t pinset, const char *msg);
|
||||
#else
|
||||
#define hpm_dumpgpio(p, m)
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_GPIO_H */
|
||||
77
arch/risc-v/src/hpm6000/hpm_head.S
Normal file
77
arch/risc-v/src/hpm6000/hpm_head.S
Normal file
@ -0,0 +1,77 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hpm_head.S
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <arch/irq.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hpm_memorymap.h"
|
||||
#include "riscv_internal.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Symbols
|
||||
****************************************************************************/
|
||||
|
||||
/* Imported symbols */
|
||||
|
||||
.extern __trap_vec
|
||||
|
||||
.section .text
|
||||
.global __start
|
||||
|
||||
__start:
|
||||
/* reset mstatus to 0*/
|
||||
|
||||
csrrw x0, mstatus, x0
|
||||
|
||||
/* Set stack pointer to the idle thread stack */
|
||||
|
||||
la sp, HPM_IDLESTACK_TOP
|
||||
|
||||
/* Disable all interrupts (i.e. timer, external) in mie */
|
||||
|
||||
csrw mie, zero
|
||||
csrw mip, zero
|
||||
|
||||
/* Initialize the Machine Trap Vector */
|
||||
|
||||
la t0, __trap_vec
|
||||
csrw mtvec, t0
|
||||
|
||||
/* Jump to __hpm_start */
|
||||
|
||||
jal x1, __hpm_start
|
||||
|
||||
/* We shouldn't return from __hpm_start */
|
||||
|
||||
.global _init
|
||||
.global _fini
|
||||
|
||||
_init:
|
||||
_fini:
|
||||
|
||||
/* These don't have to do anything since we use init_array/fini_array. */
|
||||
|
||||
ret
|
||||
|
||||
281
arch/risc-v/src/hpm6000/hpm_ioc.c
Normal file
281
arch/risc-v/src/hpm6000/hpm_ioc.c
Normal file
@ -0,0 +1,281 @@
|
||||
/***************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hpm_ioc.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
/***************************************************************************
|
||||
* Included Files
|
||||
***************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <assert.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include "hardware/hpm_ioc.h"
|
||||
#include "riscv_internal.h"
|
||||
#include "hpm_ioc.h"
|
||||
|
||||
/***************************************************************************
|
||||
* Private Data
|
||||
***************************************************************************/
|
||||
|
||||
/* This table is indexed by the Pad Mux register index and provides the
|
||||
* index to the corresponding Pad Control register.
|
||||
*
|
||||
* REVISIT: This could be greatly simplified: The Pad Control registers
|
||||
* map 1-to-1 with the Pad Mux registers except for two regions where
|
||||
* there are no corresponding Pad Mux registers. The entire table could be
|
||||
* replaced to two range checks and the appropriate offset added to the Pad
|
||||
* Mux Register index.
|
||||
*/
|
||||
|
||||
#if defined (CONFIG_ARCH_FAMILY_HPM6300)
|
||||
static const uint16_t g_iocctl_map[HPM_IOC_PAD_NREGISTERS] =
|
||||
{
|
||||
HPM_IOC_PAD_PA00_INDEX,
|
||||
HPM_IOC_PAD_PA01_INDEX,
|
||||
HPM_IOC_PAD_PA02_INDEX,
|
||||
HPM_IOC_PAD_PA03_INDEX,
|
||||
HPM_IOC_PAD_PA04_INDEX,
|
||||
HPM_IOC_PAD_PA05_INDEX,
|
||||
HPM_IOC_PAD_PA06_INDEX,
|
||||
HPM_IOC_PAD_PA07_INDEX,
|
||||
HPM_IOC_PAD_PA08_INDEX,
|
||||
HPM_IOC_PAD_PA09_INDEX,
|
||||
HPM_IOC_PAD_PA10_INDEX,
|
||||
HPM_IOC_PAD_PA11_INDEX,
|
||||
HPM_IOC_PAD_PA12_INDEX,
|
||||
HPM_IOC_PAD_PA13_INDEX,
|
||||
HPM_IOC_PAD_PA14_INDEX,
|
||||
HPM_IOC_PAD_PA15_INDEX,
|
||||
HPM_IOC_PAD_PA16_INDEX,
|
||||
HPM_IOC_PAD_PA17_INDEX,
|
||||
HPM_IOC_PAD_PA18_INDEX,
|
||||
HPM_IOC_PAD_PA19_INDEX,
|
||||
HPM_IOC_PAD_PA20_INDEX,
|
||||
HPM_IOC_PAD_PA21_INDEX,
|
||||
HPM_IOC_PAD_PA22_INDEX,
|
||||
HPM_IOC_PAD_PA23_INDEX,
|
||||
HPM_IOC_PAD_PA24_INDEX,
|
||||
HPM_IOC_PAD_PA25_INDEX,
|
||||
HPM_IOC_PAD_PA26_INDEX,
|
||||
HPM_IOC_PAD_PA27_INDEX,
|
||||
HPM_IOC_PAD_PA28_INDEX,
|
||||
HPM_IOC_PAD_PA29_INDEX,
|
||||
HPM_IOC_PAD_PA30_INDEX,
|
||||
HPM_IOC_PAD_PA31_INDEX,
|
||||
HPM_IOC_PAD_PB00_INDEX,
|
||||
HPM_IOC_PAD_PB01_INDEX,
|
||||
HPM_IOC_PAD_PB02_INDEX,
|
||||
HPM_IOC_PAD_PB03_INDEX,
|
||||
HPM_IOC_PAD_PB04_INDEX,
|
||||
HPM_IOC_PAD_PB05_INDEX,
|
||||
HPM_IOC_PAD_PB06_INDEX,
|
||||
HPM_IOC_PAD_PB07_INDEX,
|
||||
HPM_IOC_PAD_PB08_INDEX,
|
||||
HPM_IOC_PAD_PB09_INDEX,
|
||||
HPM_IOC_PAD_PB10_INDEX,
|
||||
HPM_IOC_PAD_PB11_INDEX,
|
||||
HPM_IOC_PAD_PB12_INDEX,
|
||||
HPM_IOC_PAD_PB13_INDEX,
|
||||
HPM_IOC_PAD_PB14_INDEX,
|
||||
HPM_IOC_PAD_PB15_INDEX,
|
||||
HPM_IOC_PAD_PB16_INDEX,
|
||||
HPM_IOC_PAD_PB17_INDEX,
|
||||
HPM_IOC_PAD_PB18_INDEX,
|
||||
HPM_IOC_PAD_PB19_INDEX,
|
||||
HPM_IOC_PAD_PB20_INDEX,
|
||||
HPM_IOC_PAD_PB21_INDEX,
|
||||
HPM_IOC_PAD_PB22_INDEX,
|
||||
HPM_IOC_PAD_PB23_INDEX,
|
||||
HPM_IOC_PAD_PB24_INDEX,
|
||||
HPM_IOC_PAD_PB25_INDEX,
|
||||
HPM_IOC_PAD_PB26_INDEX,
|
||||
HPM_IOC_PAD_PB27_INDEX,
|
||||
HPM_IOC_PAD_PB28_INDEX,
|
||||
HPM_IOC_PAD_PB29_INDEX,
|
||||
HPM_IOC_PAD_PB30_INDEX,
|
||||
HPM_IOC_PAD_PB31_INDEX,
|
||||
HPM_IOC_PAD_PC00_INDEX,
|
||||
HPM_IOC_PAD_PC01_INDEX,
|
||||
HPM_IOC_PAD_PC02_INDEX,
|
||||
HPM_IOC_PAD_PC03_INDEX,
|
||||
HPM_IOC_PAD_PC04_INDEX,
|
||||
HPM_IOC_PAD_PC05_INDEX,
|
||||
HPM_IOC_PAD_PC06_INDEX,
|
||||
HPM_IOC_PAD_PC07_INDEX,
|
||||
HPM_IOC_PAD_PC08_INDEX,
|
||||
HPM_IOC_PAD_PC09_INDEX,
|
||||
HPM_IOC_PAD_PC10_INDEX,
|
||||
HPM_IOC_PAD_PC11_INDEX,
|
||||
HPM_IOC_PAD_PC12_INDEX,
|
||||
HPM_IOC_PAD_PC13_INDEX,
|
||||
HPM_IOC_PAD_PC14_INDEX,
|
||||
HPM_IOC_PAD_PC15_INDEX,
|
||||
HPM_IOC_PAD_PC16_INDEX,
|
||||
HPM_IOC_PAD_PC17_INDEX,
|
||||
HPM_IOC_PAD_PC18_INDEX,
|
||||
HPM_IOC_PAD_PC19_INDEX,
|
||||
HPM_IOC_PAD_PC20_INDEX,
|
||||
HPM_IOC_PAD_PC21_INDEX,
|
||||
HPM_IOC_PAD_PC22_INDEX,
|
||||
HPM_IOC_PAD_PC23_INDEX,
|
||||
HPM_IOC_PAD_PC24_INDEX,
|
||||
HPM_IOC_PAD_PC25_INDEX,
|
||||
HPM_IOC_PAD_PC26_INDEX,
|
||||
HPM_IOC_PAD_PC27_INDEX,
|
||||
HPM_IOC_PAD_PX00_INDEX,
|
||||
HPM_IOC_PAD_PX01_INDEX,
|
||||
HPM_IOC_PAD_PX02_INDEX,
|
||||
HPM_IOC_PAD_PX03_INDEX,
|
||||
HPM_IOC_PAD_PX04_INDEX,
|
||||
HPM_IOC_PAD_PX05_INDEX,
|
||||
HPM_IOC_PAD_PX06_INDEX,
|
||||
HPM_IOC_PAD_PX07_INDEX,
|
||||
HPM_IOC_PAD_PY00_INDEX,
|
||||
HPM_IOC_PAD_PY01_INDEX,
|
||||
HPM_IOC_PAD_PY02_INDEX,
|
||||
HPM_IOC_PAD_PY03_INDEX,
|
||||
HPM_IOC_PAD_PY04_INDEX,
|
||||
HPM_IOC_PAD_PY05_INDEX,
|
||||
HPM_IOC_PAD_PY06_INDEX,
|
||||
HPM_IOC_PAD_PY07_INDEX,
|
||||
HPM_IOC_PAD_PZ00_INDEX,
|
||||
HPM_IOC_PAD_PZ01_INDEX,
|
||||
HPM_IOC_PAD_PZ02_INDEX,
|
||||
HPM_IOC_PAD_PZ03_INDEX,
|
||||
HPM_IOC_PAD_PZ04_INDEX,
|
||||
HPM_IOC_PAD_PZ05_INDEX,
|
||||
HPM_IOC_PAD_PZ06_INDEX,
|
||||
HPM_IOC_PAD_PZ07_INDEX,
|
||||
};
|
||||
#endif
|
||||
|
||||
/***************************************************************************
|
||||
* Public Functions
|
||||
***************************************************************************/
|
||||
|
||||
unsigned int hpm_iocpad_map(unsigned int iocpad)
|
||||
{
|
||||
return (unsigned int)g_iocctl_map[iocpad];
|
||||
}
|
||||
|
||||
int hpm_iocpad_configure(uintptr_t padctl, ioc_pinset_t ioset)
|
||||
{
|
||||
uint32_t regval = 0;
|
||||
uint32_t value;
|
||||
uint32_t alt;
|
||||
uintptr_t funcctl;
|
||||
|
||||
/* Select CMOS input or Schmitt Trigger input */
|
||||
|
||||
if ((ioset & PAD_SCHMITT_TRIGGER) != 0)
|
||||
{
|
||||
regval |= IOC_PAD_PAD_HYS;
|
||||
}
|
||||
|
||||
/* Select drive strength */
|
||||
|
||||
value = (ioset & PAD_DRIVE_MASK) >> PAD_DRIVE_SHIFT;
|
||||
regval |= IOC_PAD_PAD_DS(value);
|
||||
|
||||
/* Select speed */
|
||||
|
||||
value = (ioset & PAD_SPEED_MASK) >> PAD_SPEED_SHIFT;
|
||||
regval |= IOC_PAD_PAD_SPD(value);
|
||||
|
||||
/* Select CMOS output or Open Drain output */
|
||||
|
||||
if ((ioset & PAD_OPENDRAIN) != 0)
|
||||
{
|
||||
regval |= IOC_PAD_PAD_OD;
|
||||
}
|
||||
|
||||
/* Handle pull/keep selection */
|
||||
|
||||
switch (ioset & _PAD_PULLTYPE_MASK)
|
||||
{
|
||||
default:
|
||||
break;
|
||||
|
||||
case _PAD_PULL_KEEP:
|
||||
{
|
||||
regval |= IOC_PAD_PAD_KE;
|
||||
}
|
||||
break;
|
||||
|
||||
case _PAD_PULL_ENABLE:
|
||||
{
|
||||
regval |= (IOC_PAD_PAD_KE | IOC_PAD_PAD_PE);
|
||||
if ((ioset & _PAD_PULLTYPE_MASK) != _PAD_PULL_DOWN_100K)
|
||||
{
|
||||
regval |= IOC_PAD_PAD_PS;
|
||||
}
|
||||
|
||||
value = (ioset & _PAD_PULLDESC_MASK) >> _PAD_PULLDESC_SHIFT;
|
||||
regval |= IOC_PAD_PAD_PRS(value);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
/* Select slow/fast slew rate */
|
||||
|
||||
if ((ioset & PAD_SLEW_FAST) != 0)
|
||||
{
|
||||
regval |= IOC_PAD_PAD_SR;
|
||||
}
|
||||
|
||||
/* Write the result to the specified Pad Control register */
|
||||
|
||||
putreg32(regval, padctl);
|
||||
|
||||
/* Configure IOC FUNCTL Register */
|
||||
|
||||
funcctl = padctl - 0x0004;
|
||||
regval = 0;
|
||||
|
||||
/* Configure analog */
|
||||
|
||||
if ((ioset & FUNC_ANALOG_MASK) == FUNC_ANALOG)
|
||||
{
|
||||
regval |= IOC_PAD_FUNC_ANALOG;
|
||||
putreg32(regval, funcctl);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
if ((ioset & PAD_ALT_MASK) == PAD_ALT0)
|
||||
{
|
||||
regval |= IOC_PAD_FUNC_LOOP_BACK;
|
||||
putreg32(regval, funcctl);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
alt = (ioset & PAD_ALT_MASK) >> PAD_ALT_SHIFT;
|
||||
regval |= IOC_PAD_FUNC_ALT_SELECT(alt);
|
||||
|
||||
putreg32(regval, funcctl);
|
||||
|
||||
return OK;
|
||||
}
|
||||
185
arch/risc-v/src/hpm6000/hpm_ioc.h
Normal file
185
arch/risc-v/src/hpm6000/hpm_ioc.h
Normal file
@ -0,0 +1,185 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hpm_ioc.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HPM_IOC_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HPM_IOC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "hardware/hpm_memorymap.h"
|
||||
#include "hardware/hpm_ioc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* 16-bit Encoding:
|
||||
*
|
||||
* AAAA ARRR ODDD LSST
|
||||
*/
|
||||
|
||||
/* Peripheral Alternate Function:
|
||||
* AAAA A... .... ....
|
||||
*/
|
||||
|
||||
#define PAD_ALT_SHIFT (11) /* Bits 11-15: Peripheral alternate function */
|
||||
#define PAD_ALT_MASK (0x1f << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT0 (0 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT1 (1 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT2 (2 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT3 (3 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT4 (4 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT5 (5 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT6 (6 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT7 (7 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT8 (8 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT9 (9 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT10 (10 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT11 (11 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT12 (12 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT13 (13 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT14 (14 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT15 (15 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT16 (16 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT17 (17 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT18 (18 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT19 (19 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT20 (20 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT21 (21 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT22 (22 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT23 (23 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT24 (24 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT25 (25 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT26 (26 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT27 (27 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT28 (28 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT29 (29 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT30 (30 << PAD_ALT_SHIFT)
|
||||
# define PAD_ALT31 (31 << PAD_ALT_SHIFT)
|
||||
|
||||
/* Output Pull Up/Down:
|
||||
*
|
||||
* .... RRRR .... ....
|
||||
*/
|
||||
|
||||
#define _PAD_PULLTYPE_SHIFT (8) /* Bits 8: Pull up/down type */
|
||||
#define _PAD_PULLTYPE_MASK (1 << _PAD_PULLTYPE_SHIFT)
|
||||
# define _PAD_PULL_KEEP (0 << _PAD_PULLTYPE_SHIFT) /* Output determined by keeper */
|
||||
# define _PAD_PULL_ENABLE (1 << _PAD_PULLTYPE_SHIFT) /* Output pulled up or down */
|
||||
|
||||
#define _PAD_PULLDESC_SHIFT (9) /* Bits 9-10: Pull up/down description */
|
||||
#define _PAD_PULLDESC_MASK (3 << _PAD_PULLDESC_SHIFT)
|
||||
# define _PAD_PULL_UP_22K (PULL_UP_22K << _PAD_PULLDESC_SHIFT) /* Pull up with 22 KOhm resister */
|
||||
# define _PAD_PULL_UP_47K (PULL_UP_47K << _PAD_PULLDESC_SHIFT) /* Pull up with 47 KOhm resister */
|
||||
# define _PAD_PULL_UP_100K (PULL_UP_100K << _PAD_PULLDESC_SHIFT) /* Pull up with 100 KOhm resister */
|
||||
# define _PAD_PULL_DOWN_100K (PULL_DOWN_100K << _PAD_PULLDESC_SHIFT) /* Pull down with 100 KOhm resister */
|
||||
|
||||
#define PAD_PULL_SHIFT (8) /* Bits 8-10: Pull up/down selection */
|
||||
#define PAD_PULL_MASK (15 << PAD_PULL_SHIFT)
|
||||
# define PAD_PULL_KEEP _PAD_PULL_KEEP
|
||||
# define PAD_PULL_UP_22K (_PAD_PULL_ENABLE | _PAD_PULL_UP_22K)
|
||||
# define PAD_PULL_UP_47K (_PAD_PULL_ENABLE | _PAD_PULL_UP_47K)
|
||||
# define PAD_PULL_UP_100K (_PAD_PULL_ENABLE | _PAD_PULL_UP_100K)
|
||||
# define PAD_PULL_DOWN_100K (_PAD_PULL_ENABLE | _PAD_PULL_DOWN_100K)
|
||||
|
||||
/* Open Drain Output:
|
||||
*
|
||||
* .... .... O... ....
|
||||
*/
|
||||
|
||||
#define PAD_CMOS_OUTPUT (0) /* Bit 7: 0=CMOS output */
|
||||
#define PAD_OPENDRAIN (1 << 7) /* Bit 7: 1=Enable open-drain output */
|
||||
|
||||
/* Output Drive Strength:
|
||||
*
|
||||
* .... .... .DDD ....
|
||||
*/
|
||||
|
||||
#define PAD_DRIVE_SHIFT (4) /* Bits 4-6: Output Drive Strength */
|
||||
#define PAD_DRIVE_MASK (7 << PAD_DRIVE_SHIFT)
|
||||
# define PAD_DRIVE_260OHM (DRIVE_260OHM << PAD_DRIVE_SHIFT) /* 150 Ohm @3.3V, 260 Ohm @1.8V */
|
||||
# define PAD_DRIVE_130OHM (DRIVE_130OHM << PAD_DRIVE_SHIFT) /* 75 Ohm @3.3V, 130 Ohm @1.8V */
|
||||
# define PAD_DRIVE_88OHM (DRIVE_88OHM << PAD_DRIVE_SHIFT) /* 50 Ohm @3.3V, 90 Ohm @1.8V */
|
||||
# define PAD_DRIVE_65OHM (DRIVE_65OHM << PAD_DRIVE_SHIFT) /* 37 Ohm @3.3V, 60 Ohm @1.8V */
|
||||
# define PAD_DRIVE_52OHM (DRIVE_52OHM << PAD_DRIVE_SHIFT) /* 30 Ohm @3.3V, 50 Ohm @1.8V */
|
||||
# define PAD_DRIVE_43OHM (DRIVE_43OHM << PAD_DRIVE_SHIFT) /* 25 Ohm @3.3V, 40 Ohm @1.8V */
|
||||
# define PAD_DRIVE_37OHM (DRIVE_37OHM << PAD_DRIVE_SHIFT) /* 20 Ohm @3.3V, 33 Ohm @1.8V */
|
||||
|
||||
/* Analog pin
|
||||
*
|
||||
* .... .... .DDD ....
|
||||
*/
|
||||
#define FUNC_ANALOG_SHIFT (4)
|
||||
#define FUNC_ANALOG_MASK (7 << FUNC_ANALOG_SHIFT)
|
||||
#define FUNC_ANALOG (1 << FUNC_ANALOG_SHIFT)
|
||||
|
||||
/* Output Slew Rate:
|
||||
*
|
||||
* .... .... .... L...
|
||||
*/
|
||||
|
||||
#define PAD_SLEW_SLOW (0) /* Bit 3: 0=Slow Slew Rate */
|
||||
#define PAD_SLEW_FAST (1 << 3) /* Bit 3: 1=Fast Slew Rate */
|
||||
|
||||
/* Output Speed:
|
||||
*
|
||||
* .... .... .... .SS.
|
||||
*/
|
||||
|
||||
#define PAD_SPEED_SHIFT (1) /* Bits 1-2: Speed */
|
||||
#define PAD_SPEED_MASK (3 << PAD_SPEED_SHIFT)
|
||||
# define PAD_SPEED_SLOW (SPEED_SLOW << PAD_SPEED_SHIFT) /* Low frequency (50 MHz) */
|
||||
# define PAD_SPEED_MEDIUM (SPEED_MEDIUM << PAD_SPEED_SHIFT) /* Medium frequency (100, 150 MHz) */
|
||||
# define PAD_SPEED_FAST (SPEED_FAST << PAD_SPEED_SHIFT) /* Fast frequency */
|
||||
# define PAD_SPEED_MAX (SPEED_MAX << PAD_SPEED_SHIFT) /* Maximum frequency (100, 150, 200 MHz) */
|
||||
|
||||
/* Input Schmitt Trigger:
|
||||
*
|
||||
* .... .... .... ...T
|
||||
*/
|
||||
|
||||
#define PAD_CMOS_INPUT (0) /* Bit 0: 0=CMOS input */
|
||||
#define PAD_SCHMITT_TRIGGER (1 << 0) /* Bit 0: 1=Enable Schmitt trigger if input */
|
||||
|
||||
#define IOC_FUNC_CTL_(port, pin) (HPM_IOC_BASE + port * 0x0100 + pin * 0x0008 + 0x0000)
|
||||
#define IOC_PAD_CTL_(port, pin) (HPM_IOC_BASE + port * 0x0100 + pin * 0x0008 + 0x0004)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/* The smallest integer type that can hold the IOMUX encoding */
|
||||
|
||||
typedef uint16_t ioc_pinset_t;
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
unsigned int hpm_iocpad_map(unsigned int iocpad);
|
||||
int hpm_iocpad_configure(uintptr_t padctl, ioc_pinset_t ioset);
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_IOC_H */
|
||||
976
arch/risc-v/src/hpm6000/hpm_iomux.h
Normal file
976
arch/risc-v/src/hpm6000/hpm_iomux.h
Normal file
@ -0,0 +1,976 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hpm_iomux.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HPM_IOMUX_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HPM_IOMUX_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "hardware/hpm_ioc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* IOC_PA00_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA00_FUNC_CTL_GPIO_A_00 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA00_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA00_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA00_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PA00_FUNC_CTL_SDC0_DATA_1 IOC_PAD_FUNC_ALT_SELECT(17)
|
||||
|
||||
/* IOC_PA01_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA01_FUNC_CTL_GPIO_A_01 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA01_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA01_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA01_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PA01_FUNC_CTL_SDC0_DATA_0 IOC_PAD_FUNC_ALT_SELECT(17)
|
||||
|
||||
/* IOC_PA02_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA02_FUNC_CTL_GPIO_A_02 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA02_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA02_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA02_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PA02_FUNC_CTL_SDC0_CLK IOC_PAD_FUNC_ALT_SELECT(17)
|
||||
|
||||
/* IOC_PA03_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA03_FUNC_CTL_GPIO_A_03 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA03_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA03_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA03_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PA03_FUNC_CTL_SDC0_CMD IOC_PAD_FUNC_ALT_SELECT(17)
|
||||
|
||||
/* IOC_PA04_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA04_FUNC_CTL_GPIO_A_04 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA04_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA04_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA04_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PA04_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
#define IOC_PA04_FUNC_CTL_SDC0_DATA_3 IOC_PAD_FUNC_ALT_SELECT(17)
|
||||
|
||||
/* IOC_PA05_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA05_FUNC_CTL_GPIO_A_05 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA05_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA05_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA05_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PA05_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
#define IOC_PA05_FUNC_CTL_SDC0_DATA_2 IOC_PAD_FUNC_ALT_SELECT(17)
|
||||
|
||||
/* IOC_PA06_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA06_FUNC_CTL_GPIO_A_06 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PA06_FUNC_CTL_UART2_DE IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA06_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PA06_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PA06_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA06_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PA06_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_ALT_SELECT(18)
|
||||
|
||||
/* IOC_PA07_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA07_FUNC_CTL_GPIO_A_07 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA07_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PA07_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PA07_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PA07_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA07_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PA07_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_ALT_SELECT(18)
|
||||
|
||||
/* IOC_PA08_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA08_FUNC_CTL_GPIO_A_08 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA08_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PA08_FUNC_CTL_UART3_DE IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA08_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PA08_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PA08_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA08_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PA08_FUNC_CTL_XPI0_CB_D_0 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PA08_FUNC_CTL_SDC0_DATA_2 IOC_PAD_FUNC_ALT_SELECT(17)
|
||||
#define IOC_PA08_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_ALT_SELECT(18)
|
||||
|
||||
/* IOC_PA09_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA09_FUNC_CTL_GPIO_A_09 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA09_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PA09_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PA09_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PA09_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA09_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PA09_FUNC_CTL_XPI0_CB_D_2 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PA09_FUNC_CTL_SDC0_DATA_3 IOC_PAD_FUNC_ALT_SELECT(17)
|
||||
#define IOC_PA09_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_ALT_SELECT(18)
|
||||
|
||||
/* IOC_PA10_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA10_FUNC_CTL_GPIO_A_10 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA10_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PA10_FUNC_CTL_UART4_DE IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA10_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PA10_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA10_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PA10_FUNC_CTL_XPI0_CB_D_1 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PA10_FUNC_CTL_SDC0_CMD IOC_PAD_FUNC_ALT_SELECT(17)
|
||||
#define IOC_PA10_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_ALT_SELECT(18)
|
||||
|
||||
/* IOC_PA11_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA11_FUNC_CTL_GPIO_A_11 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA11_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PA11_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PA11_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA11_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PA11_FUNC_CTL_XPI0_CB_SCLK IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PA11_FUNC_CTL_SDC0_CLK IOC_PAD_FUNC_ALT_SELECT(17)
|
||||
#define IOC_PA11_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_ALT_SELECT(18)
|
||||
|
||||
/* IOC_PA12_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA12_FUNC_CTL_GPIO_A_12 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA12_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PA12_FUNC_CTL_UART5_DE IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA12_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PA12_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA12_FUNC_CTL_XPI0_CB_D_3 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PA12_FUNC_CTL_SDC0_DATA_0 IOC_PAD_FUNC_ALT_SELECT(17)
|
||||
#define IOC_PA12_FUNC_CTL_ETH0_REFCLK IOC_PAD_FUNC_ALT_SELECT(18)
|
||||
|
||||
/* IOC_PA13_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA13_FUNC_CTL_GPIO_A_13 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA13_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PA13_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PA13_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA13_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
#define IOC_PA13_FUNC_CTL_XPI0_CB_DQS IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PA13_FUNC_CTL_SDC0_DATA_1 IOC_PAD_FUNC_ALT_SELECT(17)
|
||||
#define IOC_PA13_FUNC_CTL_ETH0_RXER IOC_PAD_FUNC_ALT_SELECT(18)
|
||||
#define IOC_PA13_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_ALT_SELECT(19)
|
||||
#define IOC_PA13_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_ALT_SELECT(24)
|
||||
|
||||
/* IOC_PA14_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA14_FUNC_CTL_GPIO_A_14 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA14_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA14_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA14_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
#define IOC_PA14_FUNC_CTL_XPI0_CB_CS1 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PA14_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
#define IOC_PA14_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_ALT_SELECT(17)
|
||||
#define IOC_PA14_FUNC_CTL_ETH0_RXD_3 IOC_PAD_FUNC_ALT_SELECT(18)
|
||||
#define IOC_PA14_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_ALT_SELECT(19)
|
||||
#define IOC_PA14_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_ALT_SELECT(24)
|
||||
|
||||
/* IOC_PA15_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA15_FUNC_CTL_GPIO_A_15 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA15_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA15_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA15_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
#define IOC_PA15_FUNC_CTL_XPI0_CB_CS0 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PA15_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
#define IOC_PA15_FUNC_CTL_SDC0_WP IOC_PAD_FUNC_ALT_SELECT(17)
|
||||
#define IOC_PA15_FUNC_CTL_ETH0_RXD_2 IOC_PAD_FUNC_ALT_SELECT(18)
|
||||
#define IOC_PA15_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_ALT_SELECT(19)
|
||||
#define IOC_PA15_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_ALT_SELECT(24)
|
||||
|
||||
/* IOC_PA16_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA16_FUNC_CTL_GPIO_A_16 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA16_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA16_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA16_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
#define IOC_PA16_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
#define IOC_PA16_FUNC_CTL_SDC0_VSEL IOC_PAD_FUNC_ALT_SELECT(17)
|
||||
#define IOC_PA16_FUNC_CTL_ETH0_RXCK IOC_PAD_FUNC_ALT_SELECT(18)
|
||||
#define IOC_PA16_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_ALT_SELECT(19)
|
||||
#define IOC_PA16_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_ALT_SELECT(24)
|
||||
|
||||
/* IOC_PA17_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA17_FUNC_CTL_GPIO_A_17 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA17_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA17_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA17_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
#define IOC_PA17_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
#define IOC_PA17_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_ALT_SELECT(18)
|
||||
#define IOC_PA17_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_ALT_SELECT(24)
|
||||
|
||||
/* IOC_PA18_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA18_FUNC_CTL_GPIO_A_18 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA18_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA18_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA18_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
#define IOC_PA18_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
#define IOC_PA18_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_ALT_SELECT(18)
|
||||
#define IOC_PA18_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_ALT_SELECT(24)
|
||||
|
||||
/* IOC_PA19_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA19_FUNC_CTL_GPIO_A_19 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA19_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PA19_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA19_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PA19_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA19_FUNC_CTL_DAOR_P IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
#define IOC_PA19_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
#define IOC_PA19_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_ALT_SELECT(18)
|
||||
|
||||
/* IOC_PA20_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA20_FUNC_CTL_GPIO_A_20 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA20_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PA20_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA20_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PA20_FUNC_CTL_DAOR_N IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
#define IOC_PA20_FUNC_CTL_TRGM1_P_00 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
#define IOC_PA20_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_ALT_SELECT(18)
|
||||
|
||||
/* IOC_PA21_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA21_FUNC_CTL_GPIO_A_21 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA21_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PA21_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA21_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PA21_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PA21_FUNC_CTL_DAOL_P IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
#define IOC_PA21_FUNC_CTL_TRGM1_P_01 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
#define IOC_PA21_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_ALT_SELECT(18)
|
||||
|
||||
/* IOC_PA22_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA22_FUNC_CTL_GPIO_A_22 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA22_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PA22_FUNC_CTL_UART6_DE IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA22_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PA22_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PA22_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PA22_FUNC_CTL_DAOL_N IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
#define IOC_PA22_FUNC_CTL_TRGM1_P_02 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
#define IOC_PA22_FUNC_CTL_ETH0_REFCLK IOC_PAD_FUNC_ALT_SELECT(18)
|
||||
|
||||
/* IOC_PA23_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA23_FUNC_CTL_GPIO_A_23 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA23_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PA23_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PA23_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PA23_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PA23_FUNC_CTL_FEMC_CS_1 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PA23_FUNC_CTL_TRGM1_P_03 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
#define IOC_PA23_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_ALT_SELECT(18)
|
||||
|
||||
/* IOC_PA24_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA24_FUNC_CTL_GPIO_A_24 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA24_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PA24_FUNC_CTL_UART7_DE IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA24_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PA24_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PA24_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PA24_FUNC_CTL_FEMC_SCLK IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PA24_FUNC_CTL_TRGM1_P_04 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
#define IOC_PA24_FUNC_CTL_ETH0_TXD_2 IOC_PAD_FUNC_ALT_SELECT(18)
|
||||
|
||||
/* IOC_PA25_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA25_FUNC_CTL_GPIO_A_25 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA25_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PA25_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PA25_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PA25_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PA25_FUNC_CTL_FEMC_DQ_07 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PA25_FUNC_CTL_TRGM1_P_05 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
#define IOC_PA25_FUNC_CTL_ETH0_TXD_3 IOC_PAD_FUNC_ALT_SELECT(18)
|
||||
#define IOC_PA25_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_ALT_SELECT(19)
|
||||
|
||||
/* IOC_PA26_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA26_FUNC_CTL_GPIO_A_26 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA26_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PA26_FUNC_CTL_UART0_DE IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA26_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PA26_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PA26_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PA26_FUNC_CTL_FEMC_DQ_06 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PA26_FUNC_CTL_TRGM1_P_06 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
#define IOC_PA26_FUNC_CTL_ETH0_CRS IOC_PAD_FUNC_ALT_SELECT(18)
|
||||
#define IOC_PA26_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_ALT_SELECT(19)
|
||||
|
||||
/* IOC_PA27_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA27_FUNC_CTL_GPIO_A_27 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA27_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PA27_FUNC_CTL_FEMC_DQ_05 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PA27_FUNC_CTL_TRGM1_P_07 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
#define IOC_PA27_FUNC_CTL_ETH0_COL IOC_PAD_FUNC_ALT_SELECT(18)
|
||||
|
||||
/* IOC_PA28_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA28_FUNC_CTL_GPIO_A_28 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA28_FUNC_CTL_UART1_DE IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA28_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PA28_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA28_FUNC_CTL_FEMC_DQ_04 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PA28_FUNC_CTL_TRGM1_P_08 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PA29_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA29_FUNC_CTL_GPIO_A_29 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA29_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PA29_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA29_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PA29_FUNC_CTL_FEMC_DQ_03 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PA29_FUNC_CTL_TRGM1_P_09 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PA30_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA30_FUNC_CTL_GPIO_A_30 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA30_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA30_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA30_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PA30_FUNC_CTL_FEMC_DQ_02 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PA30_FUNC_CTL_TRGM1_P_10 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PA31_FUNC_CTL function mux definitions */
|
||||
#define IOC_PA31_FUNC_CTL_GPIO_A_31 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PA31_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PA31_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PA31_FUNC_CTL_FEMC_DQ_01 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PA31_FUNC_CTL_TRGM1_P_11 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB00_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB00_FUNC_CTL_GPIO_B_00 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB00_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB00_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PB00_FUNC_CTL_FEMC_DQ_00 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB00_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB01_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB01_FUNC_CTL_GPIO_B_01 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB01_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB01_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PB01_FUNC_CTL_FEMC_DM_0 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB01_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB02_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB02_FUNC_CTL_GPIO_B_02 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB02_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB02_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PB02_FUNC_CTL_FEMC_DQ_08 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB02_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB03_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB03_FUNC_CTL_GPIO_B_03 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB03_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB03_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PB03_FUNC_CTL_FEMC_DQ_09 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB03_FUNC_CTL_XPI1_CB_CS0 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PB03_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB04_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB04_FUNC_CTL_GPIO_B_04 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB04_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB04_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PB04_FUNC_CTL_FEMC_DQ_10 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB04_FUNC_CTL_XPI1_CB_CS1 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PB04_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB05_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB05_FUNC_CTL_GPIO_B_05 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB05_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB05_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PB05_FUNC_CTL_FEMC_DQ_11 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB05_FUNC_CTL_XPI1_CB_DQS IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PB05_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB06_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB06_FUNC_CTL_GPIO_B_06 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB06_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB06_FUNC_CTL_FEMC_DQ_12 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB06_FUNC_CTL_XPI1_CB_D_3 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PB06_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB07_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB07_FUNC_CTL_GPIO_B_07 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB07_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB07_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PB07_FUNC_CTL_FEMC_DQ_13 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB07_FUNC_CTL_XPI1_CB_D_1 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PB07_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB08_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB08_FUNC_CTL_GPIO_B_08 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB08_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB08_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PB08_FUNC_CTL_FEMC_DQ_14 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB08_FUNC_CTL_XPI1_CB_SCLK IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PB08_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB09_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB09_FUNC_CTL_GPIO_B_09 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB09_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB09_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PB09_FUNC_CTL_FEMC_DQ_15 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB09_FUNC_CTL_XPI1_CB_D_2 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PB09_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB10_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB10_FUNC_CTL_GPIO_B_10 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB10_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB10_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PB10_FUNC_CTL_FEMC_DM_1 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB10_FUNC_CTL_XPI1_CB_D_0 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PB10_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB11_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB11_FUNC_CTL_GPIO_B_11 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB11_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB11_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PB11_FUNC_CTL_FEMC_WE IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB11_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PB11_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB12_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB12_FUNC_CTL_GPIO_B_12 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB12_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB12_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PB12_FUNC_CTL_FEMC_CAS IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB12_FUNC_CTL_XPI1_CA_D_0 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PB12_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB13_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB13_FUNC_CTL_GPIO_B_13 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB13_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB13_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PB13_FUNC_CTL_FEMC_RAS IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB13_FUNC_CTL_XPI1_CA_D_2 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PB13_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB14_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB14_FUNC_CTL_GPIO_B_14 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB14_FUNC_CTL_UART6_DE IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB14_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PB14_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PB14_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PB14_FUNC_CTL_FEMC_CS_0 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB14_FUNC_CTL_XPI1_CA_SCLK IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PB14_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB15_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB15_FUNC_CTL_GPIO_B_15 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB15_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PB15_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PB15_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PB15_FUNC_CTL_FEMC_BA0 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB15_FUNC_CTL_XPI1_CA_D_1 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PB15_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB16_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB16_FUNC_CTL_GPIO_B_16 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB16_FUNC_CTL_UART7_DE IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB16_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PB16_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PB16_FUNC_CTL_FEMC_BA1 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB16_FUNC_CTL_XPI1_CA_D_3 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PB16_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB17_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB17_FUNC_CTL_GPIO_B_17 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB17_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PB17_FUNC_CTL_FEMC_A_10 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB17_FUNC_CTL_XPI1_CA_CS0 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
#define IOC_PB17_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB18_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB18_FUNC_CTL_GPIO_B_18 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB18_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PB18_FUNC_CTL_UART0_DE IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB18_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PB18_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PB18_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PB18_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_ALT_SELECT(8)
|
||||
#define IOC_PB18_FUNC_CTL_FEMC_A_00 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB18_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB19_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB19_FUNC_CTL_GPIO_B_19 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB19_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PB19_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PB19_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PB19_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PB19_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_ALT_SELECT(8)
|
||||
#define IOC_PB19_FUNC_CTL_FEMC_A_01 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB19_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB20_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB20_FUNC_CTL_GPIO_B_20 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB20_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PB20_FUNC_CTL_UART1_DE IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB20_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PB20_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PB20_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PB20_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_ALT_SELECT(8)
|
||||
#define IOC_PB20_FUNC_CTL_FEMC_A_02 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB20_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB21_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB21_FUNC_CTL_GPIO_B_21 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB21_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PB21_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PB21_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PB21_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PB21_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_ALT_SELECT(8)
|
||||
#define IOC_PB21_FUNC_CTL_FEMC_A_03 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB21_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB22_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB22_FUNC_CTL_GPIO_B_22 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB22_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PB22_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB22_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PB22_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PB22_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_ALT_SELECT(8)
|
||||
#define IOC_PB22_FUNC_CTL_FEMC_CLK IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB22_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
#define IOC_PB22_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_ALT_SELECT(24)
|
||||
|
||||
/* IOC_PB23_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB23_FUNC_CTL_GPIO_B_23 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB23_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PB23_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB23_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PB23_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PB23_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_ALT_SELECT(8)
|
||||
#define IOC_PB23_FUNC_CTL_FEMC_CKE IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB23_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
#define IOC_PB23_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_ALT_SELECT(24)
|
||||
|
||||
/* IOC_PB24_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB24_FUNC_CTL_GPIO_B_24 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB24_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PB24_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB24_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PB24_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_ALT_SELECT(8)
|
||||
#define IOC_PB24_FUNC_CTL_FEMC_A_12 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB24_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB25_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB25_FUNC_CTL_GPIO_B_25 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB25_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PB25_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB25_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PB25_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_ALT_SELECT(8)
|
||||
#define IOC_PB25_FUNC_CTL_FEMC_A_11 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB25_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB26_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB26_FUNC_CTL_GPIO_B_26 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB26_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB26_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_ALT_SELECT(8)
|
||||
#define IOC_PB26_FUNC_CTL_FEMC_A_09 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB26_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB27_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB27_FUNC_CTL_GPIO_B_27 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB27_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB27_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PB27_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_ALT_SELECT(8)
|
||||
#define IOC_PB27_FUNC_CTL_FEMC_A_08 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB27_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB28_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB28_FUNC_CTL_GPIO_B_28 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB28_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB28_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PB28_FUNC_CTL_I2S0_RXD_3 IOC_PAD_FUNC_ALT_SELECT(8)
|
||||
#define IOC_PB28_FUNC_CTL_FEMC_A_07 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB28_FUNC_CTL_TRGM0_P_08 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB29_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB29_FUNC_CTL_GPIO_B_29 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB29_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB29_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PB29_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_ALT_SELECT(8)
|
||||
#define IOC_PB29_FUNC_CTL_FEMC_A_06 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB29_FUNC_CTL_TRGM0_P_09 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB30_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB30_FUNC_CTL_GPIO_B_30 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB30_FUNC_CTL_UART2_DE IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PB30_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PB30_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PB30_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_ALT_SELECT(8)
|
||||
#define IOC_PB30_FUNC_CTL_FEMC_A_05 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB30_FUNC_CTL_TRGM0_P_10 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PB31_FUNC_CTL function mux definitions */
|
||||
#define IOC_PB31_FUNC_CTL_GPIO_B_31 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PB31_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PB31_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PB31_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_ALT_SELECT(8)
|
||||
#define IOC_PB31_FUNC_CTL_FEMC_A_04 IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PB31_FUNC_CTL_TRGM0_P_11 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PC00_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC00_FUNC_CTL_GPIO_C_00 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC00_FUNC_CTL_UART3_DE IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PC00_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PC00_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PC00_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_ALT_SELECT(8)
|
||||
#define IOC_PC00_FUNC_CTL_FEMC_SRDY IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PC00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
#define IOC_PC00_FUNC_CTL_USB0_ID IOC_PAD_FUNC_ALT_SELECT(24)
|
||||
|
||||
/* IOC_PC01_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC01_FUNC_CTL_GPIO_C_01 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC01_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PC01_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PC01_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_ALT_SELECT(8)
|
||||
#define IOC_PC01_FUNC_CTL_FEMC_DQS IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PC01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
#define IOC_PC01_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_ALT_SELECT(24)
|
||||
|
||||
/* IOC_PC02_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC02_FUNC_CTL_GPIO_C_02 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC02_FUNC_CTL_UART4_DE IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PC02_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PC02_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PC02_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_ALT_SELECT(8)
|
||||
#define IOC_PC02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
#define IOC_PC02_FUNC_CTL_USB0_OC IOC_PAD_FUNC_ALT_SELECT(24)
|
||||
|
||||
/* IOC_PC03_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC03_FUNC_CTL_GPIO_C_03 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC03_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PC03_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PC03_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_ALT_SELECT(8)
|
||||
#define IOC_PC03_FUNC_CTL_I2S1_TXD_3 IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
#define IOC_PC03_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
#define IOC_PC03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PC04_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC04_FUNC_CTL_GPIO_C_04 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC04_FUNC_CTL_UART5_DE IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PC04_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PC04_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PC04_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_ALT_SELECT(8)
|
||||
#define IOC_PC04_FUNC_CTL_I2S1_TXD_2 IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
#define IOC_PC04_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
#define IOC_PC04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PC05_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC05_FUNC_CTL_GPIO_C_05 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC05_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PC05_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PC05_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_ALT_SELECT(8)
|
||||
#define IOC_PC05_FUNC_CTL_I2S1_TXD_1 IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
#define IOC_PC05_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
#define IOC_PC05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
#define IOC_PC05_FUNC_CTL_USB0_OC IOC_PAD_FUNC_ALT_SELECT(24)
|
||||
|
||||
/* IOC_PC06_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC06_FUNC_CTL_GPIO_C_06 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC06_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PC06_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PC06_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PC06_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_ALT_SELECT(8)
|
||||
#define IOC_PC06_FUNC_CTL_I2S1_TXD_0 IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
#define IOC_PC06_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
#define IOC_PC06_FUNC_CTL_USB0_ID IOC_PAD_FUNC_ALT_SELECT(24)
|
||||
|
||||
/* IOC_PC07_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC07_FUNC_CTL_GPIO_C_07 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC07_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PC07_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PC07_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PC07_FUNC_CTL_I2S0_RXD_3 IOC_PAD_FUNC_ALT_SELECT(8)
|
||||
#define IOC_PC07_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
#define IOC_PC07_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
#define IOC_PC07_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_ALT_SELECT(19)
|
||||
#define IOC_PC07_FUNC_CTL_USB0_OC IOC_PAD_FUNC_ALT_SELECT(24)
|
||||
|
||||
/* IOC_PC08_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC08_FUNC_CTL_GPIO_C_08 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC08_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PC08_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PC08_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PC08_FUNC_CTL_I2S1_FCLK IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
#define IOC_PC08_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
#define IOC_PC08_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_ALT_SELECT(19)
|
||||
#define IOC_PC08_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_ALT_SELECT(24)
|
||||
|
||||
/* IOC_PC09_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC09_FUNC_CTL_GPIO_C_09 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC09_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PC09_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PC09_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PC09_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PC09_FUNC_CTL_I2S1_BCLK IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
#define IOC_PC09_FUNC_CTL_DAOR_N IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
|
||||
/* IOC_PC10_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC10_FUNC_CTL_GPIO_C_10 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC10_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PC10_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PC10_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PC10_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PC10_FUNC_CTL_I2S1_RXD_0 IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
#define IOC_PC10_FUNC_CTL_DAOR_P IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
|
||||
/* IOC_PC11_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC11_FUNC_CTL_GPIO_C_11 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC11_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PC11_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PC11_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PC11_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PC11_FUNC_CTL_I2S1_RXD_1 IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
#define IOC_PC11_FUNC_CTL_DAOL_N IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
|
||||
/* IOC_PC12_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC12_FUNC_CTL_GPIO_C_12 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC12_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PC12_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PC12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PC12_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PC12_FUNC_CTL_I2S1_RXD_2 IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
#define IOC_PC12_FUNC_CTL_DAOL_P IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
|
||||
/* IOC_PC13_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC13_FUNC_CTL_GPIO_C_13 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC13_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PC13_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PC13_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PC13_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PC13_FUNC_CTL_I2S1_RXD_3 IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
|
||||
/* IOC_PC14_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC14_FUNC_CTL_GPIO_C_14 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC14_FUNC_CTL_UART6_DE IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PC14_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PC14_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PC14_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PC14_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
#define IOC_PC14_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PC15_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC15_FUNC_CTL_GPIO_C_15 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC15_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PC15_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PC15_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_ALT_SELECT(16)
|
||||
|
||||
/* IOC_PC16_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC16_FUNC_CTL_GPIO_C_16 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC16_FUNC_CTL_UART7_DE IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PC16_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PC16_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PC16_FUNC_CTL_I2S1_TXD_3 IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
|
||||
/* IOC_PC17_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC17_FUNC_CTL_GPIO_C_17 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC17_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PC17_FUNC_CTL_I2S1_TXD_2 IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
#define IOC_PC17_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
|
||||
/* IOC_PC18_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC18_FUNC_CTL_GPIO_C_18 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC18_FUNC_CTL_UART0_DE IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PC18_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PC18_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PC18_FUNC_CTL_I2S1_TXD_1 IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
#define IOC_PC18_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
|
||||
/* IOC_PC19_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC19_FUNC_CTL_GPIO_C_19 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC19_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PC19_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PC19_FUNC_CTL_I2S1_TXD_0 IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
#define IOC_PC19_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
|
||||
/* IOC_PC20_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC20_FUNC_CTL_GPIO_C_20 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC20_FUNC_CTL_UART1_DE IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PC20_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PC20_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PC20_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
#define IOC_PC20_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
#define IOC_PC20_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_ALT_SELECT(19)
|
||||
#define IOC_PC20_FUNC_CTL_WDG0_RST IOC_PAD_FUNC_ALT_SELECT(24)
|
||||
|
||||
/* IOC_PC21_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC21_FUNC_CTL_GPIO_C_21 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC21_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PC21_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PC21_FUNC_CTL_I2S1_FCLK IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
#define IOC_PC21_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
#define IOC_PC21_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_ALT_SELECT(19)
|
||||
#define IOC_PC21_FUNC_CTL_WDG1_RST IOC_PAD_FUNC_ALT_SELECT(24)
|
||||
|
||||
/* IOC_PC22_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC22_FUNC_CTL_GPIO_C_22 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC22_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PC22_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PC22_FUNC_CTL_I2S1_BCLK IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
#define IOC_PC22_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
#define IOC_PC22_FUNC_CTL_SDC0_WP IOC_PAD_FUNC_ALT_SELECT(17)
|
||||
#define IOC_PC22_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_ALT_SELECT(19)
|
||||
|
||||
/* IOC_PC23_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC23_FUNC_CTL_GPIO_C_23 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC23_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PC23_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PC23_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
#define IOC_PC23_FUNC_CTL_SDC0_VSEL IOC_PAD_FUNC_ALT_SELECT(17)
|
||||
#define IOC_PC23_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_ALT_SELECT(19)
|
||||
|
||||
/* IOC_PC24_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC24_FUNC_CTL_GPIO_C_24 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC24_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PC24_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PC24_FUNC_CTL_I2S1_RXD_0 IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
#define IOC_PC24_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_ALT_SELECT(17)
|
||||
|
||||
/* IOC_PC25_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC25_FUNC_CTL_GPIO_C_25 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC25_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PC25_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PC25_FUNC_CTL_I2S1_RXD_1 IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
#define IOC_PC25_FUNC_CTL_SDC0_WP IOC_PAD_FUNC_ALT_SELECT(17)
|
||||
|
||||
/* IOC_PC26_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC26_FUNC_CTL_GPIO_C_26 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC26_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PC26_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PC26_FUNC_CTL_I2S1_RXD_2 IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
#define IOC_PC26_FUNC_CTL_SDC0_VSEL IOC_PAD_FUNC_ALT_SELECT(17)
|
||||
#define IOC_PC26_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_ALT_SELECT(19)
|
||||
|
||||
/* IOC_PC27_FUNC_CTL function mux definitions */
|
||||
#define IOC_PC27_FUNC_CTL_GPIO_C_27 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PC27_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PC27_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PC27_FUNC_CTL_I2S1_RXD_3 IOC_PAD_FUNC_ALT_SELECT(9)
|
||||
#define IOC_PC27_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_ALT_SELECT(17)
|
||||
#define IOC_PC27_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_ALT_SELECT(19)
|
||||
|
||||
/* IOC_PX00_FUNC_CTL function mux definitions */
|
||||
#define IOC_PX00_FUNC_CTL_GPIO_X_00 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PX00_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
|
||||
/* IOC_PX01_FUNC_CTL function mux definitions */
|
||||
#define IOC_PX01_FUNC_CTL_GPIO_X_01 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PX01_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
|
||||
/* IOC_PX02_FUNC_CTL function mux definitions */
|
||||
#define IOC_PX02_FUNC_CTL_GPIO_X_02 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PX02_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
|
||||
/* IOC_PX03_FUNC_CTL function mux definitions */
|
||||
#define IOC_PX03_FUNC_CTL_GPIO_X_03 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PX03_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
|
||||
/* IOC_PX04_FUNC_CTL function mux definitions */
|
||||
#define IOC_PX04_FUNC_CTL_GPIO_X_04 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PX04_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
|
||||
/* IOC_PX05_FUNC_CTL function mux definitions */
|
||||
#define IOC_PX05_FUNC_CTL_GPIO_X_05 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PX05_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
|
||||
/* IOC_PX06_FUNC_CTL function mux definitions */
|
||||
#define IOC_PX06_FUNC_CTL_GPIO_X_06 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PX06_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
|
||||
/* IOC_PX07_FUNC_CTL function mux definitions */
|
||||
#define IOC_PX07_FUNC_CTL_GPIO_X_07 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PX07_FUNC_CTL_FEMC_DQS IOC_PAD_FUNC_ALT_SELECT(12)
|
||||
#define IOC_PX07_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_ALT_SELECT(14)
|
||||
|
||||
/* IOC_PY00_FUNC_CTL function mux definitions */
|
||||
#define IOC_PY00_FUNC_CTL_GPIO_Y_00 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PY00_FUNC_CTL_UART7_DE IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PY00_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PY00_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PY00_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
|
||||
/* IOC_PY01_FUNC_CTL function mux definitions */
|
||||
#define IOC_PY01_FUNC_CTL_GPIO_Y_01 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PY01_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PY01_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
#define IOC_PY01_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
|
||||
/* IOC_PY02_FUNC_CTL function mux definitions */
|
||||
#define IOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PY02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PY02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PY02_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
|
||||
/* IOC_PY03_FUNC_CTL function mux definitions */
|
||||
#define IOC_PY03_FUNC_CTL_GPIO_Y_03 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PY03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
#define IOC_PY03_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_ALT_SELECT(5)
|
||||
|
||||
/* IOC_PY04_FUNC_CTL function mux definitions */
|
||||
#define IOC_PY04_FUNC_CTL_GPIO_Y_04 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PY04_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PY04_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PY04_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PY04_FUNC_CTL_DAOR_P IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
#define IOC_PY04_FUNC_CTL_WDG0_RST IOC_PAD_FUNC_ALT_SELECT(24)
|
||||
|
||||
/* IOC_PY05_FUNC_CTL function mux definitions */
|
||||
#define IOC_PY05_FUNC_CTL_GPIO_Y_05 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PY05_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PY05_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PY05_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
#define IOC_PY05_FUNC_CTL_DAOR_N IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
#define IOC_PY05_FUNC_CTL_WDG1_RST IOC_PAD_FUNC_ALT_SELECT(24)
|
||||
|
||||
/* IOC_PY06_FUNC_CTL function mux definitions */
|
||||
#define IOC_PY06_FUNC_CTL_GPIO_Y_06 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PY06_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PY06_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PY06_FUNC_CTL_DAOL_P IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
|
||||
/* IOC_PY07_FUNC_CTL function mux definitions */
|
||||
#define IOC_PY07_FUNC_CTL_GPIO_Y_07 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PY07_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PY07_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#define IOC_PY07_FUNC_CTL_DAOL_N IOC_PAD_FUNC_ALT_SELECT(10)
|
||||
|
||||
/* IOC_PZ00_FUNC_CTL function mux definitions */
|
||||
#define IOC_PZ00_FUNC_CTL_GPIO_Z_00 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PZ00_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PZ00_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
|
||||
/* IOC_PZ01_FUNC_CTL function mux definitions */
|
||||
#define IOC_PZ01_FUNC_CTL_GPIO_Z_01 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PZ01_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PZ01_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
|
||||
/* IOC_PZ02_FUNC_CTL function mux definitions */
|
||||
#define IOC_PZ02_FUNC_CTL_GPIO_Z_02 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PZ02_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PZ02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
|
||||
/* IOC_PZ03_FUNC_CTL function mux definitions */
|
||||
#define IOC_PZ03_FUNC_CTL_GPIO_Z_03 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PZ03_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PZ03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
|
||||
/* IOC_PZ04_FUNC_CTL function mux definitions */
|
||||
#define IOC_PZ04_FUNC_CTL_GPIO_Z_04 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PZ04_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PZ04_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
|
||||
/* IOC_PZ05_FUNC_CTL function mux definitions */
|
||||
#define IOC_PZ05_FUNC_CTL_GPIO_Z_05 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PZ05_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PZ05_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_ALT_SELECT(7)
|
||||
|
||||
/* IOC_PZ06_FUNC_CTL function mux definitions */
|
||||
#define IOC_PZ06_FUNC_CTL_GPIO_Z_06 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PZ06_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PZ06_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
|
||||
/* IOC_PZ07_FUNC_CTL function mux definitions */
|
||||
#define IOC_PZ07_FUNC_CTL_GPIO_Z_07 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PZ07_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PZ07_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_ALT_SELECT(4)
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_IOMUX_H */
|
||||
213
arch/risc-v/src/hpm6000/hpm_irq.c
Normal file
213
arch/risc-v/src/hpm6000/hpm_irq.c
Normal file
@ -0,0 +1,213 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hpm_irq.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/irq.h>
|
||||
|
||||
#include "riscv_internal.h"
|
||||
#include "chip.h"
|
||||
#include "hpm.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_irqinitialize
|
||||
****************************************************************************/
|
||||
|
||||
void up_irqinitialize(void)
|
||||
{
|
||||
/* Disable Machine interrupts */
|
||||
|
||||
up_irq_save();
|
||||
|
||||
/* Disable all global interrupts */
|
||||
|
||||
putreg32(0x0, HPM_PLIC_INTEN0);
|
||||
putreg32(0x0, HPM_PLIC_INTEN1);
|
||||
putreg32(0x0, HPM_PLIC_INTEN2);
|
||||
putreg32(0x0, HPM_PLIC_INTEN3);
|
||||
|
||||
/* Clear pendings in PLIC */
|
||||
|
||||
uint32_t val = getreg32(HPM_PLIC_CLAIM);
|
||||
putreg32(val, HPM_PLIC_CLAIM);
|
||||
|
||||
/* Colorize the interrupt stack for debug purposes */
|
||||
|
||||
#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 15
|
||||
size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~15);
|
||||
riscv_stack_color(g_intstackalloc, intstack_size);
|
||||
#endif
|
||||
|
||||
/* Set priority for all global interrupts to 1 (lowest) */
|
||||
|
||||
for (int id = 1; id <= 78; id++)
|
||||
{
|
||||
putreg32(1, HPM_PLIC_PRIORITY + (4 * id));
|
||||
}
|
||||
|
||||
/* Set irq threshold to 0 (permits all global interrupts) */
|
||||
|
||||
putreg32(0, HPM_PLIC_THRESHOLD);
|
||||
|
||||
/* Attach the common interrupt handler */
|
||||
|
||||
riscv_exception_attach();
|
||||
|
||||
#ifndef CONFIG_SUPPRESS_INTERRUPTS
|
||||
|
||||
/* And finally, enable interrupts */
|
||||
|
||||
up_irq_enable();
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_disable_irq
|
||||
*
|
||||
* Description:
|
||||
* Disable the IRQ specified by 'irq'
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_disable_irq(int irq)
|
||||
{
|
||||
int extirq = 0;
|
||||
|
||||
if (irq == RISCV_IRQ_MSOFT)
|
||||
{
|
||||
/* Read mstatus & clear machine software interrupt enable in mie */
|
||||
|
||||
CLEAR_CSR(mie, MIE_MSIE);
|
||||
}
|
||||
else if (irq == RISCV_IRQ_MTIMER)
|
||||
{
|
||||
/* Read mstatus & clear machine timer interrupt enable in mie */
|
||||
|
||||
CLEAR_CSR(mie, MIE_MTIE);
|
||||
}
|
||||
else if (irq >= HPM_IRQ_PERI_START)
|
||||
{
|
||||
extirq = irq - HPM_IRQ_PERI_START;
|
||||
|
||||
/* Clear enable bit for the irq */
|
||||
|
||||
if (1 <= extirq && extirq <= 127)
|
||||
{
|
||||
modifyreg32(HPM_PLIC_INTEN0 + (4 * (extirq / 32)),
|
||||
1 << (extirq % 32), 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
ASSERT(false);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_enable_irq
|
||||
*
|
||||
* Description:
|
||||
* Enable the IRQ specified by 'irq'
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_enable_irq(int irq)
|
||||
{
|
||||
int extirq;
|
||||
|
||||
if (irq == RISCV_IRQ_MSOFT)
|
||||
{
|
||||
/* Read mstatus & set machine software interrupt enable in mie */
|
||||
|
||||
SET_CSR(mie, MIE_MSIE);
|
||||
}
|
||||
else if (irq == RISCV_IRQ_MTIMER)
|
||||
{
|
||||
/* Read mstatus & set machine timer interrupt enable in mie */
|
||||
|
||||
SET_CSR(mie, MIE_MTIE);
|
||||
}
|
||||
else if (irq >= HPM_IRQ_PERI_START)
|
||||
{
|
||||
extirq = irq - HPM_IRQ_PERI_START;
|
||||
|
||||
/* Set enable bit for the irq */
|
||||
|
||||
if (1 <= extirq && extirq <= 127)
|
||||
{
|
||||
modifyreg32(HPM_PLIC_INTEN0 + (4 * (extirq / 32)),
|
||||
0, 1 << (extirq % 32));
|
||||
}
|
||||
else
|
||||
{
|
||||
ASSERT(false);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: riscv_ack_irq
|
||||
*
|
||||
* Description:
|
||||
* Acknowledge the IRQ
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void riscv_ack_irq(int irq)
|
||||
{
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_irq_enable
|
||||
*
|
||||
* Description:
|
||||
* Return the current interrupt state and enable interrupts
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
irqstate_t up_irq_enable(void)
|
||||
{
|
||||
irqstate_t oldstat;
|
||||
|
||||
/* Enable MEIE (machine external interrupt enable) */
|
||||
|
||||
/* TODO: should move to up_enable_irq() */
|
||||
|
||||
SET_CSR(mie, MIE_MEIE);
|
||||
|
||||
/* Read mstatus & set machine interrupt enable (MIE) in mstatus */
|
||||
|
||||
oldstat = READ_AND_SET_CSR(mstatus, MSTATUS_MIE);
|
||||
return oldstat;
|
||||
}
|
||||
87
arch/risc-v/src/hpm6000/hpm_irq_dispatch.c
Normal file
87
arch/risc-v/src/hpm6000/hpm_irq_dispatch.c
Normal file
@ -0,0 +1,87 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hpm_irq_dispatch.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include "riscv_internal.h"
|
||||
#include "chip.h"
|
||||
#include "hpm.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define RV_IRQ_MASK 27
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* riscv_dispatch_irq
|
||||
****************************************************************************/
|
||||
|
||||
void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
|
||||
{
|
||||
int irq = (vector >> RV_IRQ_MASK) | (vector & 0xf);
|
||||
|
||||
/* Firstly, check if the irq is machine external interrupt */
|
||||
|
||||
if (RISCV_IRQ_MEXT == irq)
|
||||
{
|
||||
uint32_t val = getreg32(HPM_PLIC_CLAIM);
|
||||
|
||||
/* Add the value to nuttx irq which is offset to the mext */
|
||||
|
||||
irq = val + HPM_IRQ_PERI_START;
|
||||
}
|
||||
|
||||
/* Acknowledge the interrupt */
|
||||
|
||||
riscv_ack_irq(irq);
|
||||
|
||||
/* claim_irq was zero means no interrupt */
|
||||
|
||||
if (HPM_IRQ_PERI_START != irq)
|
||||
{
|
||||
/* Deliver the IRQ */
|
||||
|
||||
regs = riscv_doirq(irq, regs);
|
||||
}
|
||||
|
||||
if (HPM_IRQ_PERI_START <= irq)
|
||||
{
|
||||
/* Then write PLIC_CLAIM to clear pending in PLIC */
|
||||
|
||||
putreg32(irq - HPM_IRQ_PERI_START, HPM_PLIC_CLAIM);
|
||||
}
|
||||
|
||||
return regs;
|
||||
}
|
||||
474
arch/risc-v/src/hpm6000/hpm_lowputc.c
Normal file
474
arch/risc-v/src/hpm6000/hpm_lowputc.c
Normal file
@ -0,0 +1,474 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hpm_lowputc.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "riscv_internal.h"
|
||||
#include "chip.h"
|
||||
#include "hpm.h"
|
||||
#include "hpm_config.h"
|
||||
#include "hpm_clockconfig.h"
|
||||
#include "hpm_iomux.h"
|
||||
#include "hardware/hpm_uart.h"
|
||||
#include "hpm_gpio.h"
|
||||
#include "hpm_lowputc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Select UART parameters for the selected console */
|
||||
|
||||
#ifdef HAVE_UART_CONSOLE
|
||||
# if defined(CONFIG_UART0_SERIAL_CONSOLE)
|
||||
# define HPM_CONSOLE_BASE HPM_UART0_BASE
|
||||
# define HPM_CONSOLE_BAUD CONFIG_UART0_BAUD
|
||||
# define HPM_CONSOLE_BITS CONFIG_UART0_BITS
|
||||
# define HPM_CONSOLE_PARITY CONFIG_UART0_PARITY
|
||||
# define HPM_CONSOLE_2STOP CONFIG_UART0_2STOP
|
||||
# define HPM_CONSOLE_CLOCKBIT SYSREG_SUBBLK_CLOCK_CR_MMUART0
|
||||
# define HPM_CONSOLE_RESETBIT SYSREG_SOFT_RESET_CR_MMUART0
|
||||
# define HAVE_UART
|
||||
# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
|
||||
# define HPM_CONSOLE_BASE HPM_UART1_BASE
|
||||
# define HPM_CONSOLE_BAUD CONFIG_UART1_BAUD
|
||||
# define HPM_CONSOLE_BITS CONFIG_UART1_BITS
|
||||
# define HPM_CONSOLE_PARITY CONFIG_UART1_PARITY
|
||||
# define HPM_CONSOLE_2STOP CONFIG_UART1_2STOP
|
||||
# define HPM_CONSOLE_CLOCKBIT SYSREG_SUBBLK_CLOCK_CR_MMUART1
|
||||
# define HPM_CONSOLE_RESETBIT SYSREG_SOFT_RESET_CR_MMUART1
|
||||
# define HAVE_UART
|
||||
# elif defined(CONFIG_UART2_SERIAL_CONSOLE)
|
||||
# define HPM_CONSOLE_BASE HPM_UART2_BASE
|
||||
# define HPM_CONSOLE_BAUD CONFIG_UART2_BAUD
|
||||
# define HPM_CONSOLE_BITS CONFIG_UART2_BITS
|
||||
# define HPM_CONSOLE_PARITY CONFIG_UART2_PARITY
|
||||
# define HPM_CONSOLE_2STOP CONFIG_UART2_2STOP
|
||||
# define HPM_CONSOLE_CLOCKBIT SYSREG_SUBBLK_CLOCK_CR_MMUART2
|
||||
# define HPM_CONSOLE_RESETBIT SYSREG_SOFT_RESET_CR_MMUART2
|
||||
# define HAVE_UART
|
||||
# elif defined(CONFIG_UART3_SERIAL_CONSOLE)
|
||||
# define HPM_CONSOLE_BASE HPM_UART3_BASE
|
||||
# define HPM_CONSOLE_BAUD CONFIG_UART3_BAUD
|
||||
# define HPM_CONSOLE_BITS CONFIG_UART3_BITS
|
||||
# define HPM_CONSOLE_PARITY CONFIG_UART3_PARITY
|
||||
# define HPM_CONSOLE_2STOP CONFIG_UART3_2STOP
|
||||
# define HPM_CONSOLE_CLOCKBIT SYSREG_SUBBLK_CLOCK_CR_MMUART3
|
||||
# define HPM_CONSOLE_RESETBIT SYSREG_SOFT_RESET_CR_MMUART3
|
||||
# define HAVE_UART
|
||||
# elif defined(CONFIG_UART4_SERIAL_CONSOLE)
|
||||
# define HPM_CONSOLE_BASE HPM_UART4_BASE
|
||||
# define HPM_CONSOLE_BAUD CONFIG_UART4_BAUD
|
||||
# define HPM_CONSOLE_BITS CONFIG_UART4_BITS
|
||||
# define HPM_CONSOLE_PARITY CONFIG_UART4_PARITY
|
||||
# define HPM_CONSOLE_2STOP CONFIG_UART4_2STOP
|
||||
# define HPM_CONSOLE_CLOCKBIT SYSREG_SUBBLK_CLOCK_CR_MMUART4
|
||||
# define HPM_CONSOLE_RESETBIT SYSREG_SOFT_RESET_CR_MMUART4
|
||||
# define HAVE_UART
|
||||
# elif defined(CONFIG_UART5_SERIAL_CONSOLE)
|
||||
# define HPM_CONSOLE_BASE HPM_UART5_BASE
|
||||
# define HPM_CONSOLE_BAUD CONFIG_UART5_BAUD
|
||||
# define HPM_CONSOLE_BITS CONFIG_UART5_BITS
|
||||
# define HPM_CONSOLE_PARITY CONFIG_UART5_PARITY
|
||||
# define HPM_CONSOLE_2STOP CONFIG_UART5_2STOP
|
||||
# define HPM_CONSOLE_CLOCKBIT SYSREG_SUBBLK_CLOCK_CR_MMUART5
|
||||
# define HPM_CONSOLE_RESETBIT SYSREG_SOFT_RESET_CR_MMUART5
|
||||
# define HAVE_UART
|
||||
# elif defined(CONFIG_UART6_SERIAL_CONSOLE)
|
||||
# define HPM_CONSOLE_BASE HPM_UART6_BASE
|
||||
# define HPM_CONSOLE_BAUD CONFIG_UART6_BAUD
|
||||
# define HPM_CONSOLE_BITS CONFIG_UART6_BITS
|
||||
# define HPM_CONSOLE_PARITY CONFIG_UART6_PARITY
|
||||
# define HPM_CONSOLE_2STOP CONFIG_UART6_2STOP
|
||||
# define HPM_CONSOLE_CLOCKBIT SYSREG_SUBBLK_CLOCK_CR_MMUART6
|
||||
# define HPM_CONSOLE_RESETBIT SYSREG_SOFT_RESET_CR_MMUART6
|
||||
# define HAVE_UART
|
||||
# elif defined(CONFIG_UART7_SERIAL_CONSOLE)
|
||||
# define HPM_CONSOLE_BASE HPM_UART7_BASE
|
||||
# define HPM_CONSOLE_BAUD CONFIG_UART7_BAUD
|
||||
# define HPM_CONSOLE_BITS CONFIG_UART7_BITS
|
||||
# define HPM_CONSOLE_PARITY CONFIG_UART7_PARITY
|
||||
# define HPM_CONSOLE_2STOP CONFIG_UART7_2STOP
|
||||
# define HPM_CONSOLE_CLOCKBIT SYSREG_SUBBLK_CLOCK_CR_MMUART7
|
||||
# define HPM_CONSOLE_RESETBIT SYSREG_SOFT_RESET_CR_MMUART7
|
||||
# define HAVE_UART
|
||||
# elif defined(HAVE_UART)
|
||||
# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
|
||||
# endif
|
||||
#endif /* HAVE_UART_CONSOLE */
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
#if !defined(CONFIG_SUPPRESS_UART_CONFIG)
|
||||
|
||||
/****************************************************************************
|
||||
* Name: config_baud_divisors
|
||||
*
|
||||
* Description:
|
||||
* Configure the UART baudrate divisors.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static bool hpm_uart_calculate_baudrate(uint32_t freq, uint32_t baudrate,
|
||||
uint16_t *div_out, uint8_t *osc_out)
|
||||
{
|
||||
uint16_t div;
|
||||
uint16_t osc;
|
||||
uint16_t delta;
|
||||
float tmp;
|
||||
|
||||
if ((div_out == NULL) || (!freq) || (!baudrate)
|
||||
|| (baudrate < HPM_UART_MINIMUM_BAUDRATE)
|
||||
|| (freq / HPM_UART_BAUDRATE_DIV_MIN < baudrate * HPM_UART_OSC_MIN)
|
||||
|| (freq / HPM_UART_BAUDRATE_DIV_MAX > (baudrate * HPM_UART_OSC_MAX)))
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
tmp = (float) freq / baudrate;
|
||||
for (uint8_t i = 0; i < HPM_UART_OSC_MAX; i += 2)
|
||||
{
|
||||
/* osc range: 0 - 32, even number */
|
||||
|
||||
if (i == 0)
|
||||
{
|
||||
/* osc == 0 in bitfield, oversample rate is 32 */
|
||||
|
||||
osc = HPM_UART_OSC_MAX;
|
||||
}
|
||||
else if (i <= 8)
|
||||
{
|
||||
/* osc <= 8 in bitfield, oversample rate is 8 */
|
||||
|
||||
osc = HPM_UART_OSC_MIN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* osc > 8 && osc < 32 in bitfield, oversample rate is osc */
|
||||
|
||||
osc = i;
|
||||
}
|
||||
|
||||
delta = 0;
|
||||
div = (uint16_t)(tmp / osc);
|
||||
if (div < HPM_UART_BAUDRATE_DIV_MIN)
|
||||
{
|
||||
/* invalid div */
|
||||
|
||||
continue;
|
||||
}
|
||||
|
||||
if (div * osc > tmp)
|
||||
{
|
||||
delta = div * osc - tmp;
|
||||
}
|
||||
else if (div * osc < tmp)
|
||||
{
|
||||
delta = tmp - div * osc;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do Nothing */
|
||||
}
|
||||
|
||||
if (delta && ((delta * 100 / tmp) > HPM_UART_BAUDRATE_TOLERANCE))
|
||||
{
|
||||
continue;
|
||||
}
|
||||
else
|
||||
{
|
||||
*div_out = div;
|
||||
*osc_out = (i <= 8 && i) ? osc : i;
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: riscv_lowputc
|
||||
*
|
||||
* Description:
|
||||
* Output one byte on the serial console
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void riscv_lowputc(char ch)
|
||||
{
|
||||
#if defined HAVE_UART_CONSOLE && defined HAVE_UART
|
||||
|
||||
/* Wait until the TX data register is empty */
|
||||
|
||||
while ((getreg32(HPM_CONSOLE_BASE + HPM_UART_LSR_OFFSET)
|
||||
& UART_LSR_THRE) == 0)
|
||||
;
|
||||
|
||||
/* Then send the character */
|
||||
|
||||
putreg32(ch, HPM_CONSOLE_BASE + HPM_UART_THR_OFFSET);
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: hpm6750_lowsetup
|
||||
*
|
||||
* Description:
|
||||
* This performs basic initialization of the UART used for the serial
|
||||
* console. Its purpose is to get the console output available as soon
|
||||
* as possible.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void hpm_lowsetup(void)
|
||||
{
|
||||
#if defined(HAVE_UART_DEVICE)
|
||||
|
||||
/* Enable and configure the selected console device */
|
||||
|
||||
#if defined(HAVE_UART_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
|
||||
|
||||
#ifdef CONFIG_HPM_UART0
|
||||
hpm_gpio_config(GPIO_UART0_RXD);
|
||||
hpm_gpio_config(GPIO_UART0_TXD);
|
||||
#ifdef CONFIG_UART0_OFLOWCONTROL
|
||||
hpm_gpio_config(GPIO_UART0_CTS);
|
||||
#endif
|
||||
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_UART0_RS485RTSCONTROL)) || \
|
||||
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART0_IFLOWCONTROL)))
|
||||
hpm_config_gpio(GPIO_UART0_RTS);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HPM_UART1
|
||||
hpm_gpio_config(GPIO_UART1_RXD);
|
||||
hpm_gpio_config(GPIO_UART1_TXD)
|
||||
#ifdef CONFIG_UART1_OFLOWCONTROL
|
||||
hpm_gpio_config(GPIO_UART1_CTS);
|
||||
#endif
|
||||
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_UART1_RS485RTSCONTROL)) || \
|
||||
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART1_IFLOWCONTROL)))
|
||||
hpm_config_gpio(GPIO_UART1_RTS);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HPM_UART2
|
||||
hpm_gpio_config(GPIO_UART2_RXD);
|
||||
hpm_gpio_config(GPIO_UART2_TXD)
|
||||
#ifdef CONFIG_UART2_OFLOWCONTROL
|
||||
hpm_gpio_config(GPIO_UART2_CTS);
|
||||
#endif
|
||||
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_UART2_RS485RTSCONTROL)) || \
|
||||
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART2_IFLOWCONTROL)))
|
||||
hpm_config_gpio(GPIO_UART2_RTS);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HPM_UART3
|
||||
hpm_gpio_config(GPIO_UART3_RXD);
|
||||
hpm_gpio_config(GPIO_UART3_TXD)
|
||||
#ifdef CONFIG_UART3_OFLOWCONTROL
|
||||
hpm_gpio_config(GPIO_UART3_CTS);
|
||||
#endif
|
||||
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_UART3_RS485RTSCONTROL)) || \
|
||||
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART3_IFLOWCONTROL)))
|
||||
hpm_config_gpio(GPIO_UART3_RTS);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HPM_UART4
|
||||
hpm_gpio_config(GPIO_UART4_RXD);
|
||||
hpm_gpio_config(GPIO_UART4_TXD)
|
||||
#ifdef CONFIG_UART4_OFLOWCONTROL
|
||||
hpm_gpio_config(GPIO_UART4_CTS);
|
||||
#endif
|
||||
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_UART4_RS485RTSCONTROL)) || \
|
||||
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL)))
|
||||
hpm_config_gpio(GPIO_UART4_RTS);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HPM_UART5
|
||||
hpm_gpio_config(GPIO_UART5_RXD);
|
||||
hpm_gpio_config(GPIO_UART5_TXD)
|
||||
#ifdef CONFIG_UART5_OFLOWCONTROL
|
||||
hpm_gpio_config(GPIO_UART5_CTS);
|
||||
#endif
|
||||
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_UART5_RS485RTSCONTROL)) || \
|
||||
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL)))
|
||||
hpm_config_gpio(GPIO_UART5_RTS);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HPM_UART6
|
||||
hpm_gpio_config(GPIO_UART6_RXD);
|
||||
hpm_gpio_config(GPIO_UART6_TXD)
|
||||
#ifdef CONFIG_UART6_OFLOWCONTROL
|
||||
hpm_gpio_config(GPIO_UART6_CTS);
|
||||
#endif
|
||||
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_UART6_RS485RTSCONTROL)) || \
|
||||
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART6_IFLOWCONTROL)))
|
||||
hpm_config_gpio(GPIO_UART6_RTS);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HPM_UART7
|
||||
hpm_gpio_config(GPIO_UART7_RXD);
|
||||
hpm_gpio_config(GPIO_UART7_TXD)
|
||||
#ifdef CONFIG_UART7_OFLOWCONTROL
|
||||
hpm_gpio_config(GPIO_UART7_CTS);
|
||||
#endif
|
||||
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_UART7_RS485RTSCONTROL)) || \
|
||||
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART7_IFLOWCONTROL)))
|
||||
hpm_config_gpio(GPIO_UART7_RTS);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
hpm_uart_clockconfig();
|
||||
|
||||
#endif /* HAVE_UART_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
|
||||
#endif /* HAVE_UART */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: hpm_uart_configure
|
||||
*
|
||||
* Description:
|
||||
* Configure a UART for non-interrupt driven operation
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef HAVE_UART_DEVICE
|
||||
int hpm_uart_configure(uint32_t base, const struct uart_config_s *config)
|
||||
{
|
||||
uint8_t osc = 0;
|
||||
uint16_t div = 0;
|
||||
uint8_t lcr = 0;
|
||||
|
||||
/* disable all interrupts */
|
||||
|
||||
putreg32(0, base + HPM_UART_IER_OFFSET);
|
||||
|
||||
/* set DLAB to 1 */
|
||||
|
||||
lcr = getreg32(base + HPM_UART_LCR_OFFSET) | UART_LCR_DLAB;
|
||||
while ((getreg32(base + HPM_UART_LCR_OFFSET) & UART_LCR_DLAB)
|
||||
!= UART_LCR_DLAB)
|
||||
{
|
||||
putreg32(lcr, base + HPM_UART_LCR_OFFSET);
|
||||
}
|
||||
|
||||
hpm_uart_calculate_baudrate(24000000, config->baud, &div, &osc);
|
||||
putreg32(osc, base + HPM_UART_OSCR_OFFSET);
|
||||
putreg32(div & 0xff, base + HPM_UART_DLL_OFFSET);
|
||||
putreg32(div >> 8, base + HPM_UART_DLM_OFFSET);
|
||||
|
||||
/* DLAB bit needs to be cleared once baudrate is configured */
|
||||
|
||||
while ((getreg32(base + HPM_UART_LCR_OFFSET) & UART_LCR_DLAB)
|
||||
== UART_LCR_DLAB)
|
||||
{
|
||||
lcr &= ~UART_LCR_DLAB;
|
||||
putreg32(lcr, base + HPM_UART_LCR_OFFSET);
|
||||
}
|
||||
|
||||
lcr = 0;
|
||||
switch (config->bits)
|
||||
{
|
||||
case 5:
|
||||
lcr |= UART_LCR_WLS_5BITS;
|
||||
break;
|
||||
|
||||
case 6:
|
||||
lcr |= UART_LCR_WLS_6BITS;
|
||||
break;
|
||||
|
||||
case 7:
|
||||
lcr |= UART_LCR_WLS_7BITS;
|
||||
break;
|
||||
|
||||
case 8:
|
||||
default:
|
||||
lcr |= UART_LCR_WLS_8BITS;
|
||||
break;
|
||||
}
|
||||
|
||||
if (config->stopbits2)
|
||||
{
|
||||
lcr |= UART_LCR_STB;
|
||||
}
|
||||
|
||||
if (config->parity == 1)
|
||||
{
|
||||
lcr |= UART_LCR_PEN;
|
||||
}
|
||||
else if (config->parity == 2)
|
||||
{
|
||||
lcr |= (UART_LCR_PEN | UART_LCR_EPS);
|
||||
}
|
||||
|
||||
putreg32(lcr, base + HPM_UART_LCR_OFFSET);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
#if defined (HAVE_UART_DEVICE)
|
||||
void hpm_lowputc(int ch)
|
||||
{
|
||||
#ifdef HAVE_UART_CONSOLE
|
||||
while ((getreg32(HPM_CONSOLE_BASE + HPM_UART_LSR_OFFSET) &
|
||||
UART_LSR_THRE) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
if (ch == '\n')
|
||||
{
|
||||
putreg32((uint32_t)'\r', HPM_CONSOLE_BASE + HPM_UART_THR_OFFSET);
|
||||
while ((getreg32(HPM_CONSOLE_BASE + HPM_UART_LSR_OFFSET) &
|
||||
UART_LSR_THRE) == 0)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
putreg32((uint32_t)ch, HPM_CONSOLE_BASE + HPM_UART_THR_OFFSET);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
#endif /* HAVE_UART_DEVICE */
|
||||
84
arch/risc-v/src/hpm6000/hpm_lowputc.h
Normal file
84
arch/risc-v/src/hpm6000/hpm_lowputc.h
Normal file
@ -0,0 +1,84 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hpm_lowputc.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HPM_LOWPUTC_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HPM_LOWPUTC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#ifdef HAVE_UART_DEVICE
|
||||
/* This structure describes the configuration of an UART */
|
||||
|
||||
struct uart_config_s
|
||||
{
|
||||
uint32_t baud; /* Configured baud */
|
||||
uint8_t parity; /* 0=none, 1=odd, 2=even */
|
||||
uint8_t bits; /* Number of bits (5-9) */
|
||||
bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
|
||||
bool userts; /* True: Assert RTS when there are data to be sent */
|
||||
bool invrts; /* True: Invert sense of RTS pin (true=active high) */
|
||||
bool usects; /* True: Condition transmission on CTS asserted */
|
||||
bool users485; /* True: Assert RTS while transmission progresses */
|
||||
};
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: hpm_lowsetup
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN void hpm_lowsetup(void);
|
||||
|
||||
#ifdef HAVE_UART_DEVICE
|
||||
int hpm_uart_configure(uint32_t base, const struct uart_config_s *config);
|
||||
#endif
|
||||
|
||||
#ifdef HAVE_UART_DEVICE
|
||||
void hpm_lowputc(int ch);
|
||||
#else
|
||||
# define hpm_lowputc(ch)
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_LOWPUTC_H */
|
||||
50
arch/risc-v/src/hpm6000/hpm_memorymap.h
Normal file
50
arch/risc-v/src/hpm6000/hpm_memorymap.h
Normal file
@ -0,0 +1,50 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hpm_memorymap.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HPM_MEMORYMAP_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HPM_MEMORYMAP_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "riscv_common_memorymap.h"
|
||||
#include "hardware/hpm_memorymap.h"
|
||||
#include "hardware/hpm_uart.h"
|
||||
#include "hardware/hpm_mchtmr.h"
|
||||
#include "hardware/hpm_ioc.h"
|
||||
#include "hardware/hpm_plic.h"
|
||||
#include "hardware/hpm_sysctl.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Idle thread stack starts from _ebss */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define HPM_IDLESTACK_BASE (uintptr_t)_ebss
|
||||
#else
|
||||
#define HPM_IDLESTACK_BASE _ebss
|
||||
#endif
|
||||
|
||||
#define HPM_IDLESTACK_TOP (HPM_IDLESTACK_BASE + CONFIG_IDLETHREAD_STACKSIZE)
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_MEMORYMAP_H */
|
||||
82
arch/risc-v/src/hpm6000/hpm_pmic_iomux.h
Normal file
82
arch/risc-v/src/hpm6000/hpm_pmic_iomux.h
Normal file
@ -0,0 +1,82 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hpm_pmic_iomux.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HPM_PMIC_IOMUX_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HPM_PMIC_IOMUX_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "hardware/hpm_ioc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* IOC_PY00_FUNC_CTL function mux definitions */
|
||||
#define IOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PY00_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PY00_FUNC_CTL_SOC_PY_00 IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
|
||||
/* IOC_PY01_FUNC_CTL function mux definitions */
|
||||
#define IOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PY01_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PY01_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PY01_FUNC_CTL_SOC_PY_01 IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
|
||||
/* IOC_PY02_FUNC_CTL function mux definitions */
|
||||
#define IOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PY02_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PY02_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PY02_FUNC_CTL_SOC_PY_02 IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
|
||||
/* IOC_PY03_FUNC_CTL function mux definitions */
|
||||
#define IOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PY03_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PY03_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PY03_FUNC_CTL_SOC_PY_03 IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
|
||||
/* IOC_PY04_FUNC_CTL function mux definitions */
|
||||
#define IOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PY04_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PY04_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PY04_FUNC_CTL_SOC_PY_04 IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
|
||||
/* IOC_PY05_FUNC_CTL function mux definitions */
|
||||
#define IOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PY05_FUNC_CTL_PWDG_RST IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PY05_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PY05_FUNC_CTL_SOC_PY_05 IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
|
||||
/* IOC_PY06_FUNC_CTL function mux definitions */
|
||||
#define IOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PY06_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PY06_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PY06_FUNC_CTL_SOC_PY_06 IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
|
||||
/* IOC_PY07_FUNC_CTL function mux definitions */
|
||||
#define IOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_ALT_SELECT(0)
|
||||
#define IOC_PY07_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_ALT_SELECT(1)
|
||||
#define IOC_PY07_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_ALT_SELECT(2)
|
||||
#define IOC_PY07_FUNC_CTL_SOC_PY_07 IOC_PAD_FUNC_ALT_SELECT(3)
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_PMIC_IOMUX_H */
|
||||
1345
arch/risc-v/src/hpm6000/hpm_serial.c
Normal file
1345
arch/risc-v/src/hpm6000/hpm_serial.c
Normal file
File diff suppressed because it is too large
Load Diff
49
arch/risc-v/src/hpm6000/hpm_serial.h
Normal file
49
arch/risc-v/src/hpm6000/hpm_serial.h
Normal file
@ -0,0 +1,49 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hpm_serial.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_HPM6000_HPM_SERIAL_H
|
||||
#define __ARCH_RISCV_SRC_HPM6000_HPM_SERIAL_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_SERIAL_H */
|
||||
115
arch/risc-v/src/hpm6000/hpm_start.c
Normal file
115
arch/risc-v/src/hpm6000/hpm_start.c
Normal file
@ -0,0 +1,115 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hpm_start.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <nuttx/init.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hpm.h"
|
||||
#include "hpm_clockconfig.h"
|
||||
#include "hpm_lowputc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
|
||||
* linker script. _ebss lies at the end of the BSS region. The idle task
|
||||
* stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
|
||||
* The IDLE thread is the thread that the system boots on and, eventually,
|
||||
* becomes the IDLE, do nothing task that runs only when there is nothing
|
||||
* else to run. The heap continues from there until the end of memory.
|
||||
* g_idle_topstack is a read-only variable the provides this computed
|
||||
* address.
|
||||
*/
|
||||
|
||||
uintptr_t g_idle_topstack = HPM_IDLESTACK_TOP;
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: __hpm6750_start
|
||||
****************************************************************************/
|
||||
|
||||
void __hpm_start(void)
|
||||
{
|
||||
const uint32_t *src;
|
||||
uint32_t *dest;
|
||||
|
||||
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
|
||||
* certain that there are no issues with the state of global variables.
|
||||
*/
|
||||
|
||||
for (dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; )
|
||||
{
|
||||
*dest++ = 0;
|
||||
}
|
||||
|
||||
/* Move the initialized data section from his temporary holding spot in
|
||||
* FLASH into the correct place in SRAM. The correct place in SRAM is
|
||||
* give by _sdata and _edata. The temporary location is in FLASH at the
|
||||
* end of all of the other read-only data (.text, .rodata) at _eronly.
|
||||
*/
|
||||
|
||||
for (src = (const uint32_t *)_eronly,
|
||||
dest = (uint32_t *)_sdata; dest < (uint32_t *)_edata;
|
||||
)
|
||||
{
|
||||
*dest++ = *src++;
|
||||
}
|
||||
|
||||
/* Setup PLL */
|
||||
|
||||
hpm_clockconfig();
|
||||
|
||||
/* Configure the UART so we can get debug output */
|
||||
|
||||
hpm_lowsetup();
|
||||
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
riscv_earlyserialinit();
|
||||
#endif
|
||||
|
||||
/* Do board initialization */
|
||||
|
||||
hpm6360_boardinitialize();
|
||||
|
||||
/* Call nx_start() */
|
||||
|
||||
nx_start();
|
||||
|
||||
/* Shouldn't get here */
|
||||
|
||||
for (; ; );
|
||||
}
|
||||
70
arch/risc-v/src/hpm6000/hpm_timerisr.c
Normal file
70
arch/risc-v/src/hpm6000/hpm_timerisr.c
Normal file
@ -0,0 +1,70 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/hpm6000/hpm_timerisr.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <assert.h>
|
||||
#include <stdint.h>
|
||||
#include <time.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/clock.h>
|
||||
#include <nuttx/spinlock.h>
|
||||
#include <nuttx/timers/arch_alarm.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "riscv_internal.h"
|
||||
#include "riscv_mtimer.h"
|
||||
#include "chip.h"
|
||||
#include "hpm.h"
|
||||
#include "hpm_clockconfig.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_timer_initialize
|
||||
*
|
||||
* Description:
|
||||
* This function is called during start-up to initialize
|
||||
* the timer interrupt.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_timer_initialize(void)
|
||||
{
|
||||
struct oneshot_lowerhalf_s *lower = riscv_mtimer_initialize(
|
||||
HPM_MCHTMR_MTIME, HPM_MCHTMR_MTIMECMP,
|
||||
RISCV_IRQ_MTIMER, hpm_get_osc_freq());
|
||||
|
||||
DEBUGASSERT(lower);
|
||||
|
||||
up_alarm_set_lowerhalf(lower);
|
||||
}
|
||||
@ -2976,6 +2976,14 @@ config ARCH_BOARD_S698PM_DKIT
|
||||
---help---
|
||||
none
|
||||
|
||||
config ARCH_BOARD_HPM6360EVK
|
||||
bool "Hpmicro hpm6360evk"
|
||||
depends on ARCH_CHIP_HPM6360IPA
|
||||
select ARCH_HAVE_LEDS
|
||||
---help---
|
||||
This is the board configuration for the port of NuttX to the Hpmicro hpm6750evk2
|
||||
board. This board features the RISC-V hpm6340.
|
||||
|
||||
config ARCH_BOARD_HPM6750EVK2
|
||||
bool "Hpmicro hpm6750evk2"
|
||||
depends on ARCH_CHIP_HPM6750
|
||||
@ -3379,6 +3387,7 @@ config ARCH_BOARD
|
||||
default "xx3803" if ARCH_BOARD_XX3803
|
||||
default "xx3823" if ARCH_BOARD_XX3823
|
||||
default "s698pm-dkit" if ARCH_BOARD_S698PM_DKIT
|
||||
default "hpm6360evk" if ARCH_BOARD_HPM6360EVK
|
||||
default "hpm6750evk2" if ARCH_BOARD_HPM6750EVK2
|
||||
default "at32f437-mini" if ARCH_BOARD_AT32F437_MINI
|
||||
|
||||
@ -4325,6 +4334,9 @@ endif
|
||||
if ARCH_BOARD_TLSR8278ADK80D
|
||||
source "boards/arm/tlsr82/tlsr8278adk80d/Kconfig"
|
||||
endif
|
||||
if ARCH_BOARD_HPM6360EVK
|
||||
source "boards/risc-v/hpm6000/hpm6360evk/Kconfig"
|
||||
endif
|
||||
if ARCH_BOARD_HPM6750EVK2
|
||||
source "boards/risc-v/hpm6750/hpm6750evk2/Kconfig"
|
||||
endif
|
||||
|
||||
21
boards/risc-v/hpm6000/hpm6360evk/CMakeLists.txt
Normal file
21
boards/risc-v/hpm6000/hpm6360evk/CMakeLists.txt
Normal file
@ -0,0 +1,21 @@
|
||||
# ##############################################################################
|
||||
# boards/risc-v/hpm6000/hpm6360evk/CMakeLists.txt
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
|
||||
# license agreements. See the NOTICE file distributed with this work for
|
||||
# additional information regarding copyright ownership. The ASF licenses this
|
||||
# file to you under the Apache License, Version 2.0 (the "License"); you may not
|
||||
# use this file except in compliance with the License. You may obtain a copy of
|
||||
# the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations under
|
||||
# the License.
|
||||
#
|
||||
# ##############################################################################
|
||||
|
||||
add_subdirectory(src)
|
||||
8
boards/risc-v/hpm6000/hpm6360evk/Kconfig
Normal file
8
boards/risc-v/hpm6000/hpm6360evk/Kconfig
Normal file
@ -0,0 +1,8 @@
|
||||
#
|
||||
# For a description of the syntax of this configuration file,
|
||||
# see misc/tools/kconfig-language.txt.
|
||||
#
|
||||
|
||||
if ARCH_BOARD_HPM6360EVK
|
||||
|
||||
endif
|
||||
42
boards/risc-v/hpm6000/hpm6360evk/README.txt
Normal file
42
boards/risc-v/hpm6000/hpm6360evk/README.txt
Normal file
@ -0,0 +1,42 @@
|
||||
1. Download and install toolchain
|
||||
|
||||
$ curl https://github.com/hpmicro/riscv-gnu-toolchain/releases/tag/2022.05.15
|
||||
|
||||
2. Download and install openocd
|
||||
|
||||
Download hpmicro sdk_env, openocd in the path: sdk_env/tools/openocd
|
||||
|
||||
3. Configure and build NuttX
|
||||
|
||||
$ mkdir ./nuttxspace
|
||||
$ cd ./nuttxspace
|
||||
$ git clone https://github.com/apache/nuttx.git nuttx
|
||||
$ git clone https://github.com/apache/nuttx-apps.git apps
|
||||
$ cd nuttx
|
||||
$ make distclean
|
||||
$ ./tools/configure.sh hpm6750evk2:nsh
|
||||
$ make menuconfig
|
||||
$ make V=1
|
||||
|
||||
Note: make menuconfig to config toolchain
|
||||
==================
|
||||
To switch GNU riscv64 toolchain to GNU riscv32 toolchain, the following option must be selected:
|
||||
|
||||
System Type --->
|
||||
Toolchain Selection --->
|
||||
[ ] Generic GNU RV64 toolchain
|
||||
[x] Generic GNU RV32 toolchain
|
||||
|
||||
Make sure HPMicro GNU riscv32 toolchain have been installed and be found in PATH.
|
||||
|
||||
4. Debug the nuttx with openocd and run
|
||||
|
||||
$ picocom -b 115200 /dev/ttyACM0
|
||||
|
||||
When using fireDAP, command as follows. Those cfg files in the path: sdk_env/hpm_sdk/boards/openocd.
|
||||
$ openocd -f probes/cmsis_dap.cfg -f soc/hpm6750-single-core.cfg -f boards/hpm6750evk2.cfg
|
||||
|
||||
$ riscv32-unknown-elf-gdb ./nuttx
|
||||
(gdb) target extended-remote [ip_addr]:3333
|
||||
(gdb) load
|
||||
(gdb) c
|
||||
81
boards/risc-v/hpm6000/hpm6360evk/configs/nsh/defconfig
Normal file
81
boards/risc-v/hpm6000/hpm6360evk/configs/nsh/defconfig
Normal file
@ -0,0 +1,81 @@
|
||||
#
|
||||
# This file is autogenerated: PLEASE DO NOT EDIT IT.
|
||||
#
|
||||
# You can use "make menuconfig" to make any modifications to the installed .config file.
|
||||
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
|
||||
# modifications.
|
||||
#
|
||||
# CONFIG_DISABLE_ENVIRON is not set
|
||||
# CONFIG_DISABLE_PTHREAD is not set
|
||||
# CONFIG_FS_PROCFS_EXCLUDE_BLOCKS is not set
|
||||
# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set
|
||||
# CONFIG_FS_PROCFS_EXCLUDE_MEMDUMP is not set
|
||||
# CONFIG_FS_PROCFS_EXCLUDE_MEMINFO is not set
|
||||
# CONFIG_FS_PROCFS_EXCLUDE_MOUNT is not set
|
||||
# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set
|
||||
# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set
|
||||
# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set
|
||||
# CONFIG_FS_PROCFS_EXCLUDE_USAGE is not set
|
||||
# CONFIG_FS_PROCFS_EXCLUDE_VERSION is not set
|
||||
# CONFIG_NSH_DISABLEBG is not set
|
||||
# CONFIG_NSH_DISABLE_CAT is not set
|
||||
# CONFIG_NSH_DISABLE_CD is not set
|
||||
# CONFIG_NSH_DISABLE_ECHO is not set
|
||||
# CONFIG_NSH_DISABLE_ENV is not set
|
||||
# CONFIG_NSH_DISABLE_EXEC is not set
|
||||
# CONFIG_NSH_DISABLE_FREE is not set
|
||||
# CONFIG_NSH_DISABLE_HELP is not set
|
||||
# CONFIG_NSH_DISABLE_KILL is not set
|
||||
# CONFIG_NSH_DISABLE_LOSMART is not set
|
||||
# CONFIG_NSH_DISABLE_LS is not set
|
||||
# CONFIG_NSH_DISABLE_MOUNT is not set
|
||||
# CONFIG_NSH_DISABLE_PRINTF is not set
|
||||
# CONFIG_NSH_DISABLE_PS is not set
|
||||
# CONFIG_NSH_DISABLE_PWD is not set
|
||||
# CONFIG_NSH_DISABLE_SLEEP is not set
|
||||
# CONFIG_NSH_DISABLE_UNAME is not set
|
||||
# CONFIG_NSH_DISABLE_USLEEP is not set
|
||||
# CONFIG_STANDARD_SERIAL is not set
|
||||
CONFIG_ARCH="risc-v"
|
||||
CONFIG_ARCH_BOARD="hpm6360evk"
|
||||
CONFIG_ARCH_BOARD_HPM6360EVK=y
|
||||
CONFIG_ARCH_CHIP="hpm6000"
|
||||
CONFIG_ARCH_CHIP_HPM6000=y
|
||||
CONFIG_ARCH_CHIP_HPM6360IPA=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=8192
|
||||
CONFIG_ARCH_RISCV=y
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=10000
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_DEBUG_FEATURES=y
|
||||
CONFIG_DEBUG_SYMBOLS=y
|
||||
CONFIG_DEFAULT_SMALL=y
|
||||
CONFIG_EXAMPLES_HELLO=y
|
||||
CONFIG_FS_BINFS=y
|
||||
CONFIG_FS_PROCFS=y
|
||||
CONFIG_HPM_UART0=y
|
||||
CONFIG_IDLETHREAD_STACKSIZE=8192
|
||||
CONFIG_INIT_ENTRYPOINT="nsh_main"
|
||||
CONFIG_INIT_STACKSIZE=8192
|
||||
CONFIG_INTELHEX_BINARY=y
|
||||
CONFIG_LIBC_ENVPATH=y
|
||||
CONFIG_LIBC_PERROR_STDOUT=y
|
||||
CONFIG_LIBC_STRERROR=y
|
||||
CONFIG_NSH_ARCHINIT=y
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
CONFIG_NSH_FILEIOSIZE=64
|
||||
CONFIG_NSH_STRERROR=y
|
||||
CONFIG_RAM_SIZE=262144
|
||||
CONFIG_RAM_START=0x00080000
|
||||
CONFIG_RISCV_TOOLCHAIN_GNU_RV32=y
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_SCHED_HPWORK=y
|
||||
CONFIG_SCHED_LPWORK=y
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
CONFIG_SERIAL_TERMIOS=y
|
||||
CONFIG_START_DAY=7
|
||||
CONFIG_START_MONTH=2
|
||||
CONFIG_START_YEAR=2023
|
||||
CONFIG_SYSTEM_NSH=y
|
||||
CONFIG_UART0_SERIAL_CONSOLE=y
|
||||
CONFIG_WQUEUE_NOTIFIER=y
|
||||
135
boards/risc-v/hpm6000/hpm6360evk/include/board.h
Normal file
135
boards/risc-v/hpm6000/hpm6360evk/include/board.h
Normal file
@ -0,0 +1,135 @@
|
||||
/****************************************************************************
|
||||
* boards/risc-v/hpm6000/hpm6360evk/include/board.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __BOARDS_RISCV_HPM6000_HPM6360EVK_INCLUDE_BOARD_H
|
||||
#define __BOARDS_RISCV_HPM6000_HPM6360EVK_INCLUDE_BOARD_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* LED definitions **********************************************************/
|
||||
|
||||
/* There are four LED status indicators located on the EVK Board.
|
||||
* The functions of these LEDs include:
|
||||
*
|
||||
* - Main Power Supply(D3)
|
||||
* Green: DC 5V main supply is normal.
|
||||
* Red: J2 input voltage is over 5.6V.
|
||||
* Off: The board is not powered.
|
||||
* - Reset RED LED(D15)
|
||||
* - OpenSDA LED(D16)
|
||||
* - USER LED(D18)
|
||||
*
|
||||
* Only a single LED, D18, is under software control.
|
||||
*/
|
||||
|
||||
/* LED index values for use with board_userled() */
|
||||
|
||||
#define BOARD_USERLED 0
|
||||
#define BOARD_NLEDS 1
|
||||
|
||||
/* LED bits for use with board_userled_all() */
|
||||
|
||||
#define BOARD_USERLED_BIT (1 << BOARD_USERLED)
|
||||
|
||||
/* This LED is not used by the board port unless CONFIG_ARCH_LEDS is
|
||||
* defined. In that case, the usage by the board port is defined in
|
||||
* include/board.h and src/imxrt_autoleds.c. The LED is used to encode
|
||||
* OS-related events as follows:
|
||||
*
|
||||
* -------------------- ----------------------------- ------
|
||||
* SYMBOL Meaning LED
|
||||
* -------------------- ----------------------------- ------
|
||||
*/
|
||||
|
||||
#define LED_STARTED 0 /* NuttX has been started OFF */
|
||||
#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */
|
||||
#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */
|
||||
#define LED_STACKCREATED 1 /* Idle stack created ON */
|
||||
#define LED_INIRQ 2 /* In an interrupt N/C */
|
||||
#define LED_SIGNAL 2 /* In a signal handler N/C */
|
||||
#define LED_ASSERTION 2 /* An assertion failed N/C */
|
||||
#define LED_PANIC 3 /* The system has crashed FLASH */
|
||||
#undef LED_IDLE /* Not used */
|
||||
|
||||
/* Thus if the LED is statically on, NuttX has successfully booted and is,
|
||||
* apparently, running normally. If the LED is flashing at approximately
|
||||
* 2Hz, then a fatal error has been detected and the system has halted.
|
||||
*/
|
||||
|
||||
/* Button definitions *******************************************************/
|
||||
|
||||
/* The IMXRT board has one external user button
|
||||
*
|
||||
* 1. SW8 (IRQ88) GPIO5-00
|
||||
*/
|
||||
|
||||
#define BUTTON_SW8 0
|
||||
#define NUM_BUTTONS 3
|
||||
|
||||
#define BUTTON_SW8_BIT (1 << BUTTON_SW8)
|
||||
|
||||
/* UARTs */
|
||||
|
||||
#define GPIO_UART0_RXD (GPIO_UART0_RXD4 | IOC_PAD_UART_DEFAULT)
|
||||
#define GPIO_UART0_TXD (GPIO_UART0_TXD4 | IOC_PAD_UART_DEFAULT)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: hpm6340_boardinitialize
|
||||
****************************************************************************/
|
||||
|
||||
void hpm6360_boardinitialize(void);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __BOARDS_RISCV_HPM6000_HPM6360EVK_INCLUDE_BOARD_H */
|
||||
34
boards/risc-v/hpm6000/hpm6360evk/scripts/Make.defs
Normal file
34
boards/risc-v/hpm6000/hpm6360evk/scripts/Make.defs
Normal file
@ -0,0 +1,34 @@
|
||||
############################################################################
|
||||
# boards/risc-v/hpm6750/hpm6750evk2/scripts/Make.defs
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
# contributor license agreements. See the NOTICE file distributed with
|
||||
# this work for additional information regarding copyright ownership. The
|
||||
# ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
# "License"); you may not use this file except in compliance with the
|
||||
# License. You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations
|
||||
# under the License.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
include $(TOPDIR)/.config
|
||||
include $(TOPDIR)/tools/Config.mk
|
||||
include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs
|
||||
|
||||
LDSCRIPT = ld.script
|
||||
|
||||
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
|
||||
|
||||
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
|
||||
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
|
||||
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
|
||||
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
|
||||
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
|
||||
AFLAGS += $(CFLAGS) -D__ASSEMBLY__
|
||||
108
boards/risc-v/hpm6000/hpm6360evk/scripts/flash.script
Normal file
108
boards/risc-v/hpm6000/hpm6360evk/scripts/flash.script
Normal file
@ -0,0 +1,108 @@
|
||||
/****************************************************************************
|
||||
* boards/risc-v/hpm6000/hpm6360evk/scripts/ld.script
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rx) : ORIGIN = 0x80000000, LENGTH = 16M
|
||||
ilm (rx) : ORIGIN = 0x00000000, LENGTH = 128K
|
||||
dlm (rwx) : ORIGIN = 0x00080000, LENGTH = 128K
|
||||
axi_sram (wx) : ORIGIN = 0x01080000, LENGTH = 256K
|
||||
axi_sram_noncacheable (wx) : ORIGIN = 0x010C0000, LENGTH = 256K
|
||||
ahb_sram (w) : ORIGIN = 0xF0300000, LENGTH = 32k
|
||||
}
|
||||
|
||||
OUTPUT_ARCH("riscv")
|
||||
|
||||
EXTERN(_vectors)
|
||||
SECTIONS
|
||||
{
|
||||
.nor_cfg_option 0x80000400: {
|
||||
KEEP(*(.nor_cfg_option))
|
||||
} > flash
|
||||
|
||||
.boot_header 0x80001000 : {
|
||||
__boot_header_start__ = .;
|
||||
KEEP(*(.boot_header))
|
||||
KEEP(*(.fw_info_table))
|
||||
KEEP(*(.dc_info))
|
||||
__boot_header_end__ = .;
|
||||
} > flash
|
||||
|
||||
.text 0x80003000 : {
|
||||
_stext = ABSOLUTE(.);
|
||||
*(.vectors)
|
||||
*(.text .text.*)
|
||||
*(.fixup)
|
||||
*(.gnu.warning)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.got)
|
||||
*(.gcc_except_table)
|
||||
*(.gnu.linkonce.r.*)
|
||||
_etext = ABSOLUTE(.);
|
||||
} > flash
|
||||
|
||||
.init_section : ALIGN(4) {
|
||||
_sinit = ABSOLUTE(.);
|
||||
KEEP(*(.init_array .init_array.*))
|
||||
_einit = ABSOLUTE(.);
|
||||
} > flash
|
||||
|
||||
_eronly = ABSOLUTE(.);
|
||||
|
||||
.data : ALIGN(4) {
|
||||
_sdata = ABSOLUTE(.);
|
||||
*(.data .data.*)
|
||||
*(.sdata .sdata.* .sdata2.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
CONSTRUCTORS
|
||||
. = ALIGN(4);
|
||||
_edata = ABSOLUTE(.);
|
||||
} > dlm AT > flash
|
||||
|
||||
.bss : ALIGN(4) {
|
||||
_sbss = ABSOLUTE(.);
|
||||
*(.bss .bss.*)
|
||||
*(.sbss .sbss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(32);
|
||||
_ebss = ABSOLUTE(.);
|
||||
} > dlm
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
}
|
||||
95
boards/risc-v/hpm6000/hpm6360evk/scripts/ld.script
Normal file
95
boards/risc-v/hpm6000/hpm6360evk/scripts/ld.script
Normal file
@ -0,0 +1,95 @@
|
||||
/****************************************************************************
|
||||
* boards/risc-v/hpm6750/hpm6750evk2/scripts/ld.script
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ilm (rx) : ORIGIN = 0x00000000, LENGTH = 128K
|
||||
dlm (rwx) : ORIGIN = 0x00080000, LENGTH = 128K
|
||||
axi_sram (wx) : ORIGIN = 0x01080000, LENGTH = 256K
|
||||
axi_sram_noncacheable (wx) : ORIGIN = 0x010C0000, LENGTH = 256K
|
||||
ahb_sram (w) : ORIGIN = 0xF0300000, LENGTH = 32k
|
||||
}
|
||||
|
||||
OUTPUT_ARCH("riscv")
|
||||
|
||||
EXTERN(_vectors)
|
||||
SECTIONS
|
||||
{
|
||||
.text : {
|
||||
_stext = ABSOLUTE(.);
|
||||
*(.vectors)
|
||||
*(.text .text.*)
|
||||
*(.fixup)
|
||||
*(.gnu.warning)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.got)
|
||||
*(.gcc_except_table)
|
||||
*(.gnu.linkonce.r.*)
|
||||
_etext = ABSOLUTE(.);
|
||||
} > ilm
|
||||
|
||||
.init_section : ALIGN(4) {
|
||||
_sinit = ABSOLUTE(.);
|
||||
KEEP(*(.init_array .init_array.*))
|
||||
_einit = ABSOLUTE(.);
|
||||
} > ilm
|
||||
|
||||
_eronly = ABSOLUTE(.);
|
||||
|
||||
.data : ALIGN(4) {
|
||||
_sdata = ABSOLUTE(.);
|
||||
*(.data .data.*)
|
||||
*(.sdata .sdata.* .sdata2.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
CONSTRUCTORS
|
||||
. = ALIGN(4);
|
||||
_edata = ABSOLUTE(.);
|
||||
} > dlm AT > ilm
|
||||
|
||||
.bss : ALIGN(4) {
|
||||
_sbss = ABSOLUTE(.);
|
||||
*(.bss .bss.*)
|
||||
*(.sbss .sbss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(32);
|
||||
_ebss = ABSOLUTE(.);
|
||||
} > dlm
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
}
|
||||
37
boards/risc-v/hpm6000/hpm6360evk/src/CMakeLists.txt
Normal file
37
boards/risc-v/hpm6000/hpm6360evk/src/CMakeLists.txt
Normal file
@ -0,0 +1,37 @@
|
||||
# ##############################################################################
|
||||
# boards/risc-v/hpm6000/hpm6360evk/src/CMakeLists.txt
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
|
||||
# license agreements. See the NOTICE file distributed with this work for
|
||||
# additional information regarding copyright ownership. The ASF licenses this
|
||||
# file to you under the Apache License, Version 2.0 (the "License"); you may not
|
||||
# use this file except in compliance with the License. You may obtain a copy of
|
||||
# the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations under
|
||||
# the License.
|
||||
#
|
||||
# ##############################################################################
|
||||
|
||||
set(SRCS hpm6360_bringup.c hpm6360_boot.c hpm6360_appinit.c)
|
||||
|
||||
if(CONFIG_BOARDCTL)
|
||||
if(EXISTS hpm6360_appinit.c)
|
||||
list(APPEND SRCS hpm6360_appinit.c)
|
||||
endif()
|
||||
endif()
|
||||
|
||||
if(CONFIG_ARCH_LEDS)
|
||||
list(APPEND SRCS hpm6360_autoleds.c)
|
||||
endif()
|
||||
|
||||
target_sources(board PRIVATE ${SRCS})
|
||||
|
||||
set(LDFILE ld.script)
|
||||
|
||||
set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/${LDFILE}")
|
||||
33
boards/risc-v/hpm6000/hpm6360evk/src/Makefile
Normal file
33
boards/risc-v/hpm6000/hpm6360evk/src/Makefile
Normal file
@ -0,0 +1,33 @@
|
||||
############################################################################
|
||||
# boards/risc-v/hpm6750/hpm6750evk2/src/Makefile
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
# contributor license agreements. See the NOTICE file distributed with
|
||||
# this work for additional information regarding copyright ownership. The
|
||||
# ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
# "License"); you may not use this file except in compliance with the
|
||||
# License. You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations
|
||||
# under the License.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
include $(TOPDIR)/Make.defs
|
||||
|
||||
CSRCS = hpm6360_bringup.c hpm6360_boot.c
|
||||
|
||||
ifeq ($(CONFIG_BOARDCTL),y)
|
||||
CSRCS += hpm6360_appinit.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_LEDS),y)
|
||||
CSRCS += hpm6360_autoleds.c
|
||||
endif
|
||||
|
||||
include $(TOPDIR)/boards/Board.mk
|
||||
74
boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_appinit.c
Normal file
74
boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_appinit.c
Normal file
@ -0,0 +1,74 @@
|
||||
/****************************************************************************
|
||||
* boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_appinit.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdio.h>
|
||||
#include <syslog.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
|
||||
#include "hpm6360evk.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_app_initialize
|
||||
*
|
||||
* Description:
|
||||
* Perform architecture specific initialization
|
||||
*
|
||||
* Input Parameters:
|
||||
* arg - The boardctl() argument is passed to the board_app_initialize()
|
||||
* implementation without modification. The argument has no
|
||||
* meaning to NuttX; the meaning of the argument is a contract
|
||||
* between the board-specific initialization logic and the
|
||||
* matching application logic. The value could be such things as a
|
||||
* mode enumeration value, a set of DIP switch switch settings, a
|
||||
* pointer to configuration data read from a file or serial FLASH,
|
||||
* or whatever you would like to do with it. Every implementation
|
||||
* should accept zero/NULL as a default configuration.
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success; a negated errno value is returned on
|
||||
* any failure to indicate the nature of the failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int board_app_initialize(uintptr_t arg)
|
||||
{
|
||||
#ifdef CONFIG_BOARD_LATE_INITIALIZE
|
||||
/* Board initialization already performed by board_late_initialize() */
|
||||
|
||||
return OK;
|
||||
#else
|
||||
/* Perform board-specific initialization */
|
||||
|
||||
return hpm6360_bringup();
|
||||
#endif
|
||||
}
|
||||
165
boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_autoleds.c
Normal file
165
boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_autoleds.c
Normal file
@ -0,0 +1,165 @@
|
||||
/****************************************************************************
|
||||
* boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_autoleds.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* There are four LED status indicators located on the EVK Board. The
|
||||
* functions of these LEDs include:
|
||||
*
|
||||
* - Main Power Supply(D3)
|
||||
* Green: DC 5V main supply is normal.
|
||||
* Red: J2 input voltage is over 5.6V.
|
||||
* Off: The board is not powered.
|
||||
* - Reset RED LED(D21)
|
||||
* - OpenSDA LED(D20)
|
||||
* - USER LED(D18)
|
||||
*
|
||||
* Only a single LED, D18, is under software control.
|
||||
*
|
||||
* This LED is not used by the board port unless CONFIG_ARCH_LEDS is
|
||||
* defined. In that case, the usage by the board port is defined in
|
||||
* include/board.h and src/imxrt_autoleds.c. The LED is used to encode
|
||||
* OS-related events as follows:
|
||||
*
|
||||
* -------------------- ----------------------- ------
|
||||
* SYMBOL Meaning LED
|
||||
* -------------------- ----------------------- ------
|
||||
*
|
||||
* LED_STARTED 0 NuttX has been started OFF
|
||||
* LED_HEAPALLOCATE 0 Heap has been allocated OFF
|
||||
* LED_IRQSENABLED 0 Interrupts enabled OFF
|
||||
* LED_STACKCREATED 1 Idle stack created ON
|
||||
* LED_INIRQ 2 In an interrupt N/C
|
||||
* LED_SIGNAL 2 In a signal handler N/C
|
||||
* LED_ASSERTION 2 An assertion failed N/C
|
||||
* LED_PANIC 3 The system has crashed FLASH
|
||||
* LED_IDLE Not used
|
||||
*
|
||||
* Thus if the LED is statically on, NuttX has successfully booted and is,
|
||||
* apparently, running normally. If the LED is flashing at approximately
|
||||
* 2Hz, then a fatal error has been detected and the system has halted.
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
|
||||
#include "hpm_gpio.h"
|
||||
#include "hpm_iomux.h"
|
||||
#include <arch/board/board.h>
|
||||
#include "hpm6360evk.h"
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_autoled_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize NuttX-controlled LED logic
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void hpm6360_autoled_initialize(void)
|
||||
{
|
||||
/* Configure LED GPIO for output */
|
||||
|
||||
hpm_gpio_config(GPIO_LED);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_autoled_on
|
||||
*
|
||||
* Description:
|
||||
* Turn on the "logical" LED state
|
||||
*
|
||||
* Input Parameters:
|
||||
* led - Identifies the "logical" LED state (see definitions in
|
||||
* include/board.h)
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void board_autoled_on(int led)
|
||||
{
|
||||
bool ledoff = false;
|
||||
|
||||
switch (led)
|
||||
{
|
||||
case 0: /* LED Off */
|
||||
ledoff = true;
|
||||
break;
|
||||
|
||||
case 2: /* LED No change */
|
||||
return;
|
||||
|
||||
case 1: /* LED On */
|
||||
case 3: /* LED On */
|
||||
break;
|
||||
}
|
||||
|
||||
hpm_gpio_write(GPIO_LED, ledoff); /* Low illuminates */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_autoled_off
|
||||
*
|
||||
* Description:
|
||||
* Turn off the "logical" LED state
|
||||
*
|
||||
* Input Parameters:
|
||||
* led - Identifies the "logical" LED state (see definitions in
|
||||
* include/board.h)
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void board_autoled_off(int led)
|
||||
{
|
||||
switch (led)
|
||||
{
|
||||
case 0: /* LED Off */
|
||||
case 1: /* LED Off */
|
||||
case 3: /* LED Off */
|
||||
break;
|
||||
|
||||
case 2: /* LED No change */
|
||||
return;
|
||||
}
|
||||
|
||||
hpm_gpio_write(GPIO_LED, true); /* Low illuminates */
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ARCH_LEDS */
|
||||
64
boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_boot.c
Normal file
64
boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_boot.c
Normal file
@ -0,0 +1,64 @@
|
||||
/****************************************************************************
|
||||
* boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_boot.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "hpm6360evk.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: hpm6340_boardinitialize
|
||||
*
|
||||
* Description:
|
||||
* All FE310 architectures must provide the following entry point.
|
||||
* This entry point is called early in the initialization -- after all
|
||||
* memory has been configured and mapped but before any devices have been
|
||||
* initialized.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void hpm6360_boardinitialize(void)
|
||||
{
|
||||
/* Configure on-board LEDs if LED support has been selected. */
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
hpm6360_autoled_initialize();
|
||||
#endif
|
||||
}
|
||||
67
boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_bringup.c
Normal file
67
boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_bringup.c
Normal file
@ -0,0 +1,67 @@
|
||||
/****************************************************************************
|
||||
* boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_bringup.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdio.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: hpm6750_bringup
|
||||
****************************************************************************/
|
||||
|
||||
int hpm6360_bringup(void)
|
||||
{
|
||||
int ret = OK;
|
||||
|
||||
#ifdef CONFIG_FS_BINFS
|
||||
/* Mount the binfs file system */
|
||||
|
||||
ret = nx_mount(NULL, "/bin", "binfs", 0, NULL);
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: Failed to mount binfs at /bin: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FS_PROCFS
|
||||
/* Mount the procfs file system */
|
||||
|
||||
ret = nx_mount(NULL, "/proc", "procfs", 0, NULL);
|
||||
if (ret < 0)
|
||||
{
|
||||
serr("ERROR: Failed to mount procfs at %s: %d\n", "/proc", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
78
boards/risc-v/hpm6000/hpm6360evk/src/hpm6360evk.h
Normal file
78
boards/risc-v/hpm6000/hpm6360evk/src/hpm6360evk.h
Normal file
@ -0,0 +1,78 @@
|
||||
/****************************************************************************
|
||||
* boards/risc-v/hpm6000/hpm6360evk/src/hpm6360evk.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __BOARDS_RISCV_HPM6000_HPM6360EVK_SRC_HPM6360EVK_H
|
||||
#define __BOARDS_RISCV_HPM6000_HPM6360EVK_SRC_HPM6360EVK_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "hpm_gpio.h"
|
||||
#include "hpm_iomux.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* GPIO Pin Definitions *****************************************************/
|
||||
|
||||
/* LEDs */
|
||||
|
||||
/* There are four LED status indicators located on the EVK Board.
|
||||
* The functions of these LEDs include:
|
||||
*
|
||||
* - Main Power Supply(D3)
|
||||
* Green: DC 5V main supply is normal.
|
||||
* Red: J2 input voltage is over 5.6V.
|
||||
* Off: The board is not powered.
|
||||
* - Reset RED LED(D15)
|
||||
* - OpenSDA LED(D16)
|
||||
* - USER LED(D18)
|
||||
*
|
||||
* Only a single LED, D18, is under software control.
|
||||
*/
|
||||
|
||||
#define GPIO_LED (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | GPIO_PORTA | GPIO_PIN7) /* PA07 */
|
||||
|
||||
#define LED_DRIVER_PATH "/dev/userleds"
|
||||
|
||||
int hpm6360_bringup(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_autoled_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize NuttX-controlled LED logic
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
void hpm6360_autoled_initialize(void);
|
||||
#endif
|
||||
|
||||
#endif /* __BOARDS_RISCV_HPM6000_HPM6360EVK_SRC_HPM6360EVK_H */
|
||||
Loading…
Reference in New Issue
Block a user