SMP: Basic function
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@ -605,9 +605,8 @@
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#define MMU_L2_VECTROFLAGS (PTE_TYPE_SMALL | PTE_WRITE_THROUGH | PTE_AP_R1)
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#define MMU_L2_VECTORFLAGS MMU_L2_VECTRWFLAGS
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#define MMU_L1_INTERCPUFLAGS (PMD_TYPE_PTE | PMD_PTE_PXN | PMD_DEVICE | \
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PMD_PTE_DOM(0))
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#define MMU_L2_INTERCPUFLAGS (PTE_TYPE_SMALL | PTE_DEVICE | PTE_AP_R1)
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#define MMU_L1_INTERCPUFLAGS (PMD_TYPE_PTE | PMD_PTE_PXN | PMD_PTE_DOM(0))
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#define MMU_L2_INTERCPUFLAGS (PTE_TYPE_SMALL | PTE_DEVICE | PTE_AP_RW1)
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/* Mapped section size */
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@ -917,8 +917,7 @@
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* the address space.
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*/
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#define INTERCPU_L2_PAGES 1 /* Pages allowed for inter-processor communications */
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#define L2_BASE 0x80000000 /* Beginning of L2 page table */
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#define INTERCPU_L2_PAGES 1 /* Pages allowed for inter-processor communications */
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#ifndef CONFIG_ARCH_LOWVECTORS
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/* Memory map
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@ -1051,10 +1050,14 @@
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# define IMX_VECTOR_VADDR 0x00000000
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#ifdef CONFIG_SMP
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/* Inter-processor communications */
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/* Inter-processor communications.
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*
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* NOTICE that we use the unused virtual address space at 0x00400000 for
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* the inter-CPU virtual communication area.
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*/
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# define INTERCPU_PADDR (IMX_VECTOR_PADDR + VECTOR_TABLE_SIZE)
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# define INTERCPU_VADDR (INTERCPU_L2_VBASE << 18)
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# define INTERCPU_VADDR (0x00400000)
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# define INTERCPU_SIZE (INTERCPU_L2_PAGES << 12)
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# define INTERCPU_VSRAM (IMX_VECTOR_VSRAM + VECTOR_TABLE_SIZE)
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#endif
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@ -1075,10 +1078,14 @@
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# define IMX_VECTOR_VADDR 0xffff0000
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#ifdef CONFIG_SMP
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/* Inter-processor communications */
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/* Inter-processor communications
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*
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* NOTICE that we use the unused virtual address space at 0x00400000 for
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* the inter-CPU virtual communication area.
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*/
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# define INTERCPU_PADDR (IMX_VECTOR_PADDR - INTERCPU_L2_SIZE)
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# define INTERCPU_VADDR (INTERCPU_L2_VBASE << 18)
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# define INTERCPU_VADDR (0x00400000)
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# define INTERCPU_SIZE (INTERCPU_L2_PAGES << 12)
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# define INTERCPU_VSRAM (IMX_VECTOR_VSRAM - INTERCPU_L2_SIZE)
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#endif
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@ -256,7 +256,7 @@ static void imx_intercpu_mapping(void)
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/* Now set the level 1 descriptor to refer to the level 2 page table. */
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mmu_l1_setentry(INTERCPU_PADDR & PMD_PTE_PADDR_MASK,
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mmu_l1_setentry(INTERCPU_L2_PBASE & PMD_PTE_PADDR_MASK,
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INTERCPU_VADDR & PMD_PTE_PADDR_MASK,
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MMU_L1_INTERCPUFLAGS);
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}
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@ -44,9 +44,9 @@
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MEMORY
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{
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nocache (WR) : ORIGIN = 0x00400000, LENGTH = 4K
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oscram (W!RX) : ORIGIN = 0x00900000, LENGTH = 256K - 16K
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ddr3 (W!RX) : ORIGIN = 0x10800000, LENGTH = 1024M - 8M
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nocache (WR) : ORIGIN = 0xe0000000, LENGTH = 4K
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}
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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