SAM3U SPI driver update
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4017 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
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@ -248,27 +248,15 @@
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#define GPIO_SPI0_MISO (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN13)
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#define GPIO_SPI0_MOSI (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN14)
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#define GPIO_SPI0_SPCK (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN15)
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#if 0
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# define GPIO_SPI0_NPCS0 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN16)
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# define GPIO_SPI0_NPCS1_1 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN0)
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# define GPIO_SPI0_NPCS1_2 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN3)
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# define GPIO_SPI0_NPCS1_3 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN19)
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# define GPIO_SPI0_NPCS2_1 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN1)
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# define GPIO_SPI0_NPCS2_2 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN4)
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# define GPIO_SPI0_NPCS2_3 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN14)
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# define GPIO_SPI0_NPCS3_1 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN19)
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# define GPIO_SPI0_NPCS3_2 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN5)
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#else
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# define GPIO_SPI0_NPCS0 (GPIO_OUTPUT|GPIO_CFG_PULLUP|GPIO_OUTPUT_CLEAR|GPIO_PORT_PIOA|GPIO_PIN16)
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# define GPIO_SPI0_NPCS1_1 (GPIO_OUTPUT|GPIO_CFG_PULLUP|GPIO_OUTPUT_CLEAR|GPIO_PORT_PIOA|GPIO_PIN0)
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# define GPIO_SPI0_NPCS1_2 (GPIO_OUTPUT|GPIO_CFG_PULLUP|GPIO_OUTPUT_CLEAR|GPIO_PORT_PIOC|GPIO_PIN3)
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# define GPIO_SPI0_NPCS1_3 (GPIO_OUTPUT|GPIO_CFG_PULLUP|GPIO_OUTPUT_CLEAR|GPIO_PORT_PIOC|GPIO_PIN19)
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# define GPIO_SPI0_NPCS2_1 (GPIO_OUTPUT|GPIO_CFG_PULLUP|GPIO_OUTPUT_CLEAR|GPIO_PORT_PIOA|GPIO_PIN1)
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# define GPIO_SPI0_NPCS2_2 (GPIO_OUTPUT|GPIO_CFG_PULLUP|GPIO_OUTPUT_CLEAR|GPIO_PORT_PIOC|GPIO_PIN4)
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# define GPIO_SPI0_NPCS2_3 (GPIO_OUTPUT|GPIO_CFG_PULLUP|GPIO_OUTPUT_CLEAR|GPIO_PORT_PIOC|GPIO_PIN14)
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# define GPIO_SPI0_NPCS3_1 (GPIO_OUTPUT|GPIO_CFG_PULLUP|GPIO_OUTPUT_CLEAR|GPIO_PORT_PIOA|GPIO_PIN19)
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# define GPIO_SPI0_NPCS3_2 (GPIO_OUTPUT|GPIO_CFG_PULLUP|GPIO_OUTPUT_CLEAR|GPIO_PORT_PIOC|GPIO_PIN5)
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#endif
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#define GPIO_SPI0_NPCS0 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN16)
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#define GPIO_SPI0_NPCS1_1 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN0)
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#define GPIO_SPI0_NPCS1_2 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN3)
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#define GPIO_SPI0_NPCS1_3 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN19)
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#define GPIO_SPI0_NPCS2_1 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN1)
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#define GPIO_SPI0_NPCS2_2 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN4)
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#define GPIO_SPI0_NPCS2_3 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN14)
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#define GPIO_SPI0_NPCS3_1 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN19)
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#define GPIO_SPI0_NPCS3_2 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN5)
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#define GPIO_SSC_TD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN26)
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#define GPIO_SSC_TK (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN28)
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@ -804,7 +792,7 @@ struct spi_dev_s;
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enum spi_dev_e;
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#ifdef CONFIG_SAM3U_SPI
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EXTERN void sam3u_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
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EXTERN int sam3u_spiselect(enum spi_dev_e devid);
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EXTERN uint8_t sam3u_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
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#ifdef CONFIG_SPI_CMDDATA
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EXTERN int sam3u_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
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@ -2,7 +2,8 @@
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* arch/arm/src/sam3u/sam3u_spi.c
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* Diego Sanchez <dsanchez@nx-engineering.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -82,24 +83,32 @@
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# define spivdbg(x...)
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#endif
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/* SPI Clocking */
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#warning "Missing logi"
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* The state of one chip select */
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#ifndef CONFIG_SPI_OWNBUS
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struct sam3u_chipselect_s
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{
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uint32_t frequency; /* Requested clock frequency */
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uint32_t actual; /* Actual clock frequency */
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uint8_t nbits; /* Width of word in bits (8 to 16) */
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uint8_t mode; /* Mode 0,1,2,3 */
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};
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#endif
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/* The overall state of the SPI interface */
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struct sam3u_spidev_s
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{
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struct spi_dev_s spidev; /* Externally visible part of the SPI interface */
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#ifndef CONFIG_SPI_OWNBUS
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sem_t exclsem; /* Held while chip is selected for mutual exclusion */
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uint32_t frequency; /* Requested clock frequency */
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uint32_t actual; /* Actual clock frequency */
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uint8_t nbits; /* Width of word in bits (8 to 16) */
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uint8_t mode; /* Mode 0,1,2,3 */
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struct sam3u_chipselect_s csstate[4];
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#endif
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uint8_t cs; /* Chip select number */
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};
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/****************************************************************************
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@ -123,12 +132,14 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_
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* Private Data
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****************************************************************************/
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/* SPI driver operations */
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static const struct spi_ops_s g_spiops =
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{
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#ifndef CONFIG_SPI_OWNBUS
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.lock = spi_lock,
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#endif
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.select = sam3u_spiselect,
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.select = spi_select,
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.setfrequency = spi_setfrequency,
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.setmode = spi_setmode,
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.setbits = spi_setbits,
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@ -142,11 +153,20 @@ static const struct spi_ops_s g_spiops =
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.registercallback = 0, /* Not implemented */
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};
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/* SPI device structure */
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static struct sam3u_spidev_s g_spidev =
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{
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.spidev = { &g_spiops },
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};
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/* This array maps chip select numbers (0-3) to CSR register addresses */
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static const uint32_t g_csraddr[4] =
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{
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SAM3U_SPI_CSR0, SAM3U_SPI_CSR1, SAM3U_SPI_CSR2, SAM3U_SPI_CSR3
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};
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/****************************************************************************
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* Public Data
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****************************************************************************/
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@ -202,6 +222,65 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
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}
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#endif
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/****************************************************************************
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* Name: spi_select
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*
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* Description:
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* This function does not actually set the chip select line. Rather, it
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* simply maps the device ID into a chip select number and retains that
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* chip select number for later use.
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*
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* Input Parameters:
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* dev - Device-specific state data
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* frequency - The SPI frequency requested
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*
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* Returned Value:
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* Returns the actual frequency selected
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*
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****************************************************************************/
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static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
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{
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FAR struct sam3u_spidev_s *priv = (FAR struct sam3u_spidev_s *)dev;
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uint32_t regval;
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/* Are we selecting or de-selecting the device? */
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if (selected)
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{
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/* At this point, we expect no chip selected */
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DEBUGASSERT(priv->cs == 0xff);
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/* Get the chip select associated with this SPI device */
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priv->cs = sam3u_spiselect(devid);
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DEBUGASSERT(priv->cs >= 0 && priv->cs <= 3);
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/* Before writing the TDR, the PCS field in the SPI_MR register must be set
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* in order to select a slave.
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*/
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regval = getreg32(SAM3U_SPI_MR);
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regval &= ~SPI_MR_PCS_MASK;
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regval |= (priv->cs << SPI_MR_PCS_SHIFT);
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putreg32(regval, SAM3U_SPI_MR);
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}
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else
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{
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/* At this point, we expect the chip to have already been selected */
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#ifdef CONFIG_DEBUG
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int cs = sam3u_spiselect(devid);
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DEBUGASSERT(priv->cs == cs);
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#endif
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/* Mark no chip selected */
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priv->cs = 0xff;
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}
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}
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/****************************************************************************
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* Name: spi_setfrequency
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*
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@ -221,34 +300,56 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
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{
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FAR struct sam3u_spidev_s *priv = (FAR struct sam3u_spidev_s *)dev;
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uint32_t actual;
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uint32_t divisor;
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uint32_t regval;
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uint32_t regaddr;
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/* Check if the requested frequence is the same as the frequency selection */
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DEBUGASSERT(priv->cs >= 0 && priv->cs <= 3);
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/* Check if the requested frequency is the same as the frequency selection */
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#ifndef CONFIG_SPI_OWNBUS
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if (priv->frequency == frequency)
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if (priv->csstate[priv->cs].frequency == frequency)
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{
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/* We are already at this frequency. Return the actual. */
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return priv->actual;
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return priv->csstate[priv->cs].actual;
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}
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#endif
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/* Configure SPI to a frequency as close as possible to the requested
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* frequency.
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*/
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#warning "Missing logic"
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/* Configure SPI to a frequency as close as possible to the requested frequency. */
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/* Calculate the actual actual frequency that is used */
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/* frequency = SPI_CLOCK / divisor, or divisor = SPI_CLOCK / frequency */
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#warning "Missing logic"
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actual = 0;
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divisor = SAM3U_MCK_FREQUENCY / frequency;
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if (divisor < 8)
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{
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divisor = 8;
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}
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else if (divisor > 254)
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{
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divisor = 254;
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}
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divisor = (divisor + 1) & ~1;
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/* Save the new divisor value */
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regaddr = g_csraddr[priv->cs];
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regval = getreg32(regaddr);
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regval &= ~SPI_CSR_SCBR_MASK;
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putreg32(divisor << SPI_CSR_SCBR_SHIFT, regaddr);
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/* Calculate the new actual */
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actual = SAM3U_MCK_FREQUENCY / divisor;
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/* Save the frequency setting */
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#ifndef CONFIG_SPI_OWNBUS
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priv->frequency = frequency;
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priv->actual = actual;
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priv->csstate[priv->cs].frequency = frequency;
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priv->csstate[priv->cs].actual = actual;
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#endif
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spidbg("Frequency %d->%d\n", frequency, actual);
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@ -274,28 +375,37 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
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{
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FAR struct sam3u_spidev_s *priv = (FAR struct sam3u_spidev_s *)dev;
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uint32_t regval;
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uint32_t regaddr;
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DEBUGASSERT(priv->cs >= 0 && priv->cs <= 3);
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/* Has the mode changed? */
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#ifndef CONFIG_SPI_OWNBUS
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if (mode != priv->mode)
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if (mode != priv->csstate[priv->cs].mode)
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{
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#endif
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/* Yes... Set the mode appropriately */
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#warning "Missing logic"
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regaddr = g_csraddr[priv->cs];
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regval = getreg32(regaddr);
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regval &= ~(SPI_CSR_CPOL|SPI_CSR_NCPHA);
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switch (mode)
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{
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case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
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case SPIDEV_MODE0: /* CPOL=0; NCPHA=0 */
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break;
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case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
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case SPIDEV_MODE1: /* CPOL=0; NCPHA=1 */
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regval |= SPI_CSR_NCPHA;
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break;
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case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
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case SPIDEV_MODE2: /* CPOL=1; NCPHA=0 */
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regval |= SPI_CSR_CPOL;
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break;
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case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
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case SPIDEV_MODE3: /* CPOL=1; NCPHA=1 */
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regval |= (SPI_CSR_CPOL|SPI_CSR_NCPHA);
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break;
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default:
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@ -303,10 +413,12 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
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return;
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}
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putreg32(regval, regaddr);
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/* Save the mode so that subsequent re-configurations will be faster */
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#ifndef CONFIG_SPI_OWNBUS
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priv->mode = mode;
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priv->csstate[priv->cs].mode = mode;
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}
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#endif
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}
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@ -329,22 +441,30 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
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static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
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{
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FAR struct sam3u_spidev_s *priv = (FAR struct sam3u_spidev_s *)dev;
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uint32_t regaddr;
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uint32_t regval;
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/* Has the number of bits changed? */
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DEBUGASSERT(priv && nbits > 7 && nbits < 17);
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DEBUGASSERT(priv->cs >= 0 && priv->cs <= 3);
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#ifndef CONFIG_SPI_OWNBUS
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if (nbits != priv->nbits)
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if (nbits != priv->csstate[priv->cs].nbits)
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{
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#endif
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/* Yes... Set number of bits appropriately */
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#warning "Missing logic"
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regaddr = g_csraddr[priv->cs];
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regval = getreg32(regaddr);
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regval &= ~SPI_CSR_BITS_MASK;
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regval |= SPI_CSR_BITS(nbits);
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putreg32(regval, regaddr);
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/* Save the selection so the subsequence re-configurations will be faster */
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#ifndef CONFIG_SPI_OWNBUS
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priv->nbits = nbits;
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priv->csstate[priv->cs].nbits = nbits;
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}
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#endif
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}
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@ -367,15 +487,23 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
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static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
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{
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/* Write the data to transmitted to the SPI Data Register */
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#warning "Missing logic"
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/* Wait for any previous data written to the TDR to be transferred to the
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* serializer.
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*/
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/* Wait for the data exchange to complete */
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#warning "Missing logic"
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while ((getreg32(SAM3U_SPI_SR) & SPI_INT_TDRE) == 0);
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/* Clear any pending status and return the received data */
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#warning "Missing logic"
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return 0;
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/* Write the data to transmitted to the Transmit Data Register (TDR) */
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putreg32((uint32_t)wd, SAM3U_SPI_TDR);
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/* Wait for the read data to be available in the RDR */
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while ((getreg32(SAM3U_SPI_SR) & SPI_INT_RDRF) == 0);
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/* Return the received data */
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return (uint16_t)getreg32(SAM3U_SPI_RDR);
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}
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/*************************************************************************
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@ -403,19 +531,21 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
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uint8_t data;
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spidbg("nwords: %d\n", nwords);
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while (nwords)
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/* Loop, sending each word in the user-provied data buffer */
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for ( ; nwords > 0; nwords--)
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{
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/* Write the data to transmitted to the SPI Data Register */
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/* Wait for any previous data written to the TDR to be transferred
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* to the serializer.
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*/
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while ((getreg32(SAM3U_SPI_SR) & SPI_INT_TDRE) == 0);
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/* Write the data to transmitted to the Transmit Data Register (TDR) */
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data = *ptr++;
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#warning "Missing logic"
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/* Wait for the data exchange to complete */
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#warning "Missing logic"
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/* Clear any pending status */
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#warning "Missing logic"
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nwords--;
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putreg32((uint32_t)data, SAM3U_SPI_TDR);
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}
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}
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|
||||
@ -443,28 +573,30 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
|
||||
FAR uint8_t *ptr = (FAR uint8_t*)buffer;
|
||||
|
||||
spidbg("nwords: %d\n", nwords);
|
||||
while (nwords)
|
||||
|
||||
/* Loop, receiving each word */
|
||||
|
||||
for ( ; nwords > 0; nwords--)
|
||||
{
|
||||
/* Write some dummy data to the SPI Data Register in order to clock the
|
||||
* read data.
|
||||
/* Wait for any previous data written to the TDR to be transferred
|
||||
* to the serializer.
|
||||
*/
|
||||
|
||||
while ((getreg32(SAM3U_SPI_SR) & SPI_INT_TDRE) == 0);
|
||||
|
||||
/* Write the some dummy data the Transmit Data Register (TDR) in order
|
||||
* to clock the read data.
|
||||
*/
|
||||
|
||||
#warning "Missing logic"
|
||||
putreg32(0xff, SAM3U_SPI_TDR);
|
||||
|
||||
/* Wait for the data exchange to complete */
|
||||
#warning "Missing logic"
|
||||
/* Wait for the read data to be available in the RDR */
|
||||
|
||||
/* Read the received data from the SPI Data Register */
|
||||
#warning "Missing logic"
|
||||
while ((getreg32(SAM3U_SPI_SR) & SPI_INT_RDRF) == 0);
|
||||
|
||||
/* Clear any pending status */
|
||||
#warning "Missing logic"
|
||||
/* Read the received data from the SPI Data Register */
|
||||
|
||||
/* Read the received data from the SPI Data Register */
|
||||
|
||||
#warning "Missing logic"
|
||||
*ptr++ = 0;
|
||||
nwords--;
|
||||
*ptr++ = (uint8_t)getreg32(SAM3U_SPI_RDR);
|
||||
}
|
||||
}
|
||||
|
||||
@ -496,6 +628,10 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
|
||||
|
||||
DEBUGASSERT(port == 0);
|
||||
|
||||
/* Set up the initial state */
|
||||
|
||||
priv->cs = 0xff;
|
||||
|
||||
/* Apply power to the SPI block */
|
||||
|
||||
flags = irqsave();
|
||||
@ -514,30 +650,25 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
|
||||
sam3u_configgpio(GPIO_SPI0_MOSI);
|
||||
sam3u_configgpio(GPIO_SPI0_SPCK);
|
||||
|
||||
/* Execute a software reset of the SPI twice */
|
||||
/* Execute a software reset of the SPI (twice) */
|
||||
|
||||
putreg32(SPI_CR_SWRST, SAM3U_SPI_CR);
|
||||
putreg32(SPI_CR_SWRST, SAM3U_SPI_CR);
|
||||
|
||||
/* Configure clocking */
|
||||
#warning "Missing logic - Check SPI MR register"
|
||||
|
||||
irqrestore(flags);
|
||||
|
||||
/* Configure 8-bit SPI mode and master mode */
|
||||
#warning "Missing logic"
|
||||
|
||||
/* Set the initial SPI configuration */
|
||||
/* Configure the SPI mode register */
|
||||
#warning "Need to review this -- what other settngs are necessary"
|
||||
putreg32(SPI_MR_MSTR, SAM3U_SPI_MR);
|
||||
|
||||
#ifndef CONFIG_SPI_OWNBUS
|
||||
priv->frequency = 0;
|
||||
priv->nbits = 8;
|
||||
priv->mode = SPIDEV_MODE0;
|
||||
#endif
|
||||
/* And enable the SPI */
|
||||
|
||||
/* Select a default frequency of approx. 400KHz */
|
||||
putreg32(SPI_CR_SPIEN, SAM3U_SPI_CR);
|
||||
up_mdelay(20);
|
||||
|
||||
spi_setfrequency((FAR struct spi_dev_s *)priv, 400000);
|
||||
/* Flush any pending transfers */
|
||||
|
||||
(void)getreg32(SAM3U_SPI_SR);
|
||||
(void)getreg32(SAM3U_SPI_RDR);
|
||||
|
||||
/* Initialize the SPI semaphore that enforces mutually exclusive access */
|
||||
|
||||
|
||||
@ -1,188 +1,189 @@
|
||||
/****************************************************************************************
|
||||
* arch/arm/src/sam3u/sam3u_spi.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_SPI_H
|
||||
#define __ARCH_ARM_SRC_SAM3U_SAM3U_SPI_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "sam3u_memorymap.h"
|
||||
|
||||
/****************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************/
|
||||
|
||||
/* SPI register offsets *****************************************************************/
|
||||
|
||||
#define SAM3U_SPI_CR_OFFSET 0x00 /* Control Register */
|
||||
#define SAM3U_SPI_MR_OFFSET 0x04 /* Mode Register */
|
||||
#define SAM3U_SPI_RDR_OFFSET 0x08 /* Receive Data Register */
|
||||
#define SAM3U_SPI_TDR_OFFSET 0x0c /* Transmit Data Register */
|
||||
#define SAM3U_SPI_SR_OFFSET 0x10 /* Status Register */
|
||||
#define SAM3U_SPI_IER_OFFSET 0x14 /* Interrupt Enable Register */
|
||||
#define SAM3U_SPI_IDR_OFFSET 0x18 /* Interrupt Disable Register */
|
||||
#define SAM3U_SPI_IMR_OFFSET 0x1c /* Interrupt Mask Register */
|
||||
/* 0x20-0x2c: Reserved */
|
||||
#define SAM3U_SPI_CSR0_OFFSET 0x30 /* Chip Select Register 0 */
|
||||
#define SAM3U_SPI_CSR1_OFFSET 0x34 /* Chip Select Register 1 */
|
||||
#define SAM3U_SPI_CSR2_OFFSET 0x38 /* Chip Select Register 2 */
|
||||
#define SAM3U_SPI_CSR3_OFFSET 0x3c /* Chip Select Register 3 */
|
||||
/* 0x40-0xe0: Reserved */
|
||||
#define SAM3U_SPI_WPCR_OFFSET 0xe4 /* Write Protection Control Register */
|
||||
#define SAM3U_SPI_WPSR_OFFSET 0xe8 /* Write Protection Status Register */
|
||||
/* 0xec-0xf8: Reserved*/
|
||||
|
||||
/* SPI register adresses ****************************************************************/
|
||||
|
||||
#define SAM3U_SPI_CR (SAM3U_SPI_BASE+SAM3U_SPI_CR_OFFSET) /* Control Register */
|
||||
#define SAM3U_SPI_MR (SAM3U_SPI_BASE+SAM3U_SPI_MR_OFFSET) /* Mode Register */
|
||||
#define SAM3U_SPI_RDR (SAM3U_SPI_BASE+SAM3U_SPI_RDR_OFFSET) /* Receive Data Register */
|
||||
#define SAM3U_SPI_TDR (SAM3U_SPI_BASE+SAM3U_SPI_TDR_OFFSET) /* Transmit Data Register */
|
||||
#define SAM3U_SPI_SR (SAM3U_SPI_BASE+SAM3U_SPI_SR_OFFSET) /* Status Register */
|
||||
#define SAM3U_SPI_IER (SAM3U_SPI_BASE+SAM3U_SPI_IER_OFFSET) /* Interrupt Enable Register */
|
||||
#define SAM3U_SPI_IDR (SAM3U_SPI_BASE+SAM3U_SPI_IDR_OFFSET) /* Interrupt Disable Register */
|
||||
#define SAM3U_SPI_IMR (SAM3U_SPI_BASE+SAM3U_SPI_IMR_OFFSET) /* Interrupt Mask Register */
|
||||
#define SAM3U_SPI_CSR0 (SAM3U_SPI_BASE+SAM3U_SPI_CSR0_OFFSET) /* Chip Select Register 0 */
|
||||
#define SAM3U_SPI_CSR1 (SAM3U_SPI_BASE+SAM3U_SPI_CSR1_OFFSET) /* Chip Select Register 1 */
|
||||
#define SAM3U_SPI_CSR2 (SAM3U_SPI_BASE+SAM3U_SPI_CSR2_OFFSET) /* Chip Select Register 2 */
|
||||
#define SAM3U_SPI_CSR3 (SAM3U_SPI_BASE+SAM3U_SPI_CSR3_OFFSET) /* Chip Select Register 3 */
|
||||
#define SAM3U_SPI_WPCR (SAM3U_SPI_BASE+SAM3U_SPI_WPCR_OFFSET) /* Write Protection Control Register */
|
||||
#define SAM3U_SPI_WPSR (SAM3U_SPI_BASE+SAM3U_SPI_WPSR_OFFSET) /* Write Protection Status Register */
|
||||
|
||||
/* SPI register bit definitions *********************************************************/
|
||||
|
||||
/* SPI Control Register */
|
||||
|
||||
#define SPI_CR_SPIEN (1 << 0) /* Bit 0: SPI Enable */
|
||||
#define SPI_CR_SPIDIS (1 << 1) /* Bit 1: SPI Disable */
|
||||
#define SPI_CR_SWRST (1 << 7) /* Bit 7: SPI Software Reset */
|
||||
#define SPI_CR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */
|
||||
|
||||
/* SPI Mode Register */
|
||||
|
||||
#define SPI_MR_MSTR (1 << 0) /* Bit 0: Master/Slave Mode */
|
||||
#define SPI_MR_PS (1 << 1) /* Bit 1: Peripheral Select */
|
||||
#define SPI_MR_PCSDEC (1 << 2) /* Bit 2: Chip Select Decode */
|
||||
#define SPI_MR_MODFDIS (1 << 4) /* Bit 4: Mode Fault Detection */
|
||||
#define SPI_MR_WDRBT (1 << 5) /* Bit 5: Wait Data Read Before Transfer */
|
||||
#define SPI_MR_LLB (1 << 7) /* Bit 7: Local Loopback Enable */
|
||||
#define SPI_MR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
|
||||
#define SPI_MR_PCS_MASK (15 << SPI_MR_PCS_SHIFT)
|
||||
#define SPI_MR_DLYBCS_SHIFT (24) /* Bits 24-31: Delay Between Chip Selects */
|
||||
#define SPI_MR_DLYBCS_MASK (0xff << SPI_MR_DLYBCS_SHIFT)
|
||||
|
||||
/* SPI Receive Data Register */
|
||||
|
||||
#define SPI_RDR_RD_SHIFT (0) /* Bits 0-15: Receive Data */
|
||||
#define SPI_RDR_RD_MASK (0xffff << SPI_RDR_RD_SHIFT)
|
||||
#define SPI_RDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
|
||||
#define SPI_RDR_PCS_MASK (15 << SPI_RDR_PCS_SHIFT)
|
||||
|
||||
/* SPI Transmit Data Register */
|
||||
|
||||
#define SPI_TDR_TD_SHIFT (0) /* Bits 0-15: Transmit Data */
|
||||
#define SPI_TDR_TD_MASK (0xffff << SPI_TDR_TD_SHIFT)
|
||||
#define SPI_TDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
|
||||
#define SPI_TDR_PCS_MASK (15 << SPI_TDR_PCS_SHIFT)
|
||||
#define SPI_TDR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */
|
||||
|
||||
/* SPI Status Register, SPI Interrupt Enable Register, SPI Interrupt Disable Register,
|
||||
* and SPI Interrupt Mask Register (common bit fields)
|
||||
*/
|
||||
|
||||
#define SPI_INT_RDRF (1 << 0) /* Bit 0: Receive Data Register Full Interrupt */
|
||||
#define SPI_INT_TDRE (1 << 1) /* Bit 1: Transmit Data Register Empty Interrupt */
|
||||
#define SPI_INT_MODF (1 << 2) /* Bit 2: Mode Fault Error Interrupt */
|
||||
#define SPI_INT_OVRES (1 << 3) /* Bit 3: Overrun Error Interrupt */
|
||||
#define SPI_INT_NSSR (1 << 8) /* Bit 8: NSS Rising Interrupt */
|
||||
#define SPI_INT_TXEMPTY (1 << 9) /* Bit 9: Transmission Registers Empty Interrupt */
|
||||
#define SPI_INT_UNDES (1 << 10) /* Bit 10: Underrun Error Status Interrupt (slave) */
|
||||
#define SPI_SR_SPIENS (1 << 16) /* Bit 16: SPI Enable Status (SR only) */
|
||||
|
||||
/* SPI Chip Select Registers 0-3 */
|
||||
|
||||
#define SPI_CSR_CPOL (1 << 0) /* Bit 0: Clock Polarity */
|
||||
#define SPI_CSR_NCPHA (1 << 1) /* Bit 1: Clock Phase */
|
||||
#define SPI_CSR_CSNAAT (1 << 2) /* Bit 2: Chip Select Not Active After Transfer */
|
||||
#define SPI_CSR_CSAAT (1 << 3) /* Bit 3: Chip Select Active After Transfer */
|
||||
#define SPI_CSR_BITS_SHIFT (4) /* Bits 4-7: Bits Per Transfer */
|
||||
#define SPI_CSR_BITS_MASK (15 << SPI_CSR_BITS_SHIFT)
|
||||
# define SPI_CSR_BITS8 (0 << SPI_CSR_BITS_SHIFT) /* 8 */
|
||||
# define SPI_CSR_BITS9 (1 << SPI_CSR_BITS_SHIFT) /* 9 */
|
||||
# define SPI_CSR_BITS10 (2 << SPI_CSR_BITS_SHIFT) /* 10 */
|
||||
# define SPI_CSR_BITS11 (3 << SPI_CSR_BITS_SHIFT) /* 11 */
|
||||
# define SPI_CSR_BITS12 (4 << SPI_CSR_BITS_SHIFT) /* 12 */
|
||||
# define SPI_CSR_BITS13 (5 << SPI_CSR_BITS_SHIFT) /* 13 */
|
||||
# define SPI_CSR_BITS14 (6 << SPI_CSR_BITS_SHIFT) /* 14 */
|
||||
# define SPI_CSR_BITS15 (7 << SPI_CSR_BITS_SHIFT) /* 15 */
|
||||
# define SPI_CSR_BITS15 (8 << SPI_CSR_BITS_SHIFT) /* 16 */
|
||||
#define SPI_CSR_SCBR_SHIFT (8) /* Bits 8-15: Serial Clock Baud Rate */
|
||||
#define SPI_CSR_SCBR_MASK (0xff << SPI_CSR_SCBR_SHIFT)
|
||||
#define SPI_CSR_DLYBS_SHIFT (16) /* Bits 16-23: Delay Before SPCK */
|
||||
#define SPI_CSR_DLYBS_MASK (0xff << SPI_CSR_DLYBS_SHIFT)
|
||||
#define SPI_CSR_DLYBCT_SHIFT (24) /* Bits 24-31: Delay Between Consecutive Transfers */
|
||||
#define SPI_CSR_DLYBCT_MASK (0xff << SPI_CSR_DLYBCT_SHIFT)
|
||||
|
||||
/* SPI Write Protection Control Register */
|
||||
|
||||
#define SPI_WPCR_SPIWPEN (1 << 0) /* Bit 0: SPI Write Protection Enable */
|
||||
#define SPI_WPCR_SPIWPKEY_SHIFT (8) /* Bits 8-31: SPI Write Protection Key Password */
|
||||
#define SPI_WPCR_SPIWPKEY_MASK (0x00ffffff << SPI_WPCR_SPIWPKEY_SHIFT)
|
||||
|
||||
/* SPI Write Protection Status Register */
|
||||
|
||||
#define SPI_WPSR_SPIWPVS_SHIFT (0) /* Bits 0-2: SPI Write Protection Violation Status */
|
||||
#define SPI_WPSR_SPIWPVS_MASK (7 << SPI_WPSR_SPIWPVS_SHIFT)
|
||||
#define SPI_WPSR_SPIWPVSRC_SHIFT (8) /* Bits 8-15: SPI Write Protection Violation Source */
|
||||
#define SPI_WPSR_SPIWPVSRC_MASK (0xff << SPI_WPSR_SPIWPVSRC_SHIFT)
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_SPI_H */
|
||||
/****************************************************************************************
|
||||
* arch/arm/src/sam3u/sam3u_spi.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_SPI_H
|
||||
#define __ARCH_ARM_SRC_SAM3U_SAM3U_SPI_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "sam3u_memorymap.h"
|
||||
|
||||
/****************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************/
|
||||
|
||||
/* SPI register offsets *****************************************************************/
|
||||
|
||||
#define SAM3U_SPI_CR_OFFSET 0x00 /* Control Register */
|
||||
#define SAM3U_SPI_MR_OFFSET 0x04 /* Mode Register */
|
||||
#define SAM3U_SPI_RDR_OFFSET 0x08 /* Receive Data Register */
|
||||
#define SAM3U_SPI_TDR_OFFSET 0x0c /* Transmit Data Register */
|
||||
#define SAM3U_SPI_SR_OFFSET 0x10 /* Status Register */
|
||||
#define SAM3U_SPI_IER_OFFSET 0x14 /* Interrupt Enable Register */
|
||||
#define SAM3U_SPI_IDR_OFFSET 0x18 /* Interrupt Disable Register */
|
||||
#define SAM3U_SPI_IMR_OFFSET 0x1c /* Interrupt Mask Register */
|
||||
/* 0x20-0x2c: Reserved */
|
||||
#define SAM3U_SPI_CSR0_OFFSET 0x30 /* Chip Select Register 0 */
|
||||
#define SAM3U_SPI_CSR1_OFFSET 0x34 /* Chip Select Register 1 */
|
||||
#define SAM3U_SPI_CSR2_OFFSET 0x38 /* Chip Select Register 2 */
|
||||
#define SAM3U_SPI_CSR3_OFFSET 0x3c /* Chip Select Register 3 */
|
||||
/* 0x40-0xe0: Reserved */
|
||||
#define SAM3U_SPI_WPCR_OFFSET 0xe4 /* Write Protection Control Register */
|
||||
#define SAM3U_SPI_WPSR_OFFSET 0xe8 /* Write Protection Status Register */
|
||||
/* 0xec-0xf8: Reserved*/
|
||||
|
||||
/* SPI register adresses ****************************************************************/
|
||||
|
||||
#define SAM3U_SPI_CR (SAM3U_SPI_BASE+SAM3U_SPI_CR_OFFSET) /* Control Register */
|
||||
#define SAM3U_SPI_MR (SAM3U_SPI_BASE+SAM3U_SPI_MR_OFFSET) /* Mode Register */
|
||||
#define SAM3U_SPI_RDR (SAM3U_SPI_BASE+SAM3U_SPI_RDR_OFFSET) /* Receive Data Register */
|
||||
#define SAM3U_SPI_TDR (SAM3U_SPI_BASE+SAM3U_SPI_TDR_OFFSET) /* Transmit Data Register */
|
||||
#define SAM3U_SPI_SR (SAM3U_SPI_BASE+SAM3U_SPI_SR_OFFSET) /* Status Register */
|
||||
#define SAM3U_SPI_IER (SAM3U_SPI_BASE+SAM3U_SPI_IER_OFFSET) /* Interrupt Enable Register */
|
||||
#define SAM3U_SPI_IDR (SAM3U_SPI_BASE+SAM3U_SPI_IDR_OFFSET) /* Interrupt Disable Register */
|
||||
#define SAM3U_SPI_IMR (SAM3U_SPI_BASE+SAM3U_SPI_IMR_OFFSET) /* Interrupt Mask Register */
|
||||
#define SAM3U_SPI_CSR0 (SAM3U_SPI_BASE+SAM3U_SPI_CSR0_OFFSET) /* Chip Select Register 0 */
|
||||
#define SAM3U_SPI_CSR1 (SAM3U_SPI_BASE+SAM3U_SPI_CSR1_OFFSET) /* Chip Select Register 1 */
|
||||
#define SAM3U_SPI_CSR2 (SAM3U_SPI_BASE+SAM3U_SPI_CSR2_OFFSET) /* Chip Select Register 2 */
|
||||
#define SAM3U_SPI_CSR3 (SAM3U_SPI_BASE+SAM3U_SPI_CSR3_OFFSET) /* Chip Select Register 3 */
|
||||
#define SAM3U_SPI_WPCR (SAM3U_SPI_BASE+SAM3U_SPI_WPCR_OFFSET) /* Write Protection Control Register */
|
||||
#define SAM3U_SPI_WPSR (SAM3U_SPI_BASE+SAM3U_SPI_WPSR_OFFSET) /* Write Protection Status Register */
|
||||
|
||||
/* SPI register bit definitions *********************************************************/
|
||||
|
||||
/* SPI Control Register */
|
||||
|
||||
#define SPI_CR_SPIEN (1 << 0) /* Bit 0: SPI Enable */
|
||||
#define SPI_CR_SPIDIS (1 << 1) /* Bit 1: SPI Disable */
|
||||
#define SPI_CR_SWRST (1 << 7) /* Bit 7: SPI Software Reset */
|
||||
#define SPI_CR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */
|
||||
|
||||
/* SPI Mode Register */
|
||||
|
||||
#define SPI_MR_MSTR (1 << 0) /* Bit 0: Master/Slave Mode */
|
||||
#define SPI_MR_PS (1 << 1) /* Bit 1: Peripheral Select */
|
||||
#define SPI_MR_PCSDEC (1 << 2) /* Bit 2: Chip Select Decode */
|
||||
#define SPI_MR_MODFDIS (1 << 4) /* Bit 4: Mode Fault Detection */
|
||||
#define SPI_MR_WDRBT (1 << 5) /* Bit 5: Wait Data Read Before Transfer */
|
||||
#define SPI_MR_LLB (1 << 7) /* Bit 7: Local Loopback Enable */
|
||||
#define SPI_MR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
|
||||
#define SPI_MR_PCS_MASK (15 << SPI_MR_PCS_SHIFT)
|
||||
#define SPI_MR_DLYBCS_SHIFT (24) /* Bits 24-31: Delay Between Chip Selects */
|
||||
#define SPI_MR_DLYBCS_MASK (0xff << SPI_MR_DLYBCS_SHIFT)
|
||||
|
||||
/* SPI Receive Data Register */
|
||||
|
||||
#define SPI_RDR_RD_SHIFT (0) /* Bits 0-15: Receive Data */
|
||||
#define SPI_RDR_RD_MASK (0xffff << SPI_RDR_RD_SHIFT)
|
||||
#define SPI_RDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
|
||||
#define SPI_RDR_PCS_MASK (15 << SPI_RDR_PCS_SHIFT)
|
||||
|
||||
/* SPI Transmit Data Register */
|
||||
|
||||
#define SPI_TDR_TD_SHIFT (0) /* Bits 0-15: Transmit Data */
|
||||
#define SPI_TDR_TD_MASK (0xffff << SPI_TDR_TD_SHIFT)
|
||||
#define SPI_TDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
|
||||
#define SPI_TDR_PCS_MASK (15 << SPI_TDR_PCS_SHIFT)
|
||||
#define SPI_TDR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */
|
||||
|
||||
/* SPI Status Register, SPI Interrupt Enable Register, SPI Interrupt Disable Register,
|
||||
* and SPI Interrupt Mask Register (common bit fields)
|
||||
*/
|
||||
|
||||
#define SPI_INT_RDRF (1 << 0) /* Bit 0: Receive Data Register Full Interrupt */
|
||||
#define SPI_INT_TDRE (1 << 1) /* Bit 1: Transmit Data Register Empty Interrupt */
|
||||
#define SPI_INT_MODF (1 << 2) /* Bit 2: Mode Fault Error Interrupt */
|
||||
#define SPI_INT_OVRES (1 << 3) /* Bit 3: Overrun Error Interrupt */
|
||||
#define SPI_INT_NSSR (1 << 8) /* Bit 8: NSS Rising Interrupt */
|
||||
#define SPI_INT_TXEMPTY (1 << 9) /* Bit 9: Transmission Registers Empty Interrupt */
|
||||
#define SPI_INT_UNDES (1 << 10) /* Bit 10: Underrun Error Status Interrupt (slave) */
|
||||
#define SPI_SR_SPIENS (1 << 16) /* Bit 16: SPI Enable Status (SR only) */
|
||||
|
||||
/* SPI Chip Select Registers 0-3 */
|
||||
|
||||
#define SPI_CSR_CPOL (1 << 0) /* Bit 0: Clock Polarity */
|
||||
#define SPI_CSR_NCPHA (1 << 1) /* Bit 1: Clock Phase */
|
||||
#define SPI_CSR_CSNAAT (1 << 2) /* Bit 2: Chip Select Not Active After Transfer */
|
||||
#define SPI_CSR_CSAAT (1 << 3) /* Bit 3: Chip Select Active After Transfer */
|
||||
#define SPI_CSR_BITS_SHIFT (4) /* Bits 4-7: Bits Per Transfer */
|
||||
#define SPI_CSR_BITS_MASK (15 << SPI_CSR_BITS_SHIFT)
|
||||
# define SPI_CSR_BITS(n) (((n)-8) << SPI_CSR_BITS_SHIFT) /* n, n=8-16 */
|
||||
# define SPI_CSR_BITS8 (0 << SPI_CSR_BITS_SHIFT) /* 8 */
|
||||
# define SPI_CSR_BITS9 (1 << SPI_CSR_BITS_SHIFT) /* 9 */
|
||||
# define SPI_CSR_BITS10 (2 << SPI_CSR_BITS_SHIFT) /* 10 */
|
||||
# define SPI_CSR_BITS11 (3 << SPI_CSR_BITS_SHIFT) /* 11 */
|
||||
# define SPI_CSR_BITS12 (4 << SPI_CSR_BITS_SHIFT) /* 12 */
|
||||
# define SPI_CSR_BITS13 (5 << SPI_CSR_BITS_SHIFT) /* 13 */
|
||||
# define SPI_CSR_BITS14 (6 << SPI_CSR_BITS_SHIFT) /* 14 */
|
||||
# define SPI_CSR_BITS15 (7 << SPI_CSR_BITS_SHIFT) /* 15 */
|
||||
# define SPI_CSR_BITS16 (8 << SPI_CSR_BITS_SHIFT) /* 16 */
|
||||
#define SPI_CSR_SCBR_SHIFT (8) /* Bits 8-15: Serial Clock Baud Rate */
|
||||
#define SPI_CSR_SCBR_MASK (0xff << SPI_CSR_SCBR_SHIFT)
|
||||
#define SPI_CSR_DLYBS_SHIFT (16) /* Bits 16-23: Delay Before SPCK */
|
||||
#define SPI_CSR_DLYBS_MASK (0xff << SPI_CSR_DLYBS_SHIFT)
|
||||
#define SPI_CSR_DLYBCT_SHIFT (24) /* Bits 24-31: Delay Between Consecutive Transfers */
|
||||
#define SPI_CSR_DLYBCT_MASK (0xff << SPI_CSR_DLYBCT_SHIFT)
|
||||
|
||||
/* SPI Write Protection Control Register */
|
||||
|
||||
#define SPI_WPCR_SPIWPEN (1 << 0) /* Bit 0: SPI Write Protection Enable */
|
||||
#define SPI_WPCR_SPIWPKEY_SHIFT (8) /* Bits 8-31: SPI Write Protection Key Password */
|
||||
#define SPI_WPCR_SPIWPKEY_MASK (0x00ffffff << SPI_WPCR_SPIWPKEY_SHIFT)
|
||||
|
||||
/* SPI Write Protection Status Register */
|
||||
|
||||
#define SPI_WPSR_SPIWPVS_SHIFT (0) /* Bits 0-2: SPI Write Protection Violation Status */
|
||||
#define SPI_WPSR_SPIWPVS_MASK (7 << SPI_WPSR_SPIWPVS_SHIFT)
|
||||
#define SPI_WPSR_SPIWPVSRC_SHIFT (8) /* Bits 8-15: SPI Write Protection Violation Source */
|
||||
#define SPI_WPSR_SPIWPVSRC_MASK (0xff << SPI_WPSR_SPIWPVSRC_SHIFT)
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_SPI_H */
|
||||
|
||||
@ -134,18 +134,21 @@ void weak_function sam3u_spiinitialize(void)
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAM3U_SPI
|
||||
void sam3u_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
|
||||
int sam3u_spiselect(enum spi_dev_e devid)
|
||||
{
|
||||
spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
|
||||
int cs = -EINVAL;
|
||||
|
||||
#if defined(CONFIG_INPUT) && defined(CONFIG_INPUT_ADS7843E)
|
||||
if (devid == SPIDEV_TOUCHSCREEN)
|
||||
{
|
||||
/* Assert the CS pin to the OLED display */
|
||||
|
||||
(void)lpc17_gpiowrite(GPIO_TSC_NPCS2, !selected);
|
||||
cs = 2;
|
||||
}
|
||||
#endif
|
||||
|
||||
spidbg("devid: %d CS: %d\n", (int)devid, cs);
|
||||
return cs;
|
||||
}
|
||||
|
||||
uint8_t sam3u_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
|
||||
|
||||
@ -50,11 +50,21 @@
|
||||
#include <nuttx/input/ads7843e.h>
|
||||
|
||||
#include "sam3u_internal.h"
|
||||
#include "sam3uek_internal.h.h"
|
||||
#include "sam3uek_internal.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-Processor Definitions
|
||||
****************************************************************************/
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
#ifdef CONFIG_INPUT_ADS7843E
|
||||
#ifndef CONFIG_INPUT
|
||||
# error "Touchscreen support requires CONFIG_INPUT"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SAM3U_SPI
|
||||
# error "Touchscreen support requires CONFIG_SAM3U_SPI"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Static Function Prototypes
|
||||
@ -150,7 +160,6 @@ static bool tsc_pendown(FAR struct ads7843e_config_s *state)
|
||||
|
||||
return sam3u_gpioread(GPIO_ADS7843E);
|
||||
}
|
||||
#endif /* HAVE_TOUCHSCREEN */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
@ -195,3 +204,4 @@ int up_tcinitialize(void)
|
||||
|
||||
return OK;
|
||||
}
|
||||
#endif /* CONFIG_INPUT_ADS7843E */
|
||||
@ -322,7 +322,7 @@ CONFIG_SEM_NNESTPRIO=0
|
||||
CONFIG_FDCLONE_DISABLE=n
|
||||
CONFIG_FDCLONE_STDIO=n
|
||||
CONFIG_SDCLONE_DISABLE=y
|
||||
CONFIG_SCHED_WORKQUEUE=n
|
||||
CONFIG_SCHED_WORKQUEUE=y
|
||||
CONFIG_SCHED_WORKPRIORITY=50
|
||||
CONFIG_SCHED_WORKPERIOD=(50*1000)
|
||||
CONFIG_SCHED_WORKSTACKSIZE=1024
|
||||
|
||||
Loading…
Reference in New Issue
Block a user