SAMV7: Add configuration logic and clock setup for USB device

arch/arm/src/sama5/Kconfig

@@ -2580,13 +2580,13 @@ menu "USB High Speed Device Controller driver (DCD) options"
 config SAMA5_UDPHS_SCATTERGATHER
 	bool
 	default n
+	depends on EXPERIMENTAL
 	---help---
 		Scatter gather DMA is not yet supported
 
 config SAMA5_UDPHS_NDTDS
 	int "Number of UDPHS DMA transfer descriptors"
-	default 9
-	depends on UDPHS_SCATTERGATHER
+	default 8
 	---help---
 		DMA transfer descriptors are allocated in a pool at boot time.  This
 		setting provides the number of DMA transfer descriptors to be
@@ -2595,7 +2595,6 @@ config SAMA5_UDPHS_NDTDS
 config SAMA5_UDPHS_PREALLOCATE
 	bool "Pre-allocate DMA transfer descriptors"
 	default y
-	depends on UDPHS_SCATTERGATHER
 	---help---
 		If this option is selected then DMA transfer descriptors will be
 		pre-allocated in .bss.  Otherwise, the descriptors will be allocated

arch/arm/src/samv7/Kconfig

@@ -408,21 +408,25 @@ config SAMV7_USBDEVFS
 	bool "USB Device Full Speed (USBFS)"
 	default n
 	depends on SAMV7_HAVE_USBFS
+	select USBDEV
 
 config SAMV7_USBDEVHS
 	bool "USB Device High Speed (USBHS)"
 	default n
 	depends on SAMV7_HAVE_USBHS
+	select USBDEV
 
 config SAMV7_USBHOSTFS
 	bool "USB Host Full Speed (USBFS)"
 	default n
 	depends on SAMV7_HAVE_USBFS
+	select USBHOST
 
 config SAMV7_USBHOSTHS
 	bool "USB Host High Speed (USBHS)"
 	default n
 	depends on SAMV7_HAVE_USBHS
+	select USBHOST
 
 config SAMV7_USART0
 	bool "USART 0"
@@ -1236,3 +1240,37 @@ config SAMV7_EMAC_REGDEBUG
 		Enable very low-level register access debug.  Depends on DEBUG.
 
 endmenu # EMAC0 device driver options
+
+menu "USB High Speed Device Controller driver (DCD) options"
+	depends on SAMV7_USBDEVHS
+
+config SAMV7_USBHS_SCATTERGATHER
+	bool
+	default n
+	depends on EXPERIMENTAL
+	---help---
+		Scatter gather DMA is not yet supported
+
+config SAMV7_USBHS_NDTDS
+	int "Number of USBHS DMA transfer descriptors"
+	default 8
+	---help---
+		DMA transfer descriptors are allocated in a pool at boot time.  This
+		setting provides the number of DMA transfer descriptors to be
+		allocated.
+
+config SAMV7_USBHS_PREALLOCATE
+	bool "Pre-allocate DMA transfer descriptors"
+	default y
+	---help---
+		If this option is selected then DMA transfer descriptors will be
+		pre-allocated in .bss.  Otherwise, the descriptors will be allocated
+		at start-up time with kmm_malloc().  This might be important if a larger
+		memory pool is available after startup.
+
+config SAMV7_USBHS_REGDEBUG
+	bool "Enable low-level USBHS register debug"
+	default n
+	depends on DEBUG
+
+endmenu # USB High Speed Device Controller driver (DCD) options

arch/arm/src/samv7/Make.defs

@@ -147,3 +147,7 @@ endif
 ifeq ($(CONFIG_SAMV7_EMAC),y)
 CHIP_CSRCS += sam_emac.c sam_ethernet.c
 endif
+
+ifeq ($(CONFIG_SAMV7_USBDEVHS),y)
+#CHIP_CSRCS += sam_usbdevhs.c
+endif

arch/arm/src/samv7/chip/sam_pmc.h

@@ -209,7 +209,7 @@
 #define PMC_CKGR_UCKR_UPLLCOUNT_SHIFT  (20)      /* Bits 20-23: UTMI PLL Start-up Time */
 #define PMC_CKGR_UCKR_UPLLCOUNT_MASK   (15 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT)
 #  define PMC_CKGR_UCKR_UPLLCOUNT(n)   ((uint32_t)(n) << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT)
-
+#  define PMC_CKGR_UCKR_UPLLCOUNT_MAX  (15 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT)
 
 /* PMC Clock Generator Main Oscillator Register */
 

arch/arm/src/samv7/sam_clockconfig.c

@@ -72,7 +72,6 @@
                              BOARD_PMC_MCKR_MDIV | BOARD_PMC_MCKR_UPLLDIV2)
 #define BOARD_PMC_MCKR      (BOARD_PMC_MCKR_CSS | BOARD_PMC_MCKR_PRES | \
                              BOARD_PMC_MCKR_MDIV | BOARD_PMC_MCKR_UPLLDIV2)
-#define BOARD_CKGR_UCKR     (BOARD_CKGR_UCKR_UPLLCOUNT | PMC_CKGR_UCKR_UPLLEN)
 
 /****************************************************************************
  * Public Data
@@ -225,11 +224,22 @@ static inline void sam_pmcsetup(void)
   sam_pmcwait(PMC_INT_LOCKA);
 
 #ifdef CONFIG_USBDEV
-  /* Setup UTMI for USB and wait for LOCKU */
+  /* UTMI parallel mode, High/Full/Low Speed */
+  /* UUSBCLK is not used in this configuration (High Speed) */
 
-  regval = getreg32(SAM_PMC_CKGR_UCKR);
-  regval |= BOARD_CKGR_UCKR;
+  putreg32(PMC_USBCLK, SAM_PMC_SCDR);
+
+  /* Select the UTMI PLL as the USB clock input with divider = 1. */
+
+  putreg32(PMC_USB_USBS_UPLL, SAM_PMC_USB);
+
+  /* Enable the UTMI PLL with the maximum startup time */
+
+  regval = PMC_CKGR_UCKR_UPLLEN | PMC_CKGR_UCKR_UPLLCOUNT_MAX;
   putreg32(regval, SAM_PMC_CKGR_UCKR);
+
+  /* Wait for LOCKU */
+
   sam_pmcwait(PMC_INT_LOCKU);
 #endif