From b3792fcd865f009f0c80ac3f8a377c2bacef15ba Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 10 Feb 2014 18:08:49 -0600 Subject: [PATCH] Many changes to reduce complaints from CppCheck. Several latent bugs fixes, but probably some new typos introduced --- arch/arm/src/c5471/c5471_irq.c | 2 +- arch/arm/src/c5471/c5471_watchdog.c | 2 +- arch/arm/src/common/up_allocateheap.c | 4 - arch/arm/src/dm320/dm320_framebuffer.c | 6 +- arch/arm/src/dm320/dm320_usbdev.c | 2 +- arch/arm/src/imx/imx_serial.c | 2 + arch/arm/src/imx/imx_spi.c | 4 +- arch/arm/src/kl/kl_serial.c | 2 +- arch/arm/src/lm/lm_start.c | 2 + arch/arm/src/lpc31xx/lpc31_i2c.c | 568 +++++++++++++------------ arch/arm/src/sam34/sam4l_gpio.c | 8 +- arch/arm/src/stm32/stm32_dumpgpio.c | 2 - arch/arm/src/str71x/str71x_serial.c | 2 + arch/avr/src/avr/up_checkstack.c | 7 +- arch/hc/src/m9s12/m9s12_ethernet.c | 2 +- arch/sim/src/up_touchscreen.c | 2 +- arch/z16/src/z16f/z16f_serial.c | 4 +- arch/z80/src/ez80/ez80_i2c.c | 1 - arch/z80/src/ez80/ez80_spi.c | 5 +- arch/z80/src/z180/z180_mmu.c | 1 - arch/z80/src/z8/z8_serial.c | 7 +- 21 files changed, 335 insertions(+), 300 deletions(-) diff --git a/arch/arm/src/c5471/c5471_irq.c b/arch/arm/src/c5471/c5471_irq.c index 49930f60fc..fc7f83e082 100644 --- a/arch/arm/src/c5471/c5471_irq.c +++ b/arch/arm/src/c5471/c5471_irq.c @@ -228,7 +228,7 @@ void up_enable_irq(int irq) void up_maskack_irq(int irq) { - uint32_t reg = getreg32(INT_CTRL_REG); + uint32_t reg; /* Mask the interrupt */ diff --git a/arch/arm/src/c5471/c5471_watchdog.c b/arch/arm/src/c5471/c5471_watchdog.c index f9cf52244c..489921292d 100644 --- a/arch/arm/src/c5471/c5471_watchdog.c +++ b/arch/arm/src/c5471/c5471_watchdog.c @@ -261,7 +261,7 @@ static ssize_t wdt_read(struct file *filep, char *buffer, size_t buflen) dbg("buflen=%d\n", buflen); if (buflen >= 18) { - sprintf(buffer, "#08x %08x\n", c5471_wdt_cntl, c5471_wdt_count); + sprintf(buffer, "%08x %08x\n", c5471_wdt_cntl, c5471_wdt_count); return 18; } return 0; diff --git a/arch/arm/src/common/up_allocateheap.c b/arch/arm/src/common/up_allocateheap.c index 9435a55b2a..a5c1a068c6 100644 --- a/arch/arm/src/common/up_allocateheap.c +++ b/arch/arm/src/common/up_allocateheap.c @@ -112,7 +112,6 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; size_t usize = CONFIG_RAM_END - ubase; - int log2; DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END); @@ -151,9 +150,6 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) */ uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; - size_t usize = CONFIG_RAM_END - ubase; - int log2; - DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END); /* Return the kernel heap settings (i.e., the part of the heap region diff --git a/arch/arm/src/dm320/dm320_framebuffer.c b/arch/arm/src/dm320/dm320_framebuffer.c index 0b118e4df4..1abc028020 100644 --- a/arch/arm/src/dm320/dm320_framebuffer.c +++ b/arch/arm/src/dm320/dm320_framebuffer.c @@ -1254,7 +1254,7 @@ static int dm320_getcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_cursora attrib->size.w = getreg16(DM320_OSD_CURXL); attrib->size.h = getreg16(DM320_OSD_CURYL); #endif - irqrestore(); + irqrestore(flags); attrib->mxsize.w = MAX_XRES; attrib->mxsize.h = MAX_YRES; @@ -1325,10 +1325,8 @@ static int dm320_setcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_setcurs settings->size.h = MAX_YRES; } - flags = irqsave(); putreg16(settings->size.w, DM320_OSD_CURXL); putreg16(settings->size.h, DM320_OSD_CURYL); - restore_flags(flags); } #endif @@ -1342,7 +1340,7 @@ static int dm320_setcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_setcurs regval &= ~1; } putreg16(regval, DM320_OSD_RECTCUR); - restore_flags(flags); + irqrestore(flags); gvdbg("DM320_OSD_CURXP: %04x\n", getreg16(DM320_OSD_CURXP)); gvdbg("DM320_OSD_CURYP: %04x\n", getreg16(DM320_OSD_CURYP)); diff --git a/arch/arm/src/dm320/dm320_usbdev.c b/arch/arm/src/dm320/dm320_usbdev.c index b30aba72c5..97804b4926 100644 --- a/arch/arm/src/dm320/dm320_usbdev.c +++ b/arch/arm/src/dm320/dm320_usbdev.c @@ -1761,7 +1761,7 @@ static inline void dm320_epinitialize(struct dm320_usbdev_s *priv) /* FIFO address, max packet size, dual/single buffered */ - dm320_putreg8(addrhi, DM320_USB_TXFIFO1); + dm320_putreg8(addrlo, DM320_USB_TXFIFO1); dm320_putreg8(addrhi|g_epinfo[i].fifo, DM320_USB_TXFIFO2); /* TX endpoint max packet size */ diff --git a/arch/arm/src/imx/imx_serial.c b/arch/arm/src/imx/imx_serial.c index d7ac1a7325..08f57eeda0 100644 --- a/arch/arm/src/imx/imx_serial.c +++ b/arch/arm/src/imx/imx_serial.c @@ -879,8 +879,10 @@ static int up_interrupt(int irq, void *context) static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { +#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; +#endif int ret = OK; switch (cmd) diff --git a/arch/arm/src/imx/imx_spi.c b/arch/arm/src/imx/imx_spi.c index 0243b67dfe..83a3897a12 100644 --- a/arch/arm/src/imx/imx_spi.c +++ b/arch/arm/src/imx/imx_spi.c @@ -500,10 +500,10 @@ static int spi_transfer(struct imx_spidev_s *priv, const void *txbuffer, { #ifndef CONFIG_SPI_POLLWAIT irqstate_t flags; -#endif uint32_t regval; - int ntxd; int ret; +#endif + int ntxd; /* Set up to perform the transfer */ diff --git a/arch/arm/src/kl/kl_serial.c b/arch/arm/src/kl/kl_serial.c index faf9a7106c..2622e0db06 100644 --- a/arch/arm/src/kl/kl_serial.c +++ b/arch/arm/src/kl/kl_serial.c @@ -709,7 +709,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) } else { - priv->ie |= UART_C2_RIE; + priv->ie &= ~UART_C2_RIE; up_setuartint(priv); } diff --git a/arch/arm/src/lm/lm_start.c b/arch/arm/src/lm/lm_start.c index 96cb798223..184170dbf7 100644 --- a/arch/arm/src/lm/lm_start.c +++ b/arch/arm/src/lm/lm_start.c @@ -100,7 +100,9 @@ extern void _vectors(void); void __start(void) { +#ifdef CONFIG_BOOT_RUNFROMFLASH const uint32_t *src; +#endif uint32_t *dest; /* Configure the uart so that we can get debug output as soon as possible */ diff --git a/arch/arm/src/lpc31xx/lpc31_i2c.c b/arch/arm/src/lpc31xx/lpc31_i2c.c index 3d65c302d5..73b9ab720a 100644 --- a/arch/arm/src/lpc31xx/lpc31_i2c.c +++ b/arch/arm/src/lpc31xx/lpc31_i2c.c @@ -72,49 +72,50 @@ * Pre-processor Definitions ****************************************************************************/ -#define I2C_TIMEOUT ((20 * CLK_TCK) / 1000) /* 20 mS */ +#define I2C_TIMEOUT ((20 * CLK_TCK) / 1000) /* 20 mS */ /**************************************************************************** * Private Data ****************************************************************************/ struct lpc31_i2cdev_s { - struct i2c_dev_s dev; /* Generic I2C device */ - struct i2c_msg_s msg; /* a single message for legacy read/write */ - unsigned int base; /* Base address of registers */ - uint16_t clkid; /* Clock for this device */ - uint16_t rstid; /* Reset for this device */ - uint16_t irqid; /* IRQ for this device */ + struct i2c_dev_s dev; /* Generic I2C device */ + struct i2c_msg_s msg; /* a single message for legacy read/write */ + unsigned int base; /* Base address of registers */ + uint16_t clkid; /* Clock for this device */ + uint16_t rstid; /* Reset for this device */ + uint16_t irqid; /* IRQ for this device */ - sem_t mutex; /* Only one thread can access at a time */ + sem_t mutex; /* Only one thread can access at a time */ - sem_t wait; /* Place to wait for state machine completion */ - volatile uint8_t state; /* State of state machine */ - WDOG_ID timeout; /* watchdog to timeout when bus hung */ + sem_t wait; /* Place to wait for state machine completion */ + volatile uint8_t state; /* State of state machine */ + WDOG_ID timeout; /* watchdog to timeout when bus hung */ - struct i2c_msg_s *msgs; /* remaining transfers - first one is in progress */ - unsigned int nmsg; /* number of transfer remaining */ + struct i2c_msg_s *msgs; /* remaining transfers - first one is in progress */ + unsigned int nmsg; /* number of transfer remaining */ - uint16_t header[3]; /* I2C address header */ - uint16_t hdrcnt; /* number of bytes of header */ - uint16_t wrcnt; /* number of bytes sent to tx fifo */ - uint16_t rdcnt; /* number of bytes read from rx fifo */ + uint16_t header[3]; /* I2C address header */ + uint16_t hdrcnt; /* number of bytes of header */ + uint16_t wrcnt; /* number of bytes sent to tx fifo */ + uint16_t rdcnt; /* number of bytes read from rx fifo */ }; -#define I2C_STATE_DONE 0 -#define I2C_STATE_START 1 -#define I2C_STATE_HEADER 2 -#define I2C_STATE_TRANSFER 3 +#define I2C_STATE_DONE 0 +#define I2C_STATE_START 1 +#define I2C_STATE_HEADER 2 +#define I2C_STATE_TRANSFER 3 static struct lpc31_i2cdev_s i2cdevices[2]; /**************************************************************************** * Private Functions ****************************************************************************/ -static int i2c_interrupt (int irq, FAR void *context); -static void i2c_progress (struct lpc31_i2cdev_s *priv); -static void i2c_timeout (int argc, uint32_t arg, ...); -static void i2c_reset (struct lpc31_i2cdev_s *priv); + +static int i2c_interrupt(int irq, FAR void *context); +static void i2c_progress(struct lpc31_i2cdev_s *priv); +static void i2c_timeout(int argc, uint32_t arg, ...); +static void i2c_reset(struct lpc31_i2cdev_s *priv); /**************************************************************************** * Public Functions @@ -130,13 +131,14 @@ static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen); static int i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int count); -struct i2c_ops_s lpc31_i2c_ops = { - .setfrequency = i2c_setfrequency, - .setaddress = i2c_setaddress, - .write = i2c_write, - .read = i2c_read, +struct i2c_ops_s lpc31_i2c_ops = +{ + .setfrequency = i2c_setfrequency, + .setaddress = i2c_setaddress, + .write = i2c_write, + .read = i2c_read, #ifdef CONFIG_I2C_TRANSFER - .transfer = i2c_transfer + .transfer = i2c_transfer #endif }; @@ -151,41 +153,41 @@ struct i2c_ops_s lpc31_i2c_ops = { struct i2c_dev_s *up_i2cinitialize(int port) { struct lpc31_i2cdev_s *priv = &i2cdevices[port]; - + priv->base = (port == 0) ? LPC31_I2C0_VBASE : LPC31_I2C1_VBASE; priv->clkid = (port == 0) ? CLKID_I2C0PCLK : CLKID_I2C1PCLK; priv->rstid = (port == 0) ? RESETID_I2C0RST : RESETID_I2C1RST; priv->irqid = (port == 0) ? LPC31_IRQ_I2C0 : LPC31_IRQ_I2C1; - - sem_init (&priv->mutex, 0, 1); - sem_init (&priv->wait, 0, 0); - + + sem_init(&priv->mutex, 0, 1); + sem_init(&priv->wait, 0, 0); + /* Enable I2C system clocks */ - - lpc31_enableclock (priv->clkid); - + + lpc31_enableclock(priv->clkid); + /* Reset I2C blocks */ - - lpc31_softreset (priv->rstid); - + + lpc31_softreset(priv->rstid); + /* Soft reset the device */ - - i2c_reset (priv); - + + i2c_reset(priv); + /* Allocate a watchdog timer */ priv->timeout = wd_create(); DEBUGASSERT(priv->timeout != 0); - + /* Attach Interrupt Handler */ - irq_attach (priv->irqid, i2c_interrupt); - + irq_attach(priv->irqid, i2c_interrupt); + /* Enable Interrupt Handler */ up_enable_irq(priv->irqid); /* Install our operations */ priv->dev.ops = &lpc31_i2c_ops; - + return &priv->dev; } @@ -197,23 +199,23 @@ struct i2c_dev_s *up_i2cinitialize(int port) * *******************************************************************************/ -void up_i2cuninitalize (struct lpc31_i2cdev_s *priv) +void up_i2cuninitalize(struct lpc31_i2cdev_s *priv) { /* Disable All Interrupts, soft reset the device */ - i2c_reset (priv); - + i2c_reset(priv); + /* Detach Interrupt Handler */ - - irq_detach (priv->irqid); - + + irq_detach(priv->irqid); + /* Reset I2C blocks */ - - lpc31_softreset (priv->rstid); - + + lpc31_softreset(priv->rstid); + /* Disable I2C system clocks */ - - lpc31_disableclock (priv->clkid); + + lpc31_disableclock(priv->clkid); } /******************************************************************************* @@ -228,22 +230,25 @@ static uint32_t i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency) { struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) dev; - uint32_t freq = lpc31_clkfreq (priv->clkid, DOMAINID_AHB0APB1); + uint32_t freq = lpc31_clkfreq(priv->clkid, DOMAINID_AHB0APB1); if (freq > 100000) - { + { /* asymetric per 400Khz I2C spec */ - putreg32 (((47 * freq) / (83 + 47)) / frequency, priv->base + LPC31_I2C_CLKHI_OFFSET); - putreg32 (((83 * freq) / (83 + 47)) / frequency, priv->base + LPC31_I2C_CLKLO_OFFSET); - } + + putreg32(((47 * freq) / (83 + 47)) / frequency, priv->base + LPC31_I2C_CLKHI_OFFSET); + putreg32(((83 * freq) / (83 + 47)) / frequency, priv->base + LPC31_I2C_CLKLO_OFFSET); + } else - { + { /* 50/50 mark space ratio */ - putreg32 (((50 * freq) / 100) / frequency, priv->base + LPC31_I2C_CLKLO_OFFSET); - putreg32 (((50 * freq) / 100) / frequency, priv->base + LPC31_I2C_CLKHI_OFFSET); - } + + putreg32(((50 * freq) / 100) / frequency, priv->base + LPC31_I2C_CLKLO_OFFSET); + putreg32(((50 * freq) / 100) / frequency, priv->base + LPC31_I2C_CLKHI_OFFSET); + } /* FIXME: This function should return the actual selected frequency */ + return frequency; } @@ -254,6 +259,7 @@ static uint32_t i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency) * Set the I2C slave address for a subsequent read/write * *******************************************************************************/ + static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits) { struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) dev; @@ -275,20 +281,21 @@ static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits) * frequency and slave address. * *******************************************************************************/ + static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int buflen) { - struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) dev; - int ret; + struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) dev; + int ret; - DEBUGASSERT (dev != NULL); - - priv->msg.flags &= ~I2C_M_READ; - priv->msg.buffer = (uint8_t*)buffer; - priv->msg.length = buflen; + DEBUGASSERT(dev != NULL); - ret = i2c_transfer (dev, &priv->msg, 1); + priv->msg.flags &= ~I2C_M_READ; + priv->msg.buffer = (uint8_t*)buffer; + priv->msg.length = buflen; - return ret == 1 ? OK : -ETIMEDOUT; + ret = i2c_transfer(dev, &priv->msg, 1); + + return ret == 1 ? OK : -ETIMEDOUT; } /******************************************************************************* @@ -299,20 +306,21 @@ static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int bufle * frequency and slave address. * *******************************************************************************/ + static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen) { - struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) dev; - int ret; + struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) dev; + int ret; - DEBUGASSERT (dev != NULL); - - priv->msg.flags |= I2C_M_READ; - priv->msg.buffer = buffer; - priv->msg.length = buflen; + DEBUGASSERT(dev != NULL); - ret = i2c_transfer (dev, &priv->msg, 1); + priv->msg.flags |= I2C_M_READ; + priv->msg.buffer = buffer; + priv->msg.length = buflen; - return ret == 1 ? OK : -ETIMEDOUT; + ret = i2c_transfer(dev, &priv->msg, 1); + + return ret == 1 ? OK : -ETIMEDOUT; } /******************************************************************************* @@ -323,37 +331,39 @@ static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen) * *******************************************************************************/ -static int i2c_transfer (FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int count) +static int i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int count) { struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) dev; irqstate_t flags; int ret; - - sem_wait (&priv->mutex); + + sem_wait(&priv->mutex); flags = irqsave(); - + priv->state = I2C_STATE_START; priv->msgs = msgs; priv->nmsg = count; - - i2c_progress (priv); + + i2c_progress(priv); /* start a watchdog to timeout the transfer if - * the bus is locked up... */ - wd_start (priv->timeout, I2C_TIMEOUT, i2c_timeout, 1, (uint32_t)priv); - + * the bus is locked up... + */ + + wd_start(priv->timeout, I2C_TIMEOUT, i2c_timeout, 1, (uint32_t)priv); + while (priv->state != I2C_STATE_DONE) { - sem_wait (&priv->wait); + sem_wait(&priv->wait); } - wd_cancel (priv->timeout); - + wd_cancel(priv->timeout); + ret = count - priv->nmsg; - - irqrestore (flags); - sem_post (&priv->mutex); - + + irqrestore(flags); + sem_post(&priv->mutex); + return ret; } @@ -365,16 +375,16 @@ static int i2c_transfer (FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, * *******************************************************************************/ -static int i2c_interrupt (int irq, FAR void *context) +static int i2c_interrupt(int irq, FAR void *context) { if (irq == LPC31_IRQ_I2C0) { - i2c_progress (&i2cdevices[0]); + i2c_progress(&i2cdevices[0]); } if (irq == LPC31_IRQ_I2C1) { - i2c_progress (&i2cdevices[1]); + i2c_progress(&i2cdevices[1]); } return OK; @@ -388,170 +398,194 @@ static int i2c_interrupt (int irq, FAR void *context) * *******************************************************************************/ -static void i2c_progress (struct lpc31_i2cdev_s *priv) +static void i2c_progress(struct lpc31_i2cdev_s *priv) { struct i2c_msg_s *msg; uint32_t stat, ctrl; - stat = getreg32 (priv->base + LPC31_I2C_STAT_OFFSET); + stat = getreg32(priv->base + LPC31_I2C_STAT_OFFSET); /* Were there arbitration problems? */ + if ((stat & I2C_STAT_AFI) != 0) { /* Perform a soft reset */ - i2c_reset (priv); - + + i2c_reset(priv); + /* FIXME: automatic retry? */ - + priv->state = I2C_STATE_DONE; - sem_post (&priv->wait); + sem_post(&priv->wait); return; } - + while (priv->nmsg > 0) { ctrl = I2C_CTRL_NAIE | I2C_CTRL_AFIE | I2C_CTRL_TDIE; msg = priv->msgs; - + switch (priv->state) { - case I2C_STATE_START: - if ((msg->flags & I2C_M_TEN) != 0) - { - priv->header[0] = I2C_TX_START | 0xF0 | ((msg->addr & 0x300) >> 7); - priv->header[1] = msg->addr & 0xFF; - priv->hdrcnt = 2; - if (msg->flags & I2C_M_READ) - { - priv->header[2] = priv->header[0] | 1; - priv->hdrcnt++; - } - } - else - { - priv->header[0] = I2C_TX_START | (msg->addr << 1) | (msg->flags & I2C_M_READ); - priv->hdrcnt = 1; - } + case I2C_STATE_START: + if ((msg->flags & I2C_M_TEN) != 0) + { + priv->header[0] = I2C_TX_START | 0xF0 | ((msg->addr & 0x300) >> 7); + priv->header[1] = msg->addr & 0xFF; + priv->hdrcnt = 2; + if (msg->flags & I2C_M_READ) + { + priv->header[2] = priv->header[0] | 1; + priv->hdrcnt++; + } + } + else + { + priv->header[0] = I2C_TX_START | (msg->addr << 1) | (msg->flags & I2C_M_READ); + priv->hdrcnt = 1; + } - putreg32 (ctrl, priv->base + LPC31_I2C_CTRL_OFFSET); + putreg32(ctrl, priv->base + LPC31_I2C_CTRL_OFFSET); - priv->state = I2C_STATE_HEADER; - priv->wrcnt = 0; - /* DROP THROUGH */ - - case I2C_STATE_HEADER: - while ((priv->wrcnt != priv->hdrcnt) && (stat & I2C_STAT_TFF) == 0) - { - putreg32(priv->header[priv->wrcnt], priv->base + LPC31_I2C_TX_OFFSET); - priv->wrcnt++; - - stat = getreg32 (priv->base + LPC31_I2C_STAT_OFFSET); - } - - if (priv->wrcnt < priv->hdrcnt) - { - /* Enable Tx FIFO Not Full Interrupt */ - putreg32 (ctrl | I2C_CTRL_TFFIE, priv->base + LPC31_I2C_CTRL_OFFSET); - goto out; - } - - priv->state = I2C_STATE_TRANSFER; - priv->wrcnt = 0; - priv->rdcnt = 0; - /* DROP THROUGH */ - - case I2C_STATE_TRANSFER: - if (msg->flags & I2C_M_READ) - { - while ((priv->rdcnt != msg->length) && (stat & I2C_STAT_RFE) == 0) - { - msg->buffer[priv->rdcnt] = getreg32 (priv->base + LPC31_I2C_RX_OFFSET); - priv->rdcnt++; - - stat = getreg32 (priv->base + LPC31_I2C_STAT_OFFSET); - } - - if (priv->rdcnt < msg->length) - { - /* Not all data received, fill the Tx FIFO with more dummies */ - while ((priv->wrcnt != msg->length) && (stat & I2C_STAT_TFF) == 0) - { - if ((priv->wrcnt + 1) == msg->length && priv->nmsg == 1) - putreg32 (I2C_TX_STOP, priv->base + LPC31_I2C_TX_OFFSET); - else - putreg32 (0, priv->base + LPC31_I2C_TX_OFFSET); - priv->wrcnt++; - - stat = getreg32 (priv->base + LPC31_I2C_STAT_OFFSET); - } - - if (priv->wrcnt < msg->length) - { - /* Enable Tx FIFO not full and Rx Fifo Avail Interrupts */ - putreg32 (ctrl | I2C_CTRL_TFFIE | I2C_CTRL_RFDAIE, priv->base + LPC31_I2C_CTRL_OFFSET); - } - else - { - /* Enable Rx Fifo Avail Interrupts */ - putreg32 (ctrl | I2C_CTRL_RFDAIE, priv->base + LPC31_I2C_CTRL_OFFSET); - } - goto out; - } - } - else /* WRITE */ - { - while ((priv->wrcnt != msg->length) && (stat & I2C_STAT_TFF) == 0) - { - if ((priv->wrcnt + 1) == msg->length && priv->nmsg == 1) - putreg32 (I2C_TX_STOP | msg->buffer[priv->wrcnt], priv->base + LPC31_I2C_TX_OFFSET); - else - putreg32 (msg->buffer[priv->wrcnt], priv->base + LPC31_I2C_TX_OFFSET); - - priv->wrcnt++; - - stat = getreg32 (priv->base + LPC31_I2C_STAT_OFFSET); - } - - if (priv->wrcnt < msg->length) - { - /* Enable Tx Fifo not full Interrupt */ - putreg32 (ctrl | I2C_CTRL_TFFIE, priv->base + LPC31_I2C_CTRL_OFFSET); - goto out; - } - } - - /* Transfer completed, move onto the next one */ - priv->state = I2C_STATE_START; - - if (--priv->nmsg == 0) - { - /* Final transfer, wait for Transmit Done Interrupt */ - putreg32 (ctrl, priv->base + LPC31_I2C_CTRL_OFFSET); - goto out; - } - priv->msgs++; - break; - } - } + priv->state = I2C_STATE_HEADER; + priv->wrcnt = 0; + /* DROP THROUGH */ -out: + case I2C_STATE_HEADER: + while ((priv->wrcnt != priv->hdrcnt) && (stat & I2C_STAT_TFF) == 0) + { + putreg32(priv->header[priv->wrcnt], priv->base + LPC31_I2C_TX_OFFSET); + priv->wrcnt++; + + stat = getreg32(priv->base + LPC31_I2C_STAT_OFFSET); + } + + if (priv->wrcnt < priv->hdrcnt) + { + /* Enable Tx FIFO Not Full Interrupt */ + + putreg32(ctrl | I2C_CTRL_TFFIE, priv->base + LPC31_I2C_CTRL_OFFSET); + goto out; + } + + priv->state = I2C_STATE_TRANSFER; + priv->wrcnt = 0; + priv->rdcnt = 0; + /* DROP THROUGH */ + + case I2C_STATE_TRANSFER: + if (msg->flags & I2C_M_READ) + { + while ((priv->rdcnt != msg->length) && (stat & I2C_STAT_RFE) == 0) + { + msg->buffer[priv->rdcnt] = getreg32 (priv->base + LPC31_I2C_RX_OFFSET); + priv->rdcnt++; + + stat = getreg32(priv->base + LPC31_I2C_STAT_OFFSET); + } + + if (priv->rdcnt < msg->length) + { + /* Not all data received, fill the Tx FIFO with more dummies */ + + while ((priv->wrcnt != msg->length) && (stat & I2C_STAT_TFF) == 0) + { + if ((priv->wrcnt + 1) == msg->length && priv->nmsg == 1) + { + putreg32(I2C_TX_STOP, priv->base + LPC31_I2C_TX_OFFSET); + } + else + { + putreg32(0, priv->base + LPC31_I2C_TX_OFFSET); + } + + priv->wrcnt++; + + stat = getreg32(priv->base + LPC31_I2C_STAT_OFFSET); + } + + if (priv->wrcnt < msg->length) + { + /* Enable Tx FIFO not full and Rx Fifo Avail Interrupts */ + + putreg32(ctrl | I2C_CTRL_TFFIE | I2C_CTRL_RFDAIE, priv->base + LPC31_I2C_CTRL_OFFSET); + } + else + { + /* Enable Rx Fifo Avail Interrupts */ + + putreg32(ctrl | I2C_CTRL_RFDAIE, priv->base + LPC31_I2C_CTRL_OFFSET); + } + goto out; + } + } + else /* WRITE */ + { + while ((priv->wrcnt != msg->length) && (stat & I2C_STAT_TFF) == 0) + { + if ((priv->wrcnt + 1) == msg->length && priv->nmsg == 1) + { + putreg32(I2C_TX_STOP | msg->buffer[priv->wrcnt], priv->base + LPC31_I2C_TX_OFFSET); + } + else + { + putreg32(msg->buffer[priv->wrcnt], priv->base + LPC31_I2C_TX_OFFSET); + } + + priv->wrcnt++; + + stat = getreg32(priv->base + LPC31_I2C_STAT_OFFSET); + } + + if (priv->wrcnt < msg->length) + { + /* Enable Tx Fifo not full Interrupt */ + + putreg32(ctrl | I2C_CTRL_TFFIE, priv->base + LPC31_I2C_CTRL_OFFSET); + goto out; + } + } + + /* Transfer completed, move onto the next one */ + + priv->state = I2C_STATE_START; + + if (--priv->nmsg == 0) + { + /* Final transfer, wait for Transmit Done Interrupt */ + + putreg32(ctrl, priv->base + LPC31_I2C_CTRL_OFFSET); + goto out; + } + + priv->msgs++; + break; + } + } + +out: if (stat & I2C_STAT_TDI) { - putreg32 (I2C_STAT_TDI, priv->base + LPC31_I2C_STAT_OFFSET); + putreg32(I2C_STAT_TDI, priv->base + LPC31_I2C_STAT_OFFSET); /* You'd expect the NAI bit to be set when no acknowledge was - * received - but it gets cleared whenever a write it done to + * received - but it gets cleared whenever a write it done to * the TXFIFO - so we've gone and cleared it while priming the - * rest of the transfer! */ - if ((stat = getreg32 (priv->base + LPC31_I2C_TXFL_OFFSET)) != 0) - { - if (priv->nmsg == 0) - priv->nmsg++; - i2c_reset (priv); - } - + * rest of the transfer! + */ + + if ((stat = getreg32(priv->base + LPC31_I2C_TXFL_OFFSET)) != 0) + { + if (priv->nmsg == 0) + { + priv->nmsg++; + } + + i2c_reset(priv); + } + priv->state = I2C_STATE_DONE; - sem_post (&priv->wait); + sem_post(&priv->wait); } } @@ -563,32 +597,37 @@ out: * *******************************************************************************/ -static void i2c_timeout (int argc, uint32_t arg, ...) +static void i2c_timeout(int argc, uint32_t arg, ...) { - struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) arg; + struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) arg; - irqstate_t flags = irqsave(); - - if (priv->state != I2C_STATE_DONE) + irqstate_t flags = irqsave(); + + if (priv->state != I2C_STATE_DONE) { - /* If there's data remaining in the TXFIFO, then ensure at least - * one transfer has failed to complete.. */ + /* If there's data remaining in the TXFIFO, then ensure at least + * one transfer has failed to complete. + */ - if (getreg32 (priv->base + LPC31_I2C_TXFL_OFFSET) != 0) - { - if (priv->nmsg == 0) - priv->nmsg++; - } + if (getreg32(priv->base + LPC31_I2C_TXFL_OFFSET) != 0) + { + if (priv->nmsg == 0) + { + priv->nmsg++; + } + } - /* Soft reset the USB controller */ - i2c_reset (priv); + /* Soft reset the USB controller */ - /* Mark the transfer as finished */ - priv->state = I2C_STATE_DONE; - sem_post (&priv->wait); + i2c_reset(priv); + + /* Mark the transfer as finished */ + + priv->state = I2C_STATE_DONE; + sem_post(&priv->wait); } - - irqrestore (flags); + + irqrestore(flags); } /******************************************************************************* @@ -598,11 +637,12 @@ static void i2c_timeout (int argc, uint32_t arg, ...) * Perform a soft reset of the I2C controller * *******************************************************************************/ -static void i2c_reset (struct lpc31_i2cdev_s *priv) +static void i2c_reset(struct lpc31_i2cdev_s *priv) { - putreg32 (I2C_CTRL_RESET, priv->base + LPC31_I2C_CTRL_OFFSET); + putreg32(I2C_CTRL_RESET, priv->base + LPC31_I2C_CTRL_OFFSET); /* Wait for Reset to complete */ - while ((getreg32 (priv->base + LPC31_I2C_CTRL_OFFSET) & I2C_CTRL_RESET) != 0) + + while ((getreg32(priv->base + LPC31_I2C_CTRL_OFFSET) & I2C_CTRL_RESET) != 0) ; } diff --git a/arch/arm/src/sam34/sam4l_gpio.c b/arch/arm/src/sam34/sam4l_gpio.c index 977e91e608..bb312db0bc 100644 --- a/arch/arm/src/sam34/sam4l_gpio.c +++ b/arch/arm/src/sam34/sam4l_gpio.c @@ -214,7 +214,7 @@ static inline int sam_configinterrupt(uintptr_t base, uint32_t pin, * 11 Reserved */ - gpio_pinset_t edges = cfgset & GPIO_INT_MASK; + gpio_pinset_t edges = (cfgset & GPIO_INT_MASK); if (edges == GPIO_INT_RISING) { @@ -398,16 +398,16 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin, * 11 Reserved */ - edges = cfgset & GPIO_INT_MASK; + edges = (cfgset & GPIO_INT_MASK); if (edges == GPIO_INT_RISING) { - /* Rising only.. disable interrrupts on the falling edge */ + /* Rising only.. disable interrupts on the falling edge */ putreg32(pin, base + SAM_GPIO_IMR0S_OFFSET); } else if (edges == GPIO_INT_FALLING) { - /* Falling only.. disable interrrupts on the rising edge */ + /* Falling only.. disable interrupts on the rising edge */ putreg32(pin, base + SAM_GPIO_IMR1S_OFFSET); } diff --git a/arch/arm/src/stm32/stm32_dumpgpio.c b/arch/arm/src/stm32/stm32_dumpgpio.c index 2e06a3eebf..06976956df 100644 --- a/arch/arm/src/stm32/stm32_dumpgpio.c +++ b/arch/arm/src/stm32/stm32_dumpgpio.c @@ -109,12 +109,10 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) irqstate_t flags; uint32_t base; unsigned int port; - unsigned int pin; /* Get the base address associated with the GPIO port */ port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; base = g_gpiobase[port]; /* The following requires exclusive access to the GPIO registers */ diff --git a/arch/arm/src/str71x/str71x_serial.c b/arch/arm/src/str71x/str71x_serial.c index 2356898bb5..2f4e56ff02 100644 --- a/arch/arm/src/str71x/str71x_serial.c +++ b/arch/arm/src/str71x/str71x_serial.c @@ -753,8 +753,10 @@ static int up_interrupt(int irq, void *context) static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { +#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; +#endif int ret = OK; switch (cmd) diff --git a/arch/avr/src/avr/up_checkstack.c b/arch/avr/src/avr/up_checkstack.c index 6ff0db083a..07b1f9d141 100644 --- a/arch/avr/src/avr/up_checkstack.c +++ b/arch/avr/src/avr/up_checkstack.c @@ -82,7 +82,10 @@ size_t up_check_tcbstack(FAR struct tcb_s *tcb) { FAR uint8_t *ptr; size_t mark; - int i, j; +#if 0 + int i; + int j; +#endif /* The AVR uses a push-down stack: the stack grows toward lower addresses * in memory. We need to start at the lowest address in the stack memory @@ -121,8 +124,10 @@ size_t up_check_tcbstack(FAR struct tcb_s *tcb) { ch = 'X'; } + up_putc(ch); } + up_putc('\n'); } } diff --git a/arch/hc/src/m9s12/m9s12_ethernet.c b/arch/hc/src/m9s12/m9s12_ethernet.c index 75c6f8ad77..d380f7757a 100644 --- a/arch/hc/src/m9s12/m9s12_ethernet.c +++ b/arch/hc/src/m9s12/m9s12_ethernet.c @@ -291,7 +291,7 @@ static void emac_receive(FAR struct emac_driver_s *priv) } } } - while (); /* While there are more packets to be processed */ + while (true); /* While there are more packets to be processed */ } /**************************************************************************** diff --git a/arch/sim/src/up_touchscreen.c b/arch/sim/src/up_touchscreen.c index f0d7417601..c650137382 100644 --- a/arch/sim/src/up_touchscreen.c +++ b/arch/sim/src/up_touchscreen.c @@ -534,7 +534,7 @@ static int up_poll(FAR struct file *filep, FAR struct pollfd *fds, { FAR struct inode *inode; FAR struct up_dev_s *priv; - int ret = OK; + int ret; int i; ivdbg("setup: %d\n", (int)setup); diff --git a/arch/z16/src/z16f/z16f_serial.c b/arch/z16/src/z16f/z16f_serial.c index 0d4e4876d5..0b4468899f 100644 --- a/arch/z16/src/z16f/z16f_serial.c +++ b/arch/z16/src/z16f/z16f_serial.c @@ -302,8 +302,7 @@ static uint8_t z16f_disableuartirq(struct uart_dev_s *dev) static void z16f_restoreuartirq(struct uart_dev_s *dev, uint8_t state) { - struct z16f_uart_s *priv = (struct z16f_uart_s*)dev->priv; - irqstate_t flags = irqsave(); + irqstate_t flags = irqsave(); z16f_txint(dev, (state & STATE_TXENABLED) ? true : false); z16f_rxint(dev, (state & STATE_RXENABLED) ? true : false); @@ -400,7 +399,6 @@ static int z16f_setup(struct uart_dev_s *dev) static void z16f_shutdown(struct uart_dev_s *dev) { - struct z16f_uart_s *priv = (struct z16f_uart_s*)dev->priv; (void)z16f_disableuartirq(dev); } diff --git a/arch/z80/src/ez80/ez80_i2c.c b/arch/z80/src/ez80/ez80_i2c.c index 6668704dcd..83942a542e 100644 --- a/arch/z80/src/ez80/ez80_i2c.c +++ b/arch/z80/src/ez80/ez80_i2c.c @@ -393,7 +393,6 @@ static void i2c_stop(void) static int i2c_sendaddr(struct ez80_i2cdev_s *priv, uint8_t readbit) { uint8_t sr; - int ret = OK; /* Wait for the IFLG bit to transition to 1. At this point, we should * have status == 8 meaning that the start bit was sent successfully. diff --git a/arch/z80/src/ez80/ez80_spi.c b/arch/z80/src/ez80/ez80_spi.c index 1cbe873f07..475c946a58 100644 --- a/arch/z80/src/ez80/ez80_spi.c +++ b/arch/z80/src/ez80/ez80_spi.c @@ -284,7 +284,7 @@ static uint8_t spi_waitspif(void) * Name: spi_transfer * * Description: - * Send one byte on SPI, return th response + * Send one byte on SPI, return the response * * Input Parameters: * ch - the byte to send @@ -361,7 +361,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, FAR const uint8_t *ptr = (FAR const uint8_t*)buffer; uint8_t response; - /* Loop while thre are bytes remaining to be sent */ + /* Loop while there are bytes remaining to be sent */ while (buflen-- > 0) { @@ -392,7 +392,6 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t buflen) { FAR uint8_t *ptr = (FAR uint8_t*)buffer; - uint8_t response; /* Loop while thre are bytes remaining to be sent */ diff --git a/arch/z80/src/z180/z180_mmu.c b/arch/z80/src/z180/z180_mmu.c index 09fa65f210..d6ed1ebcf9 100644 --- a/arch/z80/src/z180/z180_mmu.c +++ b/arch/z80/src/z180/z180_mmu.c @@ -438,7 +438,6 @@ int up_addrenv_destroy(task_addrenv_t addrenv) int up_addrenv_assign(task_addrenv_t addrenv, FAR struct tcb_s *tcb) { FAR struct z180_cbr_s *cbr = (FAR struct z180_cbr_s *)addrenv; - int ret; /* Make sure that there is no address environment in place on this TCB */ diff --git a/arch/z80/src/z8/z8_serial.c b/arch/z80/src/z8/z8_serial.c index 553e3fb400..8e809988c8 100644 --- a/arch/z80/src/z8/z8_serial.c +++ b/arch/z80/src/z8/z8_serial.c @@ -284,8 +284,7 @@ static uint8_t z8_disableuartirq(FAR struct uart_dev_s *dev) static void z8_restoreuartirq(FAR struct uart_dev_s *dev, uint8_t state) { - struct z8_uart_s *priv = (struct z8_uart_s*)dev->priv; - irqstate_t flags = irqsave(); + irqstate_t flags = irqsave(); z8_txint(dev, (state & STATE_TXENABLED) ? true : false); z8_rxint(dev, (state & STATE_RXENABLED) ? true : false); @@ -322,8 +321,7 @@ static void z8_consoleput(uint8_t ch) void z8_uartconfigure(void) { - uint16_t brg; - uint8_t val; + uint8_t val; /* Configure GPIO Port A pins 4 & 5 for alternate function */ @@ -421,7 +419,6 @@ static int z8_setup(FAR struct uart_dev_s *dev) static void z8_shutdown(FAR struct uart_dev_s *dev) { - struct z8_uart_s *priv = (struct z8_uart_s*)dev->priv; (void)z8_disableuartirq(dev); }