PIC32: Fix timer 1 source, uart priority, add pre-fetch cache header file
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3636 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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176
arch/mips/src/pic32mx/pic32mx-che.h
Executable file
176
arch/mips/src/pic32mx/pic32mx-che.h
Executable file
@ -0,0 +1,176 @@
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/********************************************************************************************
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* arch/mips/src/pic32mx/pic32mx-che.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CHE_H
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#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CHE_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "pic32mx-memorymap.h"
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/********************************************************************************************
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* Pre-Processor Definitions
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********************************************************************************************/
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/* Register Offsets *************************************************************************/
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#define PIC32MX_CHE_CON_OFFSET 0x0000 /* Pre-fetch cache control register */
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#define PIC32MX_CHE_CONCLR_OFFSET 0x0004 /* Pre-fetch cache control clear register */
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#define PIC32MX_CHE_CONSET_OFFSET 0x0008 /* Pre-fetch cache control set register */
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#define PIC32MX_CHE_CONINV_OFFSET 0x000c /* Pre-fetch cache control invert register */
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#define PIC32MX_CHE_ACC_OFFSET 0x0010 /* Pre-fetch cache access register */
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#define PIC32MX_CHE_ACCCLR_OFFSET 0x0014 /* Pre-fetch cache access clear register */
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#define PIC32MX_CHE_ACCSET_OFFSET 0x0018 /* Pre-fetch cache access set register */
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#define PIC32MX_CHE_ACCINV_OFFSET 0x001c /* Pre-fetch cache access invert register */
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#define PIC32MX_CHE_TAG_OFFSET 0x0020 /* Pre-fetch cache tag register */
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#define PIC32MX_CHE_TAGCLR_OFFSET 0x0024 /* Pre-fetch cache tag clear register */
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#define PIC32MX_CHE_TAGSET_OFFSET 0x0028 /* Pre-fetch cache tag set register */
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#define PIC32MX_CHE_TAGINV_OFFSET 0x002c /* Pre-fetch cache tag invert register */
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#define PIC32MX_CHE_MSK_OFFSET 0x0030 /* Pre-fetch cache tag mask register */
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#define PIC32MX_CHE_MSKCLR_OFFSET 0x0034 /* Pre-fetch cache tag mask clear register */
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#define PIC32MX_CHE_MSKSET_OFFSET 0x0038 /* Pre-fetch cache tag mask set register */
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#define PIC32MX_CHE_MSKINV_OFFSET 0x003c /* Pre-fetch cache tag mask invert register */
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#define PIC32MX_CHE_W0_OFFSET 0x0040 /* Cache word 0 register */
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#define PIC32MX_CHE_W1_OFFSET 0x0050 /* Cache word 1 register */
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#define PIC32MX_CHE_W2_OFFSET 0x0060 /* Cache word 2 register */
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#define PIC32MX_CHE_W3_OFFSET 0x0070 /* Cache word 3 register */
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#define PIC32MX_CHE_LRU_OFFSET 0x0080 /* Cache LRU register */
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#define PIC32MX_CHE_HIT_OFFSET 0x0090 /* Cache hit statistics register */
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#define PIC32MX_CHE_MIS_OFFSET 0x00a0 /* Cache miss statistics register */
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#define PIC32MX_CHE_PFABT_OFFSET 0x00c0 /* Pre-fetch cache abort statistics register */
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/* Register Addresses ***********************************************************************/
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#define PIC32MX_CHE_CON (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CON_OFFSET)
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#define PIC32MX_CHE_CONCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CONCLR_OFFSET)
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#define PIC32MX_CHE_CONSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CONSET_OFFSET)
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#define PIC32MX_CHE_CONINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CONINV_OFFSET)
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#define PIC32MX_CHE_ACC (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACC_OFFSET)
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#define PIC32MX_CHE_ACCCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACCCLR_OFFSET)
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#define PIC32MX_CHE_ACCSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACCSET_OFFSET)
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#define PIC32MX_CHE_ACCINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACCINV_OFFSET)
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#define PIC32MX_CHE_TAG (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAG_OFFSET)
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#define PIC32MX_CHE_TAGCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAGCLR_OFFSET)
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#define PIC32MX_CHE_TAGSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAGSET_OFFSET)
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#define PIC32MX_CHE_TAGINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAGINV_OFFSET)
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#define PIC32MX_CHE_MSK (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSK_OFFSET)
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#define PIC32MX_CHE_MSKCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSKCLR_OFFSET)
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#define PIC32MX_CHE_MSKSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSKSET_OFFSET)
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#define PIC32MX_CHE_MSKINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSKINV_OFFSET)
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#define PIC32MX_CHE_W0 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W0_OFFSET)
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#define PIC32MX_CHE_W1 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W1_OFFSET)
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#define PIC32MX_CHE_W2 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W2_OFFSET)
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#define PIC32MX_CHE_W3 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W3_OFFSET)
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#define PIC32MX_CHE_LRU (PIC32MX_CHE_K1BASE+PIC32MX_CHE_LRU_OFFSET)
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#define PIC32MX_CHE_HIT (PIC32MX_CHE_K1BASE+PIC32MX_CHE_HIT_OFFSET)
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#define PIC32MX_CHE_MIS (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MIS_OFFSET)
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#define PIC32MX_CHE_PFABT (PIC32MX_CHE_K1BASE+PIC32MX_CHE_PFABT_OFFSET)
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/* Register Bit-Field Definitions ***********************************************************/
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/* Pre-fetch cache control register */
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#define CHE_CON_PFMWS_SHIFT (0) /* Bits 0-2: xx */
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#define CHE_CON_PFMWS_MASK (7 << CHE_CON_PFMWS_SHIFT)
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#define CHE_CON_PREFEN_SHIFT (4) /* Bits 4-5: xx */
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#define CHE_CON_PREFEN_MASK (3 << CHE_CON_PREFEN_SHIFT)
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#define CHE_CON_DCSZ_SHIFT (8) /* Bits 8-9: xx */
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#define CHE_CON_DCSZ_MASK (3 << CHE_CON_DCSZ_SHIFT)
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#define CHE_CON_CHECOH (1 << 16) /* Bit 16: xx */
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/* Pre-fetch cache access register */
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#define CHE_ACC_CHEIDX_SHIFT (0) /* Bits 0-3: xx */
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#define CHE_ACC_CHEIDX_MASK (15 << CHE_ACC_CHEIDX_SHIFT)
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#define CHE_ACC_CHEWEN (1 << 31) /* Bit 31: xx */
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/* Pre-fetch cache tag register */
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#define CHE_TAG_LTYPE (1 << 1) /* Bit 1: xx */
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#define CHE_TAG_LLOCK (1 << 2) /* Bit 2: xx */
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#define CHE_TAG_LVALID (1 << 3) /* Bit 3: xx */
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#define CHE_TAG_LTAG_SHIFT (4) /* Bits 4-23: xx */
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#define CHE_TAG_LTAG_MASK (0x000fffff << CHE_TAG_LTAG_SHIFT)
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#define CHE_TAG_LTAGBOOT (1 << 31) /* Bit 31: xx */
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/* Pre-fetch cache tag mask register */
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#define CHE_MSK_SHIFT (5) /* Bits 5-15: xx */
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#define CHE_MSK_MASK (0x7ff << CHE_MSK_SHIFT)
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/* Cache word 0-3 register -- 32-bit cache line data */
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/* Cache LRU register */
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#define CHE_LRU_MASK 0x01ffffff /* Bits 0-24 */
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/* Cache hit statistics register -- 32 bit counter value */
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/* Cache miss statistics register -- 32 bit counter value */
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/* Pre-fetch cache abort statistics register -- 32 bit counter value */
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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#ifndef __ASSEMBLY__
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/********************************************************************************************
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* Inline Functions
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********************************************************************************************/
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/********************************************************************************************
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* Public Function Prototypes
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********************************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CHE_H */
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@ -54,28 +54,97 @@
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************************************************************************************/
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/* Interrupt Priorities *************************************************************/
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#ifndef CONFIG_PIC32MX_WDTPRIO
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# define CONFIG_PIC32MX_WDTPRIO (INT_CP0_MID_PRIORITY << 2)
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#ifndef CONFIG_PIC32MX_CTPRIO /* Core Timer Interrupt */
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# define CONFIG_PIC32MX_CTPRIO (INT_CP0_MID_PRIORITY << 2)
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#endif
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#if CONFIG_PIC32MX_WDTPRIO < 4
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# error "CONFIG_PIC32MX_WDTPRIO is too small"
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#if CONFIG_PIC32MX_CTPRIO < 4
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# error "CONFIG_PIC32MX_CTPRIO is too small"
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#endif
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#if CONFIG_PIC32MX_WDTPRIO > 31
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# error "CONFIG_PIC32MX_WDTPRIO is too large"
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#if CONFIG_PIC32MX_CTPRIO > 31
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# error "CONFIG_PIC32MX_CTPRIO is too large"
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#endif
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#ifndef CONFIG_PIC32MX_RTCCPRIO
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# define CONFIG_PIC32MX_RTCCPRIO (INT_CP0_MID_PRIORITY << 2)
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#ifndef CONFIG_PIC32MX_CS0PRIO /* Core Software Interrupt 0 */
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# define CONFIG_PIC32MX_CS0PRIO (INT_CP0_MID_PRIORITY << 2)
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#endif
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#if CONFIG_PIC32MX_RTCCPRIO < 4
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# error "CONFIG_PIC32MX_RTCCPRIO is too small"
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#if CONFIG_PIC32MX_CS0PRIO < 4
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# error "CONFIG_PIC32MX_CS0PRIO is too small"
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#endif
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#if CONFIG_PIC32MX_RTCCPRIO > 31
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# error "CONFIG_PIC32MX_RTCCPRIO is too large"
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#if CONFIG_PIC32MX_CS0PRIO > 31
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# error "CONFIG_PIC32MX_CS0PRIO is too large"
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#endif
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#ifndef CONFIG_PIC32MX_T1PRIO
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#ifndef CONFIG_PIC32MX_CS1PRIO /* Core Software Interrupt 1 */
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# define CONFIG_PIC32MX_CS1PRIO (INT_CP0_MID_PRIORITY << 2)
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#endif
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#if CONFIG_PIC32MX_CS1PRIO < 4
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# error "CONFIG_PIC32MX_CS1PRIO is too small"
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#endif
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#if CONFIG_PIC32MX_CS1PRIO > 31
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# error "CONFIG_PIC32MX_CS1PRIO is too large"
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#endif
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#ifndef CONFIG_PIC32MX_INT0PRIO /* External interrupt 0 */
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# define CONFIG_PIC32MX_INT0PRIO (INT_CP0_MID_PRIORITY << 2)
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#endif
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#if CONFIG_PIC32MX_INT0PRIO < 4
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# error "CONFIG_PIC32MX_INT0PRIO is too small"
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#endif
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#if CONFIG_PIC32MX_INT0PRIO > 31
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# error "CONFIG_PIC32MX_INT0PRIO is too large"
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#endif
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#ifndef CONFIG_PIC32MX_INT1PRIO /* External interrupt 1 */
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# define CONFIG_PIC32MX_INT1PRIO (INT_CP0_MID_PRIORITY << 2)
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#endif
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#if CONFIG_PIC32MX_INT1PRIO < 4
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# error "CONFIG_PIC32MX_INT1PRIO is too small"
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#endif
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#if CONFIG_PIC32MX_INT1PRIO > 31
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# error "CONFIG_PIC32MX_INT1PRIO is too large"
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#endif
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#ifndef CONFIG_PIC32MX_INT2PRIO /* External interrupt 2 */
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# define CONFIG_PIC32MX_INT2PRIO (INT_CP0_MID_PRIORITY << 2)
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#endif
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#if CONFIG_PIC32MX_INT2PRIO < 4
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# error "CONFIG_PIC32MX_INT2PRIO is too small"
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#endif
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#if CONFIG_PIC32MX_INT2PRIO > 31
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# error "CONFIG_PIC32MX_INT2PRIO is too large"
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#endif
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#ifndef CONFIG_PIC32MX_INT3PRIO /* External interrupt 3 */
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# define CONFIG_PIC32MX_INT3PRIO (INT_CP0_MID_PRIORITY << 2)
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#endif
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#if CONFIG_PIC32MX_INT3PRIO < 4
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# error "CONFIG_PIC32MX_INT3PRIO is too small"
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#endif
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#if CONFIG_PIC32MX_INT3PRIO > 31
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# error "CONFIG_PIC32MX_INT3PRIO is too large"
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#endif
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#ifndef CONFIG_PIC32MX_INT4PRIO /* External interrupt 4 */
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# define CONFIG_PIC32MX_INT4PRIO (INT_CP0_MID_PRIORITY << 2)
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#endif
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#if CONFIG_PIC32MX_INT4PRIO < 4
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# error "CONFIG_PIC32MX_INT4PRIO is too small"
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#endif
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#if CONFIG_PIC32MX_INT4PRIO > 31
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# error "CONFIG_PIC32MX_INT4PRIO is too large"
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#endif
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#ifndef CONFIG_PIC32MX_FSCMPRIO /* Fail-Safe Clock Monitor */
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# define CONFIG_PIC32MX_FSCMPRIO (INT_CP0_MID_PRIORITY << 2)
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#endif
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#if CONFIG_PIC32MX_FSCMPRIO < 4
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# error "CONFIG_PIC32MX_FSCMPRIO is too small"
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#endif
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#if CONFIG_PIC32MX_FSCMPRIO > 31
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# error "CONFIG_PIC32MX_FSCMPRIO is too large"
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#endif
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#ifndef CONFIG_PIC32MX_T1PRIO /* Timer 1 (System timer) priority */
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# define CONFIG_PIC32MX_T1PRIO (INT_CP0_MID_PRIORITY << 2)
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#endif
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#if CONFIG_PIC32MX_T1PRIO < 4
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@ -85,7 +154,7 @@
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# error "CONFIG_PIC32MX_T1PRIO is too large"
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#endif
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#ifndef CONFIG_PIC32MX_T2PRIO
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#ifndef CONFIG_PIC32MX_T2PRIO /* Timer 2 priority */
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# define CONFIG_PIC32MX_T2PRIO (INT_CP0_MID_PRIORITY << 2)
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#endif
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#if CONFIG_PIC32MX_T2PRIO < 4
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@ -95,7 +164,7 @@
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# error "CONFIG_PIC32MX_T2PRIO is too large"
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#endif
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#ifndef CONFIG_PIC32MX_T3PRIO
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#ifndef CONFIG_PIC32MX_T3PRIO /* Timer 3 priority */
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# define CONFIG_PIC32MX_T3PRIO (INT_CP0_MID_PRIORITY << 2)
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#endif
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#if CONFIG_PIC32MX_T3PRIO < 4
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@ -105,7 +174,7 @@
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# error "CONFIG_PIC32MX_T3PRIO is too large"
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#endif
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#ifndef CONFIG_PIC32MX_T4PRIO
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#ifndef CONFIG_PIC32MX_T4PRIO /* Timer 4 priority */
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# define CONFIG_PIC32MX_T4PRIO (INT_CP0_MID_PRIORITY << 2)
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#endif
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#if CONFIG_PIC32MX_T4PRIO < 4
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@ -115,7 +184,7 @@
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# error "CONFIG_PIC32MX_T4PRIO is too large"
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#endif
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#ifndef CONFIG_PIC32MX_T5PRIO
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#ifndef CONFIG_PIC32MX_T5PRIO /* Timer 5 priority */
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# define CONFIG_PIC32MX_T5PRIO (INT_CP0_MID_PRIORITY << 2)
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#endif
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#if CONFIG_PIC32MX_T5PRIO < 4
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@ -125,7 +194,7 @@
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# error "CONFIG_PIC32MX_T5PRIO is too large"
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#endif
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#ifndef CONFIG_PIC32MX_IC1PRIO
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#ifndef CONFIG_PIC32MX_IC1PRIO /* Input Capture 1 */
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# define CONFIG_PIC32MX_IC1PRIO (INT_CP0_MID_PRIORITY << 2)
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#endif
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#if CONFIG_PIC32MX_IC1PRIO < 4
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@ -135,7 +204,7 @@
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# error "CONFIG_PIC32MX_IC1PRIO is too large"
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#endif
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#ifndef CONFIG_PIC32MX_IC2PRIO
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#ifndef CONFIG_PIC32MX_IC2PRIO /* Input Capture 2 */
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# define CONFIG_PIC32MX_IC2PRIO (INT_CP0_MID_PRIORITY << 2)
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#endif
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#if CONFIG_PIC32MX_IC2PRIO < 4
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@ -145,7 +214,7 @@
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# error "CONFIG_PIC32MX_IC2PRIO is too large"
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#endif
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#ifndef CONFIG_PIC32MX_IC3PRIO
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#ifndef CONFIG_PIC32MX_IC3PRIO /* Input Capture 3 */
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# define CONFIG_PIC32MX_IC3PRIO (INT_CP0_MID_PRIORITY << 2)
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#endif
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#if CONFIG_PIC32MX_IC3PRIO < 4
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@ -155,7 +224,7 @@
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# error "CONFIG_PIC32MX_IC3PRIO is too large"
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#endif
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#ifndef CONFIG_PIC32MX_IC4PRIO
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#ifndef CONFIG_PIC32MX_IC4PRIO /* Input Capture 4 */
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# define CONFIG_PIC32MX_IC4PRIO (INT_CP0_MID_PRIORITY << 2)
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#endif
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#if CONFIG_PIC32MX_IC4PRIO < 4
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@ -165,7 +234,7 @@
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# error "CONFIG_PIC32MX_IC4PRIO is too large"
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#endif
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|
||||
#ifndef CONFIG_PIC32MX_IC5PRIO
|
||||
#ifndef CONFIG_PIC32MX_IC5PRIO /* Input Capture 5 */
|
||||
# define CONFIG_PIC32MX_IC5PRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_IC5PRIO < 4
|
||||
@ -175,7 +244,7 @@
|
||||
# error "CONFIG_PIC32MX_IC5PRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_OC1PRIO
|
||||
#ifndef CONFIG_PIC32MX_OC1PRIO /* Output Compare 1 */
|
||||
# define CONFIG_PIC32MX_OC1PRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_OC1PRIO < 4
|
||||
@ -185,7 +254,7 @@
|
||||
# error "CONFIG_PIC32MX_OC1PRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_OC2PRIO
|
||||
#ifndef CONFIG_PIC32MX_OC2PRIO /* Output Compare 2 */
|
||||
# define CONFIG_PIC32MX_OC2PRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_OC2PRIO < 4
|
||||
@ -195,7 +264,7 @@
|
||||
# error "CONFIG_PIC32MX_OC2PRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_OC3PRIO
|
||||
#ifndef CONFIG_PIC32MX_OC3PRIO /* Output Compare 3 */
|
||||
# define CONFIG_PIC32MX_OC3PRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_OC3PRIO < 4
|
||||
@ -205,7 +274,7 @@
|
||||
# error "CONFIG_PIC32MX_OC3PRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_OC4PRIO
|
||||
#ifndef CONFIG_PIC32MX_OC4PRIO /* Output Compare 4 */
|
||||
# define CONFIG_PIC32MX_OC4PRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_OC4PRIO < 4
|
||||
@ -215,7 +284,7 @@
|
||||
# error "CONFIG_PIC32MX_OC4PRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_OC5PRIO
|
||||
#ifndef CONFIG_PIC32MX_OC5PRIO /* Output Compare 5 */
|
||||
# define CONFIG_PIC32MX_OC5PRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_OC5PRIO < 4
|
||||
@ -225,7 +294,7 @@
|
||||
# error "CONFIG_PIC32MX_OC5PRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_I2C1PRIO
|
||||
#ifndef CONFIG_PIC32MX_I2C1PRIO /* I2C 1 */
|
||||
# define CONFIG_PIC32MX_I2C1PRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_I2C1PRIO < 4
|
||||
@ -235,7 +304,7 @@
|
||||
# error "CONFIG_PIC32MX_I2C1PRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_I2C2PRIO
|
||||
#ifndef CONFIG_PIC32MX_I2C2PRIO /* I2C 2 */
|
||||
# define CONFIG_PIC32MX_I2C2PRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_I2C2PRIO < 4
|
||||
@ -245,7 +314,7 @@
|
||||
# error "CONFIG_PIC32MX_I2C2PRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_SPI1PRIO
|
||||
#ifndef CONFIG_PIC32MX_SPI1PRIO /* SPI 1 */
|
||||
# define CONFIG_PIC32MX_SPI1PRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_SPI1PRIO < 4
|
||||
@ -255,7 +324,7 @@
|
||||
# error "CONFIG_PIC32MX_SPI1PRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_SPI2PRIO
|
||||
#ifndef CONFIG_PIC32MX_SPI2PRIO /* SPI 2 */
|
||||
# define CONFIG_PIC32MX_SPI2PRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_SPI2PRIO < 4
|
||||
@ -265,7 +334,7 @@
|
||||
# error "CONFIG_PIC32MX_SPI2PRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_UART1PRIO
|
||||
#ifndef CONFIG_PIC32MX_UART1PRIO /* UART 1 */
|
||||
# define CONFIG_PIC32MX_UART1PRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_UART1PRIO < 4
|
||||
@ -275,7 +344,7 @@
|
||||
# error "CONFIG_PIC32MX_UART1PRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_UART2PRIO
|
||||
#ifndef CONFIG_PIC32MX_UART2PRIO /* UART 2 */
|
||||
# define CONFIG_PIC32MX_UART2PRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_UART2PRIO < 4
|
||||
@ -285,17 +354,17 @@
|
||||
# error "CONFIG_PIC32MX_UART2PRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_PMPPRIO
|
||||
# define CONFIG_PIC32MX_PMPPRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#ifndef CONFIG_PIC32MX_CN /* Input Change Interrupt */
|
||||
# define CONFIG_PIC32MX_CN (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_PMPPRIO < 4
|
||||
# error "CONFIG_PIC32MX_PMPPRIO is too small"
|
||||
#if CONFIG_PIC32MX_CN < 4
|
||||
# error "CONFIG_PIC32MX_CN is too small"
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_PMPPRIO > 31
|
||||
# error "CONFIG_PIC32MX_PMPPRIO is too large"
|
||||
#if CONFIG_PIC32MX_CN > 31
|
||||
# error "CONFIG_PIC32MX_CN is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_ADCPRIO
|
||||
#ifndef CONFIG_PIC32MX_ADCPRIO /* ADC1 Convert Done */
|
||||
# define CONFIG_PIC32MX_ADCPRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_ADCPRIO < 4
|
||||
@ -305,17 +374,17 @@
|
||||
# error "CONFIG_PIC32MX_ADCPRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_CVRPRIO
|
||||
# define CONFIG_PIC32MX_CVRPRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#ifndef CONFIG_PIC32MX_PMPPRIO /* Parallel Master Port */
|
||||
# define CONFIG_PIC32MX_PMPPRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_CVRPRIO < 4
|
||||
# error "CONFIG_PIC32MX_CVRPRIO is too small"
|
||||
#if CONFIG_PIC32MX_PMPPRIO < 4
|
||||
# error "CONFIG_PIC32MX_PMPPRIO is too small"
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_CVRPRIO > 31
|
||||
# error "CONFIG_PIC32MX_CVRPRIO is too large"
|
||||
#if CONFIG_PIC32MX_PMPPRIO > 31
|
||||
# error "CONFIG_PIC32MX_PMPPRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_CM1PRIO
|
||||
#ifndef CONFIG_PIC32MX_CM1PRIO /* Comparator 1 */
|
||||
# define CONFIG_PIC32MX_CM1PRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_CM1PRIO < 4
|
||||
@ -325,7 +394,7 @@
|
||||
# error "CONFIG_PIC32MX_CM1PRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_CM2PRIO
|
||||
#ifndef CONFIG_PIC32MX_CM2PRIO /* Comparator 2 */
|
||||
# define CONFIG_PIC32MX_CM2PRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_CM2PRIO < 4
|
||||
@ -335,67 +404,77 @@
|
||||
# error "CONFIG_PIC32MX_CM2PRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_OSCPRIO
|
||||
# define CONFIG_PIC32MX_OSCPRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#ifndef CONFIG_PIC32MX_FSCMPRIO /* Fail-Safe Clock Monitor */
|
||||
# define CONFIG_PIC32MX_FSCMPRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_OSCPRIO < 4
|
||||
# error "CONFIG_PIC32MX_OSCPRIO is too small"
|
||||
#if CONFIG_PIC32MX_FSCMPRIO < 4
|
||||
# error "CONFIG_PIC32MX_FSCMPRIO is too small"
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_OSCPRIO > 31
|
||||
# error "CONFIG_PIC32MX_OSCPRIO is too large"
|
||||
#if CONFIG_PIC32MX_FSCMPRIO > 31
|
||||
# error "CONFIG_PIC32MX_FSCMPRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_DDPPRIO
|
||||
# define CONFIG_PIC32MX_DDPPRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#ifndef CONFIG_PIC32MX_RTCCPRIO /* Real-Time Clock and Calendar */
|
||||
# define CONFIG_PIC32MX_RTCCPRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_DDPPRIO < 4
|
||||
# error "CONFIG_PIC32MX_DDPPRIO is too small"
|
||||
#if CONFIG_PIC32MX_RTCCPRIO < 4
|
||||
# error "CONFIG_PIC32MX_RTCCPRIO is too small"
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_DDPPRIO > 31
|
||||
# error "CONFIG_PIC32MX_DDPPRIO is too large"
|
||||
#if CONFIG_PIC32MX_RTCCPRIO > 31
|
||||
# error "CONFIG_PIC32MX_RTCCPRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_FLASHPRIO
|
||||
# define CONFIG_PIC32MX_FLASHPRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#ifndef CONFIG_PIC32MX_DMA0PRIO /* DMA Channel 0 */
|
||||
# define CONFIG_PIC32MX_DMA0PRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_FLASHPRIO < 4
|
||||
# error "CONFIG_PIC32MX_FLASHPRIO is too small"
|
||||
#if CONFIG_PIC32MX_DMA0PRIO < 4
|
||||
# error "CONFIG_PIC32MX_DMA0PRIO is too small"
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_FLASHPRIO > 31
|
||||
# error "CONFIG_PIC32MX_FLASHPRIO is too large"
|
||||
#if CONFIG_PIC32MX_DMA0PRIO > 31
|
||||
# error "CONFIG_PIC32MX_DMA0PRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_BMXPRIO
|
||||
# define CONFIG_PIC32MX_BMXPRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#ifndef CONFIG_PIC32MX_DMA1PRIO /* DMA Channel 1 */
|
||||
# define CONFIG_PIC32MX_DMA1PRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_BMXPRIO < 4
|
||||
# error "CONFIG_PIC32MX_BMXPRIO is too small"
|
||||
#if CONFIG_PIC32MX_DMA1PRIO < 4
|
||||
# error "CONFIG_PIC32MX_DMA1PRIO is too small"
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_BMXPRIO > 31
|
||||
# error "CONFIG_PIC32MX_BMXPRIO is too large"
|
||||
#if CONFIG_PIC32MX_DMA1PRIO > 31
|
||||
# error "CONFIG_PIC32MX_DMA1PRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_DMAPRIO
|
||||
# define CONFIG_PIC32MX_DMAPRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#ifndef CONFIG_PIC32MX_DMA2PRIO /* DMA Channel 2 */
|
||||
# define CONFIG_PIC32MX_DMA2PRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_DMAPRIO < 4
|
||||
# error "CONFIG_PIC32MX_DMAPRIO is too small"
|
||||
#if CONFIG_PIC32MX_DMA2PRIO < 4
|
||||
# error "CONFIG_PIC32MX_DMA2PRIO is too small"
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_DMAPRIO > 31
|
||||
# error "CONFIG_PIC32MX_DMAPRIO is too large"
|
||||
#if CONFIG_PIC32MX_DMA2PRIO > 31
|
||||
# error "CONFIG_PIC32MX_DMA2PRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_CHEPRIO
|
||||
# define CONFIG_PIC32MX_CHEPRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#ifndef CONFIG_PIC32MX_DMA3PRIO /* DMA Channel 3 */
|
||||
# define CONFIG_PIC32MX_DMA3PRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_CHEPRIO < 4
|
||||
# error "CONFIG_PIC32MX_CHEPRIO is too small"
|
||||
#if CONFIG_PIC32MX_DMA3PRIO < 4
|
||||
# error "CONFIG_PIC32MX_DMA3PRIO is too small"
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_CHEPRIO > 31
|
||||
# error "CONFIG_PIC32MX_CHEPRIO is too large"
|
||||
#if CONFIG_PIC32MX_DMA3PRIO > 31
|
||||
# error "CONFIG_PIC32MX_DMA3PRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_USBPRIO
|
||||
#ifndef CONFIG_PIC32MX_FCEPRIO /* Flash Control Event */
|
||||
# define CONFIG_PIC32MX_FCEPRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_FCEPRIO < 4
|
||||
# error "CONFIG_PIC32MX_FCEPRIO is too small"
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_FCEPRIO > 31
|
||||
# error "CONFIG_PIC32MX_FCEPRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_USBPRIO /* USB */
|
||||
# define CONFIG_PIC32MX_USBPRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_USBPRIO < 4
|
||||
@ -405,76 +484,6 @@
|
||||
# error "CONFIG_PIC32MX_USBPRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_IOPORTAPRIO
|
||||
# define CONFIG_PIC32MX_IOPORTAPRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_IOPORTAPRIO < 4
|
||||
# error "CONFIG_PIC32MX_IOPORTAPRIO is too small"
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_IOPORTAPRIO > 31
|
||||
# error "CONFIG_PIC32MX_IOPORTAPRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_IOPORTBPRIO
|
||||
# define CONFIG_PIC32MX_IOPORTBPRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_IOPORTBPRIO < 4
|
||||
# error "CONFIG_PIC32MX_IOPORTBPRIO is too small"
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_IOPORTBPRIO > 31
|
||||
# error "CONFIG_PIC32MX_IOPORTBPRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_IOPORTCPRIO
|
||||
# define CONFIG_PIC32MX_IOPORTCPRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_IOPORTCPRIO < 4
|
||||
# error "CONFIG_PIC32MX_IOPORTCPRIO is too small"
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_IOPORTCPRIO > 31
|
||||
# error "CONFIG_PIC32MX_IOPORTCPRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_IOPORTDPRIO
|
||||
# define CONFIG_PIC32MX_IOPORTDPRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_IOPORTDPRIO < 4
|
||||
# error "CONFIG_PIC32MX_IOPORTDPRIO is too small"
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_IOPORTDPRIO > 31
|
||||
# error "CONFIG_PIC32MX_IOPORTDPRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_IOPORTEPRIO
|
||||
# define CONFIG_PIC32MX_IOPORTEPRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_IOPORTEPRIO < 4
|
||||
# error "CONFIG_PIC32MX_IOPORTEPRIO is too small"
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_IOPORTEPRIO > 31
|
||||
# error "CONFIG_PIC32MX_IOPORTEPRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_IOPORTFPRIO
|
||||
# define CONFIG_PIC32MX_IOPORTFPRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_IOPORTFPRIO < 4
|
||||
# error "CONFIG_PIC32MX_IOPORTFPRIO is too small"
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_IOPORTFPRIO > 31
|
||||
# error "CONFIG_PIC32MX_IOPORTFPRIO is too large"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_IOPORTGPRIO
|
||||
# define CONFIG_PIC32MX_IOPORTGPRIO (INT_CP0_MID_PRIORITY << 2)
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_IOPORTGPRIO < 4
|
||||
# error "CONFIG_PIC32MX_IOPORTGPRIO is too small"
|
||||
#endif
|
||||
#if CONFIG_PIC32MX_IOPORTGPRIO > 31
|
||||
# error "CONFIG_PIC32MX_IOPORTGPRIO is too large"
|
||||
#endif
|
||||
|
||||
/* UARTs ****************************************************************************/
|
||||
/* Don't enable UARTs not supported by the chip. */
|
||||
|
||||
|
||||
@ -540,7 +540,7 @@ devconfig2:
|
||||
CONFIG_PIC32MX_UPLLIDIV | DEVCFG2_FPLLODIV_DIV1
|
||||
|
||||
devconfig1:
|
||||
.long DEVCFG1_FNOSC_POSCPLL | DEVCFG1_POSCMOD_XT | \
|
||||
.long DEVCFG1_FNOSC_POSCPLL | DEVCFG1_POSCMOD_HS | \
|
||||
CONFIG_PIC32MX_PBDIV | DEVCFG1_FCKSM_NONE | \
|
||||
CONFIG_PIC32MX_WDENABLE
|
||||
|
||||
|
||||
@ -176,7 +176,7 @@
|
||||
# define PIC32MX_DMACH2_K1BASE (PIC32MX_SFR_K1BASE + 0x000831e0)
|
||||
# define PIC32MX_DMACH3_K1BASE (PIC32MX_SFR_K1BASE + 0x000832a0)
|
||||
|
||||
/* Prefetch Register Base Address */
|
||||
/* Prefetch Cache Register Base Address */
|
||||
|
||||
# define PIC32MX_CHE_K1BASE (PIC32MX_SFR_K1BASE + 0x00084000)
|
||||
|
||||
|
||||
@ -145,6 +145,7 @@ struct up_dev_s
|
||||
uint8_t irqe; /* Error IRQ associated with this UART (for enable) */
|
||||
uint8_t irqrx; /* RX IRQ associated with this UART (for enable) */
|
||||
uint8_t irqtx; /* RX IRQ associated with this UART (for enable) */
|
||||
uint8_t irqprio; /* Interrupt priority */
|
||||
uint8_t ie; /* Interrupts enabled */
|
||||
uint8_t parity; /* 0=none, 1=odd, 2=even */
|
||||
uint8_t bits; /* Number of bits (5, 6, 7 or 8) */
|
||||
@ -211,6 +212,7 @@ static struct up_dev_s g_uart1priv =
|
||||
.irqe = PIC32MX_IRQSRC_U1E,
|
||||
.irqrx = PIC32MX_IRQSRC_U1RX,
|
||||
.irqtx = PIC32MX_IRQSRC_U1TX,
|
||||
.irqprio = CONFIG_PIC32MX_UART1PRIO,
|
||||
.parity = CONFIG_UART2_PARITY,
|
||||
.bits = CONFIG_UART2_BITS,
|
||||
.stopbits2 = CONFIG_UART2_2STOP,
|
||||
@ -244,6 +246,7 @@ static struct up_dev_s g_uart2priv =
|
||||
.irqe = PIC32MX_IRQSRC_U2E,
|
||||
.irqrx = PIC32MX_IRQSRC_U2RX,
|
||||
.irqtx = PIC32MX_IRQSRC_U2TX,
|
||||
.irqprio = CONFIG_PIC32MX_UART2PRIO,
|
||||
.parity = CONFIG_UART2_PARITY,
|
||||
.bits = CONFIG_UART2_BITS,
|
||||
.stopbits2 = CONFIG_UART2_2STOP,
|
||||
@ -341,6 +344,9 @@ static int up_setup(struct uart_dev_s *dev)
|
||||
priv->bits, priv->stopbits2);
|
||||
#endif
|
||||
|
||||
/* Set up the interrupt priority */
|
||||
|
||||
up_prioritize_irq(priv->irq, priv->irqprio);
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
||||
@ -59,28 +59,28 @@
|
||||
* Definitions
|
||||
****************************************************************************/
|
||||
/* Timer Setup **************************************************************/
|
||||
/* Select a timer prescale value. Our goal is to select the timer MATCH
|
||||
* register value givent the board's periperhal clock frequency and the
|
||||
* desired system timer frequency:
|
||||
/* Select a timer 1 prescale value. Our goal is to select the timer MATCH
|
||||
* register value given the board's SOSC clock frequency and the desired
|
||||
* system timer frequency:
|
||||
*
|
||||
* TIMER1_MATCH = BOARD_PBCLOCK / TIMER1_PRESCALE / CLOCKS_PER_SEC
|
||||
* TIMER1_MATCH = BOARD_SOSC_FREQ / TIMER1_PRESCALE / CLOCKS_PER_SEC
|
||||
*
|
||||
* We want the largest possible value for MATCH that is less than 65,535, the
|
||||
* maximum value for the 16-bit timer register:
|
||||
*
|
||||
* TIMER1_PRESCALE >= BOARD_PBCLOCK / CLOCKS_PER_SEC / 65535
|
||||
* TIMER1_PRESCALE >= BOARD_SOSC_FREQ / CLOCKS_PER_SEC / 65535
|
||||
*
|
||||
* Timer 1 does not have very many options for the perscaler value. So we
|
||||
* can pick the best by brute force. Example:
|
||||
*
|
||||
* BOARD_PBCLOCK = 40000000
|
||||
* BOARD_SOSC_FREQ = 32768
|
||||
* CLOCKS_PER_SEC = 100
|
||||
* OPTIMAL_PRESCALE = 6
|
||||
* TIMER1_PRESCALE = 8
|
||||
* TIMER1_MATCH = 50,000
|
||||
* OPTIMAL_PRESCALE = 1
|
||||
* TIMER1_PRESCALE = 1
|
||||
* TIMER1_MATCH = 328 -> 99.90 ticks/sec
|
||||
*/
|
||||
|
||||
#define OPTIMAL_PRESCALE (BOARD_PBCLOCK / CLOCKS_PER_SEC / 65535)
|
||||
#define OPTIMAL_PRESCALE (BOARD_SOSC_FREQ / CLOCKS_PER_SEC / 65535)
|
||||
#if OPTIMAL_PRESCALE <= 1
|
||||
# define TIMER1_CON_TCKPS TIMER1_CON_TCKPS_1
|
||||
# define TIMER1_PRESCALE 1
|
||||
@ -97,7 +97,7 @@
|
||||
# error "This timer frequency cannot be represented"
|
||||
#endif
|
||||
|
||||
#define TIMER1_MATCH (BOARD_PBCLOCK / TIMER1_PRESCALE / CLOCKS_PER_SEC)
|
||||
#define TIMER1_MATCH (BOARD_SOSC_FREQ / TIMER1_PRESCALE / CLOCKS_PER_SEC)
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
@ -143,7 +143,7 @@ int up_timerisr(int irq, uint32_t *regs)
|
||||
|
||||
void up_timerinit(void)
|
||||
{
|
||||
/* Configure and enable TIMER1 -- source internal (TCS=0) */
|
||||
/* Configure and enable TIMER1 -- source internal SOSC (TCS=0) */
|
||||
|
||||
putreg32(TIMER1_CON_TCKPS, PIC32MX_TIMER1_CON);
|
||||
putreg32(0, PIC32MX_TIMER1_CNT);
|
||||
|
||||
@ -150,94 +150,83 @@ PIC32MX Configuration Options
|
||||
|
||||
Individual subsystems can be enabled:
|
||||
|
||||
CONFIG_PIC32MX_WDT
|
||||
CONFIG_PIC32MX_RTCC
|
||||
CONFIG_PIC32MX_T2 /* Timer 1 is the system time and always enabled */
|
||||
CONFIG_PIC32MX_T3
|
||||
CONFIG_PIC32MX_T4
|
||||
CONFIG_PIC32MX_T5
|
||||
CONFIG_PIC32MX_IC1
|
||||
CONFIG_PIC32MX_IC2
|
||||
CONFIG_PIC32MX_IC3
|
||||
CONFIG_PIC32MX_IC4
|
||||
CONFIG_PIC32MX_IC5
|
||||
CONFIG_PIC32MX_OC1
|
||||
CONFIG_PIC32MX_OC2
|
||||
CONFIG_PIC32MX_OC3
|
||||
CONFIG_PIC32MX_OC4
|
||||
CONFIG_PIC32MX_OC5
|
||||
CONFIG_PIC32MX_I2C1
|
||||
CONFIG_PIC32MX_I2C2
|
||||
CONFIG_PIC32MX_SPI1
|
||||
CONFIG_PIC32MX_SPI2
|
||||
CONFIG_PIC32MX_UART1
|
||||
CONFIG_PIC32MX_UART2
|
||||
CONFIG_PIC32MX_PMP
|
||||
CONFIG_PIC32MX_ADC
|
||||
CONFIG_PIC32MX_CVR
|
||||
CONFIG_PIC32MX_CM1
|
||||
CONFIG_PIC32MX_CM2
|
||||
CONFIG_PIC32MX_OSC
|
||||
CONFIG_PIC32MX_DDP
|
||||
CONFIG_PIC32MX_FLASH
|
||||
CONFIG_PIC32MX_BMX
|
||||
CONFIG_PIC32MX_DMA
|
||||
CONFIG_PIC32MX_CHE
|
||||
CONFIG_PIC32MX_USB
|
||||
CONFIG_PIC32MX_IOPORTA
|
||||
CONFIG_PIC32MX_IOPORTB
|
||||
CONFIG_PIC32MX_IOPORTC
|
||||
CONFIG_PIC32MX_IOPORTD
|
||||
CONFIG_PIC32MX_IOPORTE
|
||||
CONFIG_PIC32MX_IOPORTF
|
||||
CONFIG_PIC32MX_IOPORTG
|
||||
CONFIG_PIC32MX_WDT - Watchdog timer
|
||||
CONFIG_PIC32MX_T2 - Timer 2 (Timer 1 is the system time and always enabled)
|
||||
CONFIG_PIC32MX_T3 - Timer 3
|
||||
CONFIG_PIC32MX_T4 - Timer 4
|
||||
CONFIG_PIC32MX_T5 - Timer 5
|
||||
CONFIG_PIC32MX_IC1 - Input Capture 1
|
||||
CONFIG_PIC32MX_IC2 - Input Capture 2
|
||||
CONFIG_PIC32MX_IC3 - Input Capture 3
|
||||
CONFIG_PIC32MX_IC4 - Input Capture 4
|
||||
CONFIG_PIC32MX_IC5 - Input Capture 5
|
||||
CONFIG_PIC32MX_OC1 - Output Compare 1
|
||||
CONFIG_PIC32MX_OC2 - Output Compare 2
|
||||
CONFIG_PIC32MX_OC3 - Output Compare 3
|
||||
CONFIG_PIC32MX_OC4 - Output Compare 4
|
||||
CONFIG_PIC32MX_OC5 - Output Compare 5
|
||||
CONFIG_PIC32MX_I2C1 - I2C 1
|
||||
CONFIG_PIC32MX_I2C2 - I2C 2
|
||||
CONFIG_PIC32MX_SPI1 - SPI 1
|
||||
CONFIG_PIC32MX_SPI2 - SPI 2
|
||||
CONFIG_PIC32MX_UART1 - UART 1
|
||||
CONFIG_PIC32MX_UART2 - UART 2
|
||||
CONFIG_PIC32MX_ADC - ADC 1
|
||||
CONFIG_PIC32MX_PMP - Parallel Master Port
|
||||
CONFIG_PIC32MX_CM1 - Comparator 1
|
||||
CONFIG_PIC32MX_CM2 - Comparator 2
|
||||
CONFIG_PIC32MX_RTCC - Real-Time Clock and Calendar
|
||||
CONFIG_PIC32MX_DMA - DMA
|
||||
CONFIG_PIC32MX_FLASH - FLASH
|
||||
CONFIG_PIC32MX_USB - USB
|
||||
|
||||
The priority of interrupts may be specified. The value ranage of
|
||||
priority is 4-31. The default (16) will be used if these any of these
|
||||
are undefined.
|
||||
|
||||
CONFIG_PIC32MX_WDTPRIO
|
||||
CONFIG_PIC32MX_RTCCPRIO
|
||||
CONFIG_PIC32MX_T1PRIO /* System timer priority */
|
||||
CONFIG_PIC32MX_T2PRIO
|
||||
CONFIG_PIC32MX_T3PRIO
|
||||
CONFIG_PIC32MX_T4PRIO
|
||||
CONFIG_PIC32MX_T5PRIO
|
||||
CONFIG_PIC32MX_IC1PRIO
|
||||
CONFIG_PIC32MX_IC2PRIO
|
||||
CONFIG_PIC32MX_IC3PRIO
|
||||
CONFIG_PIC32MX_IC4PRIO
|
||||
CONFIG_PIC32MX_IC5PRIO
|
||||
CONFIG_PIC32MX_OC1PRIO
|
||||
CONFIG_PIC32MX_OC2PRIO
|
||||
CONFIG_PIC32MX_OC3PRIO
|
||||
CONFIG_PIC32MX_OC4PRIO
|
||||
CONFIG_PIC32MX_OC5PRIO
|
||||
CONFIG_PIC32MX_I2C1PRIO
|
||||
CONFIG_PIC32MX_I2C2PRIO
|
||||
CONFIG_PIC32MX_SPI1PRIO
|
||||
CONFIG_PIC32MX_SPI2PRIO
|
||||
CONFIG_PIC32MX_UART1PRIO
|
||||
CONFIG_PIC32MX_UART2PRIO
|
||||
CONFIG_PIC32MX_PMPPRIO
|
||||
CONFIG_PIC32MX_ADCPRIO
|
||||
CONFIG_PIC32MX_CVRPRIO
|
||||
CONFIG_PIC32MX_CM1PRIO
|
||||
CONFIG_PIC32MX_CM2PRIO
|
||||
CONFIG_PIC32MX_OSCPRIO
|
||||
CONFIG_PIC32MX_DDPPRIO
|
||||
CONFIG_PIC32MX_FLASHPRIO
|
||||
CONFIG_PIC32MX_BMXPRIO
|
||||
CONFIG_PIC32MX_DMAPRIO
|
||||
CONFIG_PIC32MX_CHEPRIO
|
||||
CONFIG_PIC32MX_USBPRIO
|
||||
CONFIG_PIC32MX_IOPORTAPRIO
|
||||
CONFIG_PIC32MX_IOPORTBPRIO
|
||||
CONFIG_PIC32MX_IOPORTCPRIO
|
||||
CONFIG_PIC32MX_IOPORTDPRIO
|
||||
CONFIG_PIC32MX_IOPORTEPRIO
|
||||
CONFIG_PIC32MX_IOPORTFPRIO
|
||||
CONFIG_PIC32MX_IOPORTGPRIO
|
||||
CONFIG_PIC32MX_CTPRIO - Core Timer Interrupt
|
||||
CONFIG_PIC32MX_CS0PRIO - Core Software Interrupt 0
|
||||
CONFIG_PIC32MX_CS1PRIO - Core Software Interrupt 1
|
||||
CONFIG_PIC32MX_INT0PRIO - External Interrupt 0
|
||||
CONFIG_PIC32MX_INT1PRIO - External Interrupt 1
|
||||
CONFIG_PIC32MX_INT2PRIO - External Interrupt 2
|
||||
CONFIG_PIC32MX_INT3PRIO - External Interrupt 3
|
||||
CONFIG_PIC32MX_INT4PRIO - External Interrupt 4
|
||||
CONFIG_PIC32MX_FSCMPRIO - Fail-Safe Clock Monitor
|
||||
CONFIG_PIC32MX_T1PRIO - Timer 1 (System timer) priority
|
||||
CONFIG_PIC32MX_T2PRIO - Timer 2 priority
|
||||
CONFIG_PIC32MX_T3PRIO - Timer 3 priority
|
||||
CONFIG_PIC32MX_T4PRIO - Timer 4 priority
|
||||
CONFIG_PIC32MX_T5PRIO - Timer 5 priority
|
||||
CONFIG_PIC32MX_IC1PRIO - Input Capture 1
|
||||
CONFIG_PIC32MX_IC2PRIO - Input Capture 2
|
||||
CONFIG_PIC32MX_IC3PRIO - Input Capture 3
|
||||
CONFIG_PIC32MX_IC4PRIO - Input Capture 4
|
||||
CONFIG_PIC32MX_IC5PRIO - Input Capture 5
|
||||
CONFIG_PIC32MX_OC1PRIO - Output Compare 1
|
||||
CONFIG_PIC32MX_OC2PRIO - Output Compare 2
|
||||
CONFIG_PIC32MX_OC3PRIO - Output Compare 3
|
||||
CONFIG_PIC32MX_OC4PRIO - Output Compare 4
|
||||
CONFIG_PIC32MX_OC5PRIO - Output Compare 5
|
||||
CONFIG_PIC32MX_I2C1PRIO - I2C 1
|
||||
CONFIG_PIC32MX_I2C2PRIO - I2C 2
|
||||
CONFIG_PIC32MX_SPI1PRIO - SPI 1
|
||||
CONFIG_PIC32MX_SPI2PRIO - SPI 2
|
||||
CONFIG_PIC32MX_UART1PRIO - UART 1
|
||||
CONFIG_PIC32MX_UART2PRIO - UART 2
|
||||
CONFIG_PIC32MX_CN - Input Change Interrupt
|
||||
CONFIG_PIC32MX_ADCPRIO - ADC1 Convert Done
|
||||
CONFIG_PIC32MX_PMPPRIO - Parallel Master Port
|
||||
CONFIG_PIC32MX_CM1PRIO - Comparator 1
|
||||
CONFIG_PIC32MX_CM2PRIO - Comparator 2
|
||||
CONFIG_PIC32MX_FSCMPRIO - Fail-Safe Clock Monitor
|
||||
CONFIG_PIC32MX_RTCCPRIO - Real-Time Clock and Calendar
|
||||
CONFIG_PIC32MX_DMA0PRIO - DMA Channel 0
|
||||
CONFIG_PIC32MX_DMA1PRIO - DMA Channel 1
|
||||
CONFIG_PIC32MX_DMA2PRIO - DMA Channel 2
|
||||
CONFIG_PIC32MX_DMA3PRIO - DMA Channel 3
|
||||
CONFIG_PIC32MX_FCEPRIO - Flash Control Event
|
||||
CONFIG_PIC32MX_USBPRIO - USB
|
||||
|
||||
PIC32MXx specific device driver settings
|
||||
|
||||
|
||||
@ -51,8 +51,8 @@
|
||||
/* Clocking *****************************************************************/
|
||||
/* Crystal frequencies */
|
||||
|
||||
#define BOARD_POSC_XTAL 8000000 /* Primary OSC XTAL frequency (8MHz) */
|
||||
#define BOARD_SOSC_XTAL 32768 /* Secondary OSC XTAL frequency (32.768KHz) */
|
||||
#define BOARD_POSC_FREQ 8000000 /* Primary OSC XTAL frequency (8MHz) */
|
||||
#define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) */
|
||||
|
||||
/* PLL configuration and resulting CPU clock.
|
||||
* CPU_CLOCK = ((POSC_XTAL / IDIV) * MULT) / ODIV
|
||||
|
||||
Loading…
Reference in New Issue
Block a user