sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Merged in raiden00/nuttx_pe (pull request #779)

Browse Source 
Master

configs/nucleo-f334r8: add example for the SPWM generation (custom STM32 PWM usage)

arch/arm/src/stm32/stm32_pwm: fix compilation errors if the upper-half PWM logic is not enabled

include/nuttx/drivers/pwm.h: remove dependency on CONFIG_PWM for the upper-half PWM header. This allows compilation for the lower-level PWM drivers even if the upper-half PWM logic is not used.

arch/arm/src/stm32/stm32_tim.c: fix compilation error if there is no TIM8

configs/nucleo-f334r8/highpri: remove the upper-half ADC from configuration

configs/nucleo-f302r8/highpri: remove the upper-half ADC from configuration

configs/stm32f429i-disco/highpri: remove the upper-half ADC from configuration

Approved-by: GregoryN <gnutt@nuttx.org>
This commit is contained in:
Mateusz Szafoni 2018-12-09 16:31:57 +00:00 committed by GregoryN
parent 29b9b3b68b
commit b3b53a6dd4
19 changed files with 1415 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

50
arch/arm/src/stm32/Kconfig
View File

@ -1776,6 +1776,8 @@ config STM32_STM32F33XX
select STM32_HAVE_OPAMP2
select STM32_HAVE_CCM
select STM32_HAVE_TIM1
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
select STM32_HAVE_TIM15
select STM32_HAVE_TIM16
select STM32_HAVE_TIM17
@ -2506,44 +2508,46 @@ config STM32_SDADC3
depends on STM32_HAVE_SDADC3
select STM32_HAVE_SDADC3_DMA if STM32_DMA2
config STM32_COMP
bool "COMP"
default n
depends on STM32_STM32L15XX || STM32_STM32F33XX
config STM32_COMP1
bool "COMP1"
default n
select STM32_COMP
depends on STM32_HAVE_COMP1
config STM32_COMP2
bool "COMP2"
default n
select STM32_COMP
depends on STM32_HAVE_COMP2
config STM32_COMP3
bool "COMP3"
default n
select STM32_COMP
depends on STM32_HAVE_COMP3
config STM32_COMP4
bool "COMP4"
default n
select STM32_COMP
depends on STM32_HAVE_COMP4
config STM32_COMP5
bool "COMP5"
default n
select STM32_COMP
depends on STM32_HAVE_COMP5
config STM32_COMP6
bool "COMP6"
default n
select STM32_COMP
depends on STM32_HAVE_COMP6
config STM32_COMP7
bool "COMP7"
default n
select STM32_COMP
depends on STM32_HAVE_COMP7
config STM32_BKP
@ -2749,28 +2753,28 @@ config STM32_DMA2D
The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation
available on the STM32F429 and STM32F439 devices.
config STM32_OPAMP
bool "OPAMP"
default n
config STM32_OPAMP1
bool "OPAMP1"
default n
select STM32_OPAMP
depends on STM32_HAVE_OPAMP1
config STM32_OPAMP2
bool "OPAMP2"
default n
select STM32_OPAMP
depends on STM32_HAVE_OPAMP2
config STM32_OPAMP3
bool "OPAMP3"
default n
select STM32_OPAMP
depends on STM32_HAVE_OPAMP3
config STM32_OPAMP4
bool "OPAMP4"
default n
select STM32_OPAMP
depends on STM32_HAVE_OPAMP4
config STM32_RTC
@ -3066,6 +3070,19 @@ config STM32_TIM
bool
default n
config STM32_PWM
bool
default n
config STM32_COMP
bool
default n
depends on STM32_STM32L15XX || STM32_STM32F33XX
config STM32_OPAMP
bool
default n
config STM32_NOEXT_VECTORS
bool "Disable the ARMv7-M EXT vectors"
default n
@ -3445,6 +3462,7 @@ config STM32_TIM1_PWM
default n
depends on STM32_TIM1
select ARCH_HAVE_PWM_PULSECOUNT
select STM32_PWM
---help---
Reserve timer 1 for use by PWM
@ -3686,6 +3704,7 @@ config STM32_TIM2_PWM
default n
depends on STM32_TIM2
select ARCH_HAVE_PWM_PULSECOUNT
select STM32_PWM
---help---
Reserve timer 2 for use by PWM
@ -3870,6 +3889,7 @@ config STM32_TIM3_PWM
default n
depends on STM32_TIM3
select ARCH_HAVE_PWM_PULSECOUNT
select STM32_PWM
---help---
Reserve timer 3 for use by PWM
@ -4054,6 +4074,7 @@ config STM32_TIM4_PWM
default n
depends on STM32_TIM4
select ARCH_HAVE_PWM_PULSECOUNT
select STM32_PWM
---help---
Reserve timer 4 for use by PWM
@ -4238,6 +4259,7 @@ config STM32_TIM5_PWM
default n
depends on STM32_TIM5
select ARCH_HAVE_PWM_PULSECOUNT
select STM32_PWM
---help---
Reserve timer 5 for use by PWM
@ -4422,6 +4444,7 @@ config STM32_TIM8_PWM
default n
depends on STM32_TIM8
select ARCH_HAVE_PWM_PULSECOUNT
select STM32_PWM
---help---
Reserve timer 8 for use by PWM
@ -4657,6 +4680,7 @@ config STM32_TIM9_PWM
default n
depends on STM32_TIM9
select ARCH_HAVE_PWM_PULSECOUNT
select STM32_PWM
---help---
Reserve timer 9 for use by PWM
@ -4766,6 +4790,7 @@ config STM32_TIM10_PWM
default n
depends on STM32_TIM10
select ARCH_HAVE_PWM_PULSECOUNT
select STM32_PWM
---help---
Reserve timer 10 for use by PWM
@ -4841,6 +4866,7 @@ config STM32_TIM11_PWM
default n
depends on STM32_TIM11
select ARCH_HAVE_PWM_PULSECOUNT
select STM32_PWM
---help---
Reserve timer 11 for use by PWM
@ -4916,6 +4942,7 @@ config STM32_TIM12_PWM
default n
depends on STM32_TIM12
select ARCH_HAVE_PWM_PULSECOUNT
select STM32_PWM
---help---
Reserve timer 12 for use by PWM
@ -5025,6 +5052,7 @@ config STM32_TIM13_PWM
default n
depends on STM32_TIM13
select ARCH_HAVE_PWM_PULSECOUNT
select STM32_PWM
---help---
Reserve timer 13 for use by PWM
@ -5100,6 +5128,7 @@ config STM32_TIM14_PWM
default n
depends on STM32_TIM14
select ARCH_HAVE_PWM_PULSECOUNT
select STM32_PWM
---help---
Reserve timer 14 for use by PWM
@ -5174,6 +5203,7 @@ config STM32_TIM15_PWM
bool "TIM15 PWM"
default n
depends on STM32_TIM15
select STM32_PWM
---help---
Reserve timer 15 for use by PWM
@ -5321,6 +5351,7 @@ config STM32_TIM16_PWM
bool "TIM16 PWM"
default n
depends on STM32_TIM16
select STM32_PWM
---help---
Reserve timer 16 for use by PWM
@ -5414,6 +5445,7 @@ config STM32_TIM17_PWM
bool "TIM17 PWM"
default n
depends on STM32_TIM17
select STM32_PWM
---help---
Reserve timer 17 for use by PWM

10
arch/arm/src/stm32/Make.defs
View File

@ -199,15 +199,15 @@ ifeq ($(CONFIG_STM32_SDADC),y)
CHIP_CSRCS += stm32_sdadc.c
endif
ifeq ($(CONFIG_DAC),y)
ifeq ($(CONFIG_STM32_DAC),y)
CHIP_CSRCS += stm32_dac.c
endif
ifeq ($(CONFIG_COMP),y)
ifeq ($(CONFIG_STM32_COMP),y)
CHIP_CSRCS += stm32_comp.c
endif
ifeq ($(CONFIG_OPAMP),y)
ifeq ($(CONFIG_STM32_OPAMP),y)
CHIP_CSRCS += stm32_opamp.c
endif
@ -235,7 +235,7 @@ ifeq ($(CONFIG_STM32_DMA2D),y)
CHIP_CSRCS += stm32_dma2d.c
endif
ifeq ($(CONFIG_PWM),y)
ifeq ($(CONFIG_STM32_PWM),y)
CHIP_CSRCS += stm32_pwm.c
endif
@ -243,7 +243,7 @@ ifeq ($(CONFIG_SENSORS_QENCODER),y)
CHIP_CSRCS += stm32_qencoder.c
endif
ifeq ($(CONFIG_CAN),y)
ifeq ($(CONFIG_STM32_CAN),y)
CHIP_CSRCS += stm32_can.c
endif

2
arch/arm/src/stm32/stm32_adc.c
View File

@ -83,7 +83,7 @@
* - injected sequence conversion (not supported in upper-half ADC driver)
*/
/* ADC "upper half" support must be enabled */
/* STM32 ADC "lower-half" support must be enabled */
#ifdef CONFIG_STM32_ADC

1
arch/arm/src/stm32/stm32_hrtim.c
View File

@ -4625,7 +4625,6 @@ static int hrtim_irq_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer, uint16_t
hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_DIER_OFFSET, irq);
}
errout:
return ret;
}

13
arch/arm/src/stm32/stm32_pwm.c
View File

@ -49,7 +49,6 @@
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/drivers/pwm.h>
#include <arch/board/board.h>
#include "up_internal.h"
@ -67,14 +66,7 @@
* 2. STM32 TIMER IP version 2 - F3 (no F37x), F7, H7, L4, L4+
*/
#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \
defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM4_PWM) || \
defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \
defined(CONFIG_STM32_TIM9_PWM) || defined(CONFIG_STM32_TIM10_PWM) || \
defined(CONFIG_STM32_TIM11_PWM) || defined(CONFIG_STM32_TIM12_PWM) || \
defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM14_PWM) || \
defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \
defined(CONFIG_STM32_TIM17_PWM)
#ifdef CONFIG_STM32_PWM
/****************************************************************************
* Pre-processor Definitions
@ -4691,5 +4683,4 @@ errout:
return (FAR struct pwm_lowerhalf_s *)lower;
}
#endif /* CONFIG_STM32_TIMn_PWM, n = 1,...,17 */
#endif /* CONFIG_STM32_PWM */

29
arch/arm/src/stm32/stm32_pwm.h
View File

@ -51,6 +51,8 @@
#include <nuttx/config.h>
#include <nuttx/drivers/pwm.h>
#include "chip.h"
/************************************************************************************
@ -116,23 +118,14 @@
/* Check if PWM support for any channel is enabled. */
#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \
defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM4_PWM) || \
defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \
defined(CONFIG_STM32_TIM9_PWM) || defined(CONFIG_STM32_TIM10_PWM) || \
defined(CONFIG_STM32_TIM11_PWM) || defined(CONFIG_STM32_TIM12_PWM) || \
defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM14_PWM) || \
defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \
defined(CONFIG_STM32_TIM17_PWM)
#ifdef CONFIG_STM32_PWM
#include <arch/board/board.h>
#include "chip/stm32_tim.h"
#ifdef CONFIG_STM32_PWM_MULTICHAN
# ifndef CONFIG_PWM_MULTICHAN
# error CONFIG_STM32_PWM_MULTICHAN enabled but CONFIG_PWM_MULTICHAN not set!
# endif
#endif
/* Configuration needed by upper-half PWM driver */
#ifdef CONFIG_PWM
#ifdef CONFIG_PWM_MULTICHAN
@ -612,6 +605,8 @@
#endif /* CONFIG_PWM_MULTICHAN */
#endif /* CONFIG_PWM */
#ifdef CONFIG_STM32_TIM1_CH1OUT
# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT
#else
@ -884,8 +879,12 @@
(dev)->llops->freq_update((FAR struct pwm_lowerhalf_s *)dev, freq)
#define PWM_TIM_ENABLE(dev, state) \
(dev)->llops->tim_enable((FAR struct pwm_lowerhalf_s *)dev, state)
#define PWM_DUMP_REGS(dev) \
#ifdef CONFIG_DEBUG_PWM_INFO
# define PWM_DUMP_REGS(dev) \
(dev)->llops->dump_regs((FAR struct pwm_lowerhalf_s *)dev)
#else
# define PWM_DUMP_REGS(dev)
#endif
#define PWM_DT_UPDATE(dev, dt) \
(dev)->llops->dt_update((FAR struct pwm_lowerhalf_s *)dev, dt)
@ -1081,5 +1080,5 @@ FAR struct pwm_lowerhalf_s *stm32_pwminitialize(int timer);
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32_TIMx_PWM */
#endif /* CONFIG_STM32_PWM */
#endif /* __ARCH_ARM_SRC_STM32_STM32_PWM_H */

7
arch/arm/src/stm32/stm32_tim.c
View File

@ -732,8 +732,11 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t m
#if STM32_NATIM > 0
/* Advanced registers require Main Output Enable */
if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE ||
((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE)
if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE
#ifdef STM32_TIM8_BASE
|| ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE
#endif
)
{
stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE);
}

2
configs/nucleo-f302r8/highpri/defconfig
View File

@ -1,7 +1,5 @@
# CONFIG_DEV_NULL is not set
# CONFIG_LIBC_LONG_LONG is not set
CONFIG_ADC=y
CONFIG_ANALOG=y
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="nucleo-f302r8"
CONFIG_ARCH_BOARD_NUCLEO_F302R8=y

38
configs/nucleo-f334r8/Kconfig
View File

@ -9,4 +9,42 @@ config NUCLEOF334R8_HIGHPRI
bool "High priority interrupt test"
default n
menuconfig NUCLEOF334R8_SPWM
bool "Sinusoidal PWM generator example"
default n
if NUCLEOF334R8_SPWM
choice
prompt "Sinusoidal PWM source"
default NUCLEOF334R8_SPWM_USE_TIM1
config NUCLEOF334R8_SPWM_USE_TIM1
bool "Use TIM1 as PWM source"
config NUCLEOF334R8_SPWM_USE_HRTIM1
bool "Use HRTIM as PWM source"
endchoice
config NUCLEOF334R8_SPWM_PWM_FREQ
int "PWM frequency in Hz"
default 100000
config NUCLEOF334R8_SPWM_SAMPLES
int "Sine samples"
default 100
config NUCLEOF334R8_SPWM_FREQ
int "Waveform frequency in Hz"
default 60
config NUCLEOF334R8_SPWM_PHASE_NUM
int "Number of phases"
default 1
range 1 5 if NUCLEOF334R8_SPWM_USE_HRTIM1
range 1 4 if NUCLEOF334R8_SPWM_USE_TIM1
endif
endif

34
configs/nucleo-f334r8/README.txt
View File

@ -24,3 +24,37 @@ Variants include
NUCLEO-L152RE STM32L152RET6
NUCLEO-L452RE STM32L452RET6
NUCLEO-L476RG STM32L476RGT6
Configurations
==============
nsh:
----
Configures the NuttShell (nsh) located at apps/examples/nsh.
adc:
----
Configures the ADC example located at apps/examples/adc.
highpri:
--------
Configures the high priority interrupts example (ADC + PWM)
spwm1 and spwm2:
----------------
Configures the sinusoidal PWM (SPWM) example which presents a simple use case
of the STM32 PWM lower-half driver without generic upper-half PWM logic.
There are two variants of this example, where functionality is achieved with
different periperals:
- spwm1 uses HRTIM to generate PWM and change waveform samples
- spwm2 uses TIM1 to generate PWM and TIM6 to change waveform samples
At the moment, the waveform parameters are hardcoded, but it should be easy to
modify this example and make it more functional.

2
configs/nucleo-f334r8/highpri/defconfig
View File

@ -1,7 +1,5 @@
# CONFIG_DEV_NULL is not set
# CONFIG_LIBC_LONG_LONG is not set
CONFIG_ADC=y
CONFIG_ANALOG=y
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="nucleo-f334r8"
CONFIG_ARCH_BOARD_NUCLEO_F334R8=y

63
configs/nucleo-f334r8/include/board.h
View File

@ -279,6 +279,69 @@
#endif /* CONFIG_STM32_TIM1_PWM && CONFIG_STM32_ADC1_DMA */
#endif /* CONFIG_NUCLEOF334R8_HIGHPRI */
#ifdef CONFIG_NUCLEOF334R8_SPWM
# ifdef CONFIG_NUCLEOF334R8_SPWM_USE_TIM1
/* TIM1 PWM configuration ***************************************************/
# define PWM_TIM1_NCHANNELS 4
# define GPIO_TIM1_CH1OUT GPIO_TIM1_CH1OUT_1 /* TIM1 CH1 - PA8 */
# define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1N_3 /* TIM1 CH1N - PA7 */
/* TIM1 CH2 - PA9 */
# define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2N_2 /* TIM1 CH2N - PB0 */
# define GPIO_TIM1_CH3OUT GPIO_TIM1_CH3OUT_1 /* TIM1 CH3 - PA10 */
# define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3N_2 /* TIM1 CH3N - PB1 */
# define GPIO_TIM1_CH4OUT GPIO_TIM1_CH4OUT_1 /* TIM1 CH4 - PA11 */
# endif
# ifdef CONFIG_NUCLEOF334R8_SPWM_USE_HRTIM1
/* HRTIM configuration ******************************************************/
# define HRTIM_MASTER_PRESCALER HRTIM_PRESCALER_128
# define HRTIM_MASTER_MODE HRTIM_MODE_CONT
# define HRTIM_TIMA_PRESCALER HRTIM_PRESCALER_128
# define HRTIM_TIMA_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD)
# define HRTIM_TIMA_CH1_SET HRTIM_OUT_SET_PER
# define HRTIM_TIMA_CH1_RST HRTIM_OUT_RST_CMP1
# define HRTIM_TIMA_UPDATE HRTIM_UPDATE_MSTU
# define HRTIM_TIMA_RESET 0
# define HRTIM_TIMB_PRESCALER HRTIM_PRESCALER_128
# define HRTIM_TIMB_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD)
# define HRTIM_TIMB_CH1_SET HRTIM_OUT_SET_PER
# define HRTIM_TIMB_CH1_RST HRTIM_OUT_RST_CMP1
# define HRTIM_TIMB_UPDATE HRTIM_UPDATE_MSTU
# define HRTIM_TIMB_RESET 0
# define HRTIM_TIMC_PRESCALER HRTIM_PRESCALER_128
# define HRTIM_TIMC_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD)
# define HRTIM_TIMC_CH1_SET HRTIM_OUT_SET_PER
# define HRTIM_TIMC_CH1_RST HRTIM_OUT_RST_CMP1
# define HRTIM_TIMC_UPDATE HRTIM_UPDATE_MSTU
# define HRTIM_TIMC_RESET 0
# define HRTIM_TIMD_PRESCALER HRTIM_PRESCALER_128
# define HRTIM_TIMD_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD)
# define HRTIM_TIMD_CH1_SET HRTIM_OUT_SET_PER
# define HRTIM_TIMD_CH1_RST HRTIM_OUT_RST_CMP1
# define HRTIM_TIMD_UPDATE HRTIM_UPDATE_MSTU
# define HRTIM_TIMD_RESET 0
# define HRTIM_TIME_PRESCALER HRTIM_PRESCALER_128
# define HRTIM_TIME_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD)
# define HRTIM_TIME_CH1_SET HRTIM_OUT_SET_PER
# define HRTIM_TIME_CH1_RST HRTIM_OUT_RST_CMP1
# define HRTIM_TIME_UPDATE HRTIM_UPDATE_MSTU
# define HRTIM_TIME_RESET 0
# define HRTIM_MASTER_IRQ HRTIM_IRQ_MCMP1
# endif
#endif /* CONFIG_NUCLEOF334R8_SPWM */
/* DMA channels *************************************************************/
/* ADC */

79
configs/nucleo-f334r8/spwm1/defconfig Normal file
View File

@ -0,0 +1,79 @@
# CONFIG_DEV_NULL is not set
# CONFIG_LIBC_LONG_LONG is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="nucleo-f334r8"
CONFIG_ARCH_BOARD_NUCLEO_F334R8=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F334R8=y
CONFIG_ARCH_HIPRI_INTERRUPT=y
CONFIG_ARCH_RAMVECTORS=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BUILTIN=y
CONFIG_BUILTIN_PROXY_STACKSIZE=512
CONFIG_DISABLE_ENVIRON=y
CONFIG_DISABLE_MQUEUE=y
CONFIG_DISABLE_POLL=y
CONFIG_DISABLE_POSIX_TIMERS=y
CONFIG_FDCLONE_STDIO=y
CONFIG_INTELHEX_BINARY=y
CONFIG_LIBC_FLOATINGPOINT=y
CONFIG_LIBM=y
CONFIG_LIB_BOARDCTL=y
CONFIG_MAX_TASKS=4
CONFIG_MAX_WDOGPARMS=1
CONFIG_NAME_MAX=16
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_NUCLEOF334R8_SPWM=y
CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM=3
CONFIG_NUCLEOF334R8_SPWM_USE_HRTIM1=y
CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=512
CONFIG_PREALLOC_TIMERS=2
CONFIG_PREALLOC_WDOGS=1
CONFIG_PTHREAD_STACK_DEFAULT=1024
CONFIG_PTHREAD_STACK_MIN=1024
CONFIG_RAM_SIZE=12288
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_SDCLONE_DISABLE=y
CONFIG_START_DAY=6
CONFIG_START_MONTH=12
CONFIG_START_YEAR=2011
CONFIG_STM32_CCMEXCLUDE=y
CONFIG_STM32_HRTIM1=y
CONFIG_STM32_HRTIM_CLK_FROM_PLL=y
CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y
CONFIG_STM32_HRTIM_INTERRUPTS=y
CONFIG_STM32_HRTIM_MASTER=y
CONFIG_STM32_HRTIM_MASTER_IRQ=y
CONFIG_STM32_HRTIM_NO_ENABLE_TIMERS=y
CONFIG_STM32_HRTIM_PWM=y
CONFIG_STM32_HRTIM_TIMA=y
CONFIG_STM32_HRTIM_TIMA_PWM=y
CONFIG_STM32_HRTIM_TIMA_PWM_CH1=y
CONFIG_STM32_HRTIM_TIMB=y
CONFIG_STM32_HRTIM_TIMB_PWM=y
CONFIG_STM32_HRTIM_TIMB_PWM_CH1=y
CONFIG_STM32_HRTIM_TIMC=y
CONFIG_STM32_HRTIM_TIMC_PWM=y
CONFIG_STM32_HRTIM_TIMC_PWM_CH1=y
CONFIG_STM32_HRTIM_TIMD=y
CONFIG_STM32_HRTIM_TIMD_PWM=y
CONFIG_STM32_HRTIM_TIMD_PWM_CH1=y
CONFIG_STM32_HRTIM_TIME=y
CONFIG_STM32_HRTIM_TIME_PWM=y
CONFIG_STM32_HRTIM_TIME_PWM_CH1=y
CONFIG_STM32_JTAG_SW_ENABLE=y
CONFIG_STM32_PWR=y
CONFIG_STM32_USART2=y
CONFIG_SYSTEM_READLINE=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=512
CONFIG_USART2_SERIAL_CONSOLE=y
CONFIG_USERMAIN_STACKSIZE=1024
CONFIG_USER_ENTRYPOINT="spwm_main"
CONFIG_WDOG_INTRESERVE=0

71
configs/nucleo-f334r8/spwm2/defconfig Normal file
View File

@ -0,0 +1,71 @@
# CONFIG_DEV_NULL is not set
# CONFIG_LIBC_LONG_LONG is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="nucleo-f334r8"
CONFIG_ARCH_BOARD_NUCLEO_F334R8=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F334R8=y
CONFIG_ARCH_HIPRI_INTERRUPT=y
CONFIG_ARCH_RAMVECTORS=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BUILTIN=y
CONFIG_BUILTIN_PROXY_STACKSIZE=512
CONFIG_DEBUG_FULLOPT=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_DISABLE_ENVIRON=y
CONFIG_DISABLE_MQUEUE=y
CONFIG_DISABLE_POLL=y
CONFIG_DISABLE_POSIX_TIMERS=y
CONFIG_FDCLONE_STDIO=y
CONFIG_INTELHEX_BINARY=y
CONFIG_LIBC_FLOATINGPOINT=y
CONFIG_LIBM=y
CONFIG_LIB_BOARDCTL=y
CONFIG_MAX_TASKS=4
CONFIG_MAX_WDOGPARMS=1
CONFIG_NAME_MAX=16
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_NUCLEOF334R8_SPWM=y
CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM=4
CONFIG_NUCLEOF334R8_SPWM_PWM_FREQ=100000
CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=512
CONFIG_PREALLOC_TIMERS=2
CONFIG_PREALLOC_WDOGS=1
CONFIG_PTHREAD_STACK_DEFAULT=1024
CONFIG_PTHREAD_STACK_MIN=1024
CONFIG_RAM_SIZE=12288
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_SDCLONE_DISABLE=y
CONFIG_START_DAY=6
CONFIG_START_MONTH=12
CONFIG_START_YEAR=2011
CONFIG_STM32_CCMEXCLUDE=y
CONFIG_STM32_JTAG_SW_ENABLE=y
CONFIG_STM32_PWM_LL_OPS=y
CONFIG_STM32_PWM_MULTICHAN=y
CONFIG_STM32_PWR=y
CONFIG_STM32_TIM1=y
CONFIG_STM32_TIM1_CH1OUT=y
CONFIG_STM32_TIM1_CH2OUT=y
CONFIG_STM32_TIM1_CH3OUT=y
CONFIG_STM32_TIM1_CH4OUT=y
CONFIG_STM32_TIM1_CHANNEL1=y
CONFIG_STM32_TIM1_CHANNEL2=y
CONFIG_STM32_TIM1_CHANNEL3=y
CONFIG_STM32_TIM1_CHANNEL4=y
CONFIG_STM32_TIM1_PWM=y
CONFIG_STM32_TIM6=y
CONFIG_STM32_USART2=y
CONFIG_SYSTEM_READLINE=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=512
CONFIG_USART2_SERIAL_CONSOLE=y
CONFIG_USERMAIN_STACKSIZE=1024
CONFIG_USER_ENTRYPOINT="spwm_main"
CONFIG_WDOG_INTRESERVE=0

4
configs/nucleo-f334r8/src/Makefile
View File

@ -92,4 +92,8 @@ ifeq ($(CONFIG_NUCLEOF334R8_HIGHPRI),y)
CSRCS += stm32_highpri.c
endif
ifeq ($(CONFIG_NUCLEOF334R8_SPWM),y)
CSRCS += stm32_spwm.c
endif
include $(TOPDIR)/configs/Board.mk

3
configs/nucleo-f334r8/src/stm32_hrtim.c
View File

@ -47,8 +47,7 @@
#include "stm32_hrtim.h"
#if defined(CONFIG_STM32_HRTIM) && defined(CONFIG_STM32_HRTIM1) && \
!defined(CONFIG_NUCLEOF334R8_HIGHPRI)
#ifndef CONFIG_STM32_HRTIM_DISABLE_CHARDRV
/****************************************************************************
* Public Functions

1057
configs/nucleo-f334r8/src/stm32_spwm.c Normal file
View File

File diff suppressed because it is too large Load Diff

2
configs/stm32f429i-disco/highpri/defconfig
View File

@ -1,6 +1,4 @@
# CONFIG_STM32_FLASH_PREFETCH is not set
CONFIG_ADC=y
CONFIG_ANALOG=y
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="stm32f429i-disco"
CONFIG_ARCH_BOARD_STM32F429I_DISCO=y

3
include/nuttx/drivers/pwm.h
View File

@ -61,8 +61,6 @@
#include <nuttx/fs/ioctl.h>
#ifdef CONFIG_PWM
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@ -326,5 +324,4 @@ void pwm_expired(FAR void *handle);
}
#endif
#endif /* CONFIG_PWM */
#endif /* __INCLUDE_NUTTX_DRIVERS_PWM_H */