From b3d0574c985fe7e801305f5da2cebef9eac9089c Mon Sep 17 00:00:00 2001 From: Freemans Goden Date: Sun, 16 Sep 2018 05:50:35 -0600 Subject: [PATCH] configs/b-l475e-iot01a/include/b-l475e-iot01a_clock.h: Correct timer source clock frequencies. --- .../include/b-l475e-iot01a_clock.h | 57 +++++++++++-------- 1 file changed, 32 insertions(+), 25 deletions(-) diff --git a/configs/b-l475e-iot01a/include/b-l475e-iot01a_clock.h b/configs/b-l475e-iot01a/include/b-l475e-iot01a_clock.h index b8e6028952..3c190972f9 100644 --- a/configs/b-l475e-iot01a/include/b-l475e-iot01a_clock.h +++ b/configs/b-l475e-iot01a/include/b-l475e-iot01a_clock.h @@ -81,7 +81,7 @@ * PLLSAI1Q : 4 * Flash Latency(WS) : 4 * Prefetch Buffer : OFF - * 48MHz for USB OTG FS, : Doable if required using PLLSAI1 or MSI + * 48MHz for USB SDMMC OTG FS, : Doable if required using PLLSAI1 or MSI * SDIO and RNG clock */ @@ -272,28 +272,35 @@ /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ #define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) -/* Timers driven from APB1 will be twice PCLK1 */ +/* Timers driven from APB1 will be twice PCLK1, when + * NOT define STM32L4_RCC_CFGR_PPRE1 as RCC_CFGR_PPRE1_HCLK. + */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM2_CLKIN STM32L4_PCLK1_FREQUENCY +#define STM32L4_APB1_TIM3_CLKIN STM32L4_PCLK1_FREQUENCY +#define STM32L4_APB1_TIM4_CLKIN STM32L4_PCLK1_FREQUENCY +#define STM32L4_APB1_TIM5_CLKIN STM32L4_PCLK1_FREQUENCY +#define STM32L4_APB1_TIM6_CLKIN STM32L4_PCLK1_FREQUENCY +#define STM32L4_APB1_TIM7_CLKIN STM32L4_PCLK1_FREQUENCY +#define STM32L4_APB1_LPTIM1_CLKIN STM32L4_PCLK1_FREQUENCY +#define STM32L4_APB1_LPTIM2_CLKIN STM32L4_PCLK1_FREQUENCY /* APB2 clock (PCLK2) is HCLK (80MHz) */ #define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32L4_APB2_TIM1_CLKIN STM32L4_PCLK2_FREQUENCY +#define STM32L4_APB2_TIM8_CLKIN STM32L4_PCLK2_FREQUENCY +#define STM32L4_APB2_TIM15_CLKIN STM32L4_PCLK2_FREQUENCY +#define STM32L4_APB2_TIM16_CLKIN STM32L4_PCLK2_FREQUENCY +#define STM32L4_APB2_TIM17_CLKIN STM32L4_PCLK2_FREQUENCY /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -469,19 +476,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) +#define BOARD_TIM1_FREQUENCY STM32L4_APB2_TIM1_CLKIN +#define BOARD_TIM2_FREQUENCY STM32L4_APB1_TIM2_CLKIN +#define BOARD_TIM3_FREQUENCY STM32L4_APB1_TIM3_CLKIN +#define BOARD_TIM4_FREQUENCY STM32L4_APB1_TIM4_CLKIN +#define BOARD_TIM5_FREQUENCY STM32L4_APB1_TIM5_CLKIN +#define BOARD_TIM6_FREQUENCY STM32L4_APB1_TIM6_CLKIN +#define BOARD_TIM7_FREQUENCY STM32L4_APB1_TIM7_CLKIN +#define BOARD_TIM8_FREQUENCY STM32L4_APB2_TIM8_CLKIN +#define BOARD_TIM15_FREQUENCY STM32L4_APB2_TIM15_CLKIN +#define BOARD_TIM16_FREQUENCY STM32L4_APB2_TIM16_CLKIN +#define BOARD_TIM17_FREQUENCY STM32L4_APB2_TIM17_CLKIN +#define BOARD_LPTIM1_FREQUENCY STM32L4_APB1_LPTIM1_CLKIN +#define BOARD_LPTIM2_FREQUENCY STM32L4_APB1_LPTIM2_CLKIN /************************************************************************************ * Public Data