arch/arm/src/armv7-m and arch/arm/src/lc823450: Fix support for multiple interrupt stacks needed in SMP mode. This was broken in the last set of commits that force all architectures to use the common interrupt vector logic.
This commit is contained in:
Gregory Nutt
parent
10903b5b2e
commit
b3f61e8a4a
11
TODO
11
TODO
@ -1,4 +1,4 @@
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NuttX TODO List (Last updated June 16, 2018)
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NuttX TODO List (Last updated June 20, 2018)
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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This file summarizes known NuttX bugs, limitations, inconsistencies with
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@ -10,7 +10,7 @@ issues related to each board port.
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nuttx/:
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(15) Task/Scheduler (sched/)
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(3) SMP
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(4) SMP
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(1) Memory Management (mm/)
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(0) Power Management (drivers/pm)
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(3) Signals (sched/signal, arch/)
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@ -482,6 +482,13 @@ o SMP
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simplification in the design and permit commonality with
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other, non-GIC imoplementations.
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Title: BAD INTERRUPTSTACK LOGIC FOR ARMv7-A IN SMP CONFIGURATION
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Description: The handler at arch/arm/src/armv7-a/arm_vectors.S supports
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only a single interrupt stack. In SMP mode, that same
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interrupt stack is used for all CPUs. That cannot work.
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Status: Open
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Priority: High
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o Memory Management (mm/)
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^^^^^^^^^^^^^^^^^^^^^^^
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@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/armv7-m/gnu/up_exception.S
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*
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* Copyright (C) 2009-2013, 2015-2016 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009-2013, 2015-2016, 2018 Gregory Nutt. All rights reserved.
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* Copyright (C) 2012 Michael Smith. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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@ -44,6 +44,9 @@
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#include "exc_return.h"
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#include "chip.h"
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#ifdef CONFIG_SMP
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# include "smp_macros.h"
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#endif
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/************************************************************************************
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* Pre-processor Definitions
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@ -89,6 +92,16 @@
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.thumb
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.file "up_exception.S"
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/************************************************************************************
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* Macro Definitions
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************************************************************************************/
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#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
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.macro setintstack, tmp
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ldr sp, =g_intstackbase
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.endm
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#endif
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/************************************************************************************
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* .text
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************************************************************************************/
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@ -193,7 +206,7 @@ exception_common:
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* here prohibits nested interrupts without some additional logic!
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*/
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ldr sp, =g_intstackbase
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setintstack r2
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#else
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/* Otherwise, we will re-use the interrupted thread's stack. That may
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@ -317,7 +330,7 @@ exception_common:
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*
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************************************************************************************/
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#if CONFIG_ARCH_INTERRUPTSTACK > 7
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#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
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.bss
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.global g_intstackalloc
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.global g_intstackbase
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@ -1,7 +1,7 @@
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/************************************************************************************************
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* arch/arm/src/armv7-m/gnu/up_lazyexcption.S
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*
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* Copyright (C) 2009-2010, 2013-2016 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009-2010, 2013-2016, 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -43,6 +43,9 @@
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#include "exc_return.h"
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#include "chip.h"
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#ifdef CONFIG_SMP
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# include "smp_macros.h"
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#endif
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/************************************************************************************************
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* Pre-processor Definitions
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@ -86,6 +89,16 @@
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.thumb
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.file "up_lazyexception.S"
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/************************************************************************************************
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* Macro Definitions
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************************************************************************************************/
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#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
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.macro setintstack, tmp
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ldr sp, =g_intstackbase
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.endm
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#endif
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/************************************************************************************************
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* .text
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************************************************************************************************/
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@ -201,7 +214,7 @@ exception_common:
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* here prohibits nested interrupts without some additional logic!
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*/
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ldr sp, =g_intstackbase
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setintstack r2
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#else
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/* Otherwise, we will re-use the interrupted thread's stack. That may
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@ -349,7 +362,7 @@ exception_common:
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*
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************************************************************************************************/
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#if CONFIG_ARCH_INTERRUPTSTACK > 7
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#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
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.bss
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.global g_intstackalloc
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.global g_intstackbase
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@ -93,3 +93,4 @@ unsigned _vectors[] __attribute__((section(".vectors"))) =
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[2 ... (15 + ARMV7M_PERIPHERAL_INTERRUPTS)] = (unsigned)&exception_common
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};
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@ -80,6 +80,21 @@
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#define NVIC_ENA_OFFSET (0)
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#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
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/****************************************************************************
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* Private Data
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****************************************************************************/
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#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
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/* In the SMP configuration, we will need two custom interrupt stacks.
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* These definitions provide the aligned stack allocations.
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*/
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static uint64_t g_cpu0_instack_alloc[CONFIG_ARCH_INTERRUPTSTACK >> 3];
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#if CONFIG_SMP_NCPUS > 1
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static uint64_t g_cpu1_instack_alloc[CONFIG_ARCH_INTERRUPTSTACK >> 3];
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#endif
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#endif
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/****************************************************************************
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* Public Data
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****************************************************************************/
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@ -94,6 +109,19 @@ volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
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volatile uint32_t *g_current_regs[1];
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#endif
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#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
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/* In the SMP configuration, we will need two custom interrupt stacks.
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* These defintions provide the "top" of the push-down stacks.
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*/
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const uint32_t g_cpu0_instack_base = (uint32_t)g_cpu0_instack_alloc +
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sizeof(g_cpu0_instack_alloc);
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#if CONFIG_SMP_NCPUS > 1
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const uint32_t g_cpu1_instack_base = (uint32_t)g_cpu1_instack_alloc +
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sizeof(g_cpu1_instack_alloc);
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#endif
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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86
arch/arm/src/lc823450/smp_macros.h
Normal file
86
arch/arm/src/lc823450/smp_macros.h
Normal file
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/****************************************************************************
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* arch/arm/src/lc823450/smp_macros.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_LC823450_SMP_MACROS_H
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#define __ARCH_ARM_SRC_LC823450_SMP_MACROS_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#if defined(__ASSEMBLY__) && defined(CONFIG_SMP)
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define COREID_REG 0xe00fe000
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/****************************************************************************
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* Imported Public Data
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****************************************************************************/
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#if CONFIG_ARCH_INTERRUPTSTACK > 7
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.globl g_cpu0_instack_base
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.globl g_cpu1_instack_base
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#endif
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/****************************************************************************
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* Macro Definitions
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****************************************************************************/
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#if CONFIG_ARCH_INTERRUPTSTACK > 7
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.macro setintstack, tmp
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#if CONFIG_SMP_NCPUS > 1
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ldr \tmp, =COREID_REG
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ldr \tmp, [\tmp, 0] /* \tmp = getreg32(coreid_reg) */
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and \tmp, \tmp, 1 /* \tmp = COREID */
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cmp \tmp, #0
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bne 1f
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ldr sp, =g_cpu0_instack_base
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b 2f
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1:
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ldr sp, =g_cpu1_instack_base
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2:
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#else
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ldr sp, =g_cpu0_instack_base
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#endif
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.endm
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#endif
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#endif /* __ASSEMBLY__ && CONFIG_SMP */
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#endif /* __ARCH_ARM_SRC_LC823450_SMP_MACROS_H */
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@ -158,11 +158,15 @@ Status
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writing. Insufficient stress testing has been done to prove that the
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solution is stable.
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2018: Again revisited SMP. There appears to be a memory corruption problem.
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2018-06-08: Again revisited SMP. There appears to be a memory corruption problem.
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This is rarely seen with the SMP test but you enable the OS test in the smp
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configuration, you will see a crash due to memory corruption consistently,
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specially in the nested signal test (apps/examples/ostest/signest.c).
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2018-06-20: There is a problem with the Interrupt Stack for SMP in
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arch/arm/src/armv7-a/arm_vectors.S: There is only one interrupt stack for
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all CPUs!
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Platform Features
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=================
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