diff --git a/TODO b/TODO index e9dcf61970..8d4a244215 100644 --- a/TODO +++ b/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated June 16, 2018) +NuttX TODO List (Last updated June 20, 2018) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with @@ -10,7 +10,7 @@ issues related to each board port. nuttx/: (15) Task/Scheduler (sched/) - (3) SMP + (4) SMP (1) Memory Management (mm/) (0) Power Management (drivers/pm) (3) Signals (sched/signal, arch/) @@ -482,6 +482,13 @@ o SMP simplification in the design and permit commonality with other, non-GIC imoplementations. + Title: BAD INTERRUPTSTACK LOGIC FOR ARMv7-A IN SMP CONFIGURATION + Description: The handler at arch/arm/src/armv7-a/arm_vectors.S supports + only a single interrupt stack. In SMP mode, that same + interrupt stack is used for all CPUs. That cannot work. + Status: Open + Priority: High + o Memory Management (mm/) ^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/arch/arm/src/armv7-m/gnu/up_exception.S b/arch/arm/src/armv7-m/gnu/up_exception.S index 81096aaefe..f829105ae1 100644 --- a/arch/arm/src/armv7-m/gnu/up_exception.S +++ b/arch/arm/src/armv7-m/gnu/up_exception.S @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/armv7-m/gnu/up_exception.S * - * Copyright (C) 2009-2013, 2015-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2013, 2015-2016, 2018 Gregory Nutt. All rights reserved. * Copyright (C) 2012 Michael Smith. All rights reserved. * Author: Gregory Nutt * @@ -44,6 +44,9 @@ #include "exc_return.h" #include "chip.h" +#ifdef CONFIG_SMP +# include "smp_macros.h" +#endif /************************************************************************************ * Pre-processor Definitions @@ -89,6 +92,16 @@ .thumb .file "up_exception.S" +/************************************************************************************ + * Macro Definitions + ************************************************************************************/ + +#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 + .macro setintstack, tmp + ldr sp, =g_intstackbase + .endm +#endif + /************************************************************************************ * .text ************************************************************************************/ @@ -193,7 +206,7 @@ exception_common: * here prohibits nested interrupts without some additional logic! */ - ldr sp, =g_intstackbase + setintstack r2 #else /* Otherwise, we will re-use the interrupted thread's stack. That may @@ -317,7 +330,7 @@ exception_common: * ************************************************************************************/ -#if CONFIG_ARCH_INTERRUPTSTACK > 7 +#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 .bss .global g_intstackalloc .global g_intstackbase diff --git a/arch/arm/src/armv7-m/gnu/up_lazyexception.S b/arch/arm/src/armv7-m/gnu/up_lazyexception.S index 852883aa22..28f0d320d7 100644 --- a/arch/arm/src/armv7-m/gnu/up_lazyexception.S +++ b/arch/arm/src/armv7-m/gnu/up_lazyexception.S @@ -1,7 +1,7 @@ /************************************************************************************************ * arch/arm/src/armv7-m/gnu/up_lazyexcption.S * - * Copyright (C) 2009-2010, 2013-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010, 2013-2016, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -43,6 +43,9 @@ #include "exc_return.h" #include "chip.h" +#ifdef CONFIG_SMP +# include "smp_macros.h" +#endif /************************************************************************************************ * Pre-processor Definitions @@ -86,6 +89,16 @@ .thumb .file "up_lazyexception.S" +/************************************************************************************************ + * Macro Definitions + ************************************************************************************************/ + +#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 + .macro setintstack, tmp + ldr sp, =g_intstackbase + .endm +#endif + /************************************************************************************************ * .text ************************************************************************************************/ @@ -201,7 +214,7 @@ exception_common: * here prohibits nested interrupts without some additional logic! */ - ldr sp, =g_intstackbase + setintstack r2 #else /* Otherwise, we will re-use the interrupted thread's stack. That may @@ -349,7 +362,7 @@ exception_common: * ************************************************************************************************/ -#if CONFIG_ARCH_INTERRUPTSTACK > 7 +#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 .bss .global g_intstackalloc .global g_intstackbase diff --git a/arch/arm/src/armv7-m/up_vectors.c b/arch/arm/src/armv7-m/up_vectors.c index ada819c331..8325928f75 100644 --- a/arch/arm/src/armv7-m/up_vectors.c +++ b/arch/arm/src/armv7-m/up_vectors.c @@ -93,3 +93,4 @@ unsigned _vectors[] __attribute__((section(".vectors"))) = [2 ... (15 + ARMV7M_PERIPHERAL_INTERRUPTS)] = (unsigned)&exception_common }; + diff --git a/arch/arm/src/lc823450/lc823450_irq.c b/arch/arm/src/lc823450/lc823450_irq.c index 23f720234a..c111bc10aa 100644 --- a/arch/arm/src/lc823450/lc823450_irq.c +++ b/arch/arm/src/lc823450/lc823450_irq.c @@ -80,6 +80,21 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 +/* In the SMP configuration, we will need two custom interrupt stacks. + * These definitions provide the aligned stack allocations. + */ + +static uint64_t g_cpu0_instack_alloc[CONFIG_ARCH_INTERRUPTSTACK >> 3]; +#if CONFIG_SMP_NCPUS > 1 +static uint64_t g_cpu1_instack_alloc[CONFIG_ARCH_INTERRUPTSTACK >> 3]; +#endif +#endif + /**************************************************************************** * Public Data ****************************************************************************/ @@ -94,6 +109,19 @@ volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; volatile uint32_t *g_current_regs[1]; #endif +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 +/* In the SMP configuration, we will need two custom interrupt stacks. + * These defintions provide the "top" of the push-down stacks. + */ + +const uint32_t g_cpu0_instack_base = (uint32_t)g_cpu0_instack_alloc + + sizeof(g_cpu0_instack_alloc); +#if CONFIG_SMP_NCPUS > 1 +const uint32_t g_cpu1_instack_base = (uint32_t)g_cpu1_instack_alloc + + sizeof(g_cpu1_instack_alloc); +#endif +#endif + /**************************************************************************** * Private Data ****************************************************************************/ diff --git a/arch/arm/src/lc823450/smp_macros.h b/arch/arm/src/lc823450/smp_macros.h new file mode 100644 index 0000000000..c8685ff788 --- /dev/null +++ b/arch/arm/src/lc823450/smp_macros.h @@ -0,0 +1,86 @@ +/**************************************************************************** + * arch/arm/src/lc823450/smp_macros.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LC823450_SMP_MACROS_H +#define __ARCH_ARM_SRC_LC823450_SMP_MACROS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(__ASSEMBLY__) && defined(CONFIG_SMP) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define COREID_REG 0xe00fe000 + +/**************************************************************************** + * Imported Public Data + ****************************************************************************/ + +#if CONFIG_ARCH_INTERRUPTSTACK > 7 + .globl g_cpu0_instack_base + .globl g_cpu1_instack_base +#endif + +/**************************************************************************** + * Macro Definitions + ****************************************************************************/ + +#if CONFIG_ARCH_INTERRUPTSTACK > 7 + .macro setintstack, tmp +#if CONFIG_SMP_NCPUS > 1 + ldr \tmp, =COREID_REG + ldr \tmp, [\tmp, 0] /* \tmp = getreg32(coreid_reg) */ + and \tmp, \tmp, 1 /* \tmp = COREID */ + cmp \tmp, #0 + bne 1f + ldr sp, =g_cpu0_instack_base + b 2f +1: + ldr sp, =g_cpu1_instack_base +2: +#else + ldr sp, =g_cpu0_instack_base +#endif + .endm +#endif + +#endif /* __ASSEMBLY__ && CONFIG_SMP */ +#endif /* __ARCH_ARM_SRC_LC823450_SMP_MACROS_H */ diff --git a/configs/sabre-6quad/README.txt b/configs/sabre-6quad/README.txt index 628ddfbc1e..f07582b62c 100644 --- a/configs/sabre-6quad/README.txt +++ b/configs/sabre-6quad/README.txt @@ -158,11 +158,15 @@ Status writing. Insufficient stress testing has been done to prove that the solution is stable. -2018: Again revisited SMP. There appears to be a memory corruption problem. +2018-06-08: Again revisited SMP. There appears to be a memory corruption problem. This is rarely seen with the SMP test but you enable the OS test in the smp configuration, you will see a crash due to memory corruption consistently, specially in the nested signal test (apps/examples/ostest/signest.c). +2018-06-20: There is a problem with the Interrupt Stack for SMP in + arch/arm/src/armv7-a/arm_vectors.S: There is only one interrupt stack for + all CPUs! + Platform Features =================