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arch/z80/src/ez80/ez80f92.h: Fix some bad copy-paste.

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Gregory Nutt 2020-02-19 17:22:53 -06:00 committed by Abdelatif Guettouche
parent 647f2f44df
commit b403bfecd5
1 changed files with 6 additions and 6 deletions
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12
arch/z80/src/ez80/ez80f92.h
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@ -16,22 +16,22 @@
* License for the specific language governing permissions and limitations
* under the License.
*
*********************************************************************************;
************************************************************************************/
#ifndef __ARCH_Z80_SRC_EZ80_EZ80F92_H
#define __ARCH_Z80_SRC_EZ80_EZ80F92_H
/************************************************************************************
* Included Files
*********************************************************************************;
************************************************************************************/
#include "ez80f91_emac.h"
/************************************************************************************
* Pre-processor Definitions
*********************************************************************************;
************************************************************************************/
/* Memory map ********************************************************************;
/* Memory map ***********************************************************************/
#define EZ80_ONCHIPFLASH 0x000000 /* CS0: 128Kb of on-chip flash */
#define EZ80_OFFCHIPCS0 0x400000 /* CS0: Off chip use (usually flash) */
@ -39,13 +39,13 @@
#define EZ80_OFFCHIPCS1 0xc00000 /* CS1: Off chip use (usually SRAM) */
#define EZ80_ONCHIPSRAM 0xffe000 /* On-chip SRAM (8Kb) on reset */
/* Product ID Registers *********************************************************;
/* Product ID Registers ************************************************************/
#define EZ80_ZDI_ID_L 0x00
#define EZ80_ZDI_ID_H 0x01
#define EZ80_ZDI_ID_REV 0x02
/* Timer Registers **************************************************************;
/* Timer Registers *****************************************************************/
#define EZ80_TMR0_CTL 0x80 /* RW: Timer 0 control register */
#define EZ80_TMR0_DRL 0x81 /* R : Timer 0 data register (low) */