SAMA5D4: Update PWM header file
This commit is contained in:
Gregory Nutt
parent
39cb768969
commit
b43fa3910a
@ -60,7 +60,11 @@
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#define SAM_PWM_IMR1_OFFSET 0x0018 /* PWM Interrupt Mask Register 1 */
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#define SAM_PWM_ISR1_OFFSET 0x001c /* PWM Interrupt Status Register 1 */
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#define SAM_PWM_SCM_OFFSET 0x0020 /* PWM Sync Channels Mode Register */
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/* 0x0024 Reserved */
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#ifdef ATSAMA5D4
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# define SAM_PWM_DMAR_OFFSET 0x0024 /* PWM DMA Register */
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#endif
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#define SAM_PWM_SCUC_OFFSET 0x0028 /* PWM Sync Channels Update Control Register */
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#define SAM_PWM_SCUP_OFFSET 0x002c /* PWM Sync Channels Update Period Register */
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#define SAM_PWM_SCUPUPD_OFFSET 0x0030 /* PWM Sync Channels Update Period Update Register */
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@ -77,14 +81,23 @@
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#define SAM_PWM_FMR_OFFSET 0x005c /* PWM Fault Mode Register */
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#define SAM_PWM_FSR_OFFSET 0x0060 /* PWM Fault Status Register */
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#define SAM_PWM_FCR_OFFSET 0x0064 /* PWM Fault Clear Register */
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#define SAM_PWM_FPV_OFFSET 0x0068 /* PWM Fault Protection Value Register */
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#define SAM_PWM_FPV_OFFSET 0x0068 /* PWM Fault Protection Value Register 1 */
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#define SAM_PWM_FPE_OFFSET 0x006c /* PWM Fault Protection Enable Register */
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/* 0x0070-0x0078 Reserved */
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#define SAM_PWM_ELMR0_OFFSET 0x007c /* PWM Event Line 0 Mode Register */
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#define SAM_PWM_ELMR1_OFFSET 0x0080 /* PWM Event Line 1 Mode Register */
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/* 0x0084-0x00ac Reserved */
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#ifdef ATSAMA5D4
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# define SAM_PWM_SSPR_OFFSET 0x00a0 /* PWM Spread Spectrum Register */
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# define SAM_PWM_SSPUP_OFFSET 0x00a4 /* PWM Spread Spectrum Update Register */
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#endif
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#define SAM_PWM_SMMR_OFFSET 0x00b0 /* PWM Stepper Motor Mode Register */
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/* 0x00b4-0x00e0 Reserved */
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#ifdef ATSAMA5D4
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# define SAM_PWM_FPV2_OFFSET 0x00c0 /* PWM Fault Protection Value Register 2 */
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#endif
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#define SAM_PWM_WPCR_OFFSET 0x00e4 /* PWM Write Protect Control Register */
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#define SAM_PWM_WPSR_OFFSET 0x00e8 /* PWM Write Protect Status Register */
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/* 0x00ec - 0x00fc Reserved */
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@ -133,10 +146,8 @@
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#define SAM_PWM_CMPVUPD7_OFFSET 0x01a4 /* PWM Comparison 7 Value Update Register */
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#define SAM_PWM_CMPM7_OFFSET 0x01a8 /* PWM Comparison 7 Mode Register */
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#define SAM_PWM_CMPMUPD7_OFFSET 0x01ac /* PWM Comparison 7 Mode Update Register */
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/* 0x01b0 - 0x01fc Reserved */
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#define SAM_PWM_CHAN_OFFSET(n) (0x0200 + ((int)(n) << 5)) /* n=0..3 */
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#define SAM_PWM_CHANA_OFFSET(n) (0x0200 + ((int)(n) << 5)) /* n=0..3 */
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#define SAM_PWM_CMR_OFFSET 0x0000 /* PWM Channel Mode Register */
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#define SAM_PWM_CDTY_OFFSET 0x0004 /* PWM Channel Duty Cycle Register */
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#define SAM_PWM_CDTYUPD_OFFSET 0x0008 /* PWM Channel Duty Cycle Update Register */
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@ -146,6 +157,13 @@
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#define SAM_PWM_DT_OFFSET 0x0018 /* PWM Channel Dead Time Register */
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#define SAM_PWM_DTUPD_OFFSET 0x001c /* PWM Channel Dead Time Update Register */
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#define SAM_PWM_CHANAB_DELTA 0x0200 /* Offset of second group from the first */
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#ifdef ATSAMA5D4
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# define SAM_PWM_CHANB_OFFSET(n) (0x0400 + ((int)(n) << 5)) /* n=0..3 */
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# define SAM_PWM_CMUPD_OFFSET 0x0000 /* PWM Channel Mode Update Register */
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#endif
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/* PWM Register Addresses ***********************************************************/
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#define SAM_PWM_CLK (SAM_PWMC_VBASE+SAM_PWM_CLK_OFFSET)
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@ -157,6 +175,11 @@
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#define SAM_PWM_IMR1 (SAM_PWMC_VBASE+SAM_PWM_IMR1_OFFSET)
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#define SAM_PWM_ISR1 (SAM_PWMC_VBASE+SAM_PWM_ISR1_OFFSET)
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#define SAM_PWM_SCM (SAM_PWMC_VBASE+SAM_PWM_SCM_OFFSET)
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#ifdef ATSAMA5D4
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# define SAM_PWM_DMAR (SAM_PWMC_VBASE+SAM_PWM_DMAR_OFFSET)
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#endif
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#define SAM_PWM_SCUC (SAM_PWMC_VBASE+SAM_PWM_SCUC_OFFSET)
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#define SAM_PWM_SCUP (SAM_PWMC_VBASE+SAM_PWM_SCUP_OFFSET)
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#define SAM_PWM_SCUPUPD (SAM_PWMC_VBASE+SAM_PWM_SCUPUPD_OFFSET)
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@ -177,7 +200,18 @@
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#define SAM_PWM_FPE (SAM_PWMC_VBASE+SAM_PWM_FPE_OFFSET)
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#define SAM_PWM_ELMR0 (SAM_PWMC_VBASE+SAM_PWM_ELMR0_OFFSET)
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#define SAM_PWM_ELMR1 (SAM_PWMC_VBASE+SAM_PWM_ELMR1_OFFSET)
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#ifdef ATSAMA5D4
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# define SAM_PWM_SSPR (SAM_PWMC_VBASE+SAM_PWM_SSPR_OFFSET)
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# define SAM_PWM_SSPUP (SAM_PWMC_VBASE+SAM_PWM_SSPUP_OFFSET)
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#endif
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#define SAM_PWM_SMMR (SAM_PWMC_VBASE+SAM_PWM_SMMR_OFFSET)
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#ifdef ATSAMA5D4
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# define SAM_PWM_FPV2 (SAM_PWMC_VBASE+SAM_PWM_FPV2_OFFSET)
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#endif
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#define SAM_PWM_WPCR (SAM_PWMC_VBASE+SAM_PWM_WPCR_OFFSET)
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#define SAM_PWM_WPSR (SAM_PWMC_VBASE+SAM_PWM_WPSR_OFFSET)
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@ -226,15 +260,20 @@
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#define SAM_PWM_CMPM7 (SAM_PWMC_VBASE+SAM_PWM_CMPM7_OFFSET)
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#define SAM_PWM_CMPMUPD7 (SAM_PWMC_VBASE+SAM_PWM_CMPMUPD7_OFFSET)
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#define SAM_PWM_CHAN_BASE(n) (SAM_PWMC_VBASE+SAM_PWM_CHAN_OFFSET(n))
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#define SAM_PWM_CMR (SAM_PWMC_VBASE+SAM_PWM_CMR_OFFSET)
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#define SAM_PWM_CDTY (SAM_PWMC_VBASE+SAM_PWM_CDTY_OFFSET)
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#define SAM_PWM_CDTYUPD (SAM_PWMC_VBASE+SAM_PWM_CDTYUPD_OFFSET)
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#define SAM_PWM_CPRD (SAM_PWMC_VBASE+SAM_PWM_CPRD_OFFSET)
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#define SAM_PWM_CPRDUPD (SAM_PWMC_VBASE+SAM_PWM_CPRDUPD_OFFSET)
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#define SAM_PWM_CCNT (SAM_PWMC_VBASE+SAM_PWM_CCNT_OFFSET)
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#define SAM_PWM_DT (SAM_PWMC_VBASE+SAM_PWM_DT_OFFSET)
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#define SAM_PWM_DTUPD (SAM_PWMC_VBASE+SAM_PWM_DTUPD_OFFSET)
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#define SAM_PWM_CHANA_BASE(n) (SAM_PWMC_VBASE+SAM_PWM_CHANA_OFFSET(n))
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#define SAM_PWM_CMR(n) (SAM_PWM_CHANA_BASE(n)+SAM_PWM_CMR_OFFSET)
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#define SAM_PWM_CDTY(n) (SAM_PWM_CHANA_BASE(n)+SAM_PWM_CDTY_OFFSET)
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#define SAM_PWM_CDTYUPD(n) (SAM_PWM_CHANA_BASE(n)+SAM_PWM_CDTYUPD_OFFSET)
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#define SAM_PWM_CPRD(n) (SAM_PWM_CHANA_BASE(n)+SAM_PWM_CPRD_OFFSET)
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#define SAM_PWM_CPRDUPD(n) (SAM_PWM_CHANA_BASE(n)+SAM_PWM_CPRDUPD_OFFSET)
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#define SAM_PWM_CCNT(n) (SAM_PWM_CHANA_BASE(n)+SAM_PWM_CCNT_OFFSET)
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#define SAM_PWM_DT(n) (SAM_PWM_CHANA_BASE(n)+SAM_PWM_DT_OFFSET)
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#define SAM_PWM_DTUPD(n) (SAM_PWM_CHANA_BASE(n)+SAM_PWM_DTUPD_OFFSET)
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#ifdef ATSAMA5D4
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# define SAM_PWM_CHANB_BASE(n) (SAM_PWMC_VBASE+define SAM_PWM_CHANB_OFFSET(n))
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# define SAM_PWM_CMUPD(n) (SAM_PWM_CHANB_BASE(n)+SAM_PWM_CMUPD_OFFSET)
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#endif
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/* PWM Register Bit Definitions *****************************************************/
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@ -290,13 +329,31 @@
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/* PWM Sync Channels Mode Register */
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#define PWM_SCM_SYNC(n) (1 << (n)) /* Bits 0-3: Synchronous Channel n, n=0..3 */
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#define PWM_SCM_SYNC0 (1 << 0) /* Bits 0: Synchronous Channel n, n=0..3 */
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#define PWM_SCM_UPDM_SHIFT (16) /* Bits 16-17: Synchronous Channels Update Mode */
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#define PWM_SCM_SYNC(n) (1 << (n)) /* Bits 0-3: Synchronous Channel n, n=0..3 */
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# define PWM_SCM_SYNC0 (1 << 0) /* Bits 0: Synchronous Channel 0 */
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# define PWM_SCM_SYNC1 (1 << 1) /* Bits 1: Synchronous Channel 1 */
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# define PWM_SCM_SYNC2 (1 << 2) /* Bits 2: Synchronous Channel 2 */
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# define PWM_SCM_SYNC3 (1 << 3) /* Bits 3: Synchronous Channel 3 */
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#define PWM_SCM_UPDM_SHIFT (16) /* Bits 16-17: Synchronous Channels Update Mode */
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#define PWM_SCM_UPDM_MASK (3 << PWM_SCM_UPDM_SHIFT)
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# define PWM_SCM_UPDM_MODE0 (0 << PWM_SCM_UPDM_SHIFT) /* Manual double buffer / manual channel update */
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# define PWM_SCM_UPDM_MODE1 (1 << PWM_SCM_UPDM_SHIFT) /* Manual double buffer / automatic channel update */
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#ifdef ATSAMA5D4
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# define PWM_SCM_PTRM (1 << 20) /* Bit 20: DMA Transfer Request Mode */
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# define PWM_SCM_PTRCS_SHIFT (21) /* Bits 21-23: DMA Transfer Request Comparison Selection */
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# define PWM_SCM_PTRCS_MASK (7 << PWM_SCM_PTRCS_SHIFT)
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# define PWM_SCM_PTRCS(n) ((uint32_t)(n) << PWM_SCM_PTRCS_SHIFT)
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#endif
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#ifdef ATSAMA5D4
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/* PWM DMA Register */
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# define PWM_DMAR_DMADUTY_SHIFT (0) /* Bits 0-23: Duty-Cycle Holding Register for DMA Access */
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# define PWM_DMAR_DMADUTY_MASK (0x00ffffff << PWM_DMAR_DMADUTY_SHIFT)
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# define PWM_DMAR_DMADUTY(n) ((uint32_t)(n) << PWM_DMAR_DMADUTY_SHIFT)
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#endif
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/* PWM Sync Channels Update Control Register */
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#define PWM_SCUC_UPDULOCK (1 << 0) /* Bit 0: Synchronous Channels Update Unlock */
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@ -443,11 +500,11 @@
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/* PWM Fault Clear Register */
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#define PWM_FSR_FIV_SHIFT (0) /* Bits 0-7: Fault Clear */
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#define PWM_FSR_FIV_MASK (0xff << PWM_FSR_FIV_SHIFT)
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# define PWM_FCR_FIV(n) (1 << (n)) /* Fault Clear n, n=0..7 */
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#define PWM_FCR_FCLR_SHIFT (0) /* Bits 0-7: Fault Clear */
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#define PWM_FCR_FCLR_MASK (0xff << PWM_FCR_FCLR_SHIFT)
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# define PWM_FCR_FCLR(n) (1 << (n)) /* Fault Clear n, n=0..7 */
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/* PWM Fault Protection Value Register */
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/* PWM Fault Protection Value Register 1 */
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#define PWM_FPV_H(n) (1 << (n)) /* Bits 0-3: Fault Protection PWMH output on channel n, n=0..3 */
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# define PWM_FPV_H0 (1 << 0) /* Bit 0: Fault Protection PWMH output on channel 0 */
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@ -490,20 +547,54 @@
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# define PWM_ELMR_CSEL6 (1 << 6) /* Bit 6: Comparison 6 Selection */
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# define PWM_ELMR_CSEL7 (1 << 7) /* Bit 7: Comparison 7 Selection */
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#ifdef ATSAMA5D4
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/* PWM Spread Spectrum Register */
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# define PWM_SSPR_SPRD_SHIFT (0) /* Bits 0-23: Spread Spectrum Limit Value */
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# define PWM_SSPR_SPRD_MASK (0x00ffffff << PWM_SSPR_SPRD_SHIFT)
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# define PWM_SSPR_SPRD(n) ((uint32_t)(n) << PWM_SSPR_SPRD_SHIFT)
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# define PWM_SSPR_SPRDM (1 << 24) /* Bit 24: Spread Spectrum Counter Mode */
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#endif
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#ifdef ATSAMA5D4
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/* PWM Spread Spectrum Update Register */
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# define PWM_SSPUP_SPRDUP_SHIFT (0) /* Bits 0-23: Spread Spectrum Limit Value Update */
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# define PWM_SSPUP_SPRDUP_MASK (0x00ffffff << PWM_SSPUP_SPRDUP_SHIFT)
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# define PWM_SSPUP_SPRDUP(n) ((uint32_t)(n) << PWM_SSPUP_SPRDUP_SHIFT)
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#endif
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/* PWM Stepper Motor Mode Register */
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#define PWM_SMMR_GCEN(n) (1 << (n)) /* Bits 0-1: Gray Count ENable, n=0..1 */
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# define PWM_SMMR_GCEN0 (1 << 0) /* Bit 0: Enables gray count generation on PWMH/L[0] and PWMH/L[1] */
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# define PWM_SMMR_GCEN1 (1 << 1) /* Bits 1: Enables gray count generation on PWMH/L[2] and PWMH/L[3] */
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# define PWM_SMMR_GCEN0 (1 << 0) /* Bit 0: Enables gray count generation on PWMH/L[0] and PWMH/L[1] */
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# define PWM_SMMR_GCEN1 (1 << 1) /* Bits 1: Enables gray count generation on PWMH/L[2] and PWMH/L[3] */
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#define PWM_SMMR_DOWN(n) (1 << ((n)+16)) /* Bits 16-17: DOWN Count, n=0..1 */
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# define PWM_SMMR_DOWN0 (1 << 16)
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# define PWM_SMMR_DOWN1 (1 << 17)
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#ifdef ATSAMA5D4
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/* PWM Fault Protection Value Register 2 */
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#define PWM_FPV2_FPZH(n) (1 << (n)) /* Bits 0-3: Fault Protection Hi-Z for PWMH channel n, n=0..3 */
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# define PWM_FPV2_FPZH0 (1 << 0) /* Bit 0: Fault Protection Hi-Z for PWMH channel 0 */
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# define PWM_FPV2_FPZH1 (1 << 1) /* Bit 1: Fault Protection Hi-Z for PWMH channel 1 */
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# define PWM_FPV2_FPZH2 (1 << 2) /* Bit 2: Fault Protection Hi-Z for PWMH channel 2 */
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# define PWM_FPV2_FPZH3 (1 << 3) /* Bit 3: Fault Protection Hi-Z for PWMH channel 3 */
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#define PWM_FPV2_L(n) (1 << ((n)+16)) /* Bits 16-19: Fault Protection Hi-Z for PWML channel n, n=0..3 */
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# define PWM_FPV2_FPZL0 (1 << 16) /* Bit 16: Fault Protection Hi-Z for PWML channel 0 */
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# define PWM_FPV2_FPZL1 (1 << 17) /* Bit 17: Fault Protection Hi-Z for PWML channel 1 */
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# define PWM_FPV2_FPZL2 (1 << 18) /* Bit 18: Fault Protection Hi-Z for PWML channel 2 */
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# define PWM_FPV2_FPZL3 (1 << 19) /* Bit 19: FFault Protection Hi-Z for PWML channel 3 */
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#endif
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/* PWM Write Protect Control Register */
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#define PWM_WPCR_WPCMD_SHIFT (0) /* Bits 0-1: Write Protect Command */
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#define PWM_WPCR_WPCMD_MASK (3 << PWM_WPCR_WPCMD_SHIFT)
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# define PWM_WPCR_WPCMD(n) ((uint32_t)(n) << PWM_WPCR_WPCMD_SHIFT)
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# define PWM_WPCR_WPCMD_DSWPROT (0 << PWM_WPCR_WPCMD_SHIFT) /* Disable software write protection */
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# define PWM_WPCR_WPCMD_ESWPROT (1 << PWM_WPCR_WPCMD_SHIFT) /* Enable software write protection */
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# define PWM_WPCR_WPCMD_EHWPROT (2 << PWM_WPCR_WPCMD_SHIFT) /* Enable hardware write protection */
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#define PWM_WPCR_WPRG(n) (1 << ((n)+2)) /* Bits 2-7: Write Protect Register Group n, n=0..5 */
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# define PWM_WPCR_WPRG0 (1 << 2) /* Bit 2: Write Protect Register Group 0 */
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# define PWM_WPCR_WPRG1 (1 << 3) /* Bit 3: Write Protect Register Group 1 */
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@ -512,8 +603,8 @@
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# define PWM_WPCR_WPRG4 (1 << 6) /* Bit 6: Write Protect Register Group 4 */
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# define PWM_WPCR_WPRG5 (1 << 7) /* Bit 7: Write Protect Register Group 5 */
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#define PWM_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect Key */
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#define PWM_WPCR_WPKEY_MASK (0xffffff << PWM_WPCR_WPKEY_SHIFT)
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# define PWM_WPCR_WPKEY (0x50574d << PWM_WPCR_WPKEY_SHIFT) /* "PWM" in ASCII) */
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#define PWM_WPCR_WPKEY_MASK (0x00ffffff << PWM_WPCR_WPKEY_SHIFT)
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# define PWM_WPCR_WPKEY (0x0050574d << PWM_WPCR_WPKEY_SHIFT) /* "PWM" in ASCII) */
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/* PWM Write Protect Status Register */
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@ -551,7 +642,7 @@
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/* PWM Comparison n Mode Register, n=0..7 */
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#define PWM_CMPM_CEN (1 << 0)) /* Bits 0: Comparison Enable */
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#define PWM_CMPM_CEN (1 << 0)) /* Bit 0: Comparison Enable */
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#define PWM_CMPM_CTR_SHIFT (4) /* Bits 4-7: Comparison Trigger */
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#define PWM_CMPM_CTR_MASK (15 << PWM_CMPM_CTR_SHIFT)
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# define PWM_CMPM_CTR(n) ((uint32_t)(n) << PWM_CMPM_CTR_SHIFT)
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@ -570,7 +661,7 @@
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/* PWM Comparison n Mode Update Register, n=0..7 */
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#define PWM_CMPMUPD_CENUPD (1 << 0) /* Bits 0: Comparison Enable Update */
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#define PWM_CMPMUPD_CENUPD (1 << 0) /* Bit 0: Comparison Enable Update */
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#define PWM_CMPMUPD_CTRUPD_SHIFT (4) /* Bits 4-7: Comparison Trigger Update */
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#define PWM_CMPMUPD_CTRUPD_MASK (15 << PWM_CMPMUPD_CTRUPD_SHIFT)
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# define PWM_CMPMUPD_CTRUPD(n) ((uint32_t)(n) << PWM_CMPMUPD_CTRUPD_SHIFT)
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@ -599,12 +690,17 @@
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# define PWM_CMR_CPRE_MCKDIV1024 (10 << PWM_CMR_CPRE_SHIFT) /* Master clock/1024 */
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# define PWM_CMR_CPRE_CLKA (11 << PWM_CMR_CPRE_SHIFT) /* Clock A */
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# define PWM_CMR_CPRE_CLKB (12 << PWM_CMR_CPRE_SHIFT) /* Clock B */
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#define PWM_CMR_CALG (1 << 8) /* Bits 8: Channel Alignment */
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#define PWM_CMR_CPOL (1 << 9) /* Bits 9: Channel Polarity */
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#define PWM_CMR_CES (1 << 10) /* Bits 10: Counter Event Selection */
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#define PWM_CMR_DTE (1 << 16) /* Bits 16: Dead-Time Generator Enable */
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#define PWM_CMR_DTHI (1 << 17) /* Bits 17: Dead-Time PWMH Output Inverted */
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#define PWM_CMR_DTLI (1 << 18) /* Bits 18: Dead-Time PWML Output Inverted */
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#define PWM_CMR_CALG (1 << 8) /* Bit 8: Channel Alignment */
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#define PWM_CMR_CPOL (1 << 9) /* Bit 9: Channel Polarity */
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#define PWM_CMR_CES (1 << 10) /* Bit 10: Counter Event Selection */
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#ifdef ATSAMA5D4
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# define PWM_CMR_UPDS (1 << 11) /* Bit 10: Update Selection */
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#endif
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#define PWM_CMR_DTE (1 << 16) /* Bit 16: Dead-Time Generator Enable */
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#define PWM_CMR_DTHI (1 << 17) /* Bit 17: Dead-Time PWMH Output Inverted */
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#define PWM_CMR_DTLI (1 << 18) /* Bit 18: Dead-Time PWML Output Inverted */
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/* PWM Channel Duty Cycle Register */
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@ -644,4 +740,11 @@
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#define PWM_DTUPD_L_MASK (0xffff << PWM_DTUPD_L_SHIFT)
|
||||
# define PWM_DTUPD_L(n) ((uint32_t)(n) << PWM_DTUPD_L_SHIFT)
|
||||
|
||||
#ifdef ATSAMA5D4
|
||||
/* PWM Channel Mode Update Register */
|
||||
|
||||
# define PWM_CMUPD_CPOLUP (1 << 9) /* Bit 9: Channel Polarity Update */
|
||||
# define PWM_CMUPD_CPOLINVUP (1 << 13) /* Bit 13: Channel Polarity Inversion Update */
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PWM_H */
|
||||
|
||||
@ -542,7 +542,7 @@ static struct sam_pwm_chan_s g_pwm_chan0 =
|
||||
.pwm = &g_pwm,
|
||||
#endif
|
||||
.channel = 0,
|
||||
.base = SAM_PWM_CHAN_BASE(0),
|
||||
.base = SAM_PWM_CHANA_BASE(0),
|
||||
|
||||
#if defined(CONFIG_SAMA5_PWM_CHAN0_MCK)
|
||||
.clksrc = PWM_CLKSRC_MCK,
|
||||
@ -577,7 +577,7 @@ static struct sam_pwm_chan_s g_pwm_chan1 =
|
||||
.pwm = &g_pwm,
|
||||
#endif
|
||||
.channel = 1,
|
||||
.base = SAM_PWM_CHAN_BASE(1),
|
||||
.base = SAM_PWM_CHANA_BASE(1),
|
||||
|
||||
#if defined(CONFIG_SAMA5_PWM_CHAN1_MCK)
|
||||
.clksrc = PWM_CLKSRC_MCK,
|
||||
@ -612,7 +612,7 @@ static struct sam_pwm_chan_s g_pwm_chan2 =
|
||||
.pwm = &g_pwm,
|
||||
#endif
|
||||
.channel = 2,
|
||||
.base = SAM_PWM_CHAN_BASE(2),
|
||||
.base = SAM_PWM_CHANA_BASE(2),
|
||||
|
||||
#if defined(CONFIG_SAMA5_PWM_CHAN2_MCK)
|
||||
.clksrc = PWM_CLKSRC_MCK,
|
||||
@ -647,7 +647,7 @@ static struct sam_pwm_chan_s g_pwm_chan3 =
|
||||
.pwm = &g_pwm,
|
||||
#endif
|
||||
.channel = 3,
|
||||
.base = SAM_PWM_CHAN_BASE(3),
|
||||
.base = SAM_PWM_CHANA_BASE(3),
|
||||
|
||||
#if defined(CONFIG_SAMA5_PWM_CHAN3_MCK)
|
||||
.clksrc = PWM_CLKSRC_MCK,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user