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First cut at data abort page handling logic

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2862 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2010-08-17 15:41:09 +00:00
parent 07705598fd
commit b49b7ae05c
6 changed files with 143 additions and 44 deletions
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10
arch/arm/include/arm/irq.h
View File

@ -156,6 +156,16 @@ struct xcptcontext
/* Register save area */
uint32_t regs[XCPTCONTEXT_REGS];
/* Extra fault address register saved for common paging logic. In the
* case of the prefetch abort, this value is the same as regs[REG_R15];
* For the case of the data abort, this value is the value of the fault
* address register (FAR) at the time of data abort exception.
*/
#ifdef CONFIG_PAGING
uint32_t far;
#endif
};
#endif

27
arch/arm/src/arm/arm.h
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@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/arm/arm.h
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2007-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -103,6 +103,31 @@
#define CR_XP 0x00800000 /* Extended page tables */
#define CR_VE 0x01000000 /* Vectored interrupts */
/* The lowest 4-bits of the FSR register indicates the fault generated by
* the MMU.
*/
#define FSR_MASK 15 /* Bits 0-3: Type of fault */
#define FSR_VECTOR 0 /* Vector exception */
#define FSR_ALIGN1 1 /* Alignment fault */
#define FSR_TERMINAL 2 /* Terminal exception */
#define FSR_ALIGN2 3 /* Alignment fault */
#define FSR_LINESECT 4 /* External abort on linefetch for section translation */
#define FSR_SECT 5 /* Section translation fault (unmapped virtual address) */
#define FSR_LINEPAGE 6 /* External abort on linefetch for page translation */
#define FSR_PAGE 7 /* Page translation fault (unmapped virtual address) */
#define FSR_NLINESECT 8 /* External abort on non-linefetch for section translation */
#define FSR_DOMSECT 9 /* Domain fault on section translation (i.e. accessing invalid domain) */
#define FSR_NLINEPAGE 10 /* External abort on non-linefetch for page translation */
#define FSR_DOMPAGE 11 /* Domain fault on page translation (i.e. accessing invalid domain) */
#define FSR_EXTERN1 12 /* External abort on first level translation */
#define FSR_PERMSECT 13 /* Permission fault on section (i.e. no permission to access virtual address) */
#define FSR_EXTERN2 14 /* External abort on second level translation */
#define FSR_PERMPAGE 15 /* Permission fault on page (i.e. no permission to access virtual address) */
#define FSR_DOM_SHIFT 4 /* Bits 4-7: Domain */
#define FSR_DOM_MASK (15 << FSR_DOM_SHIFT)
/* Hardware page table definitions.
*
* Level 1 Descriptor (PMD)

127
arch/arm/src/arm/up_dataabort.c
View File

@ -75,12 +75,94 @@
/****************************************************************************
* Name: up_dataabort
*
* Input parameters:
* regs - The standard, ARM register save array.
*
* If CONFIG_PAGING is selected in the NuttX configuration file, then these
* additional input values are expected:
*
* far - Fault address register. On a data abort, the ARM MMU places the
* miss virtual address (MVA) into the FAR register. This is the address
* of the data which, when accessed, caused the fault.
* fsr - Fault status register. On a data a abort, the ARM MMU places an
* encoded four-bit value, the fault status, along with the four-bit
* encoded domain number, in the data FSR
*
* Description:
* This is the data abort exception handler. The ARM data abort exception
* occurs when a memory fault is detected during a data transfer.
*
****************************************************************************/
#ifdef CONFIG_PAGING
void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
{
FAR _TCB *tcb = (FAR _TCB *)g_readytorun.head;
/* Save the saved processor context in current_regs where it can be accessed
* for register dumps and possibly context switching.
*/
current_regs = regs;
/* In the NuttX on-demand paging implementation, only the read-only, .text
* section is paged. However, the ARM compiler generated PC-relative data
* fetches from within the .text sections. Also, it is customary to locate
* read-only data (.rodata) within the same section as .text so that it
* does not require copying to RAM. Misses in either of these case should
* cause a data abort.
*
* We are only interested in data aborts due to page translations faults.
* Sections should already be in place and permissions should already be
* be set correctly (to read-only) so any other data abort reason is a
* fatal error.
*/
if ((fsr & FSR_MASK) != FSR_PAGE)
{
goto segfault;
}
/* Check the (virtual) address of data that caused the data abort. When
* the exception occurred, this address was provided in the FAR register.
* (It has not yet been saved in the register context save area).
*/
if (far < CONFIG_PAGING_PAGEDBASE || far >= CONFIG_PAGING_PAGEDEND)
{
goto segfault;
}
/* Save the offending data address as the fault address in the TCB of
* the currently task. This fault address is also used by the prefetch
* abort handling; this will allow common paging logic for both
* prefetch and data aborts.
*/
tcb->far = regs[REG_R15];
/* Call pg_miss() to schedule the page fill. A consequences of this
* call are:
*
* (1) The currently executing task will be blocked and saved on
* on the g_waitingforfill task list.
* (2) An interrupt-level context switch will occur so that when
* this function returns, it will return to a different task,
* most likely the page fill worker thread.
* (3) The page fill worker task has been signalled and should
* execute immediately when we return from this exception.
*/
pg_miss();
return;
segfault:
lldbg("Data abort at PC: %x FAR: %08x FSR: %08x\n", regs[REG_PC], far, fsr);
PANIC(OSERR_ERREXCEPTION);
}
#else /* CONFIG_PAGING */
void up_dataabort(uint32_t *regs)
{
/* Save the saved processor context in current_regs where it can be accessed
@ -89,45 +171,10 @@ void up_dataabort(uint32_t *regs)
current_regs = regs;
#ifdef CONFIG_PAGING
/* In the NuttX on-demand paging implementation, only the read-only, .text
* section is paged. However, the ARM compiler generated PC-relative data
* fetches from within the .text sections. Also, it is customary to locate
* read-only data (.rodata) within the same section as .text so that it
* does not require copying to RAM. Misses in either of these case should
* cause a data abort.
*/
/* Crash -- possibly showing diagnost debug information. */
#warning "Lots of missing logic"
#if 0
/* Get the (virtual) address of instruction that caused the data abort.
* When the exception occurred, this address was provide in the lr register
* and this value was saved in the context save area as the PC at the
* REG_R15 index.
*/
if (regs[REG_R15] >= CONFIG_PAGING_PAGEDBASE &&
regs[REG_R15] < CONFIG_PAGING_PAGEDEND)
{
/* Call pg_miss() to schedule the page fill. A consequences of this
* call are:
*
* (1) The currently executing task will be blocked and saved on
* on the g_waitingforfill task list.
* (2) An interrupt-level context switch will occur so that when
* this function returns, it will return to a different task,
* most likely the page fill worker thread.
* (3) The page fill worker task has been signalled and should
* execute immediately when we return from this exception.
*/
pg_miss();
}
else
#endif
#endif
{
lldbg("Data abort at 0x%x\n", regs[REG_PC]);
PANIC(OSERR_ERREXCEPTION);
}
lldbg("Data abort at %08x\n", regs[REG_PC]);
PANIC(OSERR_ERREXCEPTION);
}
#endif /* CONFIG_PAGING */

13
arch/arm/src/arm/up_prefetchabort.c
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@ -109,7 +109,7 @@ void up_prefetchabort(uint32_t *regs)
#ifdef CONFIG_PAGING
/* Get the (virtual) address of instruction that caused the prefetch abort.
* When the exception occurred, this address was provide in the lr register
* When the exception occurred, this address was provided in the lr register
* and this value was saved in the context save area as the PC at the
* REG_R15 index.
*
@ -120,6 +120,15 @@ void up_prefetchabort(uint32_t *regs)
if (regs[REG_R15] >= CONFIG_PAGING_PAGEDBASE &&
regs[REG_R15] < CONFIG_PAGING_PAGEDEND)
{
/* Save the offending PC as the fault address in the TCB of the currently
* executing task. This value is, of course, already known in regs[REG_R15],
* but saving it in this location will allow common paging logic for both
* prefetch and data aborts.
*/
FAR _TCB *tcb = (FAR _TCB *)g_readytorun.head;
tcb->far = regs[REG_R15];
/* Call pg_miss() to schedule the page fill. A consequences of this
* call are:
*
@ -137,7 +146,7 @@ void up_prefetchabort(uint32_t *regs)
else
#endif
{
lldbg("Prefetch abort at 0x%x\n", regs[REG_PC]);
lldbg("Prefetch abort at %08x\n", regs[REG_PC]);
PANIC(OSERR_ERREXCEPTION);
}
}

4
arch/arm/src/arm/up_vectors.S
View File

@ -257,6 +257,10 @@ up_vectordata:
mov fp, #0 /* Init frame pointer */
mov r0, sp /* Get r0=xcp */
#ifdef CONFIG_PAGING
mrc p15, 0, r2, c5, c0, 0 /* Get r2=FSR */
mrc p15, 0, r1, c6, c0, 0 /* Get R1=FAR */
#endif
bl up_dataabort /* Call the handler */
/* Restore the CPSR, SVC modr registers and return */

6
arch/arm/src/common/up_internal.h
View File

@ -1,7 +1,7 @@
/****************************************************************************
* common/up_internal.h
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2007-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -182,7 +182,11 @@ extern int up_svcall(int irq, FAR void *context);
extern int up_hardfault(int irq, FAR void *context);
#else
extern void up_doirq(int irq, uint32_t *regs);
#ifdef CONFIG_PAGING
extern void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr);
#else
extern void up_dataabort(uint32_t *regs);
#endif
extern void up_prefetchabort(uint32_t *regs);
extern void up_syscall(uint32_t *regs);
extern void up_undefinedinsn(uint32_t *regs);