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SDIO fixes for the STM32 F2 from Gary Teravskis and Scott Rondestvedt

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4973 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2012-07-24 15:49:01 +00:00
parent 4c612c24a9
commit b4e9cec9ca
4 changed files with 59 additions and 53 deletions
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18
arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h
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@ -404,15 +404,15 @@
/* SDIO */ /* SDIO */
#define GPIO_SDIO_CK (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12) #define GPIO_SDIO_CK (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12)
#define GPIO_SDIO_CMD (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN2) #define GPIO_SDIO_CMD (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN2)
#define GPIO_SDIO_D0 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN8) #define GPIO_SDIO_D0 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
#define GPIO_SDIO_D1 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN9) #define GPIO_SDIO_D1 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
#define GPIO_SDIO_D2 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN10) #define GPIO_SDIO_D2 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
#define GPIO_SDIO_D3 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN11) #define GPIO_SDIO_D3 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11)
#define GPIO_SDIO_D4 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN8) #define GPIO_SDIO_D4 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
#define GPIO_SDIO_D5 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN9) #define GPIO_SDIO_D5 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
#define GPIO_SDIO_D6 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN6) #define GPIO_SDIO_D6 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
#define GPIO_SDIO_D7 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN7) #define GPIO_SDIO_D7 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
/* SPI */ /* SPI */

24
arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
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@ -1,8 +1,8 @@
/************************************************************************************ /************************************************************************************
* arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h * arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
* *
* Copyright (C) 2011 Gregory Nutt. All rights reserved. * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
@ -62,7 +62,7 @@
* The driver will then automatically configre PA11 as the CAN1 RX pin. * The driver will then automatically configre PA11 as the CAN1 RX pin.
*/ */
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as frequency, * Additional effort is required to select specific GPIO options such as frequency,
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most * open-drain/push-pull, and pull-up/down! Just the basics are defined for most
* pins in this file. * pins in this file.
@ -404,15 +404,15 @@
/* SDIO */ /* SDIO */
#define GPIO_SDIO_CK (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12) #define GPIO_SDIO_CK (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12)
#define GPIO_SDIO_CMD (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN2) #define GPIO_SDIO_CMD (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN2)
#define GPIO_SDIO_D0 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN8) #define GPIO_SDIO_D0 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
#define GPIO_SDIO_D1 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN9) #define GPIO_SDIO_D1 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
#define GPIO_SDIO_D2 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN10) #define GPIO_SDIO_D2 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
#define GPIO_SDIO_D3 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN11) #define GPIO_SDIO_D3 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11)
#define GPIO_SDIO_D4 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN8) #define GPIO_SDIO_D4 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
#define GPIO_SDIO_D5 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN9) #define GPIO_SDIO_D5 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
#define GPIO_SDIO_D6 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN6) #define GPIO_SDIO_D6 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
#define GPIO_SDIO_D7 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN7) #define GPIO_SDIO_D7 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
/* SPI */ /* SPI */

68
arch/arm/src/stm32/stm32_sdio.c
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@ -570,15 +570,20 @@ static inline void stm32_setclkcr(uint32_t clkcr)
/* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
regval &= ~(SDIO_CLKCR_CLKDIV_MASK|SDIO_CLKCR_PWRSAV|SDIO_CLKCR_BYPASS| regval &= ~(SDIO_CLKCR_CLKDIV_MASK|SDIO_CLKCR_PWRSAV|SDIO_CLKCR_BYPASS|
SDIO_CLKCR_WIDBUS_MASK|SDIO_CLKCR_NEGEDGE|SDIO_CLKCR_HWFC_EN); SDIO_CLKCR_WIDBUS_MASK|SDIO_CLKCR_NEGEDGE|SDIO_CLKCR_HWFC_EN|
SDIO_CLKCR_CLKEN);
/* Replace with user provided settings */ /* Replace with user provided settings */
clkcr &= (SDIO_CLKCR_CLKDIV_MASK|SDIO_CLKCR_PWRSAV|SDIO_CLKCR_BYPASS| clkcr &= (SDIO_CLKCR_CLKDIV_MASK|SDIO_CLKCR_PWRSAV|SDIO_CLKCR_BYPASS|
SDIO_CLKCR_WIDBUS_MASK|SDIO_CLKCR_NEGEDGE|SDIO_CLKCR_HWFC_EN); SDIO_CLKCR_WIDBUS_MASK|SDIO_CLKCR_NEGEDGE|SDIO_CLKCR_HWFC_EN|
SDIO_CLKCR_CLKEN);
regval |= clkcr; regval |= clkcr;
putreg32(regval, STM32_SDIO_CLKCR); putreg32(regval, STM32_SDIO_CLKCR);
fvdbg("CLKCR: %08x\n", getreg32(STM32_SDIO_CLKCR));
fvdbg("CLKCR: %08x PWR: %08x\n",
getreg32(STM32_SDIO_CLKCR), getreg32(STM32_SDIO_POWER));
} }
/**************************************************************************** /****************************************************************************
@ -1508,12 +1513,8 @@ static void stm32_reset(FAR struct sdio_dev_s *dev)
/* Configure the SDIO peripheral */ /* Configure the SDIO peripheral */
stm32_setclkcr(STM32_CLCKCR_INIT); stm32_setclkcr(STM32_CLCKCR_INIT | SDIO_CLKCR_CLKEN);
stm32_setpwrctrl(SDIO_POWER_PWRCTRL_ON); stm32_setpwrctrl(SDIO_POWER_PWRCTRL_ON);
/* (Re-)enable clocking */
putreg32(1, SDIO_CLKCR_CLKEN_BB);
irqrestore(flags); irqrestore(flags);
fvdbg("CLCKR: %08x POWER: %08x\n", fvdbg("CLCKR: %08x POWER: %08x\n",
@ -1581,41 +1582,46 @@ static void stm32_widebus(FAR struct sdio_dev_s *dev, bool wide)
static void stm32_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate) static void stm32_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
{ {
uint32_t clckr; uint32_t clckr;
uint32_t enable = 1;
switch (rate) switch (rate)
{ {
default: /* Disable clocking (with default ID mode divisor) */
case CLOCK_SDIO_DISABLED: /* Clock is disabled */
clckr = STM32_CLCKCR_INIT;
enable = 0;
return;
case CLOCK_IDMODE: /* Initial ID mode clocking (<400KHz) */ default:
clckr = STM32_CLCKCR_INIT; case CLOCK_SDIO_DISABLED:
break; clckr = STM32_CLCKCR_INIT;
return;
case CLOCK_MMC_TRANSFER: /* MMC normal operation clocking */ /* Enable in initial ID mode clocking (<400KHz) */
clckr = SDIO_CLKCR_MMCXFR;
break;
case CLOCK_SD_TRANSFER_4BIT: /* SD normal operation clocking (wide 4-bit mode) */ case CLOCK_IDMODE:
clckr = (STM32_CLCKCR_INIT | SDIO_CLKCR_CLKEN);
break;
/* Enable in MMC normal operation clocking */
case CLOCK_MMC_TRANSFER:
clckr = (SDIO_CLKCR_MMCXFR | SDIO_CLKCR_CLKEN);
break;
/* SD normal operation clocking (wide 4-bit mode) */
case CLOCK_SD_TRANSFER_4BIT:
#ifndef CONFIG_SDIO_WIDTH_D1_ONLY #ifndef CONFIG_SDIO_WIDTH_D1_ONLY
clckr = SDIO_CLCKR_SDWIDEXFR; clckr = (SDIO_CLCKR_SDWIDEXFR | SDIO_CLKCR_CLKEN);
break; break;
#endif #endif
case CLOCK_SD_TRANSFER_1BIT: /* SD normal operation clocking (narrow 1-bit mode) */ /* SD normal operation clocking (narrow 1-bit mode) */
clckr = SDIO_CLCKR_SDXFR;
break;
};
/* Set the new clock frequency and make sure that the clock is enabled or case CLOCK_SD_TRANSFER_1BIT:
* disabled, whatever the case. clckr = (SDIO_CLCKR_SDXFR | SDIO_CLKCR_CLKEN)
*/ break;
}
/* Set the new clock frequency along with the clock enable/disable bit */
stm32_setclkcr(clckr); stm32_setclkcr(clckr);
putreg32(enable, SDIO_CLKCR_CLKEN_BB);
} }
/**************************************************************************** /****************************************************************************

2
arch/arm/src/stm32/stm32_sdio.h
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@ -2,7 +2,7 @@
* arch/arm/src/stm32/stm32_sdio.h * arch/arm/src/stm32/stm32_sdio.h
* *
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions