arch/arm/src/s32k1xx: This commit brings in the LPSPI and LPI2C peripheral drivers from the i.MXRT which used the identical IP.
Squashed commit of the following:
arch/arm/src/s32k1xx: Update peripheral input clocking for the way that things are done for the S32K1XX. Fix other misc. compilation/configuration issues.
arch/arm/src/s32k1xx: Clean up LPSPI and LPI2C naming for S32K1XX. Using S32K1XX clock functions to get peripheral input clock.
arch/arm/src/s32k1xx: Clone i.MXRT LPSPI and LPI2C support. i.MXRT uses the same IP as S32K1XX.
This commit is contained in:
Gregory Nutt
parent
be5a40c656
commit
b4ee19f5bd
@ -96,7 +96,8 @@
|
||||
#define S32K1XX_IRQ_PMC (37) /* PMC Interrupt */
|
||||
#define S32K1XX_IRQ_WDOG (38) /* WDOG interrupt request out before wdg reset out */
|
||||
#define S32K1XX_IRQ_RCM (39) /* RCM Asynchronous Interrupt */
|
||||
#define S32K1XX_IRQ_LPI2C0 (40) /* LPI2C Master/Slave Interrupt */
|
||||
#define S32K1XX_IRQ_LPI2C0M (40) /* LPI2C Master/Slave Interrupt */
|
||||
#define S32K1XX_IRQ_LPI2C0S (40) /* LPI2C Master/Slave Interrupt */
|
||||
#define S32K1XX_IRQ_FLEXIO (41) /* FlexIO Interrupt */
|
||||
#define S32K1XX_IRQ_LPSPI0 (42) /* LPSPI0 Interrupt */
|
||||
#define S32K1XX_IRQ_LPSPI1 (43) /* LPSPI1 Interrupt */
|
||||
|
||||
@ -20,6 +20,7 @@ config ARCH_CHIP_S32K116
|
||||
config ARCH_CHIP_S32K118
|
||||
bool "S32K118"
|
||||
select ARCH_CHIP_S32K11X
|
||||
select S32K1XX_HAVE_LPSPI1
|
||||
---help---
|
||||
Cortex-M0+, 256Kb FLASH, 25Kb RAM incl. 2Kb FlexRAM
|
||||
|
||||
@ -32,12 +33,14 @@ config ARCH_CHIP_S32K142
|
||||
config ARCH_CHIP_S32K144
|
||||
bool "S32K144"
|
||||
select ARCH_CHIP_S32K14X
|
||||
select S32K1XX_HAVE_LPSPI2
|
||||
---help---
|
||||
Cortex-M4F, 512Kb FLASH, 64Kb RAM incl. 4Kb FlexRAM
|
||||
|
||||
config ARCH_CHIP_S32K146
|
||||
bool "S32K146"
|
||||
select ARCH_CHIP_S32K14X
|
||||
select S32K1XX_HAVE_LPSPI2
|
||||
---help---
|
||||
Cortex-M4F, 1Mb FLASH, 128Kb RAM incl. 4Kb FlexRAM
|
||||
|
||||
@ -45,6 +48,8 @@ config ARCH_CHIP_S32K148
|
||||
bool "S32K148"
|
||||
select ARCH_CHIP_S32K14X
|
||||
select S32K1XX_HAVE_ENET
|
||||
select S32K1XX_HAVE_LPI2C1
|
||||
select S32K1XX_HAVE_LPSPI2
|
||||
select S32K1XX_HAVE_SAI
|
||||
---help---
|
||||
Cortex-M4F, 2Mb FLASH, 256Kb RAM incl. 4Kb FlexRAM
|
||||
@ -67,6 +72,7 @@ config ARCH_CHIP_S32K14X
|
||||
select S32K1XX_HAVE_SPLL
|
||||
select S32K1XX_HAVE_HSRUN
|
||||
select S32K1XX_HAVE_LMEM
|
||||
select S32K1XX_HAVE_LPSPI1
|
||||
|
||||
# Chip Capabilities
|
||||
|
||||
@ -90,6 +96,18 @@ config S32K1XX_HAVE_LMEM
|
||||
bool
|
||||
default n
|
||||
|
||||
config S32K1XX_HAVE_LPI2C1
|
||||
bool
|
||||
default n
|
||||
|
||||
config S32K1XX_HAVE_LPSPI1
|
||||
bool
|
||||
default n
|
||||
|
||||
config S32K1XX_HAVE_LPSPI2
|
||||
bool
|
||||
default n
|
||||
|
||||
config S32K1XX_HAVE_QSPI
|
||||
bool
|
||||
default n
|
||||
@ -108,6 +126,10 @@ config S32K1XX_LPUART
|
||||
bool
|
||||
default n
|
||||
|
||||
config S32K1XX_LPI2C
|
||||
bool
|
||||
default n
|
||||
|
||||
config S32K1XX_LPSPI
|
||||
bool
|
||||
default n
|
||||
@ -125,6 +147,43 @@ config S32K1XX_ENET
|
||||
default n
|
||||
depends on S32K1XX_HAVE_ENET
|
||||
|
||||
menuconfig S32K1XX_LPI2C0
|
||||
bool "LPI2C0"
|
||||
default n
|
||||
select S32K1XX_LPI2C
|
||||
|
||||
menuconfig S32K1XX_LPI2C1
|
||||
bool "LPI2C1"
|
||||
default n
|
||||
select S32K1XX_LPI2C
|
||||
depends on S32K1XX_HAVE_LPI2C1
|
||||
|
||||
config S32K1XX_LPSPI0
|
||||
bool "LPSPI0"
|
||||
default n
|
||||
select S32K1XX_LPSPI
|
||||
select SPI
|
||||
|
||||
config S32K1XX_LPSPI1
|
||||
bool "LPSPI1"
|
||||
default n
|
||||
select S32K1XX_LPSPI
|
||||
select SPI
|
||||
depends on S32K1XX_HAVE_LPSPI1
|
||||
|
||||
config S32K1XX_LPSPI2
|
||||
bool "LPSPI2"
|
||||
default n
|
||||
select S32K1XX_LPSPI
|
||||
select SPI
|
||||
depends on S32K1XX_HAVE_LPSPI2
|
||||
|
||||
config S32K1XX_LPUART0
|
||||
bool "LPUART0"
|
||||
default n
|
||||
select S32K1XX_LPUART
|
||||
select LPUART0_SERIALDRIVER
|
||||
|
||||
config S32K1XX_LPUART0
|
||||
bool "LPUART0"
|
||||
default n
|
||||
@ -143,18 +202,6 @@ config S32K1XX_LPUART2
|
||||
select S32K1XX_LPUART
|
||||
select LPUART2_SERIALDRIVER
|
||||
|
||||
config S32K1XX_LPSPI0
|
||||
bool "LPSPI0"
|
||||
default n
|
||||
select S32K1XX_LPSPI
|
||||
select SPI
|
||||
|
||||
config S32K1XX_LPSPI1
|
||||
bool "LPSPI1"
|
||||
default n
|
||||
select S32K1XX_LPSPI
|
||||
select SPI
|
||||
|
||||
endmenu # S32K1XX Peripheral Selection
|
||||
|
||||
config S32K1XX_WDT_DISABLE
|
||||
@ -279,4 +326,38 @@ config S32K1XX_EDMA_EDBG
|
||||
|
||||
endmenu # eDMA Global Configuration
|
||||
|
||||
menu "LPI2C0 Configuration"
|
||||
depends on S32K1XX_LPI2C0
|
||||
|
||||
config LPI2C0_BUSYIDLE
|
||||
int "Bus idle timeout period in clock cycles"
|
||||
default 0
|
||||
|
||||
config LPI2C0_FILTSCL
|
||||
int "I2C master digital glitch filters for SCL input in clock cycles"
|
||||
default 0
|
||||
|
||||
config LPI2C0_FILTSDA
|
||||
int "I2C master digital glitch filters for SDA input in clock cycles"
|
||||
default 0
|
||||
|
||||
endmenu # LPI2C0 Configuration
|
||||
|
||||
menu "LPI2C1 Configuration"
|
||||
depends on S32K1XX_LPI2C1
|
||||
|
||||
config LPI2C1_BUSYIDLE
|
||||
int "Bus idle timeout period in clock cycles"
|
||||
default 0
|
||||
|
||||
config LPI2C1_FILTSCL
|
||||
int "I2C master digital glitch filters for SCL input in clock cycles"
|
||||
default 0
|
||||
|
||||
config LPI2C1_FILTSDA
|
||||
int "I2C master digital glitch filters for SDA input in clock cycles"
|
||||
default 0
|
||||
|
||||
endmenu # LPI2C1 Configuration
|
||||
|
||||
endif # ARCH_CHIP_S32K1XX
|
||||
|
||||
@ -74,6 +74,14 @@ ifeq ($(CONFIG_DEBUG_GPIO_INFO),y)
|
||||
CHIP_CSRCS += s32k1xx_pindump.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_S32K1XX_LPI2C),y)
|
||||
CHIP_CSRCS += s32k1xx_lpi2c.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_S32K1XX_LPSPI),y)
|
||||
CHIP_CSRCS += s32k1xx_lpspi.c
|
||||
endif
|
||||
|
||||
# Source files specific to the ARM CPU family and to the S32K1xx chip family
|
||||
|
||||
ifeq ($(CONFIG_ARCH_CHIP_S32K11X),y)
|
||||
|
||||
556
arch/arm/src/s32k1xx/hardware/s32k1xx_lpi2c.h
Normal file
556
arch/arm/src/s32k1xx/hardware/s32k1xx_lpi2c.h
Normal file
@ -0,0 +1,556 @@
|
||||
/************************************************************************************************************
|
||||
* arch/arm/src/s32k1xx/hardware/s32k1xx_lpi2c.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Ivan Ucherdzhiev <ivanucherdjiev@gmail.com>
|
||||
* Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_LPI2C_H
|
||||
#define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_LPI2C_H
|
||||
|
||||
/************************************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************************************/
|
||||
|
||||
#define S32K1XX_LPI2C_VERID_OFFSET 0x0000 /* Version ID Register offset */
|
||||
#define S32K1XX_LPI2C_PARAM_OFFSET 0x0004 /* Parameter Register offset */
|
||||
#define S32K1XX_LPI2C_MCR_OFFSET 0x0010 /* Master Control Register offset */
|
||||
#define S32K1XX_LPI2C_MSR_OFFSET 0x0014 /* Master Status Register offset */
|
||||
#define S32K1XX_LPI2C_MIER_OFFSET 0x0018 /* Master Interrupt Enable Register offset */
|
||||
#define S32K1XX_LPI2C_MDER_OFFSET 0x001c /* Master DMA Enable Register offset */
|
||||
#define S32K1XX_LPI2C_MCFGR0_OFFSET 0x0020 /* Master Config Register 0 offset */
|
||||
#define S32K1XX_LPI2C_MCFGR1_OFFSET 0x0024 /* Master Config Register 1 offset */
|
||||
#define S32K1XX_LPI2C_MCFGR2_OFFSET 0x0028 /* Master Config Register 2 offset */
|
||||
#define S32K1XX_LPI2C_MCFGR3_OFFSET 0x002c /* Master Config Register 3 offset */
|
||||
#define S32K1XX_LPI2C_MDMR_OFFSET 0x0040 /* Master Data Match Register offset */
|
||||
#define S32K1XX_LPI2C_MCCR0_OFFSET 0x0048 /* Master Clock Configuration Register 0 offset */
|
||||
#define S32K1XX_LPI2C_MCCR1_OFFSET 0x0050 /* Master Clock Configuration Register 1 offset */
|
||||
#define S32K1XX_LPI2C_MFCR_OFFSET 0x0058 /* Master FIFO Control Register offset */
|
||||
#define S32K1XX_LPI2C_MFSR_OFFSET 0x005c /* Master FIFO Status Register offset */
|
||||
#define S32K1XX_LPI2C_MTDR_OFFSET 0x0060 /* Master Transmit Data Register offset */
|
||||
#define S32K1XX_LPI2C_MRDR_OFFSET 0x0070 /* Master Receive Data Register offset */
|
||||
#define S32K1XX_LPI2C_SCR_OFFSET 0x0110 /* Slave Control Register offset */
|
||||
#define S32K1XX_LPI2C_SSR_OFFSET 0x0114 /* Slave Status Register offset */
|
||||
#define S32K1XX_LPI2C_SIER_OFFSET 0x0118 /* Slave Interrupt Enable Register offset */
|
||||
#define S32K1XX_LPI2C_SDER_OFFSET 0x011c /* Slave DMA Enable Register offset */
|
||||
#define S32K1XX_LPI2C_SCFGR1_OFFSET 0x0124 /* Slave Config Register 1 offset */
|
||||
#define S32K1XX_LPI2C_SCFGR2_OFFSET 0x0128 /* Slave Config Register 2 offset */
|
||||
#define S32K1XX_LPI2C_SAMR_OFFSET 0x0140 /* Slave Address Match Register offset */
|
||||
#define S32K1XX_LPI2C_SASR_OFFSET 0x0150 /* Slave Address Status Register offset */
|
||||
#define S32K1XX_LPI2C_STAR_OFFSET 0x0154 /* Slave Transmit ACK Register offset */
|
||||
#define S32K1XX_LPI2C_STDR_OFFSET 0x0160 /* Slave Transmit Data Register offset */
|
||||
#define S32K1XX_LPI2C_SRDR_OFFSET 0x0170 /* Slave Receive Data Register offset */
|
||||
|
||||
/* Register addresses ***************************************************************************************/
|
||||
|
||||
/* LPI2C0 Registers */
|
||||
|
||||
#define S32K1XX_LPI2C0_VERID (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_VERID_OFFSET) /* Version ID Register */
|
||||
#define S32K1XX_LPI2C0_PARAM (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_PARAM_OFFSET) /* Parameter Register */
|
||||
#define S32K1XX_LPI2C0_MCR (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_MCR_OFFSET) /* Master Control Register */
|
||||
#define S32K1XX_LPI2C0_MSR (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_MSR_OFFSET) /* Master Status Register */
|
||||
#define S32K1XX_LPI2C0_MIER (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_MIER_OFFSET) /* Master Interrupt Enable Register */
|
||||
#define S32K1XX_LPI2C0_MDER (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_MDER_OFFSET) /* Master DMA Enable Register */
|
||||
#define S32K1XX_LPI2C0_MCFGR0 (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_MCFGR0_OFFSET) /* Master Config Register 0 */
|
||||
#define S32K1XX_LPI2C0_MCFGR1 (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_MCFGR1_OFFSET) /* Master Config Register 1 */
|
||||
#define S32K1XX_LPI2C0_MCFGR2 (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_MCFGR2_OFFSET) /* Master Config Register 2 */
|
||||
#define S32K1XX_LPI2C0_MCFGR3 (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_MCFGR3_OFFSET) /* Master Config Register 3 */
|
||||
#define S32K1XX_LPI2C0_MDMR (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_MDMR_OFFSET) /* Master Data Match Register */
|
||||
#define S32K1XX_LPI2C0_MCCR0 (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_MCCR0_OFFSET) /* Master Clock Configuration Register 0 */
|
||||
#define S32K1XX_LPI2C0_MCCR1 (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_MCCR1_OFFSET) /* Master Clock Configuration Register 1 */
|
||||
#define S32K1XX_LPI2C0_MFCR (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_MFCR_OFFSET) /* Master FIFO Control Register */
|
||||
#define S32K1XX_LPI2C0_MFSR (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_MFSR_OFFSET) /* Master FIFO Status Register */
|
||||
#define S32K1XX_LPI2C0_MTDR (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_MTDR_OFFSET) /* Master Transmit Data Register */
|
||||
#define S32K1XX_LPI2C0_MRDR (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_MRDR_OFFSET) /* Master Receive Data Register */
|
||||
#define S32K1XX_LPI2C0_SCR (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_SCR_OFFSET) /* Slave Control Register */
|
||||
#define S32K1XX_LPI2C0_SSR (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_SSR_OFFSET) /* Slave Status Register */
|
||||
#define S32K1XX_LPI2C0_SIER (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_SIER_OFFSET) /* Slave Interrupt Enable Register */
|
||||
#define S32K1XX_LPI2C0_SDER (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_SDER_OFFSET) /* Slave DMA Enable Register */
|
||||
#define S32K1XX_LPI2C0_SCFGR1 (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_SCFGR1_OFFSET) /* Slave Config Register 1 */
|
||||
#define S32K1XX_LPI2C0_SCFGR2 (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_SCFGR2_OFFSET) /* Slave Config Register 2 */
|
||||
#define S32K1XX_LPI2C0_SAMR (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_SAMR_OFFSET) /* Slave Address Match Register */
|
||||
#define S32K1XX_LPI2C0_SASR (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_SASR_OFFSET) /* Slave Address Status Register */
|
||||
#define S32K1XX_LPI2C0_STAR (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_STAR_OFFSET) /* Slave Transmit ACK Register */
|
||||
#define S32K1XX_LPI2C0_STDR (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_STDR_OFFSET) /* Slave Transmit Data Register */
|
||||
#define S32K1XX_LPI2C0_SRDR (S32K1XX_LPI2C0_BASE + S32K1XX_LPI2C_SRDR_OFFSET) /* Slave Receive Data Register */
|
||||
|
||||
/* LPI2C1 Registers */
|
||||
|
||||
#define S32K1XX_LPI2C1_VERID (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_VERID_OFFSET) /* Version ID Register */
|
||||
#define S32K1XX_LPI2C1_PARAM (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_PARAM_OFFSET) /* Parameter Register */
|
||||
#define S32K1XX_LPI2C1_MCR (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_MCR_OFFSET) /* Master Control Register */
|
||||
#define S32K1XX_LPI2C1_MSR (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_MSR_OFFSET) /* Master Status Register */
|
||||
#define S32K1XX_LPI2C1_MIER (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_MIER_OFFSET) /* Master Interrupt Enable Register */
|
||||
#define S32K1XX_LPI2C1_MDER (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_MDER_OFFSET) /* Master DMA Enable Register */
|
||||
#define S32K1XX_LPI2C1_MCFGR0 (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_MCFGR0_OFFSET) /* Master Config Register 0 */
|
||||
#define S32K1XX_LPI2C1_MCFGR1 (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_MCFGR1_OFFSET) /* Master Config Register 1 */
|
||||
#define S32K1XX_LPI2C1_MCFGR2 (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_MCFGR2_OFFSET) /* Master Config Register 2 */
|
||||
#define S32K1XX_LPI2C1_MCFGR3 (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_MCFGR3_OFFSET) /* Master Config Register 3 */
|
||||
#define S32K1XX_LPI2C1_MDMR (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_MDMR_OFFSET) /* Master Data Match Register */
|
||||
#define S32K1XX_LPI2C1_MCCR0 (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_MCCR0_OFFSET) /* Master Clock Configuration Register 0 */
|
||||
#define S32K1XX_LPI2C1_MCCR1 (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_MCCR1_OFFSET) /* Master Clock Configuration Register 1 */
|
||||
#define S32K1XX_LPI2C1_MFCR (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_MFCR_OFFSET) /* Master FIFO Control Register */
|
||||
#define S32K1XX_LPI2C1_MFSR (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_MFSR_OFFSET) /* Master FIFO Status Register */
|
||||
#define S32K1XX_LPI2C1_MTDR (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_MTDR_OFFSET) /* Master Transmit Data Register */
|
||||
#define S32K1XX_LPI2C1_MRDR (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_MRDR_OFFSET) /* Master Receive Data Register */
|
||||
#define S32K1XX_LPI2C1_SCR (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_SCR_OFFSET) /* Slave Control Register */
|
||||
#define S32K1XX_LPI2C1_SSR (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_SSR_OFFSET) /* Slave Status Register */
|
||||
#define S32K1XX_LPI2C1_SIER (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_SIER_OFFSET) /* Slave Interrupt Enable Register */
|
||||
#define S32K1XX_LPI2C1_SDER (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_SDER_OFFSET) /* Slave DMA Enable Register */
|
||||
#define S32K1XX_LPI2C1_SCFGR1 (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_SCFGR1_OFFSET) /* Slave Config Register 1 */
|
||||
#define S32K1XX_LPI2C1_SCFGR2 (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_SCFGR2_OFFSET) /* Slave Config Register 2 */
|
||||
#define S32K1XX_LPI2C1_SAMR (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_SAMR_OFFSET) /* Slave Address Match Register */
|
||||
#define S32K1XX_LPI2C1_SASR (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_SASR_OFFSET) /* Slave Address Status Register */
|
||||
#define S32K1XX_LPI2C1_STAR (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_STAR_OFFSET) /* Slave Transmit ACK Register */
|
||||
#define S32K1XX_LPI2C1_STDR (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_STDR_OFFSET) /* Slave Transmit Data Register */
|
||||
#define S32K1XX_LPI2C1_SRDR (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_SRDR_OFFSET) /* Slave Receive Data Register */
|
||||
|
||||
/* Register bit definitions *********************************************************************************/
|
||||
|
||||
/* LPI2C Version ID Register */
|
||||
|
||||
#define LPI2C_VERID_FEATURE_SHIFT (0)
|
||||
#define LPI2C_VERID_FEATURE_MASK (0xffff << LPI2C_VERID_FEATURE_SHIFT)
|
||||
#define LPI2C_VERID_MINOR_SHIFT (16)
|
||||
#define LPI2C_VERID_MINOR_MASK (0xff << LPI2C_VERID_MINOR_SHIFT)
|
||||
#define LPI2C_VERID_MAJOR_SHIFT (24)
|
||||
#define LPI2C_VERID_MAJOR_MASK (0xff << LPI2C_VERID_MAJOR_SHIFT)
|
||||
|
||||
/* LPI2C Parameter Register */
|
||||
|
||||
#define LPI2C_PARAM_MTXFIFO_MASK (0x0f) /* Bits 0-3: Master Transmit FIFO Size */
|
||||
# define LPI2C_PARAM_MTXFIFO_1_WORDS (0)
|
||||
# define LPI2C_PARAM_MTXFIFO_2_WORDS (1)
|
||||
# define LPI2C_PARAM_MTXFIFO_4_WORDS (2)
|
||||
# define LPI2C_PARAM_MTXFIFO_8_WORDS (3)
|
||||
# define LPI2C_PARAM_MTXFIFO_16_WORDS (4)
|
||||
# define LPI2C_PARAM_MTXFIFO_32_WORDS (5)
|
||||
# define LPI2C_PARAM_MTXFIFO_64_WORDS (6)
|
||||
# define LPI2C_PARAM_MTXFIFO_128_WORDS (7)
|
||||
# define LPI2C_PARAM_MTXFIFO_256_WORDS (8)
|
||||
# define LPI2C_PARAM_MTXFIFO_512_WORDS (9)
|
||||
# define LPI2C_PARAM_MTXFIFO_1024_WORDS (10)
|
||||
# define LPI2C_PARAM_MTXFIFO_2048_WORDS (11)
|
||||
# define LPI2C_PARAM_MTXFIFO_4096_WORDS (12)
|
||||
# define LPI2C_PARAM_MTXFIFO_8192_WORDS (13)
|
||||
# define LPI2C_PARAM_MTXFIFO_16384_WORDS (14)
|
||||
# define LPI2C_PARAM_MTXFIFO_32768_WORDS (15)
|
||||
#define LPI2C_PARAM_MRXFIFO_SHIFT (8) /* Bits 8-11: Master Receive FIFO Size */
|
||||
#define LPI2C_PARAM_MRXFIFO_MASK (0x0f << LPI2C_PARAM_MRXFIFO_SHIFT)
|
||||
# define LPI2C_PARAM_MRXFIFO_1_WORDS (0 << LPI2C_PARAM_MRXFIFO_SHIFT)
|
||||
# define LPI2C_PARAM_MRXFIFO_2_WORDS (1 << LPI2C_PARAM_MRXFIFO_SHIFT)
|
||||
# define LPI2C_PARAM_MRXFIFO_4_WORDS (2 << LPI2C_PARAM_MRXFIFO_SHIFT)
|
||||
# define LPI2C_PARAM_MRXFIFO_8_WORDS (3 << LPI2C_PARAM_MRXFIFO_SHIFT)
|
||||
# define LPI2C_PARAM_MRXFIFO_16_WORDS (4 << LPI2C_PARAM_MRXFIFO_SHIFT)
|
||||
# define LPI2C_PARAM_MRXFIFO_32_WORDS (5 << LPI2C_PARAM_MRXFIFO_SHIFT)
|
||||
# define LPI2C_PARAM_MRXFIFO_64_WORDS (6 << LPI2C_PARAM_MRXFIFO_SHIFT)
|
||||
# define LPI2C_PARAM_MRXFIFO_128_WORDS (7 << LPI2C_PARAM_MRXFIFO_SHIFT)
|
||||
# define LPI2C_PARAM_MRXFIFO_256_WORDS (8 << LPI2C_PARAM_MRXFIFO_SHIFT)
|
||||
# define LPI2C_PARAM_MRXFIFO_512_WORDS (9 << LPI2C_PARAM_MRXFIFO_SHIFT)
|
||||
# define LPI2C_PARAM_MRXFIFO_1024_WORDS (10 << LPI2C_PARAM_MRXFIFO_SHIFT)
|
||||
# define LPI2C_PARAM_MRXFIFO_2048_WORDS (11 << LPI2C_PARAM_MRXFIFO_SHIFT)
|
||||
# define LPI2C_PARAM_MRXFIFO_4096_WORDS (12 << LPI2C_PARAM_MRXFIFO_SHIFT)
|
||||
# define LPI2C_PARAM_MRXFIFO_8192_WORDS (13 << LPI2C_PARAM_MRXFIFO_SHIFT)
|
||||
# define LPI2C_PARAM_MRXFIFO_16384_WORDS (14 << LPI2C_PARAM_MRXFIFO_SHIFT)
|
||||
# define LPI2C_PARAM_MRXFIFO_32768_WORDS (15 << LPI2C_PARAM_MRXFIFO_SHIFT)
|
||||
|
||||
/* LPI2C Master Control Register */
|
||||
|
||||
#define LPI2C_MCR_MEN (1 << 0) /* Master Enable Bit */
|
||||
#define LPI2C_MCR_RST (1 << 1) /* Software Reset Bit */
|
||||
#define LPI2C_MCR_DOZEN (1 << 2) /* Doze Mode Enable Bit */
|
||||
#define LPI2C_MCR_DBGEN (1 << 3) /* Debug Enable Bit */
|
||||
/* Bits 7-4 Reserved */
|
||||
#define LPI2C_MCR_RTF (1 << 8) /* Reset Transmit FIFO Bit */
|
||||
#define LPI2C_MCR_RRF (1 << 9) /* Reset Receive FIFO Bit */
|
||||
/* Bits 31-10 Reserved */
|
||||
|
||||
/* LPI2C Master Status Register */
|
||||
|
||||
#define LPI2C_MSR_TDF (1 << 0) /* Transmit Data Flag Bit */
|
||||
#define LPI2C_MSR_RDF (1 << 1) /* Receive Data Flag Bit */
|
||||
/* Bits 7-2 Reserved */
|
||||
#define LPI2C_MSR_EPF (1 << 8) /* End Packet Flag Bit */
|
||||
#define LPI2C_MSR_SDF (1 << 9) /* STOP Detect Flag Bit */
|
||||
#define LPI2C_MSR_NDF (1 << 10) /* NACK Detect Flag Bit */
|
||||
#define LPI2C_MSR_ALF (1 << 11) /* Arbitration Lost Flag Bit */
|
||||
#define LPI2C_MSR_FEF (1 << 12) /* FIFO Error Flag Bit */
|
||||
#define LPI2C_MSR_PLTF (1 << 13) /* Pin Low Timeout Flag Bit */
|
||||
#define LPI2C_MSR_DMF (1 << 14) /* Data Match Flag Bit */
|
||||
/* Bits 23-15 Reserved */
|
||||
#define LPI2C_MSR_MBF (1 << 24) /* Master Busy Flag Bit */
|
||||
#define LPI2C_MSR_BBF (1 << 25) /* Bus Busy Flag Bit */
|
||||
/* Bits 31-26 Reserved */
|
||||
#define LPI2C_MSR_ERROR_MASK (LPI2C_MSR_NDF | LPI2C_MSR_ALF | \
|
||||
LPI2C_MSR_FEF)
|
||||
|
||||
/* LPI2C Master Interrupt Enable Register */
|
||||
|
||||
#define LPI2C_MIER_TDIE (1 << 0) /* Transmit Data Interrupt Enable Bit */
|
||||
#define LPI2C_MIER_RDIE (1 << 1) /* Receive Data Interrupt Enable Bit */
|
||||
/* Bits 7-2 Reserved */
|
||||
#define LPI2C_MIER_EPIE (1 << 8) /* End Packet Interrupt Enable Bit */
|
||||
#define LPI2C_MIER_SDIE (1 << 9) /* STOP Detect Interrupt Enable Bit */
|
||||
#define LPI2C_MIER_NDIE (1 << 10) /* NACK Detect Interrupt Enable Bit */
|
||||
#define LPI2C_MIER_ALIE (1 << 11) /* Arbitration Lost Interrupt Enable Bit */
|
||||
#define LPI2C_MIER_FEIE (1 << 12) /* FIFO Error Interrupt Enable Bit */
|
||||
#define LPI2C_MIER_PLTIE (1 << 13) /* Pin Low Timeout Interrupt Enable Bit */
|
||||
#define LPI2C_MIER_DMIE (1 << 14) /* Data Match Interrupt Enable Bit */
|
||||
/* Bits 31-15 Reserved */
|
||||
|
||||
/* LPI2C Master DMA Enable Register */
|
||||
|
||||
#define LPI2C_MDER_TDDE (1 << 0) /* Transmit Data DMA Enable Bit */
|
||||
#define LPI2C_MDER_RDDE (1 << 1) /* Transmit Data DMA Enable Bit */
|
||||
/* Bits 31-2 Reserved */
|
||||
|
||||
/* LPI2C Master Config Register 0 */
|
||||
|
||||
#define LPI2C_MCFG0_HREN (1 << 0) /* Host Request Enable Bit */
|
||||
#define LPI2C_MCFG0_HRPOL (1 << 1) /* Host Request Polarity Bit */
|
||||
#define LPI2C_MCFG0_HRSEL (1 << 2) /* Host Request Select Bit */
|
||||
/* Bits 7-3 Reserved */
|
||||
#define LPI2C_MCFG0_CIRFIFO (1 << 8) /* Circular FIFO Enable Bit */
|
||||
#define LPI2C_MCFG0_RDMO (1 << 9) /* Receive Data Match Only Bit */
|
||||
/* Bits 31-10 Reserved */
|
||||
|
||||
/* LPI2C Master Config Register 1 */
|
||||
|
||||
#define LPI2C_MCFGR1_PRESCALE_MASK (7 << 0) /* Clock Prescaler Bit Mask */
|
||||
# define LPI2C_MCFGR1_PRESCALE(n) (n & LPI2C_MCFGR1_PRESCALE_MASK)
|
||||
# define LPI2C_MCFGR1_PRESCALE_1 (0)
|
||||
# define LPI2C_MCFGR1_PRESCALE_2 (1)
|
||||
# define LPI2C_MCFGR1_PRESCALE_4 (2)
|
||||
# define LPI2C_MCFGR1_PRESCALE_8 (3)
|
||||
# define LPI2C_MCFGR1_PRESCALE_16 (4)
|
||||
# define LPI2C_MCFGR1_PRESCALE_32 (5)
|
||||
# define LPI2C_MCFGR1_PRESCALE_64 (6)
|
||||
# define LPI2C_MCFGR1_PRESCALE_128 (7)
|
||||
#define LPI2C_MCFGR1_AUTOSTOP (1 << 8) /* Automatic STOP Generation Bit */
|
||||
#define LPI2C_MCFGR1_IGNACK (1 << 9) /* Ignore NACK Bit */
|
||||
#define LPI2C_MCFGR1_TIMECFG (1 << 10) /* Timeout Configuration Bit */
|
||||
/* Bits 15-11 Reserved */
|
||||
#define LPI2C_MCFGR1_MATCFG_SHIFT (16)
|
||||
#define LPI2C_MCFGR1_MATCFG_MASK (7 << LPI2C_MCFGR1_MATCFG_SHIFT) /* Match Configuration Bit Mask */
|
||||
# define LPI2C_MCFGR1_MATCFG(n) ((n << LPI2C_MCFGR1_MATCFG_SHIFT) & LPI2C_MCFGR1_MATCFG_MASK)
|
||||
# define LPI2C_MCFGR1_MATCFG_DISABLE (0 << LPI2C_MCFGR1_MATCFG_SHIFT)
|
||||
/* LPI2C_MCFG1_MATCFG = 001b Reserved */
|
||||
# define LPI2C_MCFGR1_MATCFG2 (2 << LPI2C_MCFGR1_MATCFG_SHIFT)
|
||||
# define LPI2C_MCFGR1_MATCFG3 (3 << LPI2C_MCFGR1_MATCFG_SHIFT)
|
||||
# define LPI2C_MCFGR1_MATCFG4 (4 << LPI2C_MCFGR1_MATCFG_SHIFT)
|
||||
# define LPI2C_MCFGR1_MATCFG5 (5 << LPI2C_MCFGR1_MATCFG_SHIFT)
|
||||
# define LPI2C_MCFGR1_MATCFG6 (6 << LPI2C_MCFGR1_MATCFG_SHIFT)
|
||||
# define LPI2C_MCFGR1_MATCFG7 (7 << LPI2C_MCFGR1_MATCFG_SHIFT)
|
||||
/* Bits 23-19 Reserved */
|
||||
#define LPI2C_MCFGR1_PINCFG_SHIFT (24)
|
||||
#define LPI2C_MCFGR1_PINCFG_MASK (7 << LPI2C_MCFGR1_PINCFG_SHIFT) /* Pin Configuration Bit Mask */
|
||||
# define LPI2C_MCFGR1_PINCFG(n) ((n << LPI2C_MCFGR1_PINCFG_SHIFT) & LPI2C_MCFGR1_PINCFG_MASK)
|
||||
# define LPI2C_MCFGR1_PINCFG0 (0 << LPI2C_MCFGR1_PINCFG_SHIFT)
|
||||
# define LPI2C_MCFGR1_PINCFG1 (1 << LPI2C_MCFGR1_PINCFG_SHIFT)
|
||||
# define LPI2C_MCFGR1_PINCFG2 (2 << LPI2C_MCFGR1_PINCFG_SHIFT)
|
||||
# define LPI2C_MCFGR1_PINCFG3 (3 << LPI2C_MCFGR1_PINCFG_SHIFT)
|
||||
# define LPI2C_MCFGR1_PINCFG4 (4 << LPI2C_MCFGR1_PINCFG_SHIFT)
|
||||
# define LPI2C_MCFGR1_PINCFG5 (5 << LPI2C_MCFGR1_PINCFG_SHIFT)
|
||||
# define LPI2C_MCFGR1_PINCFG6 (6 << LPI2C_MCFGR1_PINCFG_SHIFT)
|
||||
# define LPI2C_MCFGR1_PINCFG7 (7 << LPI2C_MCFGR1_PINCFG_SHIFT)
|
||||
/* Bits 31-27 Reserved */
|
||||
|
||||
/* LPI2C Master Config Register 2 */
|
||||
|
||||
#define LPI2C_MCFG2_BUSIDLE_MASK (0xfff << 0) /* Bus Idle Timeout Period in Clock Cycles */
|
||||
#define LPI2C_MCFG2_BUSIDLE_DISABLE (0)
|
||||
# define LPI2C_MCFG2_BUSIDLE(n) (n & LPI2C_MCFG2_BUSIDLE_MASK)
|
||||
/* Bits 15-12 Reserved */
|
||||
#define LPI2C_MCFG2_FILTSCL_SHIFT (16)
|
||||
#define LPI2C_MCFG2_FILTSCL_MASK (15 << LPI2C_MCFG2_FILTSCL_SHIFT) /* Glitch Filter SCL */
|
||||
#define LPI2C_MCFG2_FILTSCL_DISABLE (0 << LPI2C_MCFG2_FILTSCL_SHIFT)
|
||||
# define LPI2C_MCFG2_FILTSCL_CYCLES(n) ((n << LPI2C_MCFG2_FILTSCL_SHIFT) & LPI2C_MCFG2_FILTSCL_MASK)
|
||||
/* Bits 23-20 Reserved */
|
||||
#define LPI2C_MCFG2_FILTSDA_SHIFT (24)
|
||||
#define LPI2C_MCFG2_FILTSDA_MASK (15 << LPI2C_MCFG2_FILTSDA_SHIFT) /* Glitch Filter SDA */
|
||||
#define LPI2C_MCFG2_FILTSDA_DISABLE (0 << LPI2C_MCFG2_FILTSDA_SHIFT)
|
||||
# define LPI2C_MCFG2_FILTSDA_CYCLES(n) ((n << LPI2C_MCFG2_FILTSDA_SHIFT) & LPI2C_MCFG2_FILTSDA_MASK)
|
||||
/* Bits 31-28 Reserved */
|
||||
/* LPI2C Master Config Register 3 */
|
||||
|
||||
/* Bits 7-0 Reserved */
|
||||
#define LPI2C_MCFG3_PINLOW_SHIFT (8)
|
||||
#define LPI2C_MCFG3_PINLOW_MASK (0xfff << LPI2C_MCFG3_PINLOW_SHIFT) /* Configure The Pin Low Timeout in Clock Cycles */
|
||||
# define LPI2C_MCFG3_PINLOW_CYCLES(n) ((n << LPI2C_MCFG3_PINLOW_SHIFT) & LPI2C_MCFG3_PINLOW_MASK)
|
||||
/* Bits 31-20 Reserved */
|
||||
|
||||
/* LPI2C Master Data Match Register */
|
||||
|
||||
#define LPI2C_MDMR_MATCH0_SHIFT (0)
|
||||
#define LPI2C_MDMR_MATCH0_MASK (0xff << LPI2C_MDMR_MATCH0_SHIFT) /* Match 0 Value */
|
||||
# define LPI2C_MDMR_MATCH0(n) ((n << LPI2C_MDMR_MATCH0_SHIFT) & LPI2C_MDMR_MATCH0_MASK)
|
||||
/* Bits 15-8 Reserved */
|
||||
#define LPI2C_MDMR_MATCH1_SHIFT (16)
|
||||
#define LPI2C_MDMR_MATCH1_MASK (0xff << LPI2C_MDMR_MATCH1_SHIFT) /* Match 1 Value */
|
||||
# define LPI2C_MDMR_MATCH1(n) ((n << LPI2C_MDMR_MATCH1_SHIFT) & LPI2C_MDMR_MATCH1_MASK)
|
||||
/* Bits 31-24 Reserved */
|
||||
|
||||
/* LPI2C Master Clock Configuration Register 0 */
|
||||
|
||||
#define LPI2C_MCCR0_CLKLO_SHIFT (0)
|
||||
#define LPI2C_MCCR0_CLKLO_MASK (0x3f << LPI2C_MCCR0_CLKLO_SHIFT) /* Clock Low Period */
|
||||
# define LPI2C_MCCR0_CLKLO(n) ((n << LPI2C_MCCR0_CLKLO_SHIFT) & LPI2C_MCCR0_CLKLO_MASK)
|
||||
/* Bits 7-6 Reserved */
|
||||
#define LPI2C_MCCR0_CLKHI_SHIFT (8)
|
||||
#define LPI2C_MCCR0_CLKHI_MASK (0x3f << LPI2C_MCCR0_CLKHI_SHIFT) /* Clock High Period */
|
||||
# define LPI2C_MCCR0_CLKHI(n) ((n << LPI2C_MCCR0_CLKHI_SHIFT) & LPI2C_MCCR0_CLKHI_MASK)
|
||||
/* Bits 15-14 Reserved */
|
||||
#define LPI2C_MCCR0_SETHOLD_SHIFT (16)
|
||||
#define LPI2C_MCCR0_SETHOLD_MASK (0x3f << LPI2C_MCCR0_SETHOLD_SHIFT) /* Setup Hold Delay */
|
||||
# define LPI2C_MCCR0_SETHOLD(n) ((n << LPI2C_MCCR0_SETHOLD_SHIFT) & LPI2C_MCCR0_SETHOLD_MASK)
|
||||
/* Bits 23-22 Reserved */
|
||||
#define LPI2C_MCCR0_DATAVD_SHIFT (24)
|
||||
#define LPI2C_MCCR0_DATAVD_MASK (0x3f << LPI2C_MCCR0_DATAVD_SHIFT) /* Setup Hold Delay */
|
||||
# define LPI2C_MCCR0_DATAVD(n) ((n << LPI2C_MCCR0_DATAVD_SHIFT) & LPI2C_MCCR0_DATAVD_MASK)
|
||||
/* Bits 31-30 Reserved */
|
||||
|
||||
/* LPI2C Master Clock Configuration Register 1 */
|
||||
|
||||
#define LPI2C_MCCR1_CLKLO_SHIFT (0)
|
||||
#define LPI2C_MCCR1_CLKLO_MASK (0x3f << LPI2C_MCCR1_CLKLO_SHIFT) /* Clock Low Period */
|
||||
# define LPI2C_MCCR1_CLKLO(n) ((n << LPI2C_MCCR1_CLKLO_SHIFT) & LPI2C_MCCR1_CLKLO_MASK)
|
||||
/* Bits 7-6 Reserved */
|
||||
#define LPI2C_MCCR1_CLKHI_SHIFT (8)
|
||||
#define LPI2C_MCCR1_CLKHI_MASK (0x3f << LPI2C_MCCR1_CLKHI_SHIFT) /* Clock High Period */
|
||||
# define LPI2C_MCCR1_CLKHI(n) ((n << LPI2C_MCCR1_CLKHI_SHIFT) & LPI2C_MCCR1_CLKHI_MASK)
|
||||
/* Bits 15-14 Reserved */
|
||||
#define LPI2C_MCCR1_SETHOLD_SHIFT (16)
|
||||
#define LPI2C_MCCR1_SETHOLD_MASK (0x3f << LPI2C_MCCR1_SETHOLD_SHIFT) /* Setup Hold Delay */
|
||||
# define LPI2C_MCCR1_SETHOLD(n) ((n << LPI2C_MCCR1_SETHOLD_SHIFT) & LPI2C_MCCR1_SETHOLD_MASK)
|
||||
/* Bits 23-22 Reserved */
|
||||
#define LPI2C_MCCR1_DATAVD_SHIFT (24)
|
||||
#define LPI2C_MCCR1_DATAVD_MASK (0x3f << LPI2C_MCCR1_DATAVD_SHIFT) /* Setup Hold Delay */
|
||||
# define LPI2C_MCCR1_DATAVD(n) ((n << LPI2C_MCCR1_DATAVD_SHIFT) & LPI2C_MCCR1_DATAVD_MASK)
|
||||
/* Bits 31-30 Reserved */
|
||||
|
||||
/* LPI2C Master FIFO Control Register */
|
||||
|
||||
#define LPI2C_MFCR_TXWATER_SHIFT (0)
|
||||
#define LPI2C_MFCR_TXWATER_MASK (3 << LPI2C_MFCR_TXWATER_SHIFT) /* Transmit FIFO Watermark*/
|
||||
# define LPI2C_MFCR_TXWATER(n) ((n << LPI2C_MFCR_TXWATER_SHIFT) & LPI2C_MFCR_TXWATER_MASK) /* Transmit FIFO Watermark*/
|
||||
/* Bits 15-2 Reserved */
|
||||
#define LPI2C_MFCR_RXWATER_SHIFT (16)
|
||||
#define LPI2C_MFCR_RXWATER_MASK (3 << LPI2C_MFCR_RXWATER_SHIFT) /* Receive FIFO Watermark */
|
||||
# define LPI2C_MFCR_RXWATER(n) ((n << LPI2C_MFCR_RXWATER_SHIFT) & LPI2C_MFCR_RXWATER_MASK) /* Transmit FIFO Watermark*/
|
||||
/* Bits 31-18 Reserved */
|
||||
|
||||
/* LPI2C Master FIFO Status Register */
|
||||
|
||||
#define LPI2C_MFSR_TXCOUNT_SHIFT (0)
|
||||
#define LPI2C_MFSR_TXCOUNT_MASK (3 << LPI2C_MFSR_TXCOUNT_SHIFT) /* Transmit FIFO Count */
|
||||
/* Bits 15-2 Reserved */
|
||||
#define LPI2C_MFSR_RXCOUNT_SHIFT (16)
|
||||
#define LPI2C_MFSR_RXCOUNT_MASK (3 << LPI2C_MFSR_RXCOUNT_SHIFT) /* Receive FIFO Count */
|
||||
/* Bits 31-18 Reserved */
|
||||
|
||||
/* LPI2C Master Transmit Data Register */
|
||||
|
||||
#define LPI2C_MTDR_DATA_SHIFT (0)
|
||||
#define LPI2C_MTDR_DATA_MASK (0xff << LPI2C_MTDR_DATA_SHIFT) /* Transmit Data */
|
||||
# define LPI2C_MTDR_DATA(n) (n & LPI2C_MTDR_DATA_MASK)
|
||||
#define LPI2C_MTDR_CMD_SHIFT (8)
|
||||
#define LPI2C_MTDR_CMD_MASK (7 << LPI2C_MTDR_CMD_SHIFT) /* Command Data */
|
||||
# define LPI2C_MTDR_CMD(n) ((n << LPI2C_MTDR_CMD_SHIFT) & LPI2C_MTDR_CMD_MASK)
|
||||
# define LPI2C_MTDR_CMD_TXD (0 << LPI2C_MTDR_CMD_SHIFT)
|
||||
# define LPI2C_MTDR_CMD_RXD (1 << LPI2C_MTDR_CMD_SHIFT)
|
||||
# define LPI2C_MTDR_CMD_STOP (2 << LPI2C_MTDR_CMD_SHIFT)
|
||||
# define LPI2C_MTDR_CMD_RXD_DISC (3 << LPI2C_MTDR_CMD_SHIFT)
|
||||
# define LPI2C_MTDR_CMD_START (4 << LPI2C_MTDR_CMD_SHIFT)
|
||||
# define LPI2C_MTDR_CMD_START_NACK (5 << LPI2C_MTDR_CMD_SHIFT)
|
||||
# define LPI2C_MTDR_CMD_START_HI (6 << LPI2C_MTDR_CMD_SHIFT)
|
||||
# define LPI2C_MTDR_CMD_START_HI_NACK (7 << LPI2C_MTDR_CMD_SHIFT)
|
||||
/* Bits 31-11 Reserved */
|
||||
|
||||
/* LPI2C Master Receive Data Register */
|
||||
|
||||
#define LPI2C_MRDR_DATA_SHIFT (0)
|
||||
#define LPI2C_MRDR_DATA_MASK (0xff << LPI2C_MRDR_DATA_SHIFT) /* Receive Data */
|
||||
/* Bits 13-8 Reserved */
|
||||
#define LPI2C_MRDR_RXEMPTY_SHIFT (14)
|
||||
#define LPI2C_MRDR_RXEMPTY_MASK (1 << LPI2C_MRDR_RXEMPTY_SHIFT) /* Rx Empty */
|
||||
/* Bits 31-15 Reserved */
|
||||
|
||||
/* LPI2C Slave Control Register */
|
||||
|
||||
#define LPI2C_SCR_SEN (1 << 0) /* Slave Enable Bit */
|
||||
#define LPI2C_SCR_RST (1 << 1) /* Software Reset Bit */
|
||||
/* Bits 3-2 Reserved */
|
||||
#define LPI2C_SCR_FILTEN (1 << 4) /* Filter Enable Bit */
|
||||
#define LPI2C_SCR_FILTDZ (1 << 5) /* Filter Doze Enable Bit */
|
||||
/* Bits 7-4 Reserved */
|
||||
#define LPI2C_SCR_RTF (1 << 8) /* Reset Transmit FIFO Bit */
|
||||
#define LPI2C_SCR_RRF (1 << 9) /* Reset Receive FIFO Bit */
|
||||
/* Bits 31-10 Reserved */
|
||||
|
||||
/* LPI2C Slave Status Register */
|
||||
|
||||
#define LPI2C_SSR_TDF (1 << 0) /* Transmit Data Flag Bit */
|
||||
#define LPI2C_SSR_RDF (1 << 1) /* Receive Data Flag Bit */
|
||||
#define LPI2C_SSR_AVF (1 << 2) /* Address Valid Flag Bit */
|
||||
#define LPI2C_SSR_TAF (1 << 3) /* Transmit ACK Flag Bit */
|
||||
/* Bits 7-4 Reserved */
|
||||
#define LPI2C_SSR_RSF (1 << 8) /* Repeated Start Flag Bit */
|
||||
#define LPI2C_SSR_SDF (1 << 9) /* STOP Detect Flag Bit */
|
||||
#define LPI2C_SSR_BEF (1 << 10) /* Bit Error Flag Bit */
|
||||
#define LPI2C_SSR_FEF (1 << 11) /* FIFO Error Flag Bit */
|
||||
#define LPI2C_SSR_AM0F (1 << 12) /* Address Match 0 Flag Bit */
|
||||
#define LPI2C_SSR_AM1F (1 << 13) /* Address Match 1 Flag Bit */
|
||||
#define LPI2C_SSR_GCF (1 << 14) /* General Call Flag Bit */
|
||||
#define LPI2C_SSR_SARF (1 << 15) /* SMBus Alert Response Flag Bit */
|
||||
/* Bits 23-16 Reserved */
|
||||
#define LPI2C_MSR_SBF (1 << 24) /* Slave Busy Flag Bit */
|
||||
#define LPI2C_MSR_BBF (1 << 25) /* Bus Busy Flag Bit */
|
||||
/* Bits 31-26 Reserved */
|
||||
|
||||
/* LPI2C Slave Interrupt Enable Register */
|
||||
|
||||
#define LPI2C_SIER_TDIE (1 << 0) /* Transmit Data Interrupt Enable Bit */
|
||||
#define LPI2C_SIER_RDIE (1 << 1) /* Receive Data Interrupt Enable Bit */
|
||||
#define LPI2C_SIER_AVIE (1 << 2) /* Address Valid Interrupt Enable Bit */
|
||||
#define LPI2C_SIER_TAIE (1 << 3) /* Transmit ACK Interrupt Enable Bit */
|
||||
/* Bits 7-4 Reserved */
|
||||
#define LPI2C_SIER_RSIE (1 << 8) /* Repeated Start Interrupt Enable Bit */
|
||||
#define LPI2C_SIER_SDIE (1 << 9) /* STOP Detect Interrupt Enable Bit */
|
||||
#define LPI2C_SIER_BEIE (1 << 10) /* Bit Error Interrupt Enable Bit */
|
||||
#define LPI2C_SIER_FEIE (1 << 11) /* FIFO Error Interrupt Enable Bit */
|
||||
#define LPI2C_SIER_AM0IE (1 << 12) /* Address Match 0 Interrupt Enable Bit */
|
||||
#define LPI2C_SIER_AM1IE (1 << 13) /* Address Match 1 Interrupt Enable Bit */
|
||||
#define LPI2C_SIER_GCIE (1 << 14) /* General Call Interrupt Enable Bit */
|
||||
#define LPI2C_SIER_SARIE (1 << 15) /* SMBus Alert Response Interrupt Enable Bit */
|
||||
/* Bits 31-16 Reserved */
|
||||
|
||||
/* LPI2C Slave DMA Enable Register */
|
||||
|
||||
#define LPI2C_SDER_TDDE (1 << 0) /* Transmit Data DMA Enable Bit */
|
||||
#define LPI2C_SDER_RDDE (1 << 1) /* Transmit Data DMA Enable Bit */
|
||||
#define LPI2C_SDER_AVDE (1 << 2) /* Address Valid DMA Enable Bit */
|
||||
/* Bits 31-3 Reserved */
|
||||
|
||||
/* LPI2C Slave Configuration Register 1 */
|
||||
|
||||
#define LPI2C_SCFGR1_ADRSTALL (1 << 0) /* Address SCL Stall */
|
||||
#define LPI2C_SCFGR1_RXSTALL (1 << 1) /* RX SCL Stall */
|
||||
#define LPI2C_SCFGR1_TXSTALL (1 << 2) /* TX Data SCL Stall */
|
||||
#define LPI2C_SCFGR1_ACKSTALL (1 << 3) /* ACK SCL Stall */
|
||||
/* Bits 7-4 Reserved */
|
||||
#define LPI2C_SCFGR1_GCEN (1 << 8) /* General Call Enable */
|
||||
#define LPI2C_SCFGR1_SAEN (1 << 9) /* SMBus Alert Enable */
|
||||
#define LPI2C_SCFGR1_TXCFG (1 << 10) /* Transmit Flag Configuration */
|
||||
#define LPI2C_SCFGR1_RXCFG (1 << 11) /* Receive Data Configuration */
|
||||
#define LPI2C_SCFGR1_IFNACK (1 << 12) /* Ignore NACK */
|
||||
#define LPI2C_SCFGR1_HSMEN (1 << 13) /* High Speed Mode Enable */
|
||||
/* Bits 15-14 Reserved */
|
||||
#define LPI2C_SCFG1_ADDRCFG_SHIFT (16)
|
||||
#define LPI2C_SCFG1_ADDRCFG_MASK (7 << LPI2C_SCFG1_ADDRCFG_SHIFT) /* Address Configuration Bit Mask */
|
||||
# define LPI2C_SCFG1_ADDRCFG(n) ((n << LPI2C_SCFG1_ADDRCFG_SHIFT) & LPI2C_SCFG1_ADDRCFG_MASK)
|
||||
# define LPI2C_SCFG1_ADDRCFG0 (0 << LPI2C_SCFG1_ADDRCFG_SHIFT)
|
||||
# define LPI2C_SCFG1_ADDRCFG1 (2 << LPI2C_SCFG1_ADDRCFG_SHIFT)
|
||||
# define LPI2C_SCFG1_ADDRCFG2 (2 << LPI2C_SCFG1_ADDRCFG_SHIFT)
|
||||
# define LPI2C_SCFG1_ADDRCFG3 (3 << LPI2C_SCFG1_ADDRCFG_SHIFT)
|
||||
# define LPI2C_SCFG1_ADDRCFG4 (4 << LPI2C_SCFG1_ADDRCFG_SHIFT)
|
||||
# define LPI2C_SCFG1_ADDRCFG5 (5 << LPI2C_SCFG1_ADDRCFG_SHIFT)
|
||||
# define LPI2C_SCFG1_ADDRCFG6 (6 << LPI2C_SCFG1_ADDRCFG_SHIFT)
|
||||
# define LPI2C_SCFG1_ADDRCFG7 (7 << LPI2C_SCFG1_ADDRCFG_SHIFT)
|
||||
/* Bits 31-19 Reserved */
|
||||
|
||||
/* LPI2C Slave Configuration Register 2 */
|
||||
|
||||
#define LPI2C_SCFG2_CLKHOLD_MASK (15 << 0) /* Clock Hold Time */
|
||||
# define LPI2C_SCFG2_CLKHOLD(n) (n & LPI2C_SCFG2_CLKHOLD_MASK)
|
||||
/* Bits 7-4 Reserved */
|
||||
#define LPI2C_SCFG2_DATAVD_SHIFT (8)
|
||||
#define LPI2C_SCFG2_DATAVD_MASK (0x3f << LPI2C_SCFG2_DATAVD_SHIFT) /* Data Valid Delay */
|
||||
# define LPI2C_SCFG2_DATAVD(n) ((n << LPI2C_SCFG2_DATAVD_SHIFT) & LPI2C_SCFG2_DATAVD_MASK)
|
||||
/* Bits 15-14 Reserved */
|
||||
#define LPI2C_SCFG2_FILTSCL_SHIFT (16)
|
||||
#define LPI2C_SCFG2_FILTSCL_MASK (15 << LPI2C_SCFG2_FILTSCL_SHIFT) /* Glitch Filter SCL */
|
||||
#define LPI2C_SCFG2_FILTSCL_DISABLE (0 << LPI2C_SCFG2_FILTSCL_SHIFT)
|
||||
# define LPI2C_SCFG2_FILTSCL_CYCLES(n) ((n << LPI2C_SCFG2_FILTSCL_SHIFT) & LPI2C_SCFG2_FILTSCL_MASK)
|
||||
/* Bits 23-20 Reserved */
|
||||
#define LPI2C_SCFG2_FILTSDA_SHIFT (24)
|
||||
#define LPI2C_SCFG2_FILTSDA_MASK (15 << LPI2C_SCFG2_FILTSDA_SHIFT) /* Glitch Filter SDA */
|
||||
#define LPI2C_SCFG2_FILTSDA_DISABLE (0 << LPI2C_SCFG2_FILTSDA_SHIFT)
|
||||
# define LPI2C_SCFG2_FILTSDA_CYCLES(n) ((n << LPI2C_SCFG2_FILTSDA_SHIFT) & LPI2C_SCFG2_FILTSDA_MASK)
|
||||
/* Bits 31-28 Reserved */
|
||||
|
||||
/* LPI2C Slave Address Match Register */
|
||||
|
||||
/* Bit 0 Reserved */
|
||||
#define LPI2C_SAMR_ADDR0_SHIFT (1)
|
||||
#define LPI2C_SAMR_ADDR0_MASK (0x3ff << LPI2C_SAMR_ADDR0_SHIFT) /* Address 0 Value */
|
||||
# define LPI2C_SAMR_ADDR0(n) ((n << LPI2C_SAMR_ADDR0_SHIFT) & LPI2C_SAMR_ADDR0_MASK)
|
||||
/* Bits 16-11 Reserved */
|
||||
#define LPI2C_SAMR_ADDR1_SHIFT (17)
|
||||
#define LPI2C_SAMR_ADDR1_MASK (0x3ff << LPI2C_SAMR_ADDR1_SHIFT) /* Address 1 Value */
|
||||
# define LPI2C_SAMR_ADDR1(n) ((n << LPI2C_SAMR_ADDR1_SHIFT) & LPI2C_SAMR_ADDR1_MASK)
|
||||
/* Bits 31-27 Reserved */
|
||||
|
||||
/* LPI2C Slave Address Status Register */
|
||||
|
||||
#define LPI2C_SASR_RADDR_MASK (0x7ff << 0) /* Received Address */
|
||||
/* Bits 16-11 Reserved */
|
||||
#define LPI2C_SASR_ANV (1 << 14) /* Address Not Valid */
|
||||
/* Bits 31-15 Reserved */
|
||||
|
||||
/* LPI2C Slave Transmit ACK Register */
|
||||
|
||||
#define LPI2C_STAR_TXNACK (1 << 0) /* Transmit NACK */
|
||||
/* Bits 31-1 Reserved */
|
||||
|
||||
/* LPI2C Slave Transmit Data Register */
|
||||
|
||||
#define LPI2C_STDR_DATA_SHIFT (0)
|
||||
#define LPI2C_STDR_DATA_MASK (0xff << LPI2C_STDR_DATA_SHIFT) /* Transmit Data */
|
||||
# define LPI2C_STDR_DATA(n) ((n << LPI2C_STDR_DATA_SHIFT) & LPI2C_STDR_DATA_MASK)
|
||||
/* Bits 31-8 Reserved */
|
||||
|
||||
/* LPI2C Slave Receive Data Register */
|
||||
|
||||
#define LPI2C_SRDR_DATA_SHIFT (0)
|
||||
#define LPI2C_SRDR_DATA_MASK (0xff << LPI2C_SRDR_DATA_SHIFT) /* Receive Data */
|
||||
# define LPI2C_SRDR_DATA(n) ((n << LPI2C_SRDR_DATA_SHIFT) & LPI2C_SRDR_DATA_MASK)
|
||||
/* Bits 8-31 Reserved */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_LPI2C_H */
|
||||
354
arch/arm/src/s32k1xx/hardware/s32k1xx_lpspi.h
Normal file
354
arch/arm/src/s32k1xx/hardware/s32k1xx_lpspi.h
Normal file
@ -0,0 +1,354 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/src/s32k1xx/hardware/s32k1xx_lpspi.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Pavlina Koleva <pavlinaikoleva19@gmail.com>
|
||||
* Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_LPSPI_H
|
||||
#define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_LPSPI_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "hardware/s32k1xx_memorymap.h"
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
***************************************************************************************************/
|
||||
|
||||
/* Register offsets *********************************************************************************/
|
||||
|
||||
#define S32K1XX_LPSPI_VERID_OFFSET 0x0000 /* Version ID Register offset */
|
||||
#define S32K1XX_LPSPI_PARAM_OFFSET 0x0004 /* Parameter Register offset */
|
||||
#define S32K1XX_LPSPI_CR_OFFSET 0x0010 /* Control Register offset */
|
||||
#define S32K1XX_LPSPI_SR_OFFSET 0x0014 /* Status Register offset */
|
||||
#define S32K1XX_LPSPI_IER_OFFSET 0x0018 /* Interrupt Enable Register offset */
|
||||
#define S32K1XX_LPSPI_DER_OFFSET 0x001C /* DMA Enable Register offset */
|
||||
#define S32K1XX_LPSPI_CFGR0_OFFSET 0x0020 /* Configuration Register 0 offset */
|
||||
#define S32K1XX_LPSPI_CFGR1_OFFSET 0x0024 /* Configuration Register 1 offset */
|
||||
#define S32K1XX_LPSPI_DMR0_OFFSET 0x0030 /* Data Match Register 0 offset */
|
||||
#define S32K1XX_LPSPI_DMR1_OFFSET 0x0034 /* Data Match Register 1 offset */
|
||||
#define S32K1XX_LPSPI_CCR_OFFSET 0x0040 /* Clock Configuration Register offset */
|
||||
#define S32K1XX_LPSPI_FCR_OFFSET 0x0058 /* FIFO Control Register offset */
|
||||
#define S32K1XX_LPSPI_FSR_OFFSET 0x005C /* FIFO Status Register offset */
|
||||
#define S32K1XX_LPSPI_TCR_OFFSET 0x0060 /* Transmit Command Register offset */
|
||||
#define S32K1XX_LPSPI_TDR_OFFSET 0x0064 /* Transmit Data Register offset */
|
||||
#define S32K1XX_LPSPI_RSR_OFFSET 0x0070 /* Receive Status Register offset */
|
||||
#define S32K1XX_LPSPI_RDR_OFFSET 0x0074 /* Receive Data Register offset */
|
||||
|
||||
/* Register addresses *******************************************************************************/
|
||||
|
||||
#define S32K1XX_LPSPI0_VERID (S32K1XX_LPSPI0_BASE + S32K1XX_LPSPI_VERID_OFFSET)
|
||||
#define S32K1XX_LPSPI0_PARAM (S32K1XX_LPSPI0_BASE + S32K1XX_LPSPI_PARAM_OFFSET)
|
||||
#define S32K1XX_LPSPI0_CR (S32K1XX_LPSPI0_BASE + S32K1XX_LPSPI_CR_OFFSET)
|
||||
#define S32K1XX_LPSPI0_SR (S32K1XX_LPSPI0_BASE + S32K1XX_LPSPI_SR_OFFSET)
|
||||
#define S32K1XX_LPSPI0_IER (S32K1XX_LPSPI0_BASE + S32K1XX_LPSPI_IER_OFFSET)
|
||||
#define S32K1XX_LPSPI0_DER (S32K1XX_LPSPI0_BASE + S32K1XX_LPSPI_DER_OFFSET)
|
||||
#define S32K1XX_LPSPI0_CFGR0 (S32K1XX_LPSPI0_BASE + S32K1XX_LPSPI_CFGR0_OFFSET)
|
||||
#define S32K1XX_LPSPI0_CFGR1 (S32K1XX_LPSPI0_BASE + S32K1XX_LPSPI_CFGR1_OFFSET)
|
||||
#define S32K1XX_LPSPI0_DMR0 (S32K1XX_LPSPI0_BASE + S32K1XX_LPSPI_DMR0_OFFSET)
|
||||
#define S32K1XX_LPSPI0_DMR1 (S32K1XX_LPSPI0_BASE + S32K1XX_LPSPI_DMR1_OFFSET)
|
||||
#define S32K1XX_LPSPI0_CCR (S32K1XX_LPSPI0_BASE + S32K1XX_LPSPI_CCR_OFFSET)
|
||||
#define S32K1XX_LPSPI0_FCR (S32K1XX_LPSPI0_BASE + S32K1XX_LPSPI_FCR_OFFSET)
|
||||
#define S32K1XX_LPSPI0_FSR (S32K1XX_LPSPI0_BASE + S32K1XX_LPSPI_FSR_OFFSET)
|
||||
#define S32K1XX_LPSPI0_TCR (S32K1XX_LPSPI0_BASE + S32K1XX_LPSPI_TCR_OFFSET)
|
||||
#define S32K1XX_LPSPI0_TDR (S32K1XX_LPSPI0_BASE + S32K1XX_LPSPI_TDR_OFFSET)
|
||||
#define S32K1XX_LPSPI0_RSR (S32K1XX_LPSPI0_BASE + S32K1XX_LPSPI_RSR_OFFSET)
|
||||
#define S32K1XX_LPSPI0_RDR (S32K1XX_LPSPI0_BASE + S32K1XX_LPSPI_RDR_OFFSET)
|
||||
|
||||
#define S32K1XX_LPSPI1_VERID (S32K1XX_LPSPI1_BASE + S32K1XX_LPSPI_VERID_OFFSET)
|
||||
#define S32K1XX_LPSPI1_PARAM (S32K1XX_LPSPI1_BASE + S32K1XX_LPSPI_PARAM_OFFSET)
|
||||
#define S32K1XX_LPSPI1_CR (S32K1XX_LPSPI1_BASE + S32K1XX_LPSPI_CR_OFFSET)
|
||||
#define S32K1XX_LPSPI1_SR (S32K1XX_LPSPI1_BASE + S32K1XX_LPSPI_SR_OFFSET)
|
||||
#define S32K1XX_LPSPI1_IER (S32K1XX_LPSPI1_BASE + S32K1XX_LPSPI_IER_OFFSET)
|
||||
#define S32K1XX_LPSPI1_DER (S32K1XX_LPSPI1_BASE + S32K1XX_LPSPI_DER_OFFSET)
|
||||
#define S32K1XX_LPSPI1_CFGR0 (S32K1XX_LPSPI1_BASE + S32K1XX_LPSPI_CFGR0_OFFSET)
|
||||
#define S32K1XX_LPSPI1_CFGR1 (S32K1XX_LPSPI1_BASE + S32K1XX_LPSPI_CFGR1_OFFSET)
|
||||
#define S32K1XX_LPSPI1_DMR0 (S32K1XX_LPSPI1_BASE + S32K1XX_LPSPI_DMR0_OFFSET)
|
||||
#define S32K1XX_LPSPI1_DMR1 (S32K1XX_LPSPI1_BASE + S32K1XX_LPSPI_DMR1_OFFSET)
|
||||
#define S32K1XX_LPSPI1_CCR (S32K1XX_LPSPI1_BASE + S32K1XX_LPSPI_CCR_OFFSET)
|
||||
#define S32K1XX_LPSPI1_FCR (S32K1XX_LPSPI1_BASE + S32K1XX_LPSPI_FCR_OFFSET)
|
||||
#define S32K1XX_LPSPI1_FSR (S32K1XX_LPSPI1_BASE + S32K1XX_LPSPI_FSR_OFFSET)
|
||||
#define S32K1XX_LPSPI1_TCR (S32K1XX_LPSPI1_BASE + S32K1XX_LPSPI_TCR_OFFSET)
|
||||
#define S32K1XX_LPSPI1_TDR (S32K1XX_LPSPI1_BASE + S32K1XX_LPSPI_TDR_OFFSET)
|
||||
#define S32K1XX_LPSPI1_RSR (S32K1XX_LPSPI1_BASE + S32K1XX_LPSPI_RSR_OFFSET)
|
||||
#define S32K1XX_LPSPI1_RDR (S32K1XX_LPSPI1_BASE + S32K1XX_LPSPI_RDR_OFFSET)
|
||||
|
||||
#define S32K1XX_LPSPI2_VERID (S32K1XX_LPSPI2_BASE + S32K1XX_LPSPI_VERID_OFFSET)
|
||||
#define S32K1XX_LPSPI2_PARAM (S32K1XX_LPSPI2_BASE + S32K1XX_LPSPI_PARAM_OFFSET)
|
||||
#define S32K1XX_LPSPI2_CR (S32K1XX_LPSPI2_BASE + S32K1XX_LPSPI_CR_OFFSET)
|
||||
#define S32K1XX_LPSPI2_SR (S32K1XX_LPSPI2_BASE + S32K1XX_LPSPI_SR_OFFSET)
|
||||
#define S32K1XX_LPSPI2_IER (S32K1XX_LPSPI2_BASE + S32K1XX_LPSPI_IER_OFFSET)
|
||||
#define S32K1XX_LPSPI2_DER (S32K1XX_LPSPI2_BASE + S32K1XX_LPSPI_DER_OFFSET)
|
||||
#define S32K1XX_LPSPI2_CFGR0 (S32K1XX_LPSPI2_BASE + S32K1XX_LPSPI_CFGR0_OFFSET)
|
||||
#define S32K1XX_LPSPI2_CFGR1 (S32K1XX_LPSPI2_BASE + S32K1XX_LPSPI_CFGR1_OFFSET)
|
||||
#define S32K1XX_LPSPI2_DMR0 (S32K1XX_LPSPI2_BASE + S32K1XX_LPSPI_DMR0_OFFSET)
|
||||
#define S32K1XX_LPSPI2_DMR1 (S32K1XX_LPSPI2_BASE + S32K1XX_LPSPI_DMR1_OFFSET)
|
||||
#define S32K1XX_LPSPI2_CCR (S32K1XX_LPSPI2_BASE + S32K1XX_LPSPI_CCR_OFFSET)
|
||||
#define S32K1XX_LPSPI2_FCR (S32K1XX_LPSPI2_BASE + S32K1XX_LPSPI_FCR_OFFSET)
|
||||
#define S32K1XX_LPSPI2_FSR (S32K1XX_LPSPI2_BASE + S32K1XX_LPSPI_FSR_OFFSET)
|
||||
#define S32K1XX_LPSPI2_TCR (S32K1XX_LPSPI2_BASE + S32K1XX_LPSPI_TCR_OFFSET)
|
||||
#define S32K1XX_LPSPI2_TDR (S32K1XX_LPSPI2_BASE + S32K1XX_LPSPI_TDR_OFFSET)
|
||||
#define S32K1XX_LPSPI2_RSR (S32K1XX_LPSPI2_BASE + S32K1XX_LPSPI_RSR_OFFSET)
|
||||
#define S32K1XX_LPSPI2_RDR (S32K1XX_LPSPI2_BASE + S32K1XX_LPSPI_RDR_OFFSET)
|
||||
|
||||
/* Register bit definitions *************************************************************************/
|
||||
|
||||
/* Version ID Register */
|
||||
|
||||
#define LPSPI_VERID_FEATURE_SHIFT (0) /* Bits 0-15: Module Identification Number */
|
||||
#define LPSPI_VERID_FEATURE_MASK (0xffff << LPSPI_VERID_FEATURE_SHIFT)
|
||||
#define LPSPI_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number */
|
||||
#define LPSPI_VERID_MINOR_MASK (0xff << LPSPI_VERID_MINOR_SHIFT)
|
||||
#define LPSPI_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number */
|
||||
#define LPSPI_VERID_MAJOR_MASK (0xff << LPSPI_VERID_MAJOR_SHIFT)
|
||||
|
||||
/* Parameter Register */
|
||||
|
||||
#define LPSPI_PARAM_TXFIFO_SHIFT (0) /* Bits 0-7: Transmit FIFO Size */
|
||||
#define LPSPI_PARAM_TXFIFO_MASK (0xff << LPSPI_PARAM_TXFIFO_SHIFT)
|
||||
#define LPSPI_PARAM_RXFIFO_SHIFT (8) /* Bits 8-15: Receive FIFO Size */
|
||||
#define LPSPI_PARAM_RXFIFO_MASK (0xff << LPSPI_PARAM_RXFIFO_SHIFT)
|
||||
#define LPSPI_PARAM_PCSNUM_SHIFT (16) /* Bits 16-23: PCS Number */
|
||||
#define LPSPI_PARAM_PCSNUM_MASK (0xff << LPSPI_PARAM_PCSNUM_SHIFT)
|
||||
/* Bits 24-31: Reserved */
|
||||
|
||||
/* Control Register */
|
||||
|
||||
#define LPSPI_CR_MEN (1 << 0) /* Bit 0: Module Enable */
|
||||
#define LPSPI_CR_RST (1 << 1) /* Bit 1: Software Reset */
|
||||
#define LPSPI_CR_DOZEN (1 << 2) /* Bit 2: Doze mode enable */
|
||||
# define LPSPI_CR_DOZEN_EN (0 << 2) /* Module is enabled in Doze mode */
|
||||
# define LPSPI_CR_DOZEN_DIS (1 << 2) /* Module is disabled in Doze mode */
|
||||
#define LPSPI_CR_DBGEN (1 << 3) /* Bit 3: Debug Enable */
|
||||
/* Bits 4-7: Reserved */
|
||||
#define LPSPI_CR_RTF (1 << 8) /* Bit 8: Reset Transmit FIFO */
|
||||
#define LPSPI_CR_RRF (1 << 9) /* Bit 9: Reset Receive FIFO */
|
||||
/* Bits 10-31: Reserved */
|
||||
|
||||
/* Status Register */
|
||||
|
||||
#define LPSPI_SR_TDF (1 << 0) /* Bit 0: Transmit Data Flag */
|
||||
#define LPSPI_SR_RDF (1 << 1) /* Bit 1: Receive Data Flag */
|
||||
/* Bits 2-7: Reserved */
|
||||
#define LPSPI_SR_WCF (1 << 8) /* Bit 8: Word Complete Flag */
|
||||
#define LPSPI_SR_FCF (1 << 9) /* Bit 9: Frame Complete Flag */
|
||||
#define LPSPI_SR_TCF (1 << 10) /* Bit 10: Transfer Complete Flag */
|
||||
#define LPSPI_SR_TEF (1 << 11) /* Bit 11: Transmit Error Flag */
|
||||
#define LPSPI_SR_REF (1 << 12) /* Bit 12: Receive Error Flag */
|
||||
#define LPSPI_SR_DMF (1 << 13) /* Bit 13: Data Match Flag */
|
||||
/* Bits 14-23: Reserved */
|
||||
#define LPSPI_SR_MBF (1 << 24) /* Bit 24: Module Busy Flag */
|
||||
/* Bits 25-31: Reserved */
|
||||
|
||||
/* Interrupt Enable Register */
|
||||
|
||||
#define LPSPI_IER_TDIE (1 << 0) /* Bit 0: Transmit Data Interrupt Enable */
|
||||
#define LPSPI_IER_RDIE (1 << 1) /* Bit 1: Receive Data Interrupt Enable */
|
||||
/* Bits 2-7: Reserved */
|
||||
#define LPSPI_IER_WCIE (1 << 8) /* Bit 8: Word Complete Interrupt Enable */
|
||||
#define LPSPI_IER_FCIE (1 << 9) /* Bit 9: Frame Complete Interrupt Enable */
|
||||
#define LPSPI_IER_TCIE (1 << 10) /* Bit 10: Transfer Complete Interrupt Enable */
|
||||
#define LPSPI_IER_TEIE (1 << 11) /* Bit 11: Transmit Error Interrupt Enable */
|
||||
#define LPSPI_IER_REIE (1 << 12) /* Bit 12: Receive Error Interrupt Enable */
|
||||
#define LPSPI_IER_DMIE (1 << 13) /* Bit 13: Data Match Interrupt Enable */
|
||||
/* Bits 14-31: Reserved */
|
||||
|
||||
/* DMA Enable Register */
|
||||
|
||||
#define LPSPI_DER_TDDE (1 << 0) /* Bit 0: Transmit Data DMA Enable */
|
||||
#define LPSPI_DER_RDDE (1 << 1) /* Bit 1: Receive Data DMA Enable */
|
||||
/* Bits 2-31: Reserved */
|
||||
|
||||
/* Configuration Register 0 */
|
||||
|
||||
#define LPSPI_CFGR0_HREN (1 << 0) /* Bit 0: Host Request Enable */
|
||||
#define LPSPI_CFGR0_HRPOL (1 << 1) /* Bit 1: Host Request Polarity */
|
||||
# define LPSPI_CFGR0_HRPOL_LOW (0 << 1) /* Active low */
|
||||
# define LPSPI_CFGR0_HRPOL_HIGH (1 << 1) /* Active high */
|
||||
#define LPSPI_CFGR0_HRSEL (1 << 2) /* Bit 2: Host Request Select */
|
||||
# define LPSPI_CFGR0_HRSEL_HREQ (0 << 2) /* Host request input is the LPSPI_HREQ pin */
|
||||
# define LPSPI_CFGR0_HRSEL_INTR (1 << 2) /* Host request input is the input trigger */
|
||||
/* Bits 3-7: Reserved */
|
||||
#define LPSPI_CFGR0_CIRFIFO (1 << 8) /* Bits 8: Circular FIFO Enable */
|
||||
#define LPSPI_CFGR0_RDMO (1 << 9) /* Bits 9: Receive Data Match Only */
|
||||
# define LPSPI_CFGR0_RDMO_FIFO (0 << 9) /* RD stored in the receive FIFO as in normal operations */
|
||||
# define LPSPI_CFGR0_RDMO_DMF (1 << 9) /* RD discarded unless the Data Match Flag (DMF) is set */
|
||||
/* Bits 10-31: Reserved */
|
||||
|
||||
/* Configuration Register 1 */
|
||||
|
||||
#define LPSPI_CFGR1_MASTER (1 << 0) /* Bit 0: Master Mode */
|
||||
#define LPSPI_CFGR1_SAMPLE (1 << 1) /* Bit 1: Sample Point */
|
||||
# define LPSPI_CFGR1_SAMPLE_SCK (0 << 1) /* Input data is sampled on SCK edge */
|
||||
# define LPSPI_CFGR1_SAMPLE_DELAY (1 << 1) /* Input data is sampled on delayed SCK edge */
|
||||
#define LPSPI_CFGR1_AUTOPCS (1 << 2) /* Bit 2: Automatic PCS enabled */
|
||||
#define LPSPI_CFGR1_NOSTALL (1 << 3) /* Bit 3: No Stall enabled */
|
||||
/* Bits 4-7: Reserved */
|
||||
#define LPSPI_CFGR1_PCSPOL_SHIFT (8) /* Bits 8-11: Peripheral Chip Select Polarity */
|
||||
#define LPSPI_CFGR1_PCSPOL_MASK (0xf << LPSPI_CFGR1_PCSPOL_SHIFT)
|
||||
# define LPSPI_CFGR1_PCSPOL_LOW (0 << LPSPI_CFGR1_PCSPOL_SHIFT) /* The Peripheral Chip Select pin PCSx is active low */
|
||||
# define LPSPI_CFGR1_PCSPOL_HIGH (1 << LPSPI_CFGR1_PCSPOL_SHIFT) /* The Peripheral Chip Select pin PCSx is active high */
|
||||
/* Bits 12-15: Reserved */
|
||||
#define LPSPI_CFGR1_MATCFG_SHIFT (16) /* Bits 16-18: Match Configuration */
|
||||
#define LPSPI_CFGR1_MATCFG_MASK (7 << LPSPI_CFGR1_MATCFG_SHIFT)
|
||||
# define LPSPI_CFGR1_MATCFG(n) ((uint32_t)(n) << LPSPI_CFGR1_MATCFG_SHIFT)
|
||||
/* Bits 19-23: Reserved */
|
||||
#define LPSPI_CFGR1_PINCFG_SHIFT (24) /* Bits 24-25: Pin Configuration */
|
||||
#define LPSPI_CFGR1_PINCFG_MASK (3 << LPSPI_CFGR1_PINCFG_SHIFT)
|
||||
# define LPSPI_CFGR1_PINCFG_SIN_SOUT (0 << LPSPI_CFGR1_PINCFG_SHIFT) /* SIN is used for input data and SOUT is used for output data */
|
||||
# define LPSPI_CFGR1_PINCFG_SIN_SIN (1 << LPSPI_CFGR1_PINCFG_SHIFT) /* SIN is used for both input and output data */
|
||||
# define LPSPI_CFGR1_PINCFG_SOUT_SOUT (2 << LPSPI_CFGR1_PINCFG_SHIFT) /* SOUT is used for both input and output data */
|
||||
# define LPSPI_CFGR1_PINCFG_SOUT_SIN (3 << LPSPI_CFGR1_PINCFG_SHIFT) /* SOUT is used for input data and SIN is used for output data */
|
||||
# define LPSPI_CFGR1_PINCFG(n) ((uint32_t)(n) << LPSPI_CFGR1_PINCFG_SHIFT)
|
||||
#define LPSPI_CFGR1_OUTCFG (1 << 26) /* Bit 26: Output Config */
|
||||
# define LPSPI_CFGR1_OUTCFG_RETAIN (0 << 26) /* Output data retains last value when chip select is negated */
|
||||
# define LPSPI_CFGR1_OUTCFG_TRISTATE (1 << 26) /* Output data is tristated when chip select is negated */
|
||||
#define LPSPI_CFGR1_PCSCFG (1 << 27) /* Bit 27: Peripheral Chip Select Configuration */
|
||||
# define LPSPI_CFGR1_PCSCFG_EN (0 << 27) /* PCS[3:2] are enabled */
|
||||
# define LPSPI_CFGR1_PCSCFG_DIS (1 << 27) /* PCS[3:2] are disabled */
|
||||
/* Bits 28-31: Reserved */
|
||||
|
||||
/* Data Match Register 0 */
|
||||
|
||||
#define LPSPI_DMR0_MATCH0_SHIFT (0) /* Bits 0-31: Match 0 Value */
|
||||
#define LPSPI_DMR0_MATCH0_MASK (0xffffffff << LPSPI_DMR0_MATCH0_SHIFT)
|
||||
# define LPSPI_DMR0_MATCH0(n) ((uint32_t)(n) << LPSPI_DMR0_MATCH0_SHIFT)
|
||||
|
||||
/* Data Match Register 0 */
|
||||
|
||||
#define LPSPI_DMR1_MATCH1_SHIFT (0) /* Bits 0-31: Match 1 Value */
|
||||
#define LPSPI_DMR1_MATCH1_MASK (0xffffffff << LPSPI_DMR1_MATCH1_SHIFT)
|
||||
# define LPSPI_DMR1_MATCH1(n) ((uint32_t)(n) << LPSPI_DMR1_MATCH1_SHIFT)
|
||||
|
||||
/* Clock Configuration Register */
|
||||
|
||||
#define LPSPI_CCR_SCKDIV_SHIFT (0) /* Bits 0-7: SCK Divider */
|
||||
#define LPSPI_CCR_SCKDIV_MASK (0xff << LPSPI_CCR_SCKDIV_SHIFT)
|
||||
# define LPSPI_CCR_SCKDIV(n) ((uint32_t)(n) << LPSPI_CCR_SCKDIV_SHIFT)
|
||||
#define LPSPI_CCR_DBT_SHIFT (8) /* Bits 8-15: Delay Between Transfers */
|
||||
#define LPSPI_CCR_DBT_MASK (0xff << LPSPI_CCR_DBT_SHIFT)
|
||||
# define LPSPI_CCR_DBT(n) ((uint32_t)(n) << LPSPI_CCR_DBT_SHIFT)
|
||||
#define LPSPI_CCR_PCSSCK_SHIFT (16) /* Bits 16-23: PCS-to-SCK Delay */
|
||||
#define LPSPI_CCR_PCSSCK_MASK (0xff << LPSPI_CCR_PCSSCK_SHIFT)
|
||||
# define LPSPI_CCR_PCSSCK(n) ((uint32_t)(n) << LPSPI_CCR_PCSSCK_SHIFT)
|
||||
#define LPSPI_CCR_SCKPCS_SHIFT (24) /* Bits 24-31: SCK-to-PCS Delay */
|
||||
#define LPSPI_CCR_SCKPCS_MASK (0xff << LPSPI_CCR_SCKPCS_SHIFT)
|
||||
# define LPSPI_CCR_SCKPCS(n) ((uint32_t)(n) << LPSPI_CCR_SCKPCS_SHIFT)
|
||||
|
||||
/* FIFO Control Register */
|
||||
|
||||
#define LPSPI_FCR_TXWATER_SHIFT (0) /* Bits 0-3: Transmit FIFO Watermark */
|
||||
#define LPSPI_FCR_TXWATER_MASK (0xf << LPSPI_FCR_TXWATER_SHIFT)
|
||||
# define LPSPI_FCR_TXWATER(n) ((uint32_t)(n) << LPSPI_FCR_TXWATER_SHIFT)
|
||||
/* Bits 4-7: Reserved */
|
||||
/* Bits 8-15: Reserved */
|
||||
#define LPSPI_FCR_RXWATER_SHIFT (8) /* Bits 16-19: Receive FIFO Watermark */
|
||||
#define LPSPI_FCR_RXWATER_MASK (0xf << LPSPI_FCR_RXWATER_SHIFT)
|
||||
# define LPSPI_FCR_RXWATER(n) ((uint32_t)(n) << LPSPI_FCR_RXWATER_SHIFT)
|
||||
/* Bits 20-23: Reserved */
|
||||
/* Bits 24-31: Reserved */
|
||||
|
||||
/* FIFO Status Register */
|
||||
|
||||
#define LPSPI_FSR_TXCOUNT_SHIFT (0) /* Bits 0-4: Transmit FIFO Count */
|
||||
#define LPSPI_FSR_TXCOUNT_MASK (0x1f << LPSPI_FSR_TXCOUNT_SHIFT)
|
||||
/* Bits 5-7: Reserved */
|
||||
/* Bits 8-15: Reserved */
|
||||
#define LPSPI_FSR_RXCOUNT_SHIFT (16) /* Bits 16-20: Receive FIFO Count */
|
||||
#define LPSPI_FSR_RXCOUNT_MASK (0x1f << LPSPI_FSR_RXCOUNT_SHIFT)
|
||||
/* Bits 21-23: Reserved */
|
||||
/* Bits 24-31: Reserved */
|
||||
|
||||
/* Transmit Command Register */
|
||||
|
||||
#define LPSPI_TCR_FRAMESZ_SHIFT (0) /* Bits 0-11: Frame Size */
|
||||
#define LPSPI_TCR_FRAMESZ_MASK (0xfff << LPSPI_TCR_FRAMESZ_SHIFT)
|
||||
# define LPSPI_TCR_FRAMESZ(n) ((uint32_t)(n) << LPSPI_TCR_FRAMESZ_SHIFT)
|
||||
/* Bits 12-15: Reserved */
|
||||
#define LPSPI_TCR_WIDTH_SHIFT (16) /* Bits 16-17: Transfer Width */
|
||||
#define LPSPI_TCR_WIDTH_MASK (3 << LPSPI_TCR_WIDTH_SHIFT)
|
||||
# define LPSPI_TCR_WIDTH_1BIT (0 << LPSPI_TCR_WIDTH_SHIFT) /* 1 bit transfer */
|
||||
# define LPSPI_TCR_WIDTH_2BIT (1 << LPSPI_TCR_WIDTH_SHIFT) /* 2 bit transfer */
|
||||
# define LPSPI_TCR_WIDTH_4BIT (2 << LPSPI_TCR_WIDTH_SHIFT) /* 4 bit transfer */
|
||||
#define LPSPI_TCR_TXMSK (1 << 18) /* Bit 18: Transmit Data Mask */
|
||||
#define LPSPI_TCR_RXMSK (1 << 19) /* Bit 19: Receive Data Mask */
|
||||
#define LPSPI_TCR_CONTC (1 << 20) /* Bit 20: Continuing Command */
|
||||
#define LPSPI_TCR_CONT (1 << 21) /* Bit 21: Continuous Transfer */
|
||||
#define LPSPI_TCR_BYSW (1 << 22) /* Bit 22: Byte Swap */
|
||||
#define LPSPI_TCR_LSBF (1 << 23) /* Bit 23: LSB First */
|
||||
# define LPSPI_TCR_MSBF (0 << 23) /* MSB First */
|
||||
#define LPSPI_TCR_PCS_SHIFT (24) /* Bits 24-25: Peripheral Chip Select */
|
||||
#define LPSPI_TCR_PCS_MASK (3 << LPSPI_TCR_PCS_SHIFT)
|
||||
# define LPSPI_TCR_PCS_0 (0 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[0] */
|
||||
# define LPSPI_TCR_PCS_1 (1 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[1] */
|
||||
# define LPSPI_TCR_PCS_2 (2 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[2] */
|
||||
# define LPSPI_TCR_PCS_3 (3 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[3] */
|
||||
/* Bit 26: Reserved */
|
||||
#define LPSPI_TCR_PRESCALE_SHIFT (27) /* Bits 27-29: Prescaler Value */
|
||||
#define LPSPI_TCR_PRESCALE_MASK (7 << LPSPI_TCR_PRESCALE_SHIFT)
|
||||
# define LPSPI_TCR_PRESCALE_1 (0 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 1 */
|
||||
# define LPSPI_TCR_PRESCALE_2 (1 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 2 */
|
||||
# define LPSPI_TCR_PRESCALE_4 (2 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 4 */
|
||||
# define LPSPI_TCR_PRESCALE_8 (3 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 8 */
|
||||
# define LPSPI_TCR_PRESCALE_16 (4 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 16 */
|
||||
# define LPSPI_TCR_PRESCALE_32 (5 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 32 */
|
||||
# define LPSPI_TCR_PRESCALE_64 (6 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 64 */
|
||||
# define LPSPI_TCR_PRESCALE_128 (7 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 128 */
|
||||
# define LPSPI_TCR_PRESCALE(n) ((uint32_t)(n) << LPSPI_TCR_PRESCALE_SHIFT)
|
||||
#define LPSPI_TCR_CPHA (1 << 30) /* Bit 30: Clock Phase */
|
||||
# define LPSPI_TCR_CPHA_CPT_LEAD (0 << 30) /* Data captured - leading edge of SCK and changed - following edge of SCK */
|
||||
# define LPSPI_TCR_CPHA_CPT_FOLLOW (1 << 30) /* Data changed - leading edge of SCK and captured - following edge of SCK */
|
||||
#define LPSPI_TCR_CPOL (1 << 31) /* Bit 31: Clock Polarity */
|
||||
# define LPSPI_TCR_CPOL_INACT_LOW (0 << 31) /* The inactive state value of SCK is low */
|
||||
# define LPSPI_TCR_CPOL_INACT_HIGH (1 << 31) /* The inactive state value of SCK is high */
|
||||
|
||||
/* Transmit Data Register */
|
||||
|
||||
#define LPSPI_TDR_DATA_SHIFT (0) /* Bits 0-31: Transmit Data */
|
||||
# define LPSPI_TCR_DATA(n) ((uint32_t)(n) << LPSPI_TDR_DATA_SHIFT)
|
||||
|
||||
/* Receive Status Register */
|
||||
|
||||
#define LPSPI_RSR_SOF (1 << 0) /* Bit 0: Start Of Frame */
|
||||
#define LPSPI_RSR_RXEMPTY (1 << 1) /* Bit 1: RX FIFO Empty */
|
||||
/* Bits 2-31: Reserved */
|
||||
|
||||
/* Receive Data Register */
|
||||
|
||||
#define LPSPI_RDR_DATA_SHIFT (0) /* Bits 0-31: Receive Data */
|
||||
#define LPSPI_RDR_DATA_MASK (0xffffffff << LPSPI_RDR_DATA_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_LPSPI_H */
|
||||
@ -1,5 +1,5 @@
|
||||
/********************************************************************************************
|
||||
* arch/arm/src/s32k1xx/hardware/imxrt_lpuart.h
|
||||
* arch/arm/src/s32k1xx/hardware/s32k1xx_lpuart.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
|
||||
1839
arch/arm/src/s32k1xx/s32k1xx_lpi2c.c
Normal file
1839
arch/arm/src/s32k1xx/s32k1xx_lpi2c.c
Normal file
File diff suppressed because it is too large
Load Diff
89
arch/arm/src/s32k1xx/s32k1xx_lpi2c.h
Normal file
89
arch/arm/src/s32k1xx/s32k1xx_lpi2c.h
Normal file
@ -0,0 +1,89 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/s32k1xx/s32k1xx_lpi2c.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Ivan Ucherdzhiev <ivanucherdjiev@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_IMXRT_IMX_LPI2C_H
|
||||
#define __ARCH_ARM_SRC_IMXRT_IMX_LPI2C_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/i2c/i2c_master.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/s32k1xx_lpi2c.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: s32k1xx_i2cbus_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected I2C port. And return a unique instance of struct
|
||||
* struct i2c_master_s. This function may be called to obtain multiple
|
||||
* instances of the interface, each of which may be set up with a
|
||||
* different frequency and slave address.
|
||||
*
|
||||
* Input Parameters:
|
||||
* Port number (for hardware that has multiple I2C interfaces)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid I2C device structure reference on success; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
FAR struct i2c_master_s *s32k1xx_i2cbus_initialize(int port);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: s32k1xx_i2cbus_uninitialize
|
||||
*
|
||||
* Description:
|
||||
* De-initialize the selected I2C port, and power down the device.
|
||||
*
|
||||
* Input Parameters:
|
||||
* Device structure as returned by the s32k1xx_i2cbus_initialize()
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success, ERROR when internal reference count mismatch or dev
|
||||
* points to invalid hardware device.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int s32k1xx_i2cbus_uninitialize(FAR struct i2c_master_s *dev);
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_IMXRT_IMX_LPI2C_H */
|
||||
1573
arch/arm/src/s32k1xx/s32k1xx_lpspi.c
Normal file
1573
arch/arm/src/s32k1xx/s32k1xx_lpspi.c
Normal file
File diff suppressed because it is too large
Load Diff
176
arch/arm/src/s32k1xx/s32k1xx_lpspi.h
Normal file
176
arch/arm/src/s32k1xx/s32k1xx_lpspi.h
Normal file
@ -0,0 +1,176 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/s32k1xx/s32k1xx_lpspi.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Authors: Ivan Ucherdzhiev <ivanucherdjiev@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_S32K1XX_S32K1XX_LPSPI_H
|
||||
#define __ARCH_ARM_SRC_S32K1XX_S32K1XX_LPSPI_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <nuttx/spi/spi.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/s32k1xx_lpspi.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
struct spi_dev_s; /* Forward reference */
|
||||
|
||||
/************************************************************************************
|
||||
* Name: s32k1xx_lpspibus_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected SPI bus
|
||||
*
|
||||
* Input Parameters:
|
||||
* bus number (for hardware that has mutiple SPI interfaces)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid SPI device structure reference on succcess; a NULL on failure
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
FAR struct spi_dev_s *s32k1xx_lpspibus_initialize(int bus);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: s32k1xx_lpspi0/1/2/select and s32k1xx_lpspi0/1/2/status
|
||||
*
|
||||
* Description:
|
||||
* The external functions, s32k1xx_lpspi001/2/select, s32k1xx_lpspi0/1/2/status,
|
||||
* and s32k1xx_lpspi0/1/2/cmddata must be provided by board-specific logic.
|
||||
* These are implementations of the select, status, and cmddata methods of the SPI
|
||||
* interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other
|
||||
* methods (including s32k1xx_lpspibus_initialize()) are provided by common
|
||||
* S32K1XX logic. To use this common SPI logic on your board:
|
||||
*
|
||||
* 1. Provide logic in s32k1xx_boardinitialize() to configure SPI chip select
|
||||
* pins.
|
||||
* 2. Provide s32k1xx_lpspi0/1/2/select() and s32k1xx_lpspi0/1/2/status()
|
||||
* functions in your board-specific logic. These functions will perform chip
|
||||
* selection and status operations using GPIOs in the way your board is
|
||||
* configured.
|
||||
* 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, then
|
||||
* provide s32k1xx_lpspi0/1/2/cmddata() functions in your board-specific logic.
|
||||
* These functions will perform cmd/data selection operations using GPIOs in
|
||||
* the way your board is configured.
|
||||
* 4. Add a calls to s32k1xx_lpspibus_initialize() in your low level application
|
||||
* initialization logic
|
||||
* 5. The handle returned by s32k1xx_lpspibus_initialize() may then be used to
|
||||
* bind the SPI driver to higher level logic (e.g., calling
|
||||
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
|
||||
* the SPI MMC/SD driver).
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_S32K1XX_LPSPI0
|
||||
void s32k1xx_lpspi0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
|
||||
uint8_t s32k1xx_lpspi0status(FAR struct spi_dev_s *dev, uint32_t devid);
|
||||
int s32k1xx_lpspi0cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_S32K1XX_LPSPI1
|
||||
void s32k1xx_lpspi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
|
||||
uint8_t s32k1xx_lpspi1status(FAR struct spi_dev_s *dev, uint32_t devid);
|
||||
int s32k1xx_lpspi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_S32K1XX_LPSPI2
|
||||
void s32k1xx_lpspi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
|
||||
uint8_t s32k1xx_lpspi2status(FAR struct spi_dev_s *dev, uint32_t devid);
|
||||
int s32k1xx_lpspi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: s32k1xx_lpspi0/1/2/register
|
||||
*
|
||||
* Description:
|
||||
* If the board supports a card detect callback to inform the SPI-based MMC/SD
|
||||
* driver when an SD card is inserted or removed, then CONFIG_SPI_CALLBACK should
|
||||
* be defined and the following function(s) must be implemented. These functions
|
||||
* implements the registercallback method of the SPI interface (see
|
||||
* include/nuttx/spi/spi.h for details)
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
* callback - The function to call on the media change
|
||||
* arg - A caller provided value to return with the callback
|
||||
*
|
||||
* Returned Value:
|
||||
* 0 on success; negated errno on failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SPI_CALLBACK
|
||||
#ifdef CONFIG_S32K1XX_LPSPI0
|
||||
int s32k1xx_lpspi0register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
FAR void *arg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_S32K1XX_LPSPI1
|
||||
int s32k1xx_lpspi1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
FAR void *arg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_S32K1XX_LPSPI2
|
||||
int s32k1xx_lpspi2register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
FAR void *arg);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_S32K1XX_S32K1XX_LPSPI_H */
|
||||
Loading…
Reference in New Issue
Block a user